188 lines
5.5 KiB
C
188 lines
5.5 KiB
C
/* vxbOmap35xxGpio.h - GPIO driver header file */
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/*
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* Copyright (c) 2010, 2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01d,14sep11,jmz WIND00302612 Update omap35xxGpioAllocatePin function
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01c,28jan11,jmz Add definition for GPIO pin 182
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01b,28oct10,dbr updates for power management
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01a,06oct10,dbr created and ported to vxBus
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*/
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#ifndef __INComap35xxGpioh
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#define __INComap35xxGpioh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdio.h>
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/* GPIO modules base addresses */
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#define OMAP35XX_GPIO1 0x48310000
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#define OMAP35XX_GPIO2 0x49050000
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#define OMAP35XX_GPIO3 0x49052000
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#define OMAP35XX_GPIO4 0x49054000
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#define OMAP35XX_GPIO5 0x49056000
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#define OMAP35XX_GPIO6 0x49058000
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/* GPIO registers */
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#define OMAP35XX_GPIO_SYSCONFIG 0x010
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#define OMAP35XX_GPIO_SYSSTATUS 0x014
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#define OMAP35XX_GPIO_IRQSTATUS1 0x018
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#define OMAP35XX_GPIO_IRQENABLE1 0x01C
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#define OMAP35XX_GPIO_WAKEUPENABLE 0x020
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#define OMAP35XX_GPIO_IRQSTATUS2 0x028
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#define OMAP35XX_GPIO_IRQENABLE2 0x02C
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#define OMAP35XX_GPIO_CTRL 0x030
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#define OMAP35XX_GPIO_OE 0x034
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#define OMAP35XX_GPIO_DATAIN 0x038
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#define OMAP35XX_GPIO_DATAOUT 0x03C
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#define OMAP35XX_GPIO_LEVELDETECT0 0x040
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#define OMAP35XX_GPIO_LEVELDETECT1 0x044
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#define OMAP35XX_GPIO_RISINGDETECT 0x048
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#define OMAP35XX_GPIO_FALLINGDETECT 0x04C
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#define OMAP35XX_GPIO_DEBOUNCENABLE 0x050
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#define OMAP35XX_GPIO_DEBOUNCINGTIME 0x054
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#define OMAP35XX_GPIO_CLEARIRQENABLE1 0x060
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#define OMAP35XX_GPIO_SETIRQENABLE1 0x064
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#define OMAP35XX_GPIO_CLEARIRQENABLE2 0x070
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#define OMAP35XX_GPIO_SETIRQENABLE2 0x074
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#define OMAP35XX_GPIO_CLEARWKUENA 0x080
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#define OMAP35XX_GPIO_SETWKUENA 0x084
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#define OMAP35XX_GPIO_CLEARDATAOUT 0x090
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#define OMAP35XX_GPIO_SETDATAOUT 0x094
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/* omap35xx contains 6 modules each with 32 GPIO pins, total of 192 pins */
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#define GPIO_MAX_MODULES 6
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#define GPIO_NUM_PINS_IN_MODULE 32
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#define GPIO_MAX_PINS 192
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/* GPIO modules functional & interface clock enable masks */
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#define OMAP35XX_GPIO2_FCLK_EN (1<<13)
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#define OMAP35XX_GPIO2_ICLK_EN (1<<13)
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#define OMAP35XX_GPIO3_FCLK_EN (1<<14)
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#define OMAP35XX_GPIO3_ICLK_EN (1<<14)
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#define OMAP35XX_GPIO4_FCLK_EN (1<<15)
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#define OMAP35XX_GPIO4_ICLK_EN (1<<15)
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#define OMAP35XX_GPIO5_FCLK_EN (1<<16)
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#define OMAP35XX_GPIO5_ICLK_EN (1<<16)
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#define OMAP35XX_GPIO6_FCLK_EN (1<<17)
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#define OMAP35XX_GPIO6_ICLK_EN (1<<17)
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/*
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*============================================================
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* GPIO pin configuration for LogicPD
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*============================================================
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*/
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#define OMAP35XX_GPIO_ISP1760_SUSPEND_N 182
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#define OMAP35XX_GPIO_LAN9115_IRQ_PHYS_PIN 152 /* GPIO 5, BIT 24 */
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#define OMAP35XX_GPIO_LAN9115_IRQ_BANK 5
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#define OMAP35XX_GPIO_LAN9115_IRQ_BIT 24
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#define OMAP35XX_GPIO_LAN9115_IRQ_MASK (0x1 << 24)
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#define OMAP35XX_GPIO_LCD_ENVDD_PIN 153 /* GPIO 5, BIT 25 */
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#define OMAP35XX_GPIO_LCD_ENVDD_BANK 5
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#define OMAP35XX_GPIO_LCD_ENVDD_BIT 25
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#define OMAP35XX_GPIO_LCD_ENVDD_MASK (0x1 << 25)
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/* addresses of six GPIO registers used to allocate memory banks */
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enum _omap_gpio_bank_reg
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{
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OMAP3_GPIO1 = 0x48310000,
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OMAP3_GPIO2 = 0x49050000,
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OMAP3_GPIO3 = 0x49052000,
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OMAP3_GPIO4 = 0x49054000,
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OMAP3_GPIO5 = 0x49056000,
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OMAP3_GPIO6 = 0x49058000
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};
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/* GPIO pin modes */
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enum _omap_gpio_io_mode
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{
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OMAP3_GPIO_OUTPUT,
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OMAP3_GPIO_INPUT
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};
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/* define the power domain of the GPIO */
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enum omapGpioPowerDomain
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{
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OMAP_GPIO_PWR_WKUP,
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OMAP_GPIO_PWR_PER,
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OMAP_GPIO_PWR_CORE
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};
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/* define six GPIO modules */
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enum omapGpioModules
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{
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OMAP_GPIO_MODULE_1,
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OMAP_GPIO_MODULE_2,
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OMAP_GPIO_MODULE_3,
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OMAP_GPIO_MODULE_4,
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OMAP_GPIO_MODULE_5,
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OMAP_GPIO_MODULE_6
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};
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/* define power states for a GPIO module */
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enum omapGpioMoudlePowerState
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{
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OMAP_GPIO_MODULE_POWER_ON,
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OMAP_GPIO_MODULE_POWER_OFF
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};
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/* struct for registers and masks used to control module power */
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struct gpioPowerRegs
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{
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UINT32 regIclk;
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UINT32 regFclk;
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UINT32 maskIclk[GPIO_MAX_MODULES];
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UINT32 maskFclk[GPIO_MAX_MODULES];
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};
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#define OMAP35XX_GPIO_REGISTER_WRITE(reg, value) \
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*(volatile UINT32*)(reg) = value
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#define OMAP35XX_GPIO_REGISTER_READ(reg) \
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(*(volatile UINT32*)(reg))
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/* prototypes */
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#ifndef _ASMLANGUAGE
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IMPORT STATUS omap35xxGpioAllocatePin (UINT32 pin, UINT32 mode, BOOL outputValue);
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IMPORT STATUS omap35xxGpioDeallocatePin (UINT32 pin);
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IMPORT void omap35xxGpioPinSet (UINT32 pin, BOOL val);
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IMPORT INT32 omap35xxGpioPinGet (UINT32 pin);
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IMPORT STATUS omap35xxGpioWritePinRegister (UINT32 pin, UINT32 reg, BOOL val);
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IMPORT STATUS omap35xxGpioWriteRegister (UINT32 pin, UINT32 reg, UINT32 val);
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IMPORT STATUS omap35xxGpioReadRegister (UINT32 pin, UINT32 reg, UINT32 *val);
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IMPORT void omap35xxGpioPadConf (UINT32 pin, UINT16 cfg);
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IMPORT void omap35xxGpioConnectUsrIsr (void *usrIsr, UINT32 pin);
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IMPORT void omap35xxGpioPowerModules (UINT32 mode);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INComap35xxGpioh */
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