343 lines
8.7 KiB
C
343 lines
8.7 KiB
C
/* z8530Sio.h - header file for binary interface z8530 driver */
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/* Copyright 1984-1994 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01d,20may97,db added element options to Z8530_CHAN structure to
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implement hardware options & modem control(SPR #1037).
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01c,13oct95,ms added comments for what fields need to be set by the BSP
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01b,15jun95,ms updated for new driver structure
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01a,20dec94,ms written (from z8530Serial.h).
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*/
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#ifndef __INCwdbz8530h
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#define __INCwdbz8530h
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#include "sioLib.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* device and channel structures */
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/* The BSP must initilize all Z8530_CHAN fields which say "BSP:" */
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typedef struct /* Z8530_CHAN */
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{
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/* always goes first */
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SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
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/* callbacks */
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STATUS (*getTxChar) (); /* pointer to xmitr function */
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STATUS (*putRcvChar) (); /* pointer to rcvr functione */
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void * getTxArg;
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void * putRcvArg;
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/* control and data register addresses */
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volatile char * cr; /* BSP: control register I/O address */
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volatile char * dr; /* BSP: data port I/O address */
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/* misc values */
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int baudFreq; /* BSP: baud clock frequency */
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int baudRate; /* baud rate */
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int options; /* hardware options */
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char writeReg5; /* BSP: write register 5 value */
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char writeReg11; /* BSP: write register 11 value */
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char writeReg14; /* BSP: write register 14 value */
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/* interrupt/polled mode configuration info */
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uint_t mode; /* SIO_MODE_[INT | POLL] */
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char intVec; /* BSP: interrupt vector address */
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char intType; /* BSP: type of vector to supply from 8530 */
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uint_t channel; /* channel number (0 or 1) */
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} Z8530_CHAN;
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typedef struct
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{
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Z8530_CHAN portA; /* port A device descriptor */
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Z8530_CHAN portB; /* port B device descriptor */
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} Z8530_DUSART;
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/* channels */
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#define SCC_CHANNEL_A 0
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#define SCC_CHANNEL_B 1
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/* bit values for write register 0 */
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/* command register */
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#define SCC_WR0_SEL_WR0 0x00
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#define SCC_WR0_SEL_WR1 0x01
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#define SCC_WR0_SEL_WR2 0x02
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#define SCC_WR0_SEL_WR3 0x03
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#define SCC_WR0_SEL_WR4 0x04
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#define SCC_WR0_SEL_WR5 0x05
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#define SCC_WR0_SEL_WR6 0x06
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#define SCC_WR0_SEL_WR7 0x07
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#define SCC_WR0_SEL_WR8 0x08
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#define SCC_WR0_SEL_WR9 0x09
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#define SCC_WR0_SEL_WR10 0x0a
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#define SCC_WR0_SEL_WR11 0x0b
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#define SCC_WR0_SEL_WR12 0x0c
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#define SCC_WR0_SEL_WR13 0x0d
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#define SCC_WR0_SEL_WR14 0x0e
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#define SCC_WR0_SEL_WR15 0x0f
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#define SCC_WR0_NULL_CODE 0x00
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#define SCC_WR0_RST_INT 0x10
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#define SCC_WR0_SEND_ABORT 0x18
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#define SCC_WR0_EN_INT_RX 0x20
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#define SCC_WR0_RST_TX_INT 0x28
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#define SCC_WR0_ERR_RST 0x30
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#define SCC_WR0_RST_HI_IUS 0x38
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#define SCC_WR0_RST_RX_CRC 0x40
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#define SCC_WR0_RST_TX_CRC 0x80
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#define SCC_WR0_RST_TX_UND 0xc0
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/* write register 2 */
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/* interrupt vector */
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/* bit values for write register 1 */
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/* tx/rx interrupt and data transfer mode definition */
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#define SCC_WR1_EXT_INT_EN 0x01
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#define SCC_WR1_TX_INT_EN 0x02
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#define SCC_WR1_PARITY 0x04
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#define SCC_WR1_RX_INT_DIS 0x00
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#define SCC_WR1_RX_INT_FIR 0x08
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#define SCC_WR1_INT_ALL_RX 0x10
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#define SCC_WR1_RX_INT_SPE 0x18
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#define SCC_WR1_RDMA_RECTR 0x20
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#define SCC_WR1_RDMA_FUNC 0x40
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#define SCC_WR1_RDMA_EN 0x80
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/* bit values for write register 3 */
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/* receive parameters and control */
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#define SCC_WR3_RX_EN 0x01
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#define SCC_WR3_SYNC_CHAR 0x02
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#define SCC_WR3_ADR_SEARCH 0x04
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#define SCC_WR3_RX_CRC_EN 0x08
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#define SCC_WR3_ENTER_HUNT 0x10
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#define SCC_WR3_AUTO_EN 0x20
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#define SCC_WR3_RX_5_BITS 0x00
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#define SCC_WR3_RX_7_BITS 0x40
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#define SCC_WR3_RX_6_BITS 0x80
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#define SCC_WR3_RX_8_BITS 0xc0
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/* bit values for write register 4 */
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/* tx/rx misc parameters and modes */
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#define SCC_WR4_PAR_EN 0x01
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#define SCC_WR4_PAR_EVEN 0x02
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#define SCC_WR4_SYNC_EN 0x00
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#define SCC_WR4_1_STOP 0x04
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#define SCC_WR4_2_STOP 0x0c
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#define SCC_WR4_8_SYNC 0x00
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#define SCC_WR4_16_SYNC 0x10
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#define SCC_WR4_SDLC 0x20
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#define SCC_WR4_EXT_SYNC 0x30
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#define SCC_WR4_1_CLOCK 0x00
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#define SCC_WR4_16_CLOCK 0x40
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#define SCC_WR4_32_CLOCK 0x80
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#define SCC_WR4_64_CLOCK 0xc0
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/* bit values for write register 5 */
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/* transmit parameter and controls */
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#define SCC_WR5_TX_CRC_EN 0x01
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#define SCC_WR5_RTS 0x02
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#define SCC_WR5_SDLC 0x04
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#define SCC_WR5_TX_EN 0x08
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#define SCC_WR5_SEND_BRK 0x10
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#define SCC_WR5_TX_5_BITS 0x00
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#define SCC_WR5_TX_7_BITS 0x20
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#define SCC_WR5_TX_6_BITS 0x40
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#define SCC_WR5_TX_8_BITS 0x60
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#define SCC_WR5_DTR 0x80
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/* write register 6 */
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/* sync chars or sdlc address field */
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/* write register 7 */
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/* sync char or sdlc flag */
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/* write register 8 */
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/* transmit buffer */
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/* bit values for write register 9 */
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/* master interrupt control */
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#define SCC_WR9_VIS 0x01
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#define SCC_WR9_NV 0x02
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#define SCC_WR9_DLC 0x04
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#define SCC_WR9_MIE 0x08
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#define SCC_WR9_STATUS_HI 0x10
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#define SCC_WR9_NO_RST 0x00
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#define SCC_WR9_CH_B_RST 0x40
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#define SCC_WR9_CH_A_RST 0x80
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#define SCC_WR9_HDWR_RST 0xc0
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/* bit values for write register 10 */
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/* misc tx/rx control bits */
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#define SCC_WR10_6_BIT_SYNC 0x01
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#define SCC_WR10_LOOP_MODE 0x02
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#define SCC_WR10_ABORT_UND 0x04
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#define SCC_WR10_MARK_IDLE 0x08
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#define SCC_WR10_ACT_POLL 0x10
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#define SCC_WR10_NRZ 0x00
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#define SCC_WR10_NRZI 0x20
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#define SCC_WR10_FM1 0x40
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#define SCC_WR10_FM0 0x60
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#define SCC_WR10_CRC_PRESET 0x80
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/* bit values for write register 11 */
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/* clock mode control */
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#define SCC_WR11_OUT_XTAL 0x00
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#define SCC_WR11_OUT_TX_CLK 0x01
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#define SCC_WR11_OUT_BR_GEN 0x02
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#define SCC_WR11_OUT_DPLL 0x03
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#define SCC_WR11_TRXC_OI 0x04
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#define SCC_WR11_TX_RTXC 0x00
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#define SCC_WR11_TX_TRXC 0x08
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#define SCC_WR11_TX_BR_GEN 0x10
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#define SCC_WR11_TX_DPLL 0x18
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#define SCC_WR11_RX_RTXC 0x00
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#define SCC_WR11_RX_TRXC 0x20
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#define SCC_WR11_RX_BR_GEN 0x40
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#define SCC_WR11_RX_DPLL 0x60
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#define SCC_WR11_RTXC_XTAL 0x80
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/* write register 12 */
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/* lower byte of baud rate generator time constant */
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/* write register 13 */
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/* upper byte of baud rate generator time constant */
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/* bit values for write register 14 */
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/* misc control bits */
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#define SCC_WR14_BR_EN 0x01
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#define SCC_WR14_BR_SRC 0x02
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#define SCC_WR14_DTR_FUNC 0x04
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#define SCC_WR14_AUTO_ECHO 0x08
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#define SCC_WR14_LCL_LOOP 0x10
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#define SCC_WR14_NULL 0x00
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#define SCC_WR14_SEARCH 0x20
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#define SCC_WR14_RST_CLK 0x40
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#define SCC_WR14_DIS_DPLL 0x60
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#define SCC_WR14_SRC_BR 0x80
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#define SCC_WR14_SRC_RTXC 0xa0
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#define SCC_WR14_FM_MODE 0xc0
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#define SCC_WR14_NRZI 0xe0
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/* bit values for write register 15 */
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/* external/status interrupt control */
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#define SCC_WR15_ZERO_CNT 0x02
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#define SCC_WR15_CD_IE 0x08
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#define SCC_WR15_SYNC_IE 0x10
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#define SCC_WR15_CTS_IE 0x20
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#define SCC_WR15_TX_UND_IE 0x40
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#define SCC_WR15_BREAK_IE 0x80
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/* bit values for read register 0 */
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/* tx/rx buffer status and external status */
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#define SCC_RR0_RX_AVAIL 0x01
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#define SCC_RR0_ZERO_CNT 0x02
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#define SCC_RR0_TX_EMPTY 0x04
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#define SCC_RR0_CD 0x08
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#define SCC_RR0_SYNC 0x10
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#define SCC_RR0_CTS 0x20
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#define SCC_RR0_TX_UND 0x40
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#define SCC_RR0_BREAK 0x80
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/* bit values for read register 1 */
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#define SCC_RR1_ALL_SENT 0x01
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#define SCC_RR1_RES_CD_2 0x02
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#define SCC_RR1_RES_CD_1 0x01
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#define SCC_RR1_RES_CD_0 0x08
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#define SCC_RR1_PAR_ERR 0x10
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#define SCC_RR1_RX_OV_ERR 0x20
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#define SCC_RR1_CRC_ERR 0x40
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#define SCC_RR1_END_FRAME 0x80
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/* read register 2 */
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/* interrupt vector */
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/* bit values for read register 3 */
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/* interrupt pending register */
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#define SCC_RR3_B_EXT_IP 0x01
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#define SCC_RR3_B_TX_IP 0x02
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#define SCC_RR3_B_RX_IP 0x04
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#define SCC_RR3_A_EXT_IP 0x08
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#define SCC_RR3_A_TX_IP 0x10
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#define SCC_RR3_A_RX_IP 0x20
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/* read register 8 */
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/* receive data register */
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/* bit values for read register 10 */
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/* misc status bits */
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#define SCC_RR10_ON_LOOP 0x02
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#define SCC_RR10_LOOP_SEND 0x10
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#define SCC_RR10_2_CLK_MIS 0x40
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#define SCC_RR10_1_CLK_MIS 0x80
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/* read register 12 */
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/* lower byte of time constant */
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/* read register 13 */
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/* upper byte of time constant */
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/* bit values for read register 15 */
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/* external/status ie bits */
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#define SCC_RR15_ZERO_CNT 0x02
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#define SCC_RR15_CD_IE 0x08
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#define SCC_RR15_SYNC_IE 0x10
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#define SCC_RR15_CTS_IE 0x20
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#define SCC_RR15_TX_UND_IE 0x40
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#define SCC_RR15_BREAK_IE 0x80
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#if defined(__STDC__) || defined(__cplusplus)
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extern void z8530DevInit (Z8530_DUSART *pDusart);
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extern void z8530IntWr (Z8530_CHAN * pChan);
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extern void z8530IntRd (Z8530_CHAN * pChan);
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extern void z8530IntEx (Z8530_CHAN * pChan);
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extern void z8530Int (Z8530_DUSART *pDusart);
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#else /* __STDC__ */
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extern void z8530DevInit ();
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extern void z8530IntWr ();
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extern void z8530IntRd ();
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extern void z8530IntEx ();
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extern void z8530Int ();
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#endif /* __STDC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCwdbz8530h */
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