164 lines
4.9 KiB
C
164 lines
4.9 KiB
C
/* shScifSio.h - header file for Renesas SH on-chip SCIF serial driver */
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/*
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* Copyright (c) 1984-2006, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01r,29apr10,pad Moved extern C statement after include statements.
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01q,10mar06,h_k updated for SH7785. (SPR#118883)
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01p,18oct05,h_k added SH7710 and SH7705 support. (SPR #90076)
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01o,05nov02,h_k added tfdr2 to SCIF_CHAN for SH7760 support. (SPR #105971)
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01n,06mar02,h_k added lsr2 and ss2r2 to SCIF_CHAN and SCIF_LSR2_ORER and
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SCIF_SS2R2_ORER definitions (SPR #73777).
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01m,15nov00,csi modification to optimize SMR and BRR define
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01l,30aug00,zl added 30MHz PCLK support for SH7600
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01k,04aug00,rsh Add 33.33Mhz frequency defines for sh7729
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01j,31may00,frf SH7751 for T2
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01i,05mar99,hk Sorted out CPU conditional order.
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01h,26nov98,hk Added support for SH7750.
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01g,10aug98,jmb reg size fix.
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01f,10aug98,jmb bugfix.
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01e,10aug98,jmb Added support for Manta-DSP.
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01d,30jul98,jmb Added support for Manta-SH3 frequencies.
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01c,30may98,jmb Added options to support multiple data formats.
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01b,23may98,jmb Fixed decl's and FCR2 macros, transmit triggers.
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01a,20may98,jmb Created.
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*/
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#ifndef __INCshScifSioh
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#define __INCshScifSioh
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#include <sioLib.h>
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#include <drv/sio/shSciSio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if (CPU==SH7750)
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#define SZ_SMR2 UINT16
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#define SZ_SCR2 UINT16
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#define SZ_FCR2 UINT16
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#else
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# ifndef SZ_SMR2
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# define SZ_SMR2 UINT8
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# endif
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# ifndef SZ_SCR2
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# define SZ_SCR2 UINT8
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# endif
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# ifndef SZ_FCR2
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# define SZ_FCR2 UINT8
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# endif
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#endif
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/* device channel structure */
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typedef struct
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{
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/* always goes first */
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SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
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/* callbacks */
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STATUS (*getTxChar) ();
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STATUS (*putRcvChar) ();
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void * getTxArg;
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void * putRcvArg;
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/* info */
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int mode; /* current mode (interrupt or poll) */
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int baud; /* baud rate */
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UINT options; /* data format options */
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/* register addresses */
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volatile SZ_SMR2 * smr2; /* serial mode register */
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volatile UINT8 * brr2; /* bit rate register */
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volatile SZ_SCR2 * scr2; /* serial control register */
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volatile UINT8 * sfdr2; /* transmit FIFO data register */
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volatile UINT16 * ssr2; /* serial status register */
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volatile UINT8 * frdr2; /* receive FIFO data register */
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volatile SZ_FCR2 * fcr2; /* FIFO control register */
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volatile UINT16 * fdr2; /* data count set register */
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volatile UINT16 * lsr2; /* line status register */
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volatile UINT8 * ss2r2; /* serial status 2 register */
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volatile UINT16 * tfdr2; /* transmit data count set register */
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} SCIF_CHAN;
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/* Maximum FIFO length */
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#ifndef SCIF_FIFO_LEN
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#define SCIF_FIFO_LEN 16
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#endif
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/* Extra bit values for scr (serial control register) */
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#ifndef SCIF_SCR2_EXIE
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#define SCIF_SCR2_EXIE 0
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#endif
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/* Bit values for FIFO control register */
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#define SCIF_FCR2_RTRG 0xc0 /* Read mask for receive trigger */
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#define SCIF_FCR2_RTRG_1 0x00 /* 1 char in FIFO triggers receive */
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#define SCIF_FCR2_RTRG_4 0x40 /* 4 chars in FIFO triggers receive */
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#define SCIF_FCR2_RTRG_8 0x80 /* 8 chars in FIFO triggers receive */
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#define SCIF_FCR2_RTRG_14 0xc0 /* 14 chars in FIFO triggers receive */
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#define SCIF_FCR2_TTRG 0x30 /* Read mask for transmit trigger */
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#define SCIF_FCR2_TTRG_8 0x00 /* */
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#define SCIF_FCR2_TTRG_4 0x10 /* */
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#define SCIF_FCR2_TTRG_2 0x20 /* */
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#define SCIF_FCR2_TTRG_1 0x30 /* */
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#ifndef SCIF_FCR2_TRG_DEFAULT
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#define SCIF_FCR2_TRG_DEFAULT (SCIF_FCR2_RTRG | SCIF_FCR2_TTRG)
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#endif
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#define SCIF_FCR2_MCE 0x8 /* Enable RTS/CTS signals */
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#define SCIF_FCR2_TFRST 0x4 /* Clear transmit FIFO on reset */
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#define SCIF_FCR2_RFRST 0x2 /* Clear receive RIFO on reset */
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#define SCIF_FCR2_LOOP 0x1 /* Loopback mode */
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/* bit values for ssr (serial status register) */
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#define SCIF_SSR2_ER 0x80 /* framing or parity error */
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#define SCIF_SSR2_TEND 0x40 /* tranmission end indicator */
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#define SCIF_SSR2_TDFE 0x20 /* transmit data FIFO empty */
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#define SCIF_SSR2_BRK 0x10 /* break signal received */
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#define SCIF_SSR2_FER 0x08 /* framing error */
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#define SCIF_SSR2_PER 0x04 /* parity error */
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#define SCIF_SSR2_RDF 0x02 /* receive FIFO full */
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#define SCIF_SSR2_DR 0x01 /* data ready in receive FIFO */
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/* bit value for lsr (line status register) */
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#define SCIF_LSR2_ORER 0x1 /* overrun error */
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/* bit value for ss2r (serial status 2 register) */
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#define SCIF_SS2R2_ORER 0x1 /* overrun error */
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/* function prototypes */
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extern void shScifDevInit (SCIF_CHAN *pChan);
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extern void shScifIntRcv (SCIF_CHAN *pChan);
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extern void shScifIntTx (SCIF_CHAN *pChan);
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extern void shScifIntErr (SCIF_CHAN *pChan);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCshScifSioh */
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