146 lines
4.3 KiB
C
146 lines
4.3 KiB
C
/* qeIntrCtl.h - Quicc Engine interrupt controller header file */
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/* Copyright (c) Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,10jan05,dtr adapted from m85xxIntrCtl.
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*/
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#ifndef __INCqeIntrCtlh
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#define __INCqeIntrCtlh
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#include "vxWorks.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#ifdef QE_IVEC_TO_INUM
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# undef QE_IVEC_TO_INUM
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#endif /* IVEC_TO_INUM */
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#ifdef QE_INUM_TO_IVEC
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# undef QE_INUM_TO_IVEC
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#endif /* INUM_TO_IVEC */
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#define QE_IVEC_TO_INUM(intVec) (qeIvecToInum(intVec))
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#define QE_INUM_TO_IVEC(intNum) (qeInumToIvec(intNum))
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/* This offset used to allow intConnect/Enable etc to direct a call to the
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* quiccEngine controller vs the e300 or e500 interrupt controller
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* append this to int<func> call vector/intNum.
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* eg intEnable(QE_INUM_UCC1 + QE_INUM_OFFSET)
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*/
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#define QE_INUM_OFFSET IVEC_MAX
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#define QE_INUM_ERROR 0
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#define QE_INUM_SPI2 1
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#define QE_INUM_SPI1 2
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#define QE_INUM_RTT 3
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#define QE_INUM_SDMA 10
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#define QE_INUM_USB 11
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#define QE_INUM_TIMER1 12
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#define QE_INUM_TIMER2 13
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#define QE_INUM_TIMER3 14
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#define QE_INUM_TIMER4 15
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#define QE_INUM_VT 20
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#define QE_INUM_EXT1 25
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#define QE_INUM_EXT2 26
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#define QE_INUM_EXT3 27
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#define QE_INUM_EXT4 28
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#define QE_INUM_UCC1 32
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#define QE_INUM_UCC2 33
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#define QE_INUM_UCC3 34
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#define QE_INUM_UCC4 35
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#define QE_INUM_MCC1 36
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#define QE_INUM_UCC5 40
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#define QE_INUM_UCC6 41
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#define QE_INUM_UCC7 42
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#define QE_INUM_UCC8 43
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#define QE_INUM_MAX 64
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#define QE_IVEC_MAX 64
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#if 0
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#define QE_CICR 0x80 /* interrupt configuration Register */
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#define QE_CIVEC 0x84
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#define QE_CRIPNR 0x88
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#define QE_CIPNR 0x8C
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#define QE_CIPXCC 0x90
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#define QE_CIPYCC 0x94
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#define QE_CIPWCC 0x98
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#define QE_CIPZCC 0x9C
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#define QE_CIMR 0xA0
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#define QE_CRIMR 0xA4
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#define QE_CICNR 0xA8
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#define QE_CIPRTA 0xB0
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#define QE_CIPRTB 0xB4
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#define QE_CRIC 0xBC
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#define QE_CHIVEC 0xE0
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#else
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#define QE_CICR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x80)) /* interrupt configuration Register */
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#define QE_CIVEC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x84))
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#define QE_CRIPNR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x88))
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#define QE_CIPNR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x8C))
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#define QE_CIPXCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x90))
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#define QE_CIPYCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x94))
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#define QE_CIPWCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x98))
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#define QE_CIPZCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x9C))
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#define QE_CIMR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xA0))
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#define QE_CRIMR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xA4))
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#define QE_CICNR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xA8))
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#define QE_CIPRTA(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xB0))
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#define QE_CIPRTB(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xB4))
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#define QE_CRIC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xBC))
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#define QE_CHIVEC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xE0))
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#endif
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#ifndef _ASMLANGUAGE
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typedef struct qe_intr_handler
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{
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VOIDFUNCPTR vec; /* interrupt vector */
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int arg; /* interrupt handler argument */
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void *pNext;
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} QE_INTR_HANDLER;
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT STATUS qeIntrInit ();
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extern STATUS qeIntDisable (int );
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IMPORT STATUS qeIntEnable (int );
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extern int qeIvecToInum(VOIDFUNCPTR *);
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extern VOIDFUNCPTR * qeInumToIvec(int);
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#else
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IMPORT STATUS qeIntrInit ();
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extern STATUS qeIntDisable ();
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IMPORT STATUS qeIntEnable ();
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extern int qeIvecToInum();
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extern VOIDFUNCPTR * qeInumToIvec();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCqeIntrCtlh */
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