391 lines
17 KiB
C
391 lines
17 KiB
C
/* ppc405.h - PowerPC 405 specific header */
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/*
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* Copyright (c) 1984-2007, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01t,12apr12,cww use common ESR definitions
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01s,16jul07,pch CQ86377: re-enable MSR[FP] for syscall handler if enabled in
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caller
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01r,29jun07,pch CQ96747: rename _PPC_MSR_MMU_EXTRACT macro
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01q,06jul06,pch add MSR bit definitions & use in INT_MASK
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01p,01nov04,pch SPR 83004: move SPRG[4-7] definitions from asmPpc.h to ppc405.h
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01o,24sep04,pch add _PPC_MSR_DWE
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01n,12feb04,jtp Add _WRS_MMU_CLASS_* macro
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01m,05dec03,jtp Add _WRS_TLB_MISS_CLASS_HW, _PPC_MSR_MMU_EXTRACT
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01l,29oct03,jtp SPR 77774: Support Writethru cache
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01k,23oct03,pch SPR 80911: get PPC4xx cache dimensions from PVR
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01j,13mar03,pch Add PPC32 support & fix SPR 83162
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01i,06dec02,pch Add MSR bit number definitions
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01h,13jun02,jtp identify class of MMU support (SPR #78396)
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01g,22nov01,pch Add _WRS_STRICT_ALIGNMENT for target/src/ostool/loadElfLib.c
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01f,04dec00,s_m register cleanup
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01e,30nov00,s_m fixed PLB error address regs
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01d,30oct00,s_m changed DBCR to DBCR0
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01c,25oct00,s_m renamed PPC405 cpu types
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01b,20oct00,s_m Added defines from walnut bsp ppc405.h
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01a,07mar00,alp written.
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*/
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#ifndef __INCppc405h
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#define __INCppc405h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Tell the loader this processor can't handle any misalignment.
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* It's supposed to be able to, but this seems a
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* worthwhile precaution considering various errata.
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*/
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#define _WRS_STRICT_ALIGNMENT 1
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/* MMU supports software TLB miss handler */
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#define _WRS_TLB_MISS_CLASS_SW 1
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#undef _WRS_TLB_MISS_CLASS_HW
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/* MMU uses PID register to extend virtual address tag */
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#define _WRS_MMU_CLASS_PID_REG 1
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#undef _WRS_MMU_CLASS_SR_REGS
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#undef _WRS_MMU_CLASS_NONE
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/* MMU ASID context register name for _WRS_MMU_CLASS_PID_REG */
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#define _PPC_PID_REG PID
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/* MSR definitions */
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#undef _PPC_MSR_POW_U /* power management not supported */
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#undef _PPC_MSR_ILE_U /* little endian mode not supported */
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#undef _PPC_MSR_SF_U /* 64 bit mode not implemented */
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#undef _PPC_MSR_BE /* branch trace not supported */
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#undef _PPC_MSR_IT /* instruction address translation unsupported*/
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#undef _PPC_MSR_DT /* data address translation unsupported */
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#undef _PPC_MSR_RI /* recoverable interrupt unsupported */
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#undef _PPC_MSR_LE /* little endian mode unsupported */
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#undef _PPC_MSR_SE /* single step unsupported */
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#undef _PPC_MSR_PE /* protection enable unsupported */
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#undef _PPC_MSR_PX /* protection exclusive mode unsupported */
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/* PPC405F supports a FPU whereas the PPC405 does not */
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#if (CPU == PPC405)
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#undef _PPC_MSR_FP /* floating point unsupported */
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#undef _PPC_MSR_FE1 /* floating point not supported */
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#undef _PPC_MSR_FE0 /* floating point not supported */
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#endif /* PPC405 */
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#define _PPC_MSR_AP_U 0x0200 /* Auxiliary Processor Unit available */
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#define _PPC_MSR_APE_U 0x0008 /* APU Exception Enable */
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#define _PPC_MSR_WE_U 0x0004 /* wait state enable */
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#define _PPC_MSR_CE_U 0x0002 /* critical interrupt enable */
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#define _PPC_MSR_DWE 0x0400 /* debug wait enable */
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#define _PPC_MSR_DE 0x0200 /* debug exception enable */
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#define _PPC_MSR_IR 0x0020 /* instruction relocate */
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#define _PPC_MSR_DR 0x0010 /* data relocate */
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#define _PPC_MSR_CE 0x00020000 /* critical interrupt enable mask */
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/* MSR bit number definitions */
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#if (CPU == PPC405F)
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#define _PPC_MSR_BIT_FP 18 /* MSR Floating Ponit Aval. bit - FP */
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#define _PPC_MSR_BIT_FE0 20 /* MSR FP exception mode 0 bit - FE0 */
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#define _PPC_MSR_BIT_FE1 23 /* MSR FP exception mode 1 bit - FE1 */
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#endif /* PPC405F */
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#define _PPC_MSR_BIT_AP 6
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#define _PPC_MSR_BIT_APE 12
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#define _PPC_MSR_BIT_WE 13
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#define _PPC_MSR_BIT_CE 14
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#define _PPC_MSR_BIT_DWE 21
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#define _PPC_MSR_BIT_DE 22
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#define _PPC_MSR_BIT_IR 26 /* MSR Inst Translation bit - IR */
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#define _PPC_MSR_BIT_DR 27 /* MSR Data Translation bit - DR */
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/* MSR MMU Bit extraction */
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#define _PPC_MSR_MMU_RI_EXTRACT(src, dst) \
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rlwinm dst, src, 0, _PPC_MSR_BIT_IR, _PPC_MSR_BIT_DR
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/* No FP, so _PPC_MSR_MMU_RI_FP_EXTRACT is the same */
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#define _PPC_MSR_MMU_RI_FP_EXTRACT _PPC_MSR_MMU_RI_EXTRACT
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/* INT_MASK definition (mask EE & CE bits) : overwrite the one in asmPpc.h */
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#undef INT_MASK
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#define INT_MASK(src, des) \
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rlwinm des, src, 0, _PPC_MSR_BIT_EE+1, _PPC_MSR_BIT_EE-1; \
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rlwinm des, des, 0, _PPC_MSR_BIT_CE+1, _PPC_MSR_BIT_CE-1
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/* Special Purpose Registers - General */
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#define SPRG4 276 /* 0x114 */
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#define SPRG5 277 /* 0x115 */
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#define SPRG6 278 /* 0x116 */
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#define SPRG7 279 /* 0x117 */
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/* read-only access to SPRG4-7 */
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#define SPRG4R 0x104 /* Special Purpose General 4 - read only */
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#define SPRG5R 0x105 /* Special Purpose General 5 - read only */
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#define SPRG6R 0x106 /* Special Purpose General 6 - read only */
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#define SPRG7R 0x107 /* Special Purpose General 7 - read only */
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/* Device Control Register PowerPC405 specific */
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#undef DEC /* decrementer not supported */
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/* Special Purpose Register PowerPC405 specific */
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#define CCR0 0x3b3 /* core configuration register r/w */
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#define DAC1 0x3f6 /* data adress compare register 1 r/w */
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#define DAC2 0x3f7 /* data adress compare register 2 r/w */
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#define DBCR0 0x3f2 /* debug control register read/write */
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#define DBCR1 0x3bd /* debug control register read/write */
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#define DBSR 0x3f0 /* debug status register read/clear */
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#define DCCR 0x3fa /* data cache control register r/w */
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#define DCWR 0x3ba /* data cache write-thru register (PPC405GC) r/w */
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#define DVC1 0x3b6 /* Data value compare 1 */
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#define DVC2 0x3b7 /* Data value compare 2 */
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#define DEAR 0x3d5 /* data exception address registers r */
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#define ESR 0x3d4 /* exception syndrom register r/w */
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#define EVPR 0x3d6 /* exception prefix register r/w */
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#define IAC1 0x3f4 /* instruction adress compare register 1 r/w */
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#define IAC2 0x3f5 /* instruction adress compare register 2 r/w */
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#define IAC3 0x3b4 /* instruction adress compare register 3 r/w */
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#define IAC4 0x3b5 /* instruction adress compare register 4 r/w */
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#define ICCR 0x3fb /* instruction cache cacheability register r/w */
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#define ICDBDR 0x3d3 /* instruction cache debug data register r */
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#define PID 0x3b1 /* process id r */
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#define PIT 0x3db /* programmable interval timer r/w */
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#define SGR 0x3b9 /* storage guarded register (PPC405GC) r/w */
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#define SLER 0x3bb /* Storage Little Endian Register */
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#define SRR2 0x3de /* save/restore register 2 r/w */
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#define SRR3 0x3df /* save/restore register 3 r/w */
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#define SU0R 0x3bc /* Storage User Defined 0 Register */
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#define TBLO 0x11c /* time base low r/w */
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#define TBHI 0x11d /* time base high r/w */
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#define TCR 0x3da /* timer control register r/w */
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#define TSR 0x3d8 /* timer status register read/clear */
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#define TSRS 0x3d9 /* timer status register set (set only) */
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#define ZPR 0x3b0 /* zone protection register (PPC405GC/GCX) r/w */
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#define mtdcr(dcrn, rs) .long (0x7c0001c3 | (rs << 21) | (dcrf << 11))
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#define MTDCR 0x7c0001c3
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#define MFDCR 0x7c000143
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/* defines for cache support */
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#define _PPC405_ICCR_DEFAULT_VAL 0x80000001 /* def. inst. cachability */
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#define _PPC405_DCCR_DEFAULT_VAL 0x80000001 /* def. data cachability */
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#define _PPC405_DCWR_DEFAULT_VAL 0x00000000 /* def. data writethru */
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#undef _CPU_CACHE_ALIGN_SIZE
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#define _CPU_CACHE_ALIGN_SIZE 32 /* all 405 cores have 32-byte cache lines */
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#define _PPC405_ICACHE_NWAYS 2 /* all 405 cores have 2-way Icache */
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#define _PPC405_DCACHE_NWAYS 2 /* all 405 cores have 2-way Dcache */
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#define _CACHE_LINE_MASK 0x0000001F
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#define _PPC_CACHE_UNIFIED FALSE
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/*
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* PPC4xx processors encode the L1 cache dimensions in PVR[16-21].
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* See cacheArchLib.c for the encoding.
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*/
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#define _PPC_PVR_CACHE_SIZE_FIELD ((vxPvrGet() >> 10) & 0x03f)
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/* 405 specific special purpose registers */
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#define _PPC405_DBSR 0x3f0 /* debug status register read/clear */
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#define _PPC405_DCCR 0x3fa /* data cache control register r/w */
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#define _PPC405_DEAR 0x3d5 /* data exception address registers r */
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#define _PPC405_ESR 0x3d4 /* exception syndrom register r/w */
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#define _PPC405_EVPR 0x3d6 /* exception prefix register r/w */
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#define _PPC405_ICCR 0x3fb /* instruction cache control register r/w */
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#define _PPC405_PBL1 0x3fc /* protection bound lower 1 r/w */
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#define _PPC405_PBL2 0x3fe /* protection bound lower 2 r/w */
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#define _PPC405_PBU1 0x3fd /* protection bound upper 1 r/w */
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#define _PPC405_PBU2 0x3ff /* protection bound upper 2 r/w */
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#define _PPC405_PIT 0x3db /* programmable interval timer r/w */
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#define _PPC405_SRR2 0x3de /* save/restore register 2 r/w */
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#define _PPC405_SRR3 0x3df /* save/restore register 3 r/w */
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#define _PPC405_SGR 0x3b9 /* storage guarded register (PPC405GC) r/w */
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#define _PPC405_DCWR 0x3ba /* data cache write-thru (PPC405GC)r/w */
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/* debug control register 0 */
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#define _DBCR0_EDM_U 0x8000 /* external debug mode */
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#define _DBCR0_IDM_U 0x4000 /* internal debug mode */
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#define _DBCR0_RST_U 0x3000 /* reset */
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#define _DBCR0_IC_U 0x0800 /* instruction completion debug event */
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#define _DBCR0_BT_U 0x0400 /* branch taken */
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#define _DBCR0_EDE_U 0x0200 /* exception debug event */
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#define _DBCR0_TDE_U 0x0100 /* trap debug event */
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#define _DBCR0_IA1_U 0x0080 /* instruction address compare 1 */
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#define _DBCR0_IA2_U 0x0040 /* instruction address compare 2 */
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#define _DBCR0_IA12_U 0x0020 /* instruction address compare 1:2 */
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#define _DBCR0_IA12X_U 0x0010 /* instruction address compare 1:2 excl. */
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#define _DBCR0_IA3_U 0x0008 /* instruction address compare 3 */
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#define _DBCR0_IA4_U 0x0004 /* instruction address compare 4 */
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#define _DBCR0_IA34_U 0x0002 /* instruction address compare 3:4 */
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#define _DBCR0_IA34X_U 0x0001 /* instruction address compare 3:4 excl. */
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#define _DBCR0_EDM 0x80000000 /* external debug mode */
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#define _DBCR0_IDM 0x40000000 /* internal debug mode */
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#define _DBCR0_RST 0x30000000 /* reset */
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#define _DBCR0_IC 0x08000000 /* instruction completion debug event */
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#define _DBCR0_BT 0x04000000 /* branch taken */
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#define _DBCR0_EDE 0x02000000 /* exception debug event */
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#define _DBCR0_TDE 0x01000000 /* trap debug event */
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#define _DBCR0_IA1 0x00800000 /* instruction address compare 1 */
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#define _DBCR0_IA2 0x00400000 /* instruction address compare 2 */
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#define _DBCR0_IA12 0x00200000 /* instruction address compare 1:2 */
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#define _DBCR0_IA12X 0x00100000 /* instruction address compare 1:2 excl. */
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#define _DBCR0_IA3 0x00080000 /* instruction address compare 3 */
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#define _DBCR0_IA4 0x00040000 /* instruction address compare 4 */
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#define _DBCR0_IA34 0x00020000 /* instruction address compare 3:4 */
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#define _DBCR0_IA34X 0x00010000 /* instruction address compare 3:4 excl. */
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#define _DBCR0_FT 0x00000001 /* freeze timers on debug */
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/* debug control register 1 */
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#define _DBCR1_D1R_U 0x8000 /* data address compare 1 read */
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#define _DBCR1_D2R_U 0x4000 /* data address compare 2 read */
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#define _DBCR1_D1W_U 0x2000 /* data address compare 1 write */
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#define _DBCR1_D2W_U 0x1000 /* data address compare 2 write */
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#define _DBCR1_D1S_U 0x0C00 /* DAC 1 size */
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#define _DBCR1_D2S_U 0x0300 /* DAC 2 size */
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#define _DBCR1_DA12_U 0x0080 /* DA range compare 1:2 */
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#define _DBCR1_DA12X_U 0x0040 /* DA range excl. compare 1:2 */
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#define _DBCR1_DV1M_U 0x000C /* Data value compare 1 mode */
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#define _DBCR1_DV2M_U 0x0003 /* Data value compare 2 mode */
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#define _DBCR1_D1R 0x80000000 /* data address compare 1 read */
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#define _DBCR1_D2R 0x40000000 /* data address compare 2 read */
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#define _DBCR1_D1W 0x20000000 /* data address compare 1 write */
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#define _DBCR1_D2W 0x10000000 /* data address compare 2 write */
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#define _DBCR1_D1S 0x0C000000 /* DAC 1 size */
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#define _DBCR1_D2S 0x03000000 /* DAC 2 size */
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#define _DBCR1_DA12 0x00800000 /* DA range compare 1:2 */
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#define _DBCR1_DA12X 0x00400000 /* DA range excl. compare 1:2 */
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#define _DBCR1_DV1M 0x000C0000 /* Data value compare 1 mode */
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#define _DBCR1_DV2M 0x00030000 /* Data value compare 2 mode */
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#define _DBCR1_DV1BE 0x0000F000 /* Data value compare 1 byte enable */
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#define _DBCR1_DV2BE 0x00000F00 /* Data value compare 2 byte enable */
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/* data access sizes */
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#define _DBCR1_D1S_BYTE 0x00000000 /* byte address */
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#define _DBCR1_D1S_HWORD 0x04000000 /* halfword address */
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#define _DBCR1_D1S_WORD 0x08000000 /* word address */
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#define _DBCR1_D1S_CACHE_LINE 0x0C000000 /* cache line (8-word) addrs. */
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#define _DBCR1_D2S_BYTE 0x00000000 /* byte address */
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#define _DBCR1_D2S_HWORD 0x01000000 /* halfword address */
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#define _DBCR1_D2S_WORD 0x02000000 /* word address */
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#define _DBCR1_D2S_CACHE_LINE 0x03000000 /* cache line (8-word) addrs. */
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/* debug status register */
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#define _DBSR_IC_U 0x8000 /* instruction completion */
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#define _DBSR_BT_U 0x4000 /* branch taken */
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#define _DBSR_EXC_U 0x2000 /* exception debug */
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#define _DBSR_TIE_U 0x1000 /* trap instruction */
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#define _DBSR_UDE_U 0x0800 /* unconditional debug */
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#define _DBSR_IA1_U 0x0400 /* instruction address compare 1 */
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#define _DBSR_IA2_U 0x0200 /* instruction address compare 2 */
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#define _DBSR_DR1_U 0x0100 /* data address compare read 1 */
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#define _DBSR_DW1_U 0x0080 /* data address compare write 1 */
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#define _DBSR_DR2_U 0x0040 /* data address compare read 2 */
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#define _DBSR_DW2_U 0x0020 /* data address compare write 2 */
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#define _DBSR_IDE_U 0x0010 /* imprecise debug */
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#define _DBSR_IA3_U 0x0008 /* instruction address compare 3 */
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#define _DBSR_IA4_U 0x0004 /* instruction address compare 4 */
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#define _DBSR_IC 0x80000000 /* instruction completion */
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#define _DBSR_BT 0x40000000 /* branch taken */
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#define _DBSR_EXC 0x20000000 /* exception debug */
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#define _DBSR_TIE 0x10000000 /* trap instruction */
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#define _DBSR_UDE 0x08000000 /* unconditional debug */
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#define _DBSR_IA1 0x04000000 /* instruction address compare 1 */
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#define _DBSR_IA2 0x02000000 /* instruction address compare 2 */
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#define _DBSR_DR1 0x01000000 /* data address compare read 1 */
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#define _DBSR_DW1 0x00800000 /* data address compare write 1 */
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#define _DBSR_DR2 0x00400000 /* data address compare read 2 */
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#define _DBSR_DW2 0x00200000 /* data address compare write 2 */
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#define _DBSR_IDE 0x00100000 /* imprecise debug */
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#define _DBSR_IA3 0x00080000 /* instruction address compare 3 */
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#define _DBSR_IA4 0x00040000 /* instruction address compare 4 */
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#define _DBSR_MRRM 0x00000300 /* Most recent reset mask */
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#define _DBSR_MRR(n) ((n) << 8) /* Most recent reset */
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/* mask for hardware breakpoints */
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#define _DBSR_HWBP_MSK (_DBSR_IA1 | _DBSR_IA2 | \
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_DBSR_DR1 | _DBSR_DW1 | \
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_DBSR_DR2 | _DBSR_DW2 | \
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_DBSR_IA3 | _DBSR_IA4)
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/* timer control register */
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#define _PPC405_TCR_WPM_U 0xc000 /* watchdog period */
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#define _PPC405_TCR_WRCM_U 0x3000 /* watchdog reset control */
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#define _PPC405_TCR_WIEM_U 0x0800 /* watchdog interrupt enable */
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#define _PPC405_TCR_PIEM_U 0x0400 /* pit interrupt enable */
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#define _PPC405_TCR_FPM_U 0x0300 /* fit period */
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#define _PPC405_TCR_FIEM_U 0x0080 /* fit interrupt enable */
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#define _PPC405_TCR_ARE_U 0x0040 /* fit auto-reload enable */
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/* timer status register */
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#define _PPC405_TSR_SNWM_U 0x8000 /* supress next watchdog */
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#define _PPC405_TSR_WISM_U 0x4000 /* watchdog interrupt status */
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#define _PPC405_TSR_WRSM_U 0x3000 /* watchdog reset status */
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#define _PPC405_TSR_PISM_U 0x0800 /* pit interrupt status */
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#define _PPC405_TSR_FISM_U 0x0400 /* fit interrupt status */
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/* exception syndrome register mask bits:
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* 0 - error not occured 1 - error occured */
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#define _PPC405_ESR_MCI 0x80000000 /* instr machine check occurred */
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#define _PPC405_ESR_PIL 0x08000000 /* program exception - illegal */
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#define _PPC405_ESR_PPR 0x04000000 /* program exception - previledged */
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#define _PPC405_ESR_PTR 0x02000000 /* program exception - trap */
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#define _PPC405_ESR_DST 0x00800000 /* data storage exception - store fault */
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#define _PPC405_ESR_DIZ 0x00400000 /* data/inst storage exception - zone f.*/
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#define _PPC405_ESR_PFP 0x00080000 /* Program exception - FPU */
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#define _PPC405_ESR_U0F 0x00008000 /* data storage exception - U0 fault */
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/* common ESR macros */
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#define _PPC_ESR_MCI _PPC405_ESR_MCI
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#define _PPC_ESR_PIL _PPC405_ESR_PIL
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#define _PPC_ESR_PPR _PPC405_ESR_PPR
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#define _PPC_ESR_PTR _PPC405_ESR_PTR
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#define _PPC_ESR_DST _PPC405_ESR_DST
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#define _PPC_ESR_DIZ _PPC405_ESR_DIZ
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#define _PPC_ESR_PFP _PPC405_ESR_PFP
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#define _PPC_ESR_U0F _PPC405_ESR_U0F
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/* exception vector prefix register */
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#define _PPC405_EVPR_EVPM 0xffff0000 /* exception vector prefix mask */
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/* the following defines are needed by the 403/405 cache library */
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#define _PVR_CONF_403GA 0x0000 /* processor conf. bits for 403GA */
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#define _PVR_CONF_403GC 0x0002 /* processor conf. bits for 403GC */
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#define _PVR_CONF_403GCX 0x0014 /* processor conf. bits for 403GCX */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCppc405h */
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