159 lines
6.5 KiB
C
159 lines
6.5 KiB
C
/* mmu603Lib.h - mmuLib header for PowerPC 603 */
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/* Copyright 1984-2004 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01f,24sep04,zl fixed _MMU_UBAT_BL_MASK.
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01e,29apr02,pcs Add defines for the EXTRA BAT support on MPC755/MPC7455.
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01d,29sep98,fle doc : made it refgen parsable
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01c,12may95,caf removed bogus typedef.
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01b,15aug94,caf revised, changed name to mmu603Lib.h.
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01a,21apr94,yao written.
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*/
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#ifndef _INCmmu603Libh
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#define _INCmmu603Libh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PAGE_SIZE 4096 /* pages are 4K bytes */
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#define _MMU_NUM_IBAT 4 /* 4 instr BAT registers */
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#define _MMU_NUM_DBAT 4 /* 4 data BAT registers */
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#define _MMU_NUM_EXTRA_IBAT 4 /* 4 instr BAT registers */
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#define _MMU_NUM_EXTRA_DBAT 4 /* 4 data BAT registers */
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/* _MMU_UBAT Upper BAT Registers */
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#define _MMU_UBAT_BEPI_MASK 0xfffe0000 /* effective pg index */
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#define _MMU_UBAT_BEPI_SHIFT 17
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#define _MMU_UBAT_BL_MASK 0x0001fffc /* block size */
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#define _MMU_UBAT_BL_SHIFT 2
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#define _MMU_UBAT_BL_128K 0x00000000 /* block size 128K */
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#define _MMU_UBAT_BL_256K 0x00000004 /* block size 256K */
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#define _MMU_UBAT_BL_512K 0x0000000c /* block size 512K */
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#define _MMU_UBAT_BL_1M 0x0000001c /* block size 1M */
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#define _MMU_UBAT_BL_2M 0x0000003c /* block size 2M */
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#define _MMU_UBAT_BL_4M 0x0000007c /* block size 4M */
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#define _MMU_UBAT_BL_8M 0x000000fc /* block size 8M */
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#define _MMU_UBAT_BL_16M 0x000001fc /* block size 16M */
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#define _MMU_UBAT_BL_32M 0x000003fc /* block size 32M */
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#define _MMU_UBAT_BL_64M 0x000007fc /* block size 64M */
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#define _MMU_UBAT_BL_128M 0x00000ffc /* block size 128M */
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#define _MMU_UBAT_BL_256M 0x00001ffc /* block size 256M */
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#define _MMU_UBAT_BL_512M 0x00003ffc /* block size 512M */
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#define _MMU_UBAT_BL_1G 0x00007ffc /* block size 1G */
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#define _MMU_UBAT_BL_2G 0x0000fffc /* block size 2G */
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#define _MMU_UBAT_BL_4G 0x0001fffc /* block size 4G */
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#define _MMU_UBAT_VS 0x00000002 /* supervisor mode valid bit */
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#define _MMU_UBAT_VP 0x00000001 /* user mode valid bit */
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/* _MMU_LBAT Lower BAT Registers */
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#define _MMU_LBAT_BRPN_MASK 0xfffe0000 /* physical block number */
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#define _MMU_LBAT_BRPN_SHIFT 17
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#define _MMU_LBAT_WIMG_MASK 0x00000078 /* memory/cache access mode */
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#define _MMU_LBAT_WIMG_SHIFT 3
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#define _MMU_LBAT_WRITE_THROUGH 0x00000040 /* W - write-through */
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#define _MMU_LBAT_CACHE_INHIBIT 0x00000020 /* I - caching-inhibited */
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#define _MMU_LBAT_MEM_COHERENT 0x00000010 /* M - memory coherence */
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#define _MMU_LBAT_GUARDED 0x00000008 /* G - guarded (DBAT only) */
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#define _MMU_LBAT_PP_MASK 0x00000003 /* protection bits */
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#define _MMU_LBAT_PP_SHIFT 0
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#define _MMU_LBAT_PP_NOACC 0x00000000 /* no access */
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#define _MMU_LBAT_PP_RONLY 0x00000001 /* read (b30 is don't-care) */
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#define _MMU_LBAT_PP_RW 0x00000002 /* read/write */
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#define _MMU_LBAT_PP_SHIFT 0
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#define _MMU_LBAT_PP_NOACC 0x00000000 /* no access */
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#define _MMU_LBAT_BXPN_MASK 0x00000e00 /* Block Extended Physical Page num*/
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/* Bits 0-2 of the physical address*/
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#define _MMU_LBAT_BX_MASK 0x00000004 /* Block Extended Physical Page num*/
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/* Bit 3 of the physical address*/
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#define _MMU_LBAT_BXPN_SHIFT 9
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#define _MMU_LBAT_BX_SHIFT 2
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/* _MMU_SEG Segment Descriptors */
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#define _MMU_SEG_T 0x80000000 /* T=0 for page, T=1 for I/O */
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#define _MMU_SEG_KS 0x40000000 /* sup-state protect (T=0) */
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#define _MMU_SEG_KP 0x20000000 /* user-state protect (T=0) */
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#define _MMU_SEG_N 0x10000000 /* no-execute protect (T=0) */
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#define _MMU_SEG_VSID_MASK 0x00ffffff /* virtual segment ID (T=0) */
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#define _MMU_SEG_VSID_SHIFT 0
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/* _MMU_PTE Page Table Entries */
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#define _MMU_PTE0_V 0x80000000 /* entry valid (v=1) */
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#define _MMU_PTE0_VSID_MASK 0x7fffff80 /* virtual segment ID */
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#define _MMU_PTE0_VSID_SHIFT 7
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#define _MMU_PTE0_H 0x00000040 /* hash function identifier */
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#define _MMU_PTE0_API_MASK 0x00000003 /* abbreviated page index */
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#define _MMU_PTE0_API_SHIFT 0
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#define _MMU_PTE1_RPN_MASK 0xfffff000 /* physical page number */
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#define _MMU_PTE1_RPN_SHIFT 12
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#define _MMU_PTE1_R 0x00000100 /* referenced */
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#define _MMU_PTE1_C 0x00000080 /* changed */
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#define _MMU_PTE1_WIMG_MASK 0x00000078 /* memory/cache access mode */
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#define _MMU_PTE1_WIMG_SHIFT 3
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#define _MMU_PTE1_WRITE_THROUGH 0x00000040 /* W - write-through */
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#define _MMU_PTE1_CACHE_INHIBIT 0x00000020 /* I - caching-inhibited */
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#define _MMU_PTE1_MEM_COHERENT 0x00000010 /* M - memory coherence */
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#define _MMU_PTE1_GUARDED 0x00000008 /* G - guarded */
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#define _MMU_PTE1_PP_MASK 0x00000003 /* page protection */
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#define _MMU_PTE1_PP_SHIFT 0
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#define _MMU_PTE1_PP_00 0x00000000 /* PP bits = 00 */
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#define _MMU_PTE1_PP_01 0x00000001 /* PP bits = 01 */
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#define _MMU_PTE1_PP_10 0x00000002 /* PP bits = 10 */
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#define _MMU_PTE1_PP_11 0x00000003 /* PP bits = 11 */
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#ifndef _ASMLANGUAGE
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS mmu603LibInit (int pageSize);
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#else /* __STDC__ */
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extern STATUS mmu603LibInit ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _INCmmu603Libh */
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