441 lines
19 KiB
C
441 lines
19 KiB
C
/* rm9000.h - PMC-Sierra RM9000 CPU header */
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/* Copyright 2005, 2010 Wind River Systems, Inc. */
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01b,29apr10,pad Moved extern C statement after include statements.
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01a,14apr05,rlg created for yosemite bsp based off of yosemite 5.5 bsp
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*/
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/*
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This file contains I/O addresses and related constants for the
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PMC-Sierra RM9000 CPU core.
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*/
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#ifndef __INCrm9000h
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#define __INCrm9000h
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#include "vxWorks.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Config Register Defines */
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#define RM9000_CFG_K0_CACHE_WRITETHROUGH 0x00000001
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#define RM9000_CFG_K0_CACHE_UNCACHE_BLOCK 0x00000002
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#define RM9000_CFG_K0_CACHE_WRITEBACK 0x00000003
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#define RM9000_CFG_K0_CACHE_COH_WRITEBACK_EXC 0x00000004
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#define RM9000_CFG_K0_CACHE_COH_WRITEBACK 0x00000005
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#define RM9000_CFG_K0_CACHE_UNCACHE_NONBLOCK 0x00000006
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#define RM9000_CFG_K0_CACHE_FAST_PACKET 0x00000007
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#define RM9000_CFG_SEC_CACHE_ENABLE 0x00000008
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/* On Chip Device (OCD) Registers - Base Address */
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#ifndef RM9000x2_OCD_BASE_ADDR
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#define RM9000x2_OCD_BASE_ADDR 0xBB000000
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#endif
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#define RM9000_REG_ADDR(x) (RM9000x2_OCD_BASE_ADDR + x)
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#ifndef _ASMLANGUAGE
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/* rm9000x2 register read and write macros */
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#define RM9000_REG_READ(offset) \
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*(volatile UINT32 *)(RM9000_REG_ADDR(offset))
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#define RM9000_REG_WRITE(offset,regdata) \
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*(volatile UINT32 *)(RM9000_REG_ADDR(offset)) = regdata
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#define RM9K_REG_READ32(offset) \
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*(volatile UINT32 *)(RM9000_REG_ADDR(offset))
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#define RM9K_REG_WRITE32(offset,regdata) \
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*(volatile UINT32 *)(RM9000_REG_ADDR(offset)) = regdata
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#define RM9K_REG_READ16(offset) \
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*(volatile UINT16 *)(RM9000_REG_ADDR(offset))
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#define RM9K_REG_WRITE16(offset,regdata) \
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*(volatile UINT16 *)(RM9000_REG_ADDR(offset)) = regdata
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#define RM9K_REG_READ8(offset) \
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*(volatile UINT8 *)(RM9000_REG_ADDR(offset))
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#define RM9K_REG_WRITE8(offset,regdata) \
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*(volatile UINT8 *)(RM9000_REG_ADDR(offset)) = regdata
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#define RM9K_REG_SET32(offset,regdata) \
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*(volatile UINT32 *)(RM9000_REG_ADDR(offset)) = (*(volatile UINT32 *)(RM9000_REG_ADDR(offset))) | regdata
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#define RM9K_REG_CLEAR32(offset,regdata) \
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*(volatile UINT32 *)(RM9000_REG_ADDR(offset)) = (*(volatile UINT32 *)(RM9000_REG_ADDR(offset))) & ~regdata
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#endif /* _ASMLANGUAGE */
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/* Memory defines */
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#define DRAM_CACHE_VIRT_BASE K0BASE
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#define DRAM_NONCACHE_VIRT_BASE K1BASE
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#define KSU_MASK 0xE0000000 /* Memory window selection bits */
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/* On Chip Device (OCD) Registers */
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#define RM9000x2_OCD_OCDINFO 0x0000
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#define RM9000x2_OCD_XCAUFL 0x0010
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#define RM9000x2_OCD_UPENR 0x00f0 /* Micro Periph Enable */
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#define RM9000x2_OCD_CPURSLMT 0x00f8 /* CPU Resource Limit */
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#define RM9000x2_OCD_LKB0 0x0100 /* Bank 0 Base Addr */
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#define RM9000x2_OCD_LKM0 0x0104 /* Bank 0 Addr Mask */
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#define RM9000x2_OCD_LKB1 0x0108 /* Bank 1 Base Addr */
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#define RM9000x2_OCD_LKM1 0x010C /* Bank 1 Addr Mask */
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#define RM9000x2_OCD_LKB2 0x0110 /* Bank 2 Base Addr */
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#define RM9000x2_OCD_LKM2 0x0114 /* Bank 2 Addr Mask */
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#define RM9000x2_OCD_LKB3 0x0118 /* Bank 3 Base Addr */
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#define RM9000x2_OCD_LKM3 0x011C /* Bank 3 Addr Mask */
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#define RM9000x2_OCD_LKB4 0x0120 /* Bank 4 Base Addr */
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#define RM9000x2_OCD_LKM4 0x0124 /* Bank 4 Addr Mask */
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#define RM9000x2_OCD_LKB5 0x0128 /* Bank 5 Base Addr */
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#define RM9000x2_OCD_LKM5 0x012C /* Bank 5 Addr Mask */
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#define RM9000x2_OCD_LKB6 0x0130 /* Bank 6 Base Addr */
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#define RM9000x2_OCD_LKM6 0x0134 /* Bank 6 Addr Mask */
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#define RM9000x2_OCD_LKB7 0x0138 /* Bank 7 Base Addr */
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#define RM9000x2_OCD_LKM7 0x013C /* Bank 7 Addr Mask */
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#define RM9000x2_OCD_LKB8 0x0140 /* Bank 8 Base Addr */
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#define RM9000x2_OCD_LKM8 0x0144 /* Bank 8 Addr Mask */
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#define RM9000x2_OCD_LKB9 0x0148 /* Bank 9 Base Addr */
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#define RM9000x2_OCD_LKM9 0x014C /* Bank 9 Addr Mask */
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#define RM9000x2_OCD_LKB10 0x0150 /* Bank 10 Base Addr */
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#define RM9000x2_OCD_LKM10 0x0154 /* Bank 10 Addr Mask */
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#define RM9000x2_OCD_LKB11 0x0158 /* Bank 11 Base Addr */
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#define RM9000x2_OCD_LKM11 0x015C /* Bank 11 Addr Mask */
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#define RM9000x2_OCD_LKB12 0x0160 /* Bank 12 Base Addr */
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#define RM9000x2_OCD_LKM12 0x0164 /* Bank 12 Addr Mask */
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#define RM9000x2_OCD_LKB13 0x0168 /* Bank 13 Base Addr */
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#define RM9000x2_OCD_LKM13 0x016C /* Bank 13 Addr Mask */
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#define RM9000x2_OCD_LDP0 0x0200
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#define RM9000x2_OCD_LDP1 0x0210
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#define RM9000x2_OCD_LDP2 0x0220
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#define RM9000x2_OCD_LDP3 0x0230
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#define RM9000x2_OCD_RSTSTATUS 0x0A20 /* Reset Status */
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#define RM9000x2_OCD_RSTSET 0x0A24 /* Reset Set */
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#define RM9000x2_OCD_RSTCLEAR 0x0A28 /* Reset Clear */
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#define RM9000x2_OCD_SEM 0x0A60 /* Semaphore Register */
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#define RM9000x2_OCD_SEMSET 0x0A64 /* Semaphore Set */
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#define RM9000x2_OCD_SEMCLR 0x0A68 /* Semaphore Clear */
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/*
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* MAC subsytem registers
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*/
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/* MAC Subsystem */
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#define RM9000_GE_DEVICE_ID_REG 0x0000
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#define RM9000_GE_RESET 0x0004
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#define RM9000_GE_DLL_STATUS 0x0008
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#define RM9000_TSB_CONTROL_0 0x000c
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#define RM9000_TSB_CONTROL_1 0x0010
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#define RM9000_PRIORITY_CHECKSUM_PORT_0 0x1038
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#define RM9000_PRIORITY_CHECKSUM_PORT_1 0x2038
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#define RM9000_PRIORITY_CHECKSUM_PORT_2 0x3038
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/*
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* SCMB subsystem
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*/
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#define RM9000_SCMB_0_CONTROL 0x0180 /* SCMB 0 Control */
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#define RM9000_SCMB_0_CLKA 0x0184 /* SCMB 0 Clock A */
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#define RM9000_SCMB_0_CLKB 0x0188 /* SCMB 0 Clock B */
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#define RM9000_MDIO_0_COMMAND 0x0190 /* MDIO 0 Command */
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#define RM9000_MDIO_0_DEVICE_PORT_ADDRESS 0x0194 /* MDIO 0 Device and Port addrs */
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#define RM9000_MDIO_0_DATA 0x0198 /* MDIO 0 Data */
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#define RM9000_MDIO_0_INTERRUPTS 0x019c /* MDIO 0 Interrupts */
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#define RM9000_2BI_0_CONFIG 0x01a0 /* 2BI 0 Configuration */
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#define RM9000_2BI_0_COMMAND 0x01a4 /* 2BI 0 Command */
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#define RM9000_2BI_0_ADDRESS 0x01a8 /* 2BI 0 Address */
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#define RM9000_2BI_0_DATA0 0x01ac /* 2BI 0 Data bits 15:0 */
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#define RM9000_2BI_0_DATA1 0x01b0 /* 2BI 0 Data bits 31:16 */
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#define RM9000_2BI_0_DATA2 0x01b4 /* 2BI 0 Data bits 47:32 */
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#define RM9000_2BI_0_DATA3 0x01b8 /* 2BI 0 Data bits 63:48 */
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#define RM9000_2BI_0_INTERRUPTS 0x01bc /* 2BI 0 Interrupts */
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/* RM9000 SDRAM Register Defines */
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#define RM9000_SDRAM_GEN_CONFIG_REG 0x0300
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#define RM9000_SDRAM_MODE_REG 0x0304
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#define RM9000_SDRAM_BANK0_CONFIG_REG 0x0340
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#define RM9000_SDRAM_BANK1_CONFIG_REG 0x0350
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#define RM9000_SDRAM_BANK2_CONFIG_REG 0x0360
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#define RM9000_SDRAM_BANK3_CONFIG_REG 0x0370
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#define RM9000_SDRAM_BANK0_TIMING_REG 0x0344
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#define RM9000_SDRAM_BANK1_TIMING_REG 0x0354
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#define RM9000_SDRAM_BANK2_TIMING_REG 0x0364
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#define RM9000_SDRAM_BANK3_TIMING_REG 0x0374
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/* (PRId) Processor Revision Identifier Register definitions */
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#define RM9000x2_IMP_NUM 0x34 /* RM9000x2 */
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#define RM9000x2_PRID_REV_MASK 0x000000FF
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#define RM9000x2_PRID_REV_SHIFT 0
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#define RM9000x2_PRID_IMP_NUM_MASK 0x0000FF00
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#define RM9000x2_PRID_IMP_NUM_SHIFT 8
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#define RM9000x2_PRID_CPU_NUM_MASK 0x07000000
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#define RM9000x2_PRID_CPU_NUM_SHIFT 24
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/* (UPENR) Microprocessor Peripherals Enable definitions */
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#define RM9000x2_RESET_CONTROL_ENABLE 0x01
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#define RM9000x2_RESET_CONTROL_DISABLE 0x00
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/* (RSTSTATUS, RSTSET, RSTCLEAR) Reset Register definitions */
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#define RM9000x2_RESET_PROC_0 0x01
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#define RM9000x2_RESET_PROC_1 0x02
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#define RM9000x2_RESET_SEC_PROC 0x02 /* reset Secondary Procs */
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/* (SEM, SEMSET, SEMCLR) Semaphore Register definitions */
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#define RM9000_ROM_SEM_BIT 0x00000001 /* sem bit to use by rm9000Init.s */
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/* Cache Defines */
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#define RM9000x2_L2_CACHE_SIZE 0x00040000 /* 256 KBytes */
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#define RM9000x2_L3_CACHE_SIZE 0x00000000 /* No L3 cache */
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#define RM9000x2_CACHE_LINE_SIZE 32
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/* Interrupt Priority Control Register bit defines */
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#define RM9000x2_IPC_VEC_SPACING_MASK 0x0000001F
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#define RM9000x2_IPC_IM15 0x00008000 /* MASK OCD Fault int */
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#define RM9000x2_IPC_IM14 0x00004000 /* MASK OCD Flag int */
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#define RM9000x2_IPC_IM13 0x00002000 /* MASK Perf counter */
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#define RM9000x2_IPC_IM12 0x00001000 /* MASK alt timer int */
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#define RM9000x2_IPC_IM11 0x00000800 /* MASK level 9 int */
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#define RM9000x2_IPC_IM10 0x00000400 /* MASK level 8 int */
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#define RM9000x2_IPC_IM9 0x00000200 /* MASK level 7 int */
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#define RM9000x2_IPC_IM8 0x00000100 /* MASK level 6 int */
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#define RM9000x2_IPC_TIMER_EXCL_IPL12 0x00000080 /* timer on int 12 */
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#define RM9000x2_IPC_IM_MASK 0x0000FF00 /* extended int mask */
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/* External Interrupt Pin (n) Configuration registers */
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#define RM9000x2_EXT_INTPIN0_CONFIG 0x0A40
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#define RM9000x2_EXT_INTPIN1_CONFIG 0x0A44
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#define RM9000x2_EXT_INTPIN2_CONFIG 0x0A48
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#define RM9000x2_EXT_INTPIN3_CONFIG 0x0A4C
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#define RM9000x2_EXT_INTPIN4_CONFIG 0x0A50
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#define RM9000x2_EXT_INTPIN5_CONFIG 0x0A54
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#define RM9000x2_EXT_INTPIN6_CONFIG 0x0A58
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#define RM9000x2_EXT_INTPIN7_CONFIG 0x0A5C
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/* External Interrupt Pin (n) register defines */
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#define RM9000x2_VECTOR_MASK 0x00FF0000 /* level & status bit */
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#define RM9000x2_VECTOR_SHIFT 16
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#define RM9000x2_PROC_INT_MASK 0x00E00000 /* int level */
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#define RM9000x2_PROC_INT_SHIFT 21
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#define RM9000x2_INT_STATUS_BIT_MASK 0x001F0000 /* bit in status reg */
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#define RM9000x2_INT_STATUS_BIT_SHIFT 16
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#define RM9000x2_MESSAGE_TYPE_MASK 0x00000700 /* msg type */
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#define RM9000x2_MESSAGE_TYPE_SHIFT 8
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#define RM9000x2_INTERRUPT_DEST_MASK 0x00000003 /* proc 0 or 1 */
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#define RM9000x2_INTERRUPT_DEST_PROC0 1 /* proc 0 select */
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#define RM9000x2_INTERRUPT_DEST_PROC1 2 /* proc 1 select */
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/* Processor 0 Interrupt Status, Mask, Set and Clear registers */
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#define RM9000x2_INTP0_STATUS_0 0x1B00
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#define RM9000x2_INTP0_MASK_0 0x1B04
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#define RM9000x2_INTP0_SET_0 0x1B08
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#define RM9000x2_INTP0_CLEAR_0 0x1B0C
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#define RM9000x2_INTP0_STATUS_1 0x1B10
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#define RM9000x2_INTP0_MASK_1 0x1B14
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#define RM9000x2_INTP0_SET_1 0x1B18
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#define RM9000x2_INTP0_CLEAR_1 0x1B1C
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#define RM9000x2_INTP0_STATUS_2 0x1B20
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#define RM9000x2_INTP0_MASK_2 0x1B24
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#define RM9000x2_INTP0_SET_2 0x1B28
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#define RM9000x2_INTP0_CLEAR_2 0x1B2C
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#define RM9000x2_INTP0_STATUS_3 0x1B30
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#define RM9000x2_INTP0_MASK_3 0x1B34
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#define RM9000x2_INTP0_SET_3 0x1B38
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#define RM9000x2_INTP0_CLEAR_3 0x1B3C
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#define RM9000x2_INTP0_STATUS_4 0x1B40
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#define RM9000x2_INTP0_MASK_4 0x1B44
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#define RM9000x2_INTP0_SET_4 0x1B48
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#define RM9000x2_INTP0_CLEAR_4 0x1B4C
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#define RM9000x2_INTP0_STATUS_5 0x1B50
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#define RM9000x2_INTP0_MASK_5 0x1B54
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#define RM9000x2_INTP0_SET_5 0x1B58
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#define RM9000x2_INTP0_CLEAR_5 0x1B5C
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#define RM9000x2_INTP0_STATUS_6 0x1B60
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#define RM9000x2_INTP0_MASK_6 0x1B64
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#define RM9000x2_INTP0_SET_6 0x1B68
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#define RM9000x2_INTP0_CLEAR_6 0x1B6C
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#define RM9000x2_INTP0_STATUS_7 0x1B70
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#define RM9000x2_INTP0_MASK_7 0x1B74
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#define RM9000x2_INTP0_SET_7 0x1B78
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#define RM9000x2_INTP0_CLEAR_7 0x1B7C
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/* Processor 1 Interrupt Status, Mask, Set and Clear registers */
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#define RM9000x2_INTP1_STATUS_0 0x2B00
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#define RM9000x2_INTP1_MASK_0 0x2B04
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#define RM9000x2_INTP1_SET_0 0x2B08
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#define RM9000x2_INTP1_CLEAR_0 0x2B0C
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#define RM9000x2_INTP1_STATUS_1 0x2B10
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#define RM9000x2_INTP1_MASK_1 0x2B14
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#define RM9000x2_INTP1_SET_1 0x2B18
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#define RM9000x2_INTP1_CLEAR_1 0x2B1C
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#define RM9000x2_INTP1_STATUS_2 0x2B20
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#define RM9000x2_INTP1_MASK_2 0x2B24
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#define RM9000x2_INTP1_SET_2 0x2B28
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#define RM9000x2_INTP1_CLEAR_2 0x2B2C
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#define RM9000x2_INTP1_STATUS_3 0x2B30
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#define RM9000x2_INTP1_MASK_3 0x2B34
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#define RM9000x2_INTP1_SET_3 0x2B38
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#define RM9000x2_INTP1_CLEAR_3 0x2B3C
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#define RM9000x2_INTP1_STATUS_4 0x2B40
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#define RM9000x2_INTP1_MASK_4 0x2B44
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#define RM9000x2_INTP1_SET_4 0x2B48
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#define RM9000x2_INTP1_CLEAR_4 0x2B4C
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#define RM9000x2_INTP1_STATUS_5 0x2B50
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#define RM9000x2_INTP1_MASK_5 0x2B54
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#define RM9000x2_INTP1_SET_5 0x2B58
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#define RM9000x2_INTP1_CLEAR_5 0x2B5C
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#define RM9000x2_INTP1_STATUS_6 0x2B60
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#define RM9000x2_INTP1_MASK_6 0x2B64
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#define RM9000x2_INTP1_SET_6 0x2B68
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#define RM9000x2_INTP1_CLEAR_6 0x2B6C
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#define RM9000x2_INTP1_STATUS_7 0x2B70
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#define RM9000x2_INTP1_MASK_7 0x2B74
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#define RM9000x2_INTP1_SET_7 0x2B78
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#define RM9000x2_INTP1_CLEAR_7 0x2B7C
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/* base vector number for user programmable vectors */
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/* TLB Defines */
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#undef TLB_ENTRIES
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#define TLB_ENTRIES 64
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#define TLB_4K_PAGE_SIZE_MASK 0x00000000
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#define TLB_16K_PAGE_SIZE_MASK 0x00006000
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#define TLB_64K_PAGE_SIZE_MASK 0x0001E000
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#define TLB_256K_PAGE_SIZE_MASK 0x0007E000
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#define TLB_1M_PAGE_SIZE_MASK 0x001FE000
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#define TLB_4M_PAGE_SIZE_MASK 0x007FE000
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#define TLB_16M_PAGE_SIZE_MASK 0x01FFE000
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#define TLB_64M_PAGE_SIZE_MASK 0x07FFE000
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#define TLB_256M_PAGE_SIZE_MASK 0x1FFFE000
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#define TLB_PG_SVPN 0xfffff000 /* SW page no mask */
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#define TLB_PG_SHIFT 6
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#define TLB_PG_FRAME 0x3fffffc0
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#define TLB_P_ENTRY_SHIFT 12 /* convert VM pagenum to VA */
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#define TLB_PG_G 0x00000001 /* HW */
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#define TLB_PG_V 0x00000002
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#define TLB_PG_NV 0x00000000
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#define TLB_PG_M 0x00000004
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#define TLB_PG_ATTR 0x0000003f
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#define TLB_PG_UNCACHED 0x00000010
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#define TLB_PG_CACHED 0x00000018
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#define TLB_PG_CACHEMODE 0x00000038
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#define TLB_PG_IOPAGE (TLB_PG_G | TLB_PG_V | TLB_PG_M | TLB_PG_UNCACHED)
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#define TLBLO_MODE TLB_PG_IOPAGE
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#define TLBLO_PFNMASK TLB_PG_FRAME
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#define TLBHI_VPN2MASK 0xffffe000
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#define TLBLO_PAGEMASK TLB_256M_PAGE_SIZE_MASK
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#define TLBLO_PAGEMASK_SIZE (TLBLO_PAGEMASK | TLB_PG_IOPAGE | 0x1000)
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#define TLBLO_LO1_OFFSET 0x2000
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/* Interrupt Level bit defines to their respective register */
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/* interrupt priority control register */
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#define INT_LVL_OCD_FAULT SR_IBIT8 /* OCD Fault */
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#define INT_LVL_OCD_FLAG SR_IBIT7 /* OCD Flag (DMA complete) */
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#define INT_LVL_PERF SR_IBIT6 /* Performance Counter */
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#define INT_LVL_ALT_TIMER SR_IBIT5 /* alt timer interrupt */
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#define INT_LVL_EXT_INT_9 SR_IBIT4 /* ext interrupt 9 */
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#define INT_LVL_EXT_INT_8 SR_IBIT3 /* ext interrupt 8 */
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#define INT_LVL_EXT_INT_7 SR_IBIT2 /* ext interrupt 7 */
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#define INT_LVL_EXT_INT_6 SR_IBIT1 /* ext interrupt 6 */
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/* status register bit definitions */
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#define INT_LVL_EXT_INT_5 0x00008000 /* ext interrupt 5 */
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#define INT_LVL_EXT_INT_4 0x00004000 /* ext interrupt 4 */
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#define INT_LVL_EXT_INT_3 0x00002000 /* ext interrupt 3 */
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#define INT_LVL_EXT_INT_2 0x00001000 /* ext interrupt 2 */
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#define INT_LVL_EXT_INT_1 0x00000800 /* ext interrupt 1 */
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#define INT_LVL_EXT_INT_0 0x00000400 /* ext interrupt 0 */
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#define INT_LVL_SW1 0x00000200 /* sw interrupt 1 (fixed) */
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#define INT_LVL_SW0 0x00000100 /* sw interrupt 0 (fixed) */
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/* Exception Vector Table offset values */
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#define RM9000_CPU1_VEC_OFFSET 0x08000000 /* offset for CPU1 Exc Vec Tbl */
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/*
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* RM9000 Interrupt Controller Notes
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* There are 32 interrupt sources for each of the 8 interrupt levels (0-7)
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* SW Interrupts are generated via the set register for the level
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* SW Interrupts are cleared via the clear register for the level
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* (processor 0 registers 0x1B00 - 0x1B7C
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* and Processor 1 registers 0x2B00 - 0x2B7C).
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* One external interrupt can be mapped per interrupt level for the externally
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* generated h/w interrupt.
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*/
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/* and 8 levels internal to rm9000x2 it can set and clear */
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#define RM9000x2_INT_LVLS_INTERNAL 8
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#define RM9000x2_INT_SRCS_INTERNAL 32
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/* Exception Table Defines
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*
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* moved from yosemiteRm9k.h to here
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* this will also work for the jaguuar
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*
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*/
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#define RM9K_CPU1_TLB_EXC_ADDR 0x88000000
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#define RM9K_CPU1_XTLB_EXC_ADDR 0x88000080
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#define RM9K_CPU1_CACHE_EXC_ADDR 0x88000100
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#define RM9K_CPU1_NORM_EXC_ADDR 0x88000180
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/*
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* defines for romInit.s
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* when building bootroms
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*/
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#define RM9K_CONF000 0x00d0
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#define RM9K_CONF032 0x00d4
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#define RM9K_CONF064 0x00d8
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#define RM9K_CONF096 0x00dc
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#define RM9K_CONF128 0x00e0
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#define RM9K_CONF160 0x00e4
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#define RM9K_CONF192 0x00e8
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#define RM9K_CONF224 0x00ec
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCrm9000h */
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