367 lines
14 KiB
C
367 lines
14 KiB
C
/* cavCiu.h - Cavium interrupt controller types and defines */
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/*
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* Copyright (c) 2010-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01k,09dec11,x_f add CIU2 defines for OcteonII CN68xx
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01j,18jul11,rlg adding the type def for ciu_soft_rst - needed for uboot
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control x mods
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01i,10jun11,d_c Restore Cavium headers to original form, before splitting
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struct defs to separate headers
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01h,26oct10,rlg add CAV_CIU_QLM2_T
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01g,20oct10,d_c Include SDK data types directly from SDK
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01f,05oct10,d_c Change ull to ULL to be Diab compatible
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01e,28sep10,d_c change name to be consistent
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01d,19aug10,d_c Revert back original SDK names for copied data types
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01c,13aug10,rlg SDK REMOVAL - add another data struct
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01b,26jul10,rlg additional CIU registers addressing
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01a,15jul10,rlg created.
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*/
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#ifndef __INCvxbMipsCavIntCtlrh
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#define __INCvxbMipsCavIntCtlrh
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#include <arch/mips/private/cavSdkDrvInclude.h>
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#define CAV_INCLUDE_TYPEDEFS_ONLY
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#include CAV_SDK_DRV_INCLUDE(cvmx-abi.h)
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#include CAV_SDK_DRV_INCLUDE(cvmx-ciu-defs.h)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/*
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* ADDRESS DEFINES
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*/
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#define CAV_CIU_BASE_ADDR 0x8001070000000000ULL
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#define CAV_CIU_QLM2_ADDR 0x8001070000000790ULL
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/* INTERRUPT SUMMERY 34 registers chapter 12 of 63xx pdf */
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#define CAV_CIU_INTX_SUM0_OFF 0x0 /* start offset 33 int summery regs */
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#define CAV_CIU_INTX_SUM0_SP 0x8 /* one per core spacing = 0x8 */
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#define CAV_CIU_INT_SUM1_OFF 0x108 /* int summery of device */
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#define CAV_CIU_INT33_SUM0_OFF 0x110 /* extra sum0 reg #34 ??? */
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/* INTERRUPT ENABLE
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* cavium ugly here en0 regs are immediately followed by the
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* en1 regs - hence the addrs will jump by 0x10
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*
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* int0_en0 = ip2 for core 0 0x200
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* int0_en1 = ip2 for core 0 0x208
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* int1_en0 = ip3 for core 0 0x210
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* int1_en1 = ip3 for core 0 0x218
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* ......
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*
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* note maybe want read/write operations to access both registers
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* this way do away with confusing addressing
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*/
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#define CAV_CIU_INTX_EN0_OFF 0x200 /* start offset 34 int enable regs */
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#define CAV_CIU_INTX_EN0_SP 0x10 /* one per core spaceing = 0x10 */
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#define CAV_CIU_INTX_EN1_OFF 0x208 /* start offset 34 int enable regs */
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#define CAV_CIU_INTX_EN1_SP 0x10 /* one per core spaceing = 0x10 */
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/* MAIL BOX REGISTERS */
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#define CAV_CIU_MBOX_SETX_OFF 0x600 /* 16 registers spacing = 0x8 */
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#define CAV_CIU_MBOX_SETX_SP 0x8
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#define CAV_CIU_MBOX_CLRX_OFF 0x680 /* 16 registers spacing = 0x8 */
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#define CAV_CIU_MBOX_CLRX_SP 0x8
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/* Fuse Register Definition */
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#define CAV_CIU_FUSE_OFF 0x728 /* 1 register per box */
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#define CAV_CIU_FUSE_MASK 0x00000000ffffffffULL /* lower 32 bits only */
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/* each bit set implies */
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/* active cpu */
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#if defined (MIPSXX_cav_cn7xxx)
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#define CAV_CIU_FUSE \
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( 0x8001010000000000ULL + (0x1A0))
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#else
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#define CAV_CIU_FUSE \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_FUSE_OFF))
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#endif /* MIPSXX_cav_cn7xxx */
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/* Core Reset Register - 1 register per device */
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#define CAV_CIU_PP_RST_OFF 0x700
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#define CAV_CUI_PP_RST_MASK 0x00000000ffffffffULL
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#if defined (MIPSXX_cav_cn7xxx)
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#define CAV_CIU_PP_RST \
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( 0x8001010000000000ULL + (0x100))
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#else
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#define CAV_CIU_PP_RST \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_PP_RST_OFF))
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#endif /* MIPSXX_cav_cn7xxx */
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/* Core Soft Reset Register - 1 register per device */
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#define CAV_CIU_SOFT_RST_OFF 0x740
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#define CAV_CUI_SOFT_RST_MASK 0x00000000ffffffffULL
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#define CAV_CIU_SOFT_RST \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_SOFT_RST_OFF))
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/* REGISTER Addressing Macros */
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/* INTERRUPT SUMMERY REGISTERS
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* NOTE for all summery registers pass in core number
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* however it is not really required for sum1 or int33_sum0
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* done for consistancy
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*/
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#define CAV_CIU_INTX_SUM0(corenum ) \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_INTX_SUM0_OFF + \
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((corenum) * CAV_CIU_INTX_SUM0_SP)))
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#define CAV_CIU_INT_SUM1 \
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(CAV_CIU_BASE_ADDR + CAV_CIU_INT_SUM1_OFF )
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#define CAV_CIU_INT33_SUM0 \
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(CAV_CIU_BASE_ADDR + CAV_CIU_INT33_SUM0_OFF )
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/* INTERRUPT ENABLE REGISTERS */
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#define CAV_CIU_INTX_EN0(corenum ) \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_INTX_EN0_OFF + \
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((corenum) * CAV_CIU_INTX_EN0_SP)))
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#define CAV_CIU_INTX_EN1(corenum ) \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_INTX_EN1_OFF + \
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((corenum) * CAV_CIU_INTX_EN1_SP)))
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/* MAILBOX REGISTERS */
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#define CAV_CIU_MBOX_SETX(regnum) \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_MBOX_SETX_OFF + \
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((regnum) * CAV_CIU_MBOX_SETX_SP)))
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#define CAV_CIU_MBOX_CLRX(regnum) \
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(CAV_CIU_BASE_ADDR + (CAV_CIU_MBOX_CLRX_OFF + \
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((regnum) * CAV_CIU_MBOX_CLRX_SP)))
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/* BIT MASK AND SHIFT FOR REGISTERS */
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/* INTERRUPT SUMMERY 0 */
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#define CAV_CIU_INTX_SUM0_BOOTDMA_BIT 63
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#define CAV_CIU_INTX_SUM0_BOOTDMA_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_MII_BIT 62
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#define CAV_CIU_INTX_SUM0_MII_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_IPD_BIT 61
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#define CAV_CIU_INTX_SUM0_IPD_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_POWIQ_BIT 60
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#define CAV_CIU_INTX_SUM0_POWIQ_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_TWSI2_BIT 59
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#define CAV_CIU_INTX_SUM0_TWSI2_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_USB_BIT 56
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#define CAV_CIU_INTX_SUM0_USB_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_TIMER_BIT 52
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#define CAV_CIU_INTX_SUM0_TIMER_MASK 0x000000000000000FULL
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#define CAV_CIU_INTX_SUM0_IPDDRP_BIT 50
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#define CAV_CIU_INTX_SUM0_IPDDRP_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_GMSDRP_BIT 48
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#define CAV_CIU_INTX_SUM0_GMSDRP_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_TRACE_BIT 47
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#define CAV_CIU_INTX_SUM0_TRACE_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_RML_BIT 46
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#define CAV_CIU_INTX_SUM0_RML_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_TWSI_BIT 45
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#define CAV_CIU_INTX_SUM0_TWSI_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_WDOG_BIT 44
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#define CAV_CIU_INTX_SUM0_WDOG_MASK 0x0000000000000001ULL
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#define CAV_CIU_INTX_SUM0_PCIMSI_BIT 40
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#define CAV_CIU_INTX_SUM0_PCIMSI_MASK 0x000000000000000FULL
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#define CAV_CIU_INTX_SUM0_PCIINT_BIT 36
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#define CAV_CIU_INTX_SUM0_PCIINT_MASK 0x000000000000000FULL
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#define CAV_CIU_INTX_SUM0_UART_BIT 34
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#define CAV_CIU_INTX_SUM0_UART_MASK 0x0000000000000003ULL
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#define CAV_CIU_INTX_SUM0_MBOX_BIT 32
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#define CAV_CIU_INTX_SUM0_MBOX_MASK 0x0000000000000003ULL
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#define CAV_CIU_INTX_SUM0_GPIO_BIT 16
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#define CAV_CIU_INTX_SUM0_GPIO_MASK 0x000000000000FFFFULL
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#define CAV_CIU_INTX_SUM0_WORKQ_BIT 0
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#define CAV_CIU_INTX_SUM0_WORKQ_MASK 0x000000000000FFFFULL
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/* INTERRUPT SUMMERY 1 */
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#define CAV_CIU_INT_SUM1_RST_BIT 63
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#define CAV_CIU_INT_SUM1_RST_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_DFM_BIT 56
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#define CAV_CIU_INT_SUM1_DFM_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_LMC0_BIT 52
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#define CAV_CIU_INT_SUM1_LMC0_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_SRIO1_BIT 51
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#define CAV_CIU_INT_SUM1_SRIO1_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_SRIO0_BIT 50
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#define CAV_CIU_INT_SUM1_SRIO0_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_PEM1_BIT 49
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#define CAV_CIU_INT_SUM1_PEM1_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_PEM0_BIT 48
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#define CAV_CIU_INT_SUM1_PEM0_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_PTP_BIT 47
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#define CAV_CIU_INT_SUM1_PTP_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_AGL_BIT 46
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#define CAV_CIU_INT_SUM1_AGL_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_AGX0_BIT 36
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#define CAV_CIU_INT_SUM1_AGX0_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_DPI_BIT 35
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#define CAV_CIU_INT_SUM1_DPI_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_SLI_BIT 34
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#define CAV_CIU_INT_SUM1_SLI_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_USB_BIT 33
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#define CAV_CIU_INT_SUM1_USB_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_DFA_BIT 32
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#define CAV_CIU_INT_SUM1_DFA_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_KEY_BIT 31
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#define CAV_CIU_INT_SUM1_KEY_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_RAD_BIT 30
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#define CAV_CIU_INT_SUM1_RAD_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_TIM_BIT 29
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#define CAV_CIU_INT_SUM1_TIM_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_ZIP_BIT 28
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#define CAV_CIU_INT_SUM1_ZIP_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_PKO_BIT 27
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#define CAV_CIU_INT_SUM1_PKO_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_PIP_BIT 26
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#define CAV_CIU_INT_SUM1_PIP_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_IPD_BIT 25
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#define CAV_CIU_INT_SUM1_IPD_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_L2C_BIT 24
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#define CAV_CIU_INT_SUM1_L2C_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_POW_BIT 23
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#define CAV_CIU_INT_SUM1_POW_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_FPA_BIT 22
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#define CAV_CIU_INT_SUM1_FPA_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_IOB_BIT 21
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#define CAV_CIU_INT_SUM1_IOB_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_MIO_BIT 20
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#define CAV_CIU_INT_SUM1_MIO_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_NAND_BIT 19
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#define CAV_CIU_INT_SUM1_NAND_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_MII1_BIT 18
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#define CAV_CIU_INT_SUM1_MII1_MASK 0x0000000000000001ULL
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#define CAV_CIU_INT_SUM1_WDOG_BIT 0
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#define CAV_CIU_INT_SUM1_WDOG_MASK 0x000000000000003FULL
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/* INTERRUPT ENABLE 0 REGISTER */
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#define CAV_CIU_INTX_EN0_BOOTDMA_BIT 63
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#define CAV_CIU_INTX_EN0_MII_BIT 62
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#define CAV_CIU_INTX_EN0_IPD_BIT 61
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#define CAV_CIU_INTX_EN0_POWIQ_BIT 60
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#define CAV_CIU_INTX_EN0_TWSI2_BIT 59
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#define CAV_CIU_INTX_EN0_USB_BIT 56
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#define CAV_CIU_INTX_EN0_TIMER_BIT 52
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#define CAV_CIU_INTX_EN0_IPDDRP_BIT 50
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#define CAV_CIU_INTX_EN0_GMSDRP_BIT 48
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#define CAV_CIU_INTX_EN0_TRACE_BIT 47
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#define CAV_CIU_INTX_EN0_RML_BIT 46
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#define CAV_CIU_INTX_EN0_TWSI_BIT 45
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#define CAV_CIU_INTX_EN_WDOG_BIT 44
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#define CAV_CIU_INTX_EN0_PCIMSI_BIT 40
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#define CAV_CIU_INTX_EN0_PCIINT_BIT 36
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#define CAV_CIU_INTX_EN0_UART_BIT 34
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#define CAV_CIU_INTX_EN0_MBOX_BIT 32
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#define CAV_CIU_INTX_EN0_GPIO_BIT 16
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#define CAV_CIU_INTX_EN0_WORKQ_BIT 0
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/* INTERRUPT ENABLE 1 REGISTER */
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#define CAV_CIU_INT_EN1_RST_BIT 63
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#define CAV_CIU_INT_EN1_DFM_BIT 56
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#define CAV_CIU_INT_EN1_LMC0_BIT 52
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#define CAV_CIU_INT_EN1_SRIO1_BIT 51
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#define CAV_CIU_INT_EN1_SRIO0_BIT 50
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#define CAV_CIU_INT_EN1_PEM1_BIT 49
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#define CAV_CIU_INT_EN1_PEM0_BIT 48
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#define CAV_CIU_INT_EN1_PTP_BIT 47
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#define CAV_CIU_INT_EN1_AGL_BIT 46
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#define CAV_CIU_INT_EN1_AGX0_BIT 36
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#define CAV_CIU_INT_EN1_DPI_BIT 35
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#define CAV_CIU_INT_EN1_SLI_BIT 34
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#define CAV_CIU_INT_EN1_USB_BIT 33
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#define CAV_CIU_INT_EN1_DFA_BIT 32
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#define CAV_CIU_INT_EN1_KEY_BIT 31
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#define CAV_CIU_INT_EN1_RAD_BIT 30
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#define CAV_CIU_INT_EN1_TIM_BIT 29
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#define CAV_CIU_INT_EN1_ZIP_BIT 28
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#define CAV_CIU_INT_EN1_PKO_BIT 27
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#define CAV_CIU_INT_EN1_PIP_BIT 26
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#define CAV_CIU_INT_EN1_IPD_BIT 25
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#define CAV_CIU_INT_EN1_L2C_BIT 24
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#define CAV_CIU_INT_EN1_POW_BIT 23
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#define CAV_CIU_INT_EN1_FPA_BIT 22
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#define CAV_CIU_INT_EN1_IOB_BIT 21
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#define CAV_CIU_INT_EN1_MIO_BIT 20
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#define CAV_CIU_INT_EN1_NAND_BIT 19
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#define CAV_CIU_INT_EN1_MII1_BIT 18
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#define CAV_CIU_INT_EN1_WDOG_BIT 0
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/* Here are Octeon II CIU2 defines */
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#define CAV_CIU2_SUM(core, intLine) \
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(0x8001070100000000ULL + 0x200 * (intLine - 2) + 0x8 * (core))
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#define CAV_CIU2_RAW_PPX_IPX(core, intLine, type) \
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(0x8001070100040000ULL + 0x200000 * (core) + 0x200 * (intLine - 2) + 0x1000 * (type))
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#define CAV_CIU2_SRC_PPX_IPX(core, intLine, type) \
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(0x8001070100080000ULL + 0x200000 * (core) + 0x200 * (intLine - 2) + 0x1000 * (type))
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#define CAV_CIU2_EN_PPX_IPX(core, intLine, type) \
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(0x8001070100090000ULL + 0x200000 * (core) + 0x200 * (intLine - 2) + 0x1000 * (type))
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#define CAV_CIU2_EN_PPX_IPX_W1S(core, intLine, type) \
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(0x80010701000A0000ULL + 0x200000 * (core) + 0x200 * (intLine - 2) + 0x1000 * (type))
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#define CAV_CIU2_EN_PPX_IPX_W1C(core, intLine, type) \
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(0x80010701000B0000ULL + 0x200000 * (core) + 0x200 * (intLine - 2) + 0x1000 * (type))
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#define CAV_CIU2_ACK(core, intLine) \
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(0x80010701000C0000ULL + 0x200000 * (core) + 0x200 * (intLine - 2))
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#define CAV_CIU2_MBOX_SETX(regnum) \
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(0x8001070100100400ull + (((regnum) & 0x1F) * CAV_CIU_MBOX_SETX_SP))
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#define CAV_CIU2_MBOX_CLRX(regnum) \
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(0x8001070100100600ull + (((regnum) & 0x1F) * CAV_CIU_MBOX_CLRX_SP))
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#define CAV_CIU2_INTR_CIU_READY (0x8001070100102008ull)
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#define CAV_CIU2_NUM_INT_PER_TYPE 64
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#define CAV_CIU2_NUM_INT_TYPES 9
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#define CAV_CIU2_TYPE_WRKQ 0
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#define CAV_CIU2_TYPE_WDOG 1
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#define CAV_CIU2_TYPE_RML 2
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#define CAV_CIU2_TYPE_MIO 3
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#define CAV_CIU2_TYPE_IO 4
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#define CAV_CIU2_TYPE_MEM 5
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#define CAV_CIU2_TYPE_PKT 6
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#define CAV_CIU2_TYPE_GPIO 7
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#define CAV_CIU2_TYPE_MBOX 8
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#define CAV_CIU2_IP2 2
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#define CAV_CIU2_IP3 3
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#define CAV_CIU2_IP4 4
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#define CAV_CIU2_SUM_MBOX0 60
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#define CAV_CIU2_SUM_MBOX1 61
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#define CAV_CIU2_SUM_MBOX2 62
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#define CAV_CIU2_SUM_MBOX3 63
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/* typedefs */
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typedef cvmx_ciu_pp_rst_t CAV_CIU_PP_RST_T;
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typedef cvmx_ciu_mbox_setx_t CAV_CIU_MBOX_T;
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typedef cvmx_ciu_qlm2_t CAV_CIU_QLM2_T;
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typedef cvmx_ciu_soft_rst_t CAV_CIU_SOFT_RST_T;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbMipsIntCtlrSPh */
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