67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/* m8260Clock - Motorola MPC8260 Clock header file */
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/* Copyright 1984-1999 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,12sep99,ms_ created from m8260Cpm.h, 01d.
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*/
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/*
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* This file contains constants for the clock block in the Motorola
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* MPC8260 PowerQUICC II integrated Communications Processor
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*/
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#ifndef __INCm8260Clockh
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#define __INCm8260Clockh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef M8260ABBREVIATIONS
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#define M8260ABBREVIATIONS
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
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typedef volatile INT32 VINT32; /* volatile unsigned word */
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typedef volatile INT16 VINT16; /* volatile unsigned halfword */
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typedef volatile INT8 VINT8; /* volatile unsigned byte */
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
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typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#endif /* M8260ABBREVIATIONS */
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/*
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* MPC8260 internal register/memory map (section 17 of prelim. spec)
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* note that these are offsets from the value stored in the IMMR
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* register. Also note that in the MPC8260, the IMMR is not a special
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* purpose register, but it is memory mapped.
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*/
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/* System Clock Control Register */
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#define M8260_SCCR(base) (CAST(VUINT32 *)((base) + 0x10c80))
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/* System Clock Control Register bit definition (SCCR - 0x10c80) */
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#define M8260_SCCR_RES_MSK 0xfffffff8 /* reserved field Mask */
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#define M8260_SCCR_CPM_LOW 0x00000004 /* CPM and SIU low power */
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#define M8260_SCCR_DFBRG_4 0x00000000 /* divide by 4 */
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#define M8260_SCCR_DFBRG_16 0x00000001 /* divide by 16 */
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#define M8260_SCCR_DFBRG_64 0x00000002 /* divide by 64 */
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#define M8260_SCCR_DFBRG_128 0x00000003 /* divide by 128 */
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#define M8260_SCCR_TBS 0x02000000 /* Time Base Source */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCm8260Clockh */
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