467 lines
16 KiB
C
467 lines
16 KiB
C
/* nvr4131.h - NEC NVR4131 header file */
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/* Copyright 2002 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,20jun02,sru Added constants for cache control (SPR 78924).
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01b,12mar02,sru added VR4131_PCICLKSEL_DIV_3 and VR4131_PCIDMACTRLREG.
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01a,10oct01,sru created, based upon nvr4122.h
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*/
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/*
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DESCRIPTION
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This file contains constants for the NEC Vr4131. Register address
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definitions for the various subsystems are provided, and some (but
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not all) register field definitions are provided.
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*/
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#ifndef __INCnvr4131h
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#define __INCnvr4131h
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#include "vxWorks.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* VR4131 cache sizes */
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#define VR4131_ICACHE_SIZE 16384
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#define VR4131_DCACHE_SIZE 16384
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/* VR4131 cache line configuration (config bits in C0_CONFIG) */
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#define VR4131_ICACHE_LINE_32_MASK (1 << 5)
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#define VR4131_DCACHE_LINE_32_MASK (1 << 4)
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#define VR4131_CACHE_LINE_SIZE_16 16
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#define VR4131_CACHE_LINE_SIZE_32 32
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/* VR4131 register definitions. */
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#define VR4131_REG_BASE (0x0f000000+K1BASE)
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#ifdef _ASMLANGUAGE
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#define VR4131_REG32(reg) (VR4131_REG_BASE + (reg))
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#define VR4131_REG16(reg) (VR4131_REG_BASE + (reg))
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#define VR4131_REG8(reg) (VR4131_REG_BASE + (reg))
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#else
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#define VR4131_REG32(reg) ((volatile UINT32 *)(VR4131_REG_BASE + (reg)))
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#define VR4131_REG16(reg) ((volatile UINT16 *)(VR4131_REG_BASE + (reg)))
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#define VR4131_REG8(reg) ((volatile UINT8 *)(VR4131_REG_BASE + (reg)))
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#endif /* _ASMLANGUAGE */
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/* BCU registers */
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#define VR4131_BCUCNTREG1 VR4131_REG16(0x00)
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#define VR4131_ROMSIZEREG VR4131_REG16(0x04)
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#define VR4131_ROMSPEEDREG VR4131_REG16(0x06)
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#define VR4131_IO0SPEEDREG VR4131_REG16(0x08)
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#define VR4131_IO1SPEEDREG VR4131_REG16(0x0a)
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#define VR4131_REVIDREG VR4131_REG16(0x10)
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#define VR4131_CLKSPEEDREG VR4131_REG16(0x14)
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#define VR4131_BCUCNTREG3 VR4131_REG16(0x16)
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#define VR4131_BCUCACHECNTREG VR4131_REG16(0x18)
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/* BCUCNTREG1 bit definitions */
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#define VR4131_PAGESIZE 0x3000
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#define VR4131_PAGEROM2 0x0400
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#define VR4131_PAGEROM0 0x0100
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#define VR4131_ROMWEN2 0x0040
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#define VR4131_ROMWEN0 0x0010
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/* DMAAU registers */
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#define VR4131_CSIIBALREG VR4131_REG16(0x20)
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#define VR4131_CSIIBAHREG VR4131_REG16(0x22)
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#define VR4131_CSIIALREG VR4131_REG16(0x24)
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#define VR4131_CSIIAHREG VR4131_REG16(0x26)
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#define VR4131_CSIOBALREG VR4131_REG16(0x28)
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#define VR4131_CSIOBAHREG VR4131_REG16(0x2a)
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#define VR4131_CSIOALREG VR4131_REG16(0x2c)
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#define VR4131_CSIOAHREG VR4131_REG16(0x2e)
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#define VR4131_FIRBALREG VR4131_REG16(0x30)
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#define VR4131_FIRBAHREG VR4131_REG16(0x32)
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#define VR4131_FIRALREG VR4131_REG16(0x34)
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#define VR4131_FIRAHREG VR4131_REG16(0x36)
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#define VR4131_RAMBALREG VR4131_REG16(0x1e0)
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#define VR4131_RAMBAHREG VR4131_REG16(0x1e2)
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#define VR4131_RAMALREG VR4131_REG16(0x1e4)
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#define VR4131_RAMAHREG VR4131_REG16(0x1e6)
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#define VR4131_IOBALREG VR4131_REG16(0x1e8)
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#define VR4131_IOBAHREG VR4131_REG16(0x1ea)
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#define VR4131_IOALREG VR4131_REG16(0x1ec)
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#define VR4131_IOAHREG VR4131_REG16(0x1ee)
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/* DCU registers */
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#define VR4131_DMARSTREG VR4131_REG16(0x40)
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#define VR4131_DMAIDLEREG VR4131_REG16(0x42)
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#define VR4131_DMASENREG VR4131_REG16(0x44)
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#define VR4131_DMAMSKREG VR4131_REG16(0x46)
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#define VR4131_DMAREQREG VR4131_REG16(0x48)
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#define VR4131_TDREG VR4131_REG16(0x4a)
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#define VR4131_DMAABITREG VR4131_REG16(0x4c)
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#define VR4131_CONTROLREG VR4131_REG16(0x4e)
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#define VR4131_BASSCNTLREG VR4131_REG16(0x50)
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#define VR4131_BASSCNTHREG VR4131_REG16(0x52)
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#define VR4131_CURRENTCNTLREG VR4131_REG16(0x54)
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#define VR4131_CURRENTCNTHREG VR4131_REG16(0x56)
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#define VR4131_TCINTR VR4131_REG16(0x58)
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/* DMA mask bit definitions */
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#define VR4131_DMAMSKAIOR 0x0008
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#define VR4131_DMAMSKCOUT 0x0004
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#define VR4131_DMAMSKCIN 0x0002
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#define VR4131_DMAMSKFOUT 0x0001
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/* CMU register */
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#define VR4131_CMUCLKMSK VR4131_REG16(0x60)
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#define VR4131_MSKPCIU 0x2080
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#define VR4131_MSKSCSI 0x1000
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#define VR4131_MSKDSIU 0x0800
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#define VR4131_MSKFFIR 0x0400
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#define VR4131_MSKSSIU 0x0100
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#define VR4131_MSKCSI 0x0040
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#define VR4131_MSKFIR 0x0010
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#define VR4131_MSKSIU 0x0002
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/* ICU system and system mask registers */
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#define VR4131_SYSINT1REG VR4131_REG16(0x80)
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#define VR4131_GIUINTLREG VR4131_REG16(0x88)
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#define VR4131_DSIUINTREG VR4131_REG16(0x8a)
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#define VR4131_MSYSINT1REG VR4131_REG16(0x8c)
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#define VR4131_MGIUINTLREG VR4131_REG16(0x94)
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#define VR4131_MDSIUINTREG VR4131_REG16(0x96)
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#define VR4131_NMIREG VR4131_REG16(0x98)
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#define VR4131_SOFTINTREG VR4131_REG16(0x9a)
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#define VR4131_SYSINT2REG VR4131_REG16(0xa0)
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#define VR4131_GIUINTHREG VR4131_REG16(0xa2)
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#define VR4131_FIRINTREG VR4131_REG16(0xa4)
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#define VR4131_MSYSINT2REG VR4131_REG16(0xa6)
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#define VR4131_MGIUINTHREG VR4131_REG16(0xa8)
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#define VR4131_MFIRINTREG VR4131_REG16(0xaa)
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#define VR4131_PCIINTREG VR4131_REG16(0xac)
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#define VR4131_SCUINTREG VR4131_REG16(0xae)
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#define VR4131_CSIINTREG VR4131_REG16(0xb0)
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#define VR4131_MPCIINTREG VR4131_REG16(0xb2)
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#define VR4131_MSCUINTREG VR4131_REG16(0xb4)
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#define VR4131_MCSIINTREG VR4131_REG16(0xb6)
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#define VR4131_BCUINTREG VR4131_REG16(0xb8)
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#define VR4131_MBCUINTREG VR4131_REG16(0xba)
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#define VR4131_CLKRUNINTR 0x1000
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#define VR4131_SOFTINTR 0x0800
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#define VR4131_SIUINTR 0x0200
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#define VR4131_GIUINTR 0x0100
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#define VR4131_ETIMERINTR 0x0008
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#define VR4131_RTCL1INTR 0x0004
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#define VR4131_POWERINTR 0x0002
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#define VR4131_BATINTR 0x0001
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#define VR4131_BCUINTR 0x0200
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#define VR4131_CSIINTR 0x0100
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#define VR4131_SCUINTR 0x0080
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#define VR4131_PCIINTR 0x0040
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#define VR4131_DSIUINTR 0x0020
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#define VR4131_FIRINTR 0x0010
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#define VR4131_TCLKINTR 0x0008
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#define VR4131_LEDINTR 0x0002
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#define VR4131_RTCL2INTR 0x0001
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/* PMU registers */
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#define VR4131_PMUINTREG VR4131_REG16(0xc0)
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#define VR4131_PMUCNTREG VR4131_REG16(0xc2)
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#define VR4131_PMUINT2REG VR4131_REG16(0xc4)
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#define VR4131_PMUCNT2REG VR4131_REG16(0xc6)
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#define VR4131_PMUWAITREG VR4131_REG16(0xc8)
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#define VR4131_PMUTCLKDIVREG VR4131_REG16(0xcc)
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#define VR4131_PMUINTRCLKDIVREG VR4131_REG16(0xce)
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#define VR4131_HALTIMERRST 0x0004
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/* RTC registers */
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#define VR4131_ETIMELREG VR4131_REG16(0x100)
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#define VR4131_ETIMEMREG VR4131_REG16(0x102)
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#define VR4131_ETIMEHREG VR4131_REG16(0x104)
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#define VR4131_ECMPLREG VR4131_REG16(0x108)
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#define VR4131_ECMPMREG VR4131_REG16(0x10a)
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#define VR4131_ECMPHREG VR4131_REG16(0x10c)
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#define VR4131_RTCL1LREG VR4131_REG16(0x110)
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#define VR4131_RTCL1HREG VR4131_REG16(0x112)
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#define VR4131_RTCL1CNTLREG VR4131_REG16(0x114)
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#define VR4131_RTCL1CNTHREG VR4131_REG16(0x116)
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#define VR4131_RTCL2LREG VR4131_REG16(0x118)
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#define VR4131_RTCL2HREG VR4131_REG16(0x11a)
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#define VR4131_RTCL2CNTLREG VR4131_REG16(0x11c)
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#define VR4131_RTCL2CNTHREG VR4131_REG16(0x11e)
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#define VR4131_TCLKLREG VR4131_REG16(0x120)
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#define VR4131_TCLKHREG VR4131_REG16(0x122)
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#define VR4131_TCLKCNTLREG VR4131_REG16(0x124)
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#define VR4131_TCLKCNTHREG VR4131_REG16(0x126)
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#define VR4131_RTCINTREG VR4131_REG16(0x13e)
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#define VR4131_RTCINTR0 0x0001
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#define VR4131_RTCINTR1 0x0002
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#define VR4131_RTCINTR2 0x0004
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#define VR4131_RTCINTR3 0x0008
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/*
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* The VR4131 RTC module has identical functionality to the VR4102
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* RTC module. In order to use the nvr4102RTCTimer.c driver, we must
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* define the VR4102_... constants in terms of the VR4131 values.
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*/
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#define VR4102_ETIMELREG VR4131_ETIMELREG
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#define VR4102_ETIMEMRE VR4131_ETIMEMRE
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#define VR4102_ETIMEHREG VR4131_ETIMEHREG
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#define VR4102_ECMPLREG VR4131_ECMPLREG
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#define VR4102_ECMPMREG VR4131_ECMPMREG
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#define VR4102_ECMPHREG VR4131_ECMPHREG
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#define VR4102_RTCL1LREG VR4131_RTCL1LREG
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#define VR4102_RTCL1HREG VR4131_RTCL1HREG
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#define VR4102_RTCL1CNTLREG VR4131_RTCL1CNTLREG
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#define VR4102_RTCL1CNTHREG VR4131_RTCL1CNTHREG
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#define VR4102_RTCL2LREG VR4131_RTCL2LREG
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#define VR4102_RTCL2HREG VR4131_RTCL2HREG
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#define VR4102_RTCL2CNTLREG VR4131_RTCL2CNTLREG
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#define VR4102_RTCL2CNTHREG VR4131_RTCL2CNTHREG
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#define VR4102_TCLKLREG VR4131_TCLKLREG
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#define VR4102_TCLKHREG VR4131_TCLKHREG
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#define VR4102_TCLKCNTLREG VR4131_TCLKCNTLREG
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#define VR4102_TCLKCNTHREG VR4131_TCLKCNTHREG
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#define VR4102_RTCINTREG VR4131_RTCINTREG
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#define VR4102_RTC_RTCINTR0 VR4131_RTCINTR0
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#define VR4102_RTC_RTCINTR1 VR4131_RTCINTR1
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#define VR4102_RTC_RTCINTR2 VR4131_RTCINTR2
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#define VR4102_RTC_RTCINTR3 VR4131_RTCINTR3
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#define VR4102_RTCL1INTR VR4131_RTCL1INTR
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#define VR4102_RTCL2INTR VR4131_RTCL2INTR
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#define VR4102_ICU_MSYSINT1REG VR4131_MSYSINT1REG
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/* GIU registers */
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#define VR4131_GIUIOSELL VR4131_REG16(0x140)
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#define VR4131_GIUIOSELH VR4131_REG16(0x142)
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#define VR4131_GIUPIODL VR4131_REG16(0x144)
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#define VR4131_GIUPIODH VR4131_REG16(0x146)
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#define VR4131_GIUINTSTATL VR4131_REG16(0x148)
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#define VR4131_GIUINTSTATH VR4131_REG16(0x14a)
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#define VR4131_GIUINTENL VR4131_REG16(0x14c)
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#define VR4131_GIUINTENH VR4131_REG16(0x14e)
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#define VR4131_GIUINTTYPL VR4131_REG16(0x150)
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#define VR4131_GIUINTTYPH VR4131_REG16(0x152)
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#define VR4131_GIUINTALSELL VR4131_REG16(0x154)
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#define VR4131_GIUINTALSELH VR4131_REG16(0x156)
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#define VR4131_GIUINTHTSELL VR4131_REG16(0x158)
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#define VR4131_GIUINTHTSELH VR4131_REG16(0x15a)
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#define VR4131_GIUPODATEN VR4131_REG16(0x15c)
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#define VR4131_GIUPODATL VR4131_REG16(0x15e)
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/*
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* The general-purpose I/O pins (GPIO) are enabled and controlled via
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* identically placed bits in the GIU registers and some of the ICU
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* registers. This set of pin masks can be used with whichever registers
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* contain GPIO pin configuration.
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*/
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#define VR4131_GPIO_PIN_31 0x8000
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#define VR4131_GPIO_PIN_30 0x4000
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#define VR4131_GPIO_PIN_29 0x2000
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#define VR4131_GPIO_PIN_28 0x1000
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#define VR4131_GPIO_PIN_27 0x0800
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#define VR4131_GPIO_PIN_26 0x0400
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#define VR4131_GPIO_PIN_25 0x0200
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#define VR4131_GPIO_PIN_24 0x0100
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#define VR4131_GPIO_PIN_23 0x0080
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#define VR4131_GPIO_PIN_22 0x0040
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#define VR4131_GPIO_PIN_21 0x0020
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#define VR4131_GPIO_PIN_20 0x0010
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#define VR4131_GPIO_PIN_19 0x0008
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#define VR4131_GPIO_PIN_18 0x0004
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#define VR4131_GPIO_PIN_17 0x0002
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#define VR4131_GPIO_PIN_16 0x0001
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#define VR4131_GPIO_PIN_15 0x8000
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#define VR4131_GPIO_PIN_14 0x4000
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#define VR4131_GPIO_PIN_13 0x2000
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#define VR4131_GPIO_PIN_12 0x1000
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#define VR4131_GPIO_PIN_11 0x0800
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#define VR4131_GPIO_PIN_10 0x0400
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#define VR4131_GPIO_PIN_9 0x0200
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#define VR4131_GPIO_PIN_8 0x0100
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#define VR4131_GPIO_PIN_7 0x0080
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#define VR4131_GPIO_PIN_6 0x0040
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#define VR4131_GPIO_PIN_5 0x0020
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#define VR4131_GPIO_PIN_4 0x0010
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#define VR4131_GPIO_PIN_3 0x0008
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#define VR4131_GPIO_PIN_2 0x0004
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#define VR4131_GPIO_PIN_1 0x0002
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#define VR4131_GPIO_PIN_0 0x0001
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/* SCI registers */
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#define VR4131_TIMOUTCNTREG VR4131_REG16(0x1000)
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#define VR4131_TIMOUTCOUNTREG VR4131_REG16(0x1002)
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#define VR4131_ERRLADDRESSREG VR4131_REG16(0x1004)
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#define VR4131_ERRHADDRESSREG VR4131_REG16(0x1006)
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#define VR4131_SCUINTRREG VR4131_REG16(0x1008)
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/* SDRAMU registers */
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#define VR4131_SDRAMMODEREG VR4131_REG16(0x400)
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#define VR4131_SDRAMCNTREG VR4131_REG16(0x402)
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#define VR4131_BCURFCNTREG VR4131_REG16(0x404)
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#define VR4131_BCURFCOUNTREG VR4131_REG16(0x406)
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#define VR4131_RAMSIZEREG VR4131_REG16(0x408)
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/* PCIU registers */
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#define VR4131_PCIMMAW1REG VR4131_REG32(0xc00)
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#define VR4131_PCIMMAW2REG VR4131_REG32(0xc04)
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#define VR4131_PCITAW1REG VR4131_REG32(0xc08)
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#define VR4131_PCITAW2REG VR4131_REG32(0xc0c)
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#define VR4131_PCIMIOAWREG VR4131_REG32(0xc10)
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#define VR4131_PCICONFDREG VR4131_REG32(0xc14)
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#define VR4131_PCICONFAREG VR4131_REG32(0xc18)
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#define VR4131_PCIMAILREG VR4131_REG32(0xc1c)
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#define VR4131_BUSERRADREG VR4131_REG32(0xc24)
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#define VR4131_INTCNTSTAREG VR4131_REG32(0xc28)
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#define VR4131_PCIEXACCREG VR4131_REG32(0xc2c)
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#define VR4131_PCIRECONTREG VR4131_REG32(0xc30)
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#define VR4131_PCIENREG VR4131_REG32(0xc34)
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#define VR4131_PCICLKSELREG VR4131_REG32(0xc38)
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#define VR4131_PCITRDYVREG VR4131_REG32(0xc3c)
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#define VR4131_PCICLKRUNREG VR4131_REG16(0xc60)
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#define VR4131_PCIDMACTRLREG VR4131_REG32(0xc80)
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#define VR4131_PCICLKSEL_DIV_1 0x2
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#define VR4131_PCICLKSEL_DIV_2 0x0
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#define VR4131_PCICLKSEL_DIV_3 0x3
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#define VR4131_PCICLKSEL_DIV_4 0x1
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#define VR4131_PCICONFIGDONE 0x00000004 /* PCIENREG */
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#define VR4131_PCICLKRUN 0x0001 /* PCICLKRUNREG */
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#define VR4131_PCISTOPEN 0x8000 /* PCICLKRUNREG */
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#define VR4131_PCIIBA 0xFF000000 /* PCIM*AW*REG */
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#define VR4131_PCIMSK 0x000FE000 /* PCIM*AW*REG, PCITAWnREG */
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#define VR4131_PCIWINEN 0x00001000 /* PCIM*AW*REG, PCITAWnREG */
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#define VR4131_PCIPCIA 0x000000FF /* PCIM*AW*REG */
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#define VR4131_PCIITA 0x000007FF /* PCITAWnREG */
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/* PCI Config Registers */
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#define VR4131_PCICONF_IDENT VR4131_REG32(0xd00)
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#define VR4131_PCICONF_CMDSR VR4131_REG32(0xd04)
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#define VR4131_PCICONF_REVCLASS VR4131_REG32(0xd08)
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#define VR4131_PCICONF_CACHELAT VR4131_REG32(0xd0c)
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#define VR4131_PCICONF_MAILBA VR4131_REG32(0xd10)
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#define VR4131_PCICONF_PCIMBA1 VR4131_REG32(0xd14)
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#define VR4131_PCICONF_PCIMBA2 VR4131_REG32(0xd18)
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#define VR4131_PCICONF_PCIINT VR4131_REG32(0xd3c)
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#define VR4131_PCICONF_RETVAL VR4131_REG32(0xd40)
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/* DSIU registers */
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#define VR4131_DSIURB VR4131_REG8(0x820) /* SUILC7 = 0, read */
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#define VR4131_DSIUTH VR4131_REG8(0x820) /* SUILC7 = 0, write */
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#define VR4131_DSIUDLL VR4131_REG8(0x820) /* SUILC7 = 1 */
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#define VR4131_DSIUIE VR4131_REG8(0x821) /* SUILC7 = 0 */
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#define VR4131_DSIUDLM VR4131_REG8(0x821) /* SUILC7 = 1 */
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#define VR4131_DSIUIID VR4131_REG8(0x822) /* read */
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#define VR4131_DSIUFC VR4131_REG8(0x822) /* write */
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#define VR4131_DSIULC VR4131_REG8(0x823)
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#define VR4131_DSIUMC VR4131_REG8(0x824)
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#define VR4131_DSIULS VR4131_REG8(0x825)
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#define VR4131_DSIUMS VR4131_REG8(0x826)
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#define VR4131_DSIUSC VR4131_REG8(0x827)
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#define VR4131_DSIURESET VR4131_SIURESET /* Common with SIU */
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#define VR4131_DSIU_BASE VR4131_DSIURB
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#define VR4131_DSIU_DELTA 1
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#define VR4131_DSIU_XTAL 18432000 /* crystal input to 16550 */
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#define VR4131_DSIURST 0x0002 /* in SIURESET register */
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/* LED registers */
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#define VR4131_LEDHTSREG VR4131_REG16(0x180)
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#define VR4131_LEDLTSREG VR4131_REG16(0x182)
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#define VR4131_LEDCNTREG VR4131_REG16(0x188)
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#define VR4131_LEDASTCREG VR4131_REG16(0x18a)
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#define VR4131_LEDINTREG VR4131_REG16(0x18c)
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/* SIU registers */
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#define VR4131_SIURB VR4131_REG8(0x800) /* SUILC7 = 0, read */
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#define VR4131_SIUTH VR4131_REG8(0x800) /* SUILC7 = 0, write */
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#define VR4131_SIUDLL VR4131_REG8(0x800) /* SUILC7 = 1 */
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#define VR4131_SIUIE VR4131_REG8(0x801) /* SUILC7 = 0 */
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#define VR4131_SIUDLM VR4131_REG8(0x801) /* SUILC7 = 1 */
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#define VR4131_SIUIID VR4131_REG8(0x802) /* read */
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#define VR4131_SIUFC VR4131_REG8(0x802) /* write */
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#define VR4131_SIULC VR4131_REG8(0x803)
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#define VR4131_SIUMC VR4131_REG8(0x804)
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#define VR4131_SIULS VR4131_REG8(0x805)
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#define VR4131_SIUMS VR4131_REG8(0x806)
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#define VR4131_SIUSC VR4131_REG8(0x807)
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#define VR4131_SIUIRSEL VR4131_REG8(0x808)
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#define VR4131_SIURESET VR4131_REG8(0x809) /* common with DSIU */
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#define VR4131_SIUCSEL VR4131_REG8(0x80a)
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#define VR4131_SIU_BASE VR4131_SIURB
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#define VR4131_SIU_DELTA 1
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#define VR4131_SIU_XTAL 18432000 /* crystal input to 16550 */
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#define VR4131_SIURST 0x0001 /* in SIURESET register */
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/* CSI registers */
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#define VR4131_CSI_MODEREG VR4131_REG16(0x1a0)
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#define VR4131_CSI_CLKSELREG VR4131_REG16(0x1a1)
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#define VR4131_CSI_SIRBREG VR4131_REG16(0x1a2)
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#define VR4131_CSI_SOTBREG VR4131_REG16(0x1a4)
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#define VR4131_CSI_SIRBEREG VR4131_REG16(0x1a6)
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#define VR4131_CSI_SOTBFREG VR4131_REG16(0x1a8)
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#define VR4131_CSI_SIOREG VR4131_REG16(0x1aa)
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#define VR4131_CSI_CNTREG VR4131_REG16(0x1b0)
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#define VR4131_CSI_INTREG VR4131_REG16(0x1b2)
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#define VR4131_CSI_IFIFOVREG VR4131_REG16(0x1b4)
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#define VR4131_CSI_OFIFOVREG VR4131_REG16(0x1b6)
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#define VR4131_CSI_IFIFOREG VR4131_REG16(0x1b8)
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#define VR4131_CSI_OFIFOREG VR4131_REG16(0x1ba)
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#define VR4131_CSI_FIFOTRGREG VR4131_REG16(0x1bc)
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/* FIR registers - not included */
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/* Clock rate values for different settings of CLKSEL[2:0] pins/jumpers. */
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#define CPU_PCLOCK_RATE_111 200700000
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#define CPU_PCLOCK_RATE_110 180600000
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#define CPU_PCLOCK_RATE_101 164200000
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#define CPU_PCLOCK_RATE_100 150500000
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#define CPU_PCLOCK_RATE_011 129000000
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#define CPU_PCLOCK_RATE_010 100400000
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#define CPU_PCLOCK_RATE_001 90300000
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#define CPU_PCLOCK_RATE_000 78500000
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/* Miscellaneous */
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#define NUM_4131_TTY 2 /* SIU + DSIU */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCnvr4131h */
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