457 lines
16 KiB
C
457 lines
16 KiB
C
/* nvr4122.h - NEC NVR4122 header file */
|
|
|
|
/* Copyright 1984-2001 Wind River Systems, Inc. */
|
|
|
|
/*
|
|
modification history
|
|
--------------------
|
|
01c,17apr01,sru update after code review
|
|
01b,09apr01,sru cleanup after code review
|
|
01a,05jan01,sru fix cache sizes
|
|
01a,03jan01,sru created.
|
|
*/
|
|
|
|
/*
|
|
DESCRIPTION
|
|
This file contains constants for the NEC VR4122. Register address
|
|
definitions for the various subsystems are provided, and some (but
|
|
not all) register field definitions are provided.
|
|
*/
|
|
|
|
#ifndef __INCnvr4122h
|
|
#define __INCnvr4122h
|
|
|
|
#include "vxWorks.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define VR4122_ICACHE_SIZE 32768
|
|
#define VR4122_DCACHE_SIZE 16384
|
|
|
|
/* VR4122 register definitions. */
|
|
|
|
#define VR4122_REG_BASE (0x0f000000+K1BASE)
|
|
|
|
#ifdef _ASMLANGUAGE
|
|
#define VR4122_REG32(reg) (VR4122_REG_BASE + (reg))
|
|
#define VR4122_REG16(reg) (VR4122_REG_BASE + (reg))
|
|
#define VR4122_REG8(reg) (VR4122_REG_BASE + (reg))
|
|
#else
|
|
#define VR4122_REG32(reg) ((volatile UINT32 *)(VR4122_REG_BASE + (reg)))
|
|
#define VR4122_REG16(reg) ((volatile UINT16 *)(VR4122_REG_BASE + (reg)))
|
|
#define VR4122_REG8(reg) ((volatile UINT8 *)(VR4122_REG_BASE + (reg)))
|
|
#endif /* _ASMLANGUAGE */
|
|
|
|
/* BCU registers */
|
|
|
|
#define VR4122_BCUCNTREG1 VR4122_REG16(0x00)
|
|
#define VR4122_ROMSIZEREG VR4122_REG16(0x04)
|
|
#define VR4122_ROMSPEEDREG VR4122_REG16(0x06)
|
|
#define VR4122_IO0SPEEDREG VR4122_REG16(0x08)
|
|
#define VR4122_IO1SPEEDREG VR4122_REG16(0x0a)
|
|
#define VR4122_REVIDREG VR4122_REG16(0x10)
|
|
#define VR4122_CLKSPEEDREG VR4122_REG16(0x14)
|
|
#define VR4122_BCUCNTREG3 VR4122_REG16(0x16)
|
|
#define VR4122_BCUCACHECNTREG VR4122_REG16(0x18)
|
|
|
|
|
|
/* BCUCNTREG1 bit definitions */
|
|
|
|
#define VR4122_PAGESIZE 0x3000
|
|
#define VR4122_PAGEROM2 0x0400
|
|
#define VR4122_PAGEROM0 0x0100
|
|
#define VR4122_ROMWEN2 0x0040
|
|
#define VR4122_ROMWEN0 0x0010
|
|
|
|
/* DMAAU registers */
|
|
|
|
#define VR4122_CSIIBALREG VR4122_REG16(0x20)
|
|
#define VR4122_CSIIBAHREG VR4122_REG16(0x22)
|
|
#define VR4122_CSIIALREG VR4122_REG16(0x24)
|
|
#define VR4122_CSIIAHREG VR4122_REG16(0x26)
|
|
#define VR4122_CSIOBALREG VR4122_REG16(0x28)
|
|
#define VR4122_CSIOBAHREG VR4122_REG16(0x2a)
|
|
#define VR4122_CSIOALREG VR4122_REG16(0x2c)
|
|
#define VR4122_CSIOAHREG VR4122_REG16(0x2e)
|
|
#define VR4122_FIRBALREG VR4122_REG16(0x30)
|
|
#define VR4122_FIRBAHREG VR4122_REG16(0x32)
|
|
#define VR4122_FIRALREG VR4122_REG16(0x34)
|
|
#define VR4122_FIRAHREG VR4122_REG16(0x36)
|
|
#define VR4122_RAMBALREG VR4122_REG16(0x1e0)
|
|
#define VR4122_RAMBAHREG VR4122_REG16(0x1e2)
|
|
#define VR4122_RAMALREG VR4122_REG16(0x1e4)
|
|
#define VR4122_RAMAHREG VR4122_REG16(0x1e6)
|
|
#define VR4122_IOBALREG VR4122_REG16(0x1e8)
|
|
#define VR4122_IOBAHREG VR4122_REG16(0x1ea)
|
|
#define VR4122_IOALREG VR4122_REG16(0x1ec)
|
|
#define VR4122_IOAHREG VR4122_REG16(0x1ee)
|
|
|
|
/* DCU registers */
|
|
|
|
#define VR4122_DMARSTREG VR4122_REG16(0x40)
|
|
#define VR4122_DMAIDLEREG VR4122_REG16(0x42)
|
|
#define VR4122_DMASENREG VR4122_REG16(0x44)
|
|
#define VR4122_DMAMSKREG VR4122_REG16(0x46)
|
|
#define VR4122_DMAREQREG VR4122_REG16(0x48)
|
|
#define VR4122_TDREG VR4122_REG16(0x4a)
|
|
#define VR4122_DMAABITREG VR4122_REG16(0x4c)
|
|
#define VR4122_CONTROLREG VR4122_REG16(0x4e)
|
|
#define VR4122_BASSCNTLREG VR4122_REG16(0x50)
|
|
#define VR4122_BASSCNTHREG VR4122_REG16(0x52)
|
|
#define VR4122_CURRENTCNTLREG VR4122_REG16(0x54)
|
|
#define VR4122_CURRENTCNTHREG VR4122_REG16(0x56)
|
|
#define VR4122_TCINTR VR4122_REG16(0x58)
|
|
|
|
/* DMA mask bit definitions */
|
|
|
|
#define VR4122_DMAMSKAIOR 0x0008
|
|
#define VR4122_DMAMSKCOUT 0x0004
|
|
#define VR4122_DMAMSKCIN 0x0002
|
|
#define VR4122_DMAMSKFOUT 0x0001
|
|
|
|
/* CMU register */
|
|
|
|
#define VR4122_CMUCLKMSK VR4122_REG16(0x60)
|
|
|
|
#define VR4122_MSKPCIU 0x2000
|
|
#define VR4122_MSKSCSI 0x1000
|
|
#define VR4122_MSKDSIU 0x0800
|
|
#define VR4122_MSKFFIR 0x0400
|
|
#define VR4122_MSKSSIU 0x0100
|
|
#define VR4122_MSKCSI 0x0040
|
|
#define VR4122_MSKFIR 0x0010
|
|
#define VR4122_MSKSIU 0x0002
|
|
|
|
/* ICU system and system mask registers */
|
|
|
|
#define VR4122_SYSINT1REG VR4122_REG16(0x80)
|
|
#define VR4122_GIUINTLREG VR4122_REG16(0x88)
|
|
#define VR4122_DSIUINTREG VR4122_REG16(0x8a)
|
|
#define VR4122_MSYSINT1REG VR4122_REG16(0x8c)
|
|
#define VR4122_MGIUINTLREG VR4122_REG16(0x94)
|
|
#define VR4122_MDSIUINTREG VR4122_REG16(0x96)
|
|
#define VR4122_NMIREG VR4122_REG16(0x98)
|
|
#define VR4122_SOFTINTREG VR4122_REG16(0x9a)
|
|
#define VR4122_SYSINT2REG VR4122_REG16(0xa0)
|
|
#define VR4122_GIUINTHREG VR4122_REG16(0xa2)
|
|
#define VR4122_FIRINTREG VR4122_REG16(0xa4)
|
|
#define VR4122_MSYSINT2REG VR4122_REG16(0xa6)
|
|
#define VR4122_MGIUINTHREG VR4122_REG16(0xa8)
|
|
#define VR4122_MFIRINTREG VR4122_REG16(0xaa)
|
|
#define VR4122_PCIINTREG VR4122_REG16(0xac)
|
|
#define VR4122_SCUINTREG VR4122_REG16(0xae)
|
|
#define VR4122_CSIINTREG VR4122_REG16(0xb0)
|
|
#define VR4122_MPCIINTREG VR4122_REG16(0xb2)
|
|
#define VR4122_MSCUINTREG VR4122_REG16(0xb4)
|
|
#define VR4122_MCSIINTREG VR4122_REG16(0xb6)
|
|
#define VR4122_BCUINTREG VR4122_REG16(0xb8)
|
|
#define VR4122_MBCUINTREG VR4122_REG16(0xba)
|
|
|
|
#define VR4122_CLKRUNINTR 0x1000
|
|
#define VR4122_SOFTINTR 0x0800
|
|
#define VR4122_SIUINTR 0x0200
|
|
#define VR4122_GIUINTR 0x0100
|
|
#define VR4122_ETIMERINTR 0x0008
|
|
#define VR4122_RTCL1INTR 0x0004
|
|
#define VR4122_POWERINTR 0x0002
|
|
#define VR4122_BATINTR 0x0001
|
|
|
|
#define VR4122_BCUINTR 0x0200
|
|
#define VR4122_CSIINTR 0x0100
|
|
#define VR4122_SCUINTR 0x0080
|
|
#define VR4122_PCIINTR 0x0040
|
|
#define VR4122_DSIUINTR 0x0020
|
|
#define VR4122_FIRINTR 0x0010
|
|
#define VR4122_TCLKINTR 0x0008
|
|
#define VR4122_LEDINTR 0x0002
|
|
#define VR4122_RTCL2INTR 0x0001
|
|
|
|
/* PMU registers */
|
|
|
|
#define VR4122_PMUINTREG VR4122_REG16(0xc0)
|
|
#define VR4122_PMUCNTREG VR4122_REG16(0xc2)
|
|
#define VR4122_PMUINT2REG VR4122_REG16(0xc4)
|
|
#define VR4122_PMUCNT2REG VR4122_REG16(0xc6)
|
|
#define VR4122_PMUWAITREG VR4122_REG16(0xc8)
|
|
#define VR4122_PMUTCLKDIVREG VR4122_REG16(0xcc)
|
|
#define VR4122_PMUINTRCLKDIVREG VR4122_REG16(0xce)
|
|
|
|
#define VR4122_HALTIMERRST 0x0004
|
|
|
|
/* RTC registers */
|
|
|
|
#define VR4122_ETIMELREG VR4122_REG16(0x100)
|
|
#define VR4122_ETIMEMREG VR4122_REG16(0x102)
|
|
#define VR4122_ETIMEHREG VR4122_REG16(0x104)
|
|
#define VR4122_ECMPLREG VR4122_REG16(0x108)
|
|
#define VR4122_ECMPMREG VR4122_REG16(0x10a)
|
|
#define VR4122_ECMPHREG VR4122_REG16(0x10c)
|
|
#define VR4122_RTCL1LREG VR4122_REG16(0x110)
|
|
#define VR4122_RTCL1HREG VR4122_REG16(0x112)
|
|
#define VR4122_RTCL1CNTLREG VR4122_REG16(0x114)
|
|
#define VR4122_RTCL1CNTHREG VR4122_REG16(0x116)
|
|
#define VR4122_RTCL2LREG VR4122_REG16(0x118)
|
|
#define VR4122_RTCL2HREG VR4122_REG16(0x11a)
|
|
#define VR4122_RTCL2CNTLREG VR4122_REG16(0x11c)
|
|
#define VR4122_RTCL2CNTHREG VR4122_REG16(0x11e)
|
|
#define VR4122_TCLKLREG VR4122_REG16(0x120)
|
|
#define VR4122_TCLKHREG VR4122_REG16(0x122)
|
|
#define VR4122_TCLKCNTLREG VR4122_REG16(0x124)
|
|
#define VR4122_TCLKCNTHREG VR4122_REG16(0x126)
|
|
#define VR4122_RTCINTREG VR4122_REG16(0x13e)
|
|
|
|
#define VR4122_RTCINTR0 0x0001
|
|
#define VR4122_RTCINTR1 0x0002
|
|
#define VR4122_RTCINTR2 0x0004
|
|
#define VR4122_RTCINTR3 0x0008
|
|
|
|
/*
|
|
* The VR4122 RTC module has identical functionality to the VR4102
|
|
* RTC module. In order to use the nvr4102RTCTimer.c driver, we must
|
|
* define the VR4102_... constants in terms of the VR4122 values.
|
|
*/
|
|
|
|
#define VR4102_ETIMELREG VR4122_ETIMELREG
|
|
#define VR4102_ETIMEMRE VR4122_ETIMEMRE
|
|
#define VR4102_ETIMEHREG VR4122_ETIMEHREG
|
|
#define VR4102_ECMPLREG VR4122_ECMPLREG
|
|
#define VR4102_ECMPMREG VR4122_ECMPMREG
|
|
#define VR4102_ECMPHREG VR4122_ECMPHREG
|
|
#define VR4102_RTCL1LREG VR4122_RTCL1LREG
|
|
#define VR4102_RTCL1HREG VR4122_RTCL1HREG
|
|
#define VR4102_RTCL1CNTLREG VR4122_RTCL1CNTLREG
|
|
#define VR4102_RTCL1CNTHREG VR4122_RTCL1CNTHREG
|
|
#define VR4102_RTCL2LREG VR4122_RTCL2LREG
|
|
#define VR4102_RTCL2HREG VR4122_RTCL2HREG
|
|
#define VR4102_RTCL2CNTLREG VR4122_RTCL2CNTLREG
|
|
#define VR4102_RTCL2CNTHREG VR4122_RTCL2CNTHREG
|
|
#define VR4102_TCLKLREG VR4122_TCLKLREG
|
|
#define VR4102_TCLKHREG VR4122_TCLKHREG
|
|
#define VR4102_TCLKCNTLREG VR4122_TCLKCNTLREG
|
|
#define VR4102_TCLKCNTHREG VR4122_TCLKCNTHREG
|
|
#define VR4102_RTCINTREG VR4122_RTCINTREG
|
|
#define VR4102_RTC_RTCINTR0 VR4122_RTCINTR0
|
|
#define VR4102_RTC_RTCINTR1 VR4122_RTCINTR1
|
|
#define VR4102_RTC_RTCINTR2 VR4122_RTCINTR2
|
|
#define VR4102_RTC_RTCINTR3 VR4122_RTCINTR3
|
|
|
|
#define VR4102_RTCL1INTR VR4122_RTCL1INTR
|
|
#define VR4102_RTCL2INTR VR4122_RTCL2INTR
|
|
|
|
#define VR4102_ICU_MSYSINT1REG VR4122_MSYSINT1REG
|
|
|
|
/* GIU registers */
|
|
|
|
#define VR4122_GIUIOSELL VR4122_REG16(0x140)
|
|
#define VR4122_GIUIOSELH VR4122_REG16(0x142)
|
|
#define VR4122_GIUPIODL VR4122_REG16(0x144)
|
|
#define VR4122_GIUPIODH VR4122_REG16(0x146)
|
|
#define VR4122_GIUINTSTATL VR4122_REG16(0x148)
|
|
#define VR4122_GIUINTSTATH VR4122_REG16(0x14a)
|
|
#define VR4122_GIUINTENL VR4122_REG16(0x14c)
|
|
#define VR4122_GIUINTENH VR4122_REG16(0x14e)
|
|
#define VR4122_GIUINTTYPL VR4122_REG16(0x150)
|
|
#define VR4122_GIUINTTYPH VR4122_REG16(0x152)
|
|
#define VR4122_GIUINTALSELL VR4122_REG16(0x154)
|
|
#define VR4122_GIUINTALSELH VR4122_REG16(0x156)
|
|
#define VR4122_GIUINTHTSELL VR4122_REG16(0x158)
|
|
#define VR4122_GIUINTHTSELH VR4122_REG16(0x15a)
|
|
#define VR4122_GIUPODATEN VR4122_REG16(0x15c)
|
|
#define VR4122_GIUPODATL VR4122_REG16(0x15e)
|
|
|
|
/*
|
|
* The general-purpose I/O pins (GPIO) are enabled and controlled via
|
|
* identically placed bits in the GIU registers and some of the ICU
|
|
* registers. This set of pin masks can be used with whichever registers
|
|
* contain GPIO pin configuration.
|
|
*/
|
|
|
|
#define VR4122_GPIO_PIN_31 0x8000
|
|
#define VR4122_GPIO_PIN_30 0x4000
|
|
#define VR4122_GPIO_PIN_29 0x2000
|
|
#define VR4122_GPIO_PIN_28 0x1000
|
|
#define VR4122_GPIO_PIN_27 0x0800
|
|
#define VR4122_GPIO_PIN_26 0x0400
|
|
#define VR4122_GPIO_PIN_25 0x0200
|
|
#define VR4122_GPIO_PIN_24 0x0100
|
|
#define VR4122_GPIO_PIN_23 0x0080
|
|
#define VR4122_GPIO_PIN_22 0x0040
|
|
#define VR4122_GPIO_PIN_21 0x0020
|
|
#define VR4122_GPIO_PIN_20 0x0010
|
|
#define VR4122_GPIO_PIN_19 0x0008
|
|
#define VR4122_GPIO_PIN_18 0x0004
|
|
#define VR4122_GPIO_PIN_17 0x0002
|
|
#define VR4122_GPIO_PIN_16 0x0001
|
|
#define VR4122_GPIO_PIN_15 0x8000
|
|
#define VR4122_GPIO_PIN_14 0x4000
|
|
#define VR4122_GPIO_PIN_13 0x2000
|
|
#define VR4122_GPIO_PIN_12 0x1000
|
|
#define VR4122_GPIO_PIN_11 0x0800
|
|
#define VR4122_GPIO_PIN_10 0x0400
|
|
#define VR4122_GPIO_PIN_9 0x0200
|
|
#define VR4122_GPIO_PIN_8 0x0100
|
|
#define VR4122_GPIO_PIN_7 0x0080
|
|
#define VR4122_GPIO_PIN_6 0x0040
|
|
#define VR4122_GPIO_PIN_5 0x0020
|
|
#define VR4122_GPIO_PIN_4 0x0010
|
|
#define VR4122_GPIO_PIN_3 0x0008
|
|
#define VR4122_GPIO_PIN_2 0x0004
|
|
#define VR4122_GPIO_PIN_1 0x0002
|
|
#define VR4122_GPIO_PIN_0 0x0001
|
|
|
|
/* SCI registers */
|
|
|
|
#define VR4122_TIMOUTCNTREG VR4122_REG16(0x1000)
|
|
#define VR4122_TIMOUTCOUNTREG VR4122_REG16(0x1002)
|
|
#define VR4122_ERRLADDRESSREG VR4122_REG16(0x1004)
|
|
#define VR4122_ERRHADDRESSREG VR4122_REG16(0x1006)
|
|
#define VR4122_SCUINTRREG VR4122_REG16(0x1008)
|
|
|
|
/* SDRAMU registers */
|
|
|
|
#define VR4122_SDRAMMODEREG VR4122_REG16(0x400)
|
|
#define VR4122_SDRAMCNTREG VR4122_REG16(0x402)
|
|
#define VR4122_BCURFCNTREG VR4122_REG16(0x404)
|
|
#define VR4122_BCURFCOUNTREG VR4122_REG16(0x406)
|
|
#define VR4122_RAMSIZEREG VR4122_REG16(0x408)
|
|
|
|
/* PCIU registers */
|
|
|
|
#define VR4122_PCIMMAW1REG VR4122_REG32(0xc00)
|
|
#define VR4122_PCIMMAW2REG VR4122_REG32(0xc04)
|
|
#define VR4122_PCITAW1REG VR4122_REG32(0xc08)
|
|
#define VR4122_PCITAW2REG VR4122_REG32(0xc0c)
|
|
#define VR4122_PCIMIOAWREG VR4122_REG32(0xc10)
|
|
#define VR4122_PCICONFDREG VR4122_REG32(0xc14)
|
|
#define VR4122_PCICONFAREG VR4122_REG32(0xc18)
|
|
#define VR4122_PCIMAILREG VR4122_REG32(0xc1c)
|
|
#define VR4122_BUSERRADREG VR4122_REG32(0xc24)
|
|
#define VR4122_INTCNTSTAREG VR4122_REG32(0xc28)
|
|
#define VR4122_PCIEXACCREG VR4122_REG32(0xc2c)
|
|
#define VR4122_PCIRECONTREG VR4122_REG32(0xc30)
|
|
#define VR4122_PCIENREG VR4122_REG32(0xc34)
|
|
#define VR4122_PCICLKSELREG VR4122_REG32(0xc38)
|
|
#define VR4122_PCITRDYVREG VR4122_REG32(0xc3c)
|
|
#define VR4122_PCICLKRUNREG VR4122_REG16(0xc60)
|
|
|
|
#define VR4122_PCICLKSEL_DIV_1 0x2
|
|
#define VR4122_PCICLKSEL_DIV_2 0x0
|
|
#define VR4122_PCICLKSEL_DIV_4 0x1
|
|
|
|
#define VR4122_PCICONFIGDONE 0x00000004 /* PCIENREG */
|
|
#define VR4122_PCICLKRUN 0x0001 /* PCICLKRUNREG */
|
|
#define VR4122_PCISTOPEN 0x8000 /* PCICLKRUNREG */
|
|
#define VR4122_PCIIBA 0xFF000000 /* PCIM*AW*REG */
|
|
#define VR4122_PCIMSK 0x000FE000 /* PCIM*AW*REG, PCITAWnREG */
|
|
#define VR4122_PCIWINEN 0x00001000 /* PCIM*AW*REG, PCITAWnREG */
|
|
#define VR4122_PCIPCIA 0x000000FF /* PCIM*AW*REG */
|
|
#define VR4122_PCIITA 0x000007FF /* PCITAWnREG */
|
|
|
|
/* PCI Config Registers */
|
|
|
|
#define VR4122_PCICONF_IDENT VR4122_REG32(0xd00)
|
|
#define VR4122_PCICONF_CMDSR VR4122_REG32(0xd04)
|
|
#define VR4122_PCICONF_REVCLASS VR4122_REG32(0xd08)
|
|
#define VR4122_PCICONF_CACHELAT VR4122_REG32(0xd0c)
|
|
#define VR4122_PCICONF_MAILBA VR4122_REG32(0xd10)
|
|
#define VR4122_PCICONF_PCIMBA1 VR4122_REG32(0xd14)
|
|
#define VR4122_PCICONF_PCIMBA2 VR4122_REG32(0xd18)
|
|
#define VR4122_PCICONF_PCIINT VR4122_REG32(0xd3c)
|
|
#define VR4122_PCICONF_RETVAL VR4122_REG32(0xd40)
|
|
|
|
/* DSIU registers */
|
|
|
|
#define VR4122_DSIURB VR4122_REG8(0x820) /* SUILC7 = 0, read */
|
|
#define VR4122_DSIUTH VR4122_REG8(0x820) /* SUILC7 = 0, write */
|
|
#define VR4122_DSIUDLL VR4122_REG8(0x820) /* SUILC7 = 1 */
|
|
#define VR4122_DSIUIE VR4122_REG8(0x821) /* SUILC7 = 0 */
|
|
#define VR4122_DSIUDLM VR4122_REG8(0x821) /* SUILC7 = 1 */
|
|
#define VR4122_DSIUIID VR4122_REG8(0x822) /* read */
|
|
#define VR4122_DSIUFC VR4122_REG8(0x822) /* write */
|
|
#define VR4122_DSIULC VR4122_REG8(0x823)
|
|
#define VR4122_DSIUMC VR4122_REG8(0x824)
|
|
#define VR4122_DSIULS VR4122_REG8(0x825)
|
|
#define VR4122_DSIUMS VR4122_REG8(0x826)
|
|
#define VR4122_DSIUSC VR4122_REG8(0x827)
|
|
#define VR4122_DSIURESET VR4122_SIURESET /* Common with SIU */
|
|
|
|
#define VR4122_DSIU_BASE VR4122_DSIURB
|
|
#define VR4122_DSIU_DELTA 1
|
|
#define VR4122_DSIU_XTAL 18432000 /* crystal input to 16550 */
|
|
|
|
#define VR4122_DSIURST 0x0002 /* in SIURESET register */
|
|
|
|
/* LED registers */
|
|
|
|
#define VR4122_LEDHTSREG VR4122_REG16(0x180)
|
|
#define VR4122_LEDLTSREG VR4122_REG16(0x182)
|
|
#define VR4122_LEDCNTREG VR4122_REG16(0x188)
|
|
#define VR4122_LEDASTCREG VR4122_REG16(0x18a)
|
|
#define VR4122_LEDINTREG VR4122_REG16(0x18c)
|
|
|
|
/* SIU registers */
|
|
|
|
#define VR4122_SIURB VR4122_REG8(0x800) /* SUILC7 = 0, read */
|
|
#define VR4122_SIUTH VR4122_REG8(0x800) /* SUILC7 = 0, write */
|
|
#define VR4122_SIUDLL VR4122_REG8(0x800) /* SUILC7 = 1 */
|
|
#define VR4122_SIUIE VR4122_REG8(0x801) /* SUILC7 = 0 */
|
|
#define VR4122_SIUDLM VR4122_REG8(0x801) /* SUILC7 = 1 */
|
|
#define VR4122_SIUIID VR4122_REG8(0x802) /* read */
|
|
#define VR4122_SIUFC VR4122_REG8(0x802) /* write */
|
|
#define VR4122_SIULC VR4122_REG8(0x803)
|
|
#define VR4122_SIUMC VR4122_REG8(0x804)
|
|
#define VR4122_SIULS VR4122_REG8(0x805)
|
|
#define VR4122_SIUMS VR4122_REG8(0x806)
|
|
#define VR4122_SIUSC VR4122_REG8(0x807)
|
|
#define VR4122_SIUIRSEL VR4122_REG8(0x808)
|
|
#define VR4122_SIURESET VR4122_REG8(0x809) /* common with DSIU */
|
|
#define VR4122_SIUCSEL VR4122_REG8(0x80a)
|
|
|
|
#define VR4122_SIU_BASE VR4122_SIURB
|
|
#define VR4122_SIU_DELTA 1
|
|
#define VR4122_SIU_XTAL 18432000 /* crystal input to 16550 */
|
|
|
|
#define VR4122_SIURST 0x0001 /* in SIURESET register */
|
|
|
|
/* CSI registers */
|
|
|
|
#define VR4122_CSI_MODEREG VR4122_REG16(0x1a0)
|
|
#define VR4122_CSI_CLKSELREG VR4122_REG16(0x1a1)
|
|
#define VR4122_CSI_SIRBREG VR4122_REG16(0x1a2)
|
|
#define VR4122_CSI_SOTBREG VR4122_REG16(0x1a4)
|
|
#define VR4122_CSI_SIRBEREG VR4122_REG16(0x1a6)
|
|
#define VR4122_CSI_SOTBFREG VR4122_REG16(0x1a8)
|
|
#define VR4122_CSI_SIOREG VR4122_REG16(0x1aa)
|
|
#define VR4122_CSI_CNTREG VR4122_REG16(0x1b0)
|
|
#define VR4122_CSI_INTREG VR4122_REG16(0x1b2)
|
|
#define VR4122_CSI_IFIFOVREG VR4122_REG16(0x1b4)
|
|
#define VR4122_CSI_OFIFOVREG VR4122_REG16(0x1b6)
|
|
#define VR4122_CSI_IFIFOREG VR4122_REG16(0x1b8)
|
|
#define VR4122_CSI_OFIFOREG VR4122_REG16(0x1ba)
|
|
#define VR4122_CSI_FIFOTRGREG VR4122_REG16(0x1bc)
|
|
|
|
/* FIR registers - not included */
|
|
|
|
/* Clock rate values for different settings of CLKSEL[2:0] pins/jumpers. */
|
|
|
|
#define CPU_PCLOCK_RATE_111 200700000
|
|
#define CPU_PCLOCK_RATE_110 180600000
|
|
#define CPU_PCLOCK_RATE_101 164200000
|
|
#define CPU_PCLOCK_RATE_100 150500000
|
|
#define CPU_PCLOCK_RATE_011 129000000
|
|
#define CPU_PCLOCK_RATE_010 100400000
|
|
#define CPU_PCLOCK_RATE_001 90300000
|
|
#define CPU_PCLOCK_RATE_000 78500000
|
|
|
|
/* Miscellaneous */
|
|
|
|
#define NUM_4122_TTY 2 /* SIU + DSIU */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __INCnvr4122h */
|