193 lines
6.9 KiB
C
193 lines
6.9 KiB
C
/* m8260IntrCtl.h - MPC 8260 interrupt controller header file */
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/* Copyright 1991-2003 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01h,16jan03,dtr Adding PCI interrupt for HIP4 part.
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01g,17sep99,ms_ remove period in __INCm8260Intr
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01f,17sep99,ms_ try removing config.h
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01e,15jul99,ms_ make compliant with our coding standards
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01d,17apr99,ms_ final EAR cleanup
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01c,15apr99,ms_ add default interrupt priority ordering
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01b,13apr99,ms_ redefine IVEC_TO_INUM and INUM_TO_IVEC to use the numbers as
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shown in the
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MPC8260 user's manaul
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01a,21jan99,ms_ adapted from ppc860Intr.h
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*/
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#ifndef __INCm8260IntrCtlh
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#define __INCm8260IntrCtlh
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#include "vxWorks.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#ifdef IVEC_TO_INUM
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# undef IVEC_TO_INUM
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#endif /* IVEC_TO_INUM */
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#ifdef INUM_TO_IVEC
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# undef INUM_TO_IVEC
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#endif /* INUM_TO_IVEC */
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#define IVEC_TO_INUM(intVec) (m8260IvecToInum(intVec))
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#define INUM_TO_IVEC(intNum) (m8260InumToIvec(intNum))
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/* Interrupt Controller Registers */
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#define M8260_SICR(base) ((VINT32 *) ((base) + 0x010C00))
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#define M8260_SIVEC(base) ((VINT32 *) ((base) + 0x010C04))
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#define M8260_SIPNR_H(base) ((VINT32 *) ((base) + 0x010C08))
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#define M8260_SIPNR_L(base) ((VINT32 *) ((base) + 0x010C0C))
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#define M8260_SIPRR(base) ((VINT32 *) ((base) + 0x010C10))
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#define M8260_SCPRR_H(base) ((VINT32 *) ((base) + 0x010C14))
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#define M8260_SCPRR_L(base) ((VINT32 *) ((base) + 0x010C18))
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#define M8260_SIMR_H(base) ((VINT32 *) ((base) + 0x010C1C))
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#define M8260_SIMR_L(base) ((VINT32 *) ((base) + 0x010C20))
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#define M8260_SIEXR(base) ((VINT32 *) ((base) + 0x010C24))
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/* interrupt numbers */
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#define INUM_ERROR 0 /* Error */
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#define INUM_I2C 1 /* I2C */
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#define INUM_SPI 2 /* SPI */
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#define INUM_RISC_TIMER 3 /* Risc Timer Table */
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#define INUM_SMC1 4 /* SMC 1 */
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#define INUM_SMC2 5 /* SMC 2 */
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#define INUM_IDMA1 6 /* IDMA1 */
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#define INUM_IDMA2 7 /* IDMA2 */
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#define INUM_IDMA3 8 /* IDMA3 */
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#define INUM_IDMA4 9 /* IDMA4 */
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#define INUM_SDMA 10 /* SDMA */
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#define INUM_RESERVED11 11 /* reserved */
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#define INUM_TIMER1 12 /* Timer 1 */
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#define INUM_TIMER2 13 /* Timer 2 */
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#define INUM_TIMER3 14 /* Timer 3 */
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#define INUM_TIMER4 15 /* Timer 4 */
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#define INUM_TMCNT 16 /* TMCNT */
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#define INUM_PIT 17 /* PIT */
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#define INUM_PCI 18 /* PCI Error/DMA/Messages */
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#define INUM_IRQ1 19 /* IRQ 1 interrupt */
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#define INUM_IRQ2 20 /* IRQ 2 interrupt */
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#define INUM_IRQ3 21 /* IRQ 3 interrupt */
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#define INUM_IRQ4 22 /* IRQ 4 interrupt */
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#define INUM_IRQ5 23 /* IRQ 5 interrupt */
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#define INUM_IRQ6 24 /* IRQ 6 interrupt */
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#define INUM_IRQ7 25 /* IRQ 7 interrupt */
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#define INUM_RESERVED26 26 /* reserved */
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#define INUM_FCC1 27 /* FCC1 */
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#define INUM_FCC2 28 /* FCC2 */
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#define INUM_FCC3 29 /* FCC3 */
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#define INUM_RESERVED30 30 /* reserved */
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#define INUM_MCC1 31 /* MCC1 */
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#define INUM_MCC2 32 /* MCC2 */
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#define INUM_RESERVED33 33 /* reserved */
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#define INUM_RESERVED34 34 /* reserved */
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#define INUM_SCC1 35 /* SCC1 */
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#define INUM_SCC2 36 /* SCC2 */
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#define INUM_SCC3 37 /* SCC3 */
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#define INUM_SCC4 38 /* SCC4 */
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#define INUM_RESERVED39 39 /* reserved */
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#define INUM_PC15 40 /* Parallel I/O [15] */
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#define INUM_PC14 41 /* Parallel I/O [14] */
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#define INUM_PC13 42 /* Parallel I/O [13] */
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#define INUM_PC12 43 /* Parallel I/O [12] */
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#define INUM_PC11 44 /* Parallel I/O [11] */
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#define INUM_PC10 45 /* Parallel I/O [10] */
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#define INUM_PC9 46 /* Parallel I/O [9] */
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#define INUM_PC8 47 /* Parallel I/O [8] */
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#define INUM_PC7 48 /* Parallel I/O [7] */
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#define INUM_PC6 49 /* Parallel I/O [6] */
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#define INUM_PC5 50 /* Parallel I/O [5] */
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#define INUM_PC4 51 /* Parallel I/O [4] */
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#define INUM_PC3 52 /* Parallel I/O [3] */
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#define INUM_PC2 53 /* Parallel I/O [2] */
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#define INUM_PC1 54 /* Parallel I/O [1] */
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#define INUM_PC0 55 /* Parallel I/O [0] */
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#define INUM_MAX INUM_PC0
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#define IVEC_MAX (INUM_PC0 + 8)
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/* SICR Masks*/
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#define MPC8260_CICR_SCCDP_MSK 0xc00000 /* SCCd Priority Order Mask */
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#define MPC8260_CICR_SCCDP_SCC1 0x000000 /* SCC1 asserts the SCCd */
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#define MPC8260_CICR_SCCDP_SCC2 0x400000 /* SCC2 asserts the SCCd */
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#define MPC8260_CICR_SCCDP_SCC3 0x800000 /* SCC3 asserts the SCCd */
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#define MPC8260_CICR_SCCDP_SCC4 0xc00000 /* SCC4 asserts the SCCd */
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#define MPC8260_CICR_SCCCP_MSK 0x300000 /* SCCc Priority Order Mask */
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#define MPC8260_CICR_SCCCP_SCC1 0x000000 /* SCC1 asserts the SCCc */
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#define MPC8260_CICR_SCCCP_SCC2 0x100000 /* SCC2 asserts the SCCc */
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#define MPC8260_CICR_SCCCP_SCC3 0x200000 /* SCC3 asserts the SCCc */
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#define MPC8260_CICR_SCCCP_SCC4 0x300000 /* SCC4 asserts the SCCc */
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#define MPC8260_CICR_SCCBP_MSK 0x0c0000 /* SCCb Priority Order Mask */
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#define MPC8260_CICR_SCCBP_SCC1 0x000000 /* SCC1 asserts the SCCb */
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#define MPC8260_CICR_SCCBP_SCC2 0x040000 /* SCC2 asserts the SCCb */
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#define MPC8260_CICR_SCCBP_SCC3 0x080000 /* SCC3 asserts the SCCb */
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#define MPC8260_CICR_SCCBP_SCC4 0x0c0000 /* SCC4 asserts the SCCb */
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#define MPC8260_CICR_SCCAP_MSK 0x030000 /* SCCa Priority Order Mask */
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#define MPC8260_CICR_SCCAP_SCC1 0x000000 /* SCC1 asserts the SCCa */
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#define MPC8260_CICR_SCCAP_SCC2 0x010000 /* SCC2 asserts the SCCa */
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#define MPC8260_CICR_SCCAP_SCC3 0x020000 /* SCC3 asserts the SCCa */
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#define MPC8260_CICR_SCCAP_SCC4 0x030000 /* SCC4 asserts the SCCa */
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#define MPC8260_CICR_IRL_MSK 0x00e000 /* Interrupt Request Level */
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#define MPC8260_CICR_IRL_LVL0 0x000000 /* Interrupt Request Level 0 */
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#define MPC8260_CICR_IRL_LVL1 0x002000 /* Interrupt Request Level 1 */
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#define MPC8260_CICR_IRL_LVL2 0x004000 /* Interrupt Request Level 2 */
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#define MPC8260_CICR_IRL_LVL3 0x006000 /* Interrupt Request Level 3 */
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#define MPC8260_CICR_IRL_LVL4 0x008000 /* Interrupt Request Level 4 */
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#define MPC8260_CICR_IRL_LVL5 0x00a000 /* Interrupt Request Level 5 */
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#define MPC8260_CICR_IRL_LVL6 0x00c000 /* Interrupt Request Level 6 */
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#define MPC8260_CICR_IRL_LVL7 0x00e000 /* Interrupt Request Level 7 */
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#define MPC8260_CICR_HP_MSK 0x001f00 /* Highest Priority */
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#define MPC8260_CICR_IEN 0x000080 /* Interrupt Enable */
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#define MPC8260_CICR_SPS 0x000001 /* Spread Priority Scheme */
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/* interrupt handler */
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#ifndef _ASMLANGUAGE
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typedef struct intr_handler
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{
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VOIDFUNCPTR vec; /* interrupt vector */
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int arg; /* interrupt handler argument */
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} INTR_HANDLER;
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT STATUS m8260IntrInit ();
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extern STATUS m8260IntDisable (int );
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IMPORT STATUS m8260IntEnable (int );
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extern int m8260IvecToInum(VOIDFUNCPTR *);
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extern VOIDFUNCPTR * m8260InumToIvec(int);
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#else
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IMPORT STATUS m8260IntrInit ();
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extern STATUS m8260IntDisable ();
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IMPORT STATUS m8260IntEnable ();
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extern int m8260IvecToInum();
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extern VOIDFUNCPTR * m8260InumToIvec();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCm8260IntrCtlh */
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