290 lines
10 KiB
C
290 lines
10 KiB
C
/* loApic.h - Intel Pentium[234] Local APIC/xAPIC (Advanced PIC) */
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/* Copyright 1997-1998, 2001-2002, 2006, 2008, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01i,29jul10,pad Moved extern C statement after include statements.
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01h,27aug08,jpb Renamed VSB header file
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01g,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01f,08sep06,scm update local apic id for cluster & cpu id...
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01e,26jul06,scm update for pentium/xeon support...
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01d,08mar02,hdn added prototypes for HTT (spr 73738)
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01c,21jun01,hdn added support for Pentium4 Local xAPIC
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01b,25may98,hdn re-written
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01a,26jun97,sub written
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*/
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#ifndef __INCloApich
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#define __INCloApich
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#include <vsbConfig.h>
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/* Local APIC Register Offset */
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#define LOAPIC_ID 0x020 /* Local APIC ID Reg */
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#define LOAPIC_VER 0x030 /* Local APIC Version Reg */
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#define LOAPIC_TPR 0x080 /* Task Priority Reg */
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#define LOAPIC_APR 0x090 /* Arbitration Priority Reg */
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#define LOAPIC_PPR 0x0a0 /* Processor Priority Reg */
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#define LOAPIC_EOI 0x0b0 /* EOI Reg */
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#define LOAPIC_LDR 0x0d0 /* Logical Destination Reg */
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#define LOAPIC_DFR 0x0e0 /* Destination Format Reg */
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#define LOAPIC_SVR 0x0f0 /* Spurious Interrupt Reg */
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#define LOAPIC_ISR 0x100 /* In-service Reg */
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#define LOAPIC_TMR 0x180 /* Trigger Mode Reg */
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#define LOAPIC_IRR 0x200 /* Interrupt Request Reg */
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#define LOAPIC_ESR 0x280 /* Error Status Reg */
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#define LOAPIC_ICRLO 0x300 /* Interrupt Command Reg */
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#define LOAPIC_ICRHI 0x310 /* Interrupt Command Reg */
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#define LOAPIC_TIMER 0x320 /* LVT (Timer) */
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#define LOAPIC_THERMAL 0x330 /* LVT (Thermal) */
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#define LOAPIC_PMC 0x340 /* LVT (PMC) */
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#define LOAPIC_LINT0 0x350 /* LVT (LINT0) */
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#define LOAPIC_LINT1 0x360 /* LVT (LINT1) */
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#define LOAPIC_ERROR 0x370 /* LVT (ERROR) */
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#define LOAPIC_TIMER_ICR 0x380 /* Timer Initial Count Reg */
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#define LOAPIC_TIMER_CCR 0x390 /* Timer Current Count Reg */
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#define LOAPIC_TIMER_CONFIG 0x3e0 /* Timer Divide Config Reg */
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/* IA32_APIC_BASE MSR Bits */
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#define LOAPIC_BASE_MASK 0xfffff000 /* LO APIC Base Addr mask */
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#define LOAPIC_GLOBAL_ENABLE 0x00000800 /* LO APIC Global Enable */
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#define LOAPIC_BSP 0x00000100 /* LO APIC BSP */
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/* Local APIC ID Register Bits */
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#ifdef _WRS_CONFIG_SMP
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#define LOAPIC_ID_MASK 0x1f000000 /* ID [28-24] mask */
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#define LOAPIC_CLUSTER_ID_MASK 0x18000000 /* CLUSTER ID [28-27] mask */
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#define LOAPIC_PHY_PRC_ID_MASK 0x06000000 /* PHYSICAL PROCESSOR ID [26-25] mask */
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#define LOAPIC_LOG_PRC_ID_MASK 0x01000000 /* LOGICAL PROCESSOR ID [24] mask */
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#else
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#define LOAPIC_ID_MASK 0x0f000000 /* LO APIC ID mask */
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#endif /* _WRS_CONFIG_SMP */
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/* Local APIC Version Register Bits */
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#define LOAPIC_VERSION_MASK 0x000000ff /* LO APIC Version mask */
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#define LOAPIC_MAXLVT_MASK 0x00ff0000 /* LO APIC Max LVT mask */
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#define LOAPIC_PENTIUM4 0x00000014 /* LO APIC in Pentium4 */
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#define LOAPIC_LVT_PENTIUM4 5 /* LO APIC LVT - Pentium4 */
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#define LOAPIC_LVT_P6 4 /* LO APIC LVT - P6 */
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#define LOAPIC_LVT_P5 3 /* LO APIC LVT - P5 */
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/* Local APIC Vector Table Bits */
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#define LOAPIC_VECTOR 0x000000ff /* vectorNo */
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#define LOAPIC_MODE 0x00000700 /* delivery mode */
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#define LOAPIC_FIXED 0x00000000 /* delivery mode: FIXED */
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#define LOAPIC_SMI 0x00000200 /* delivery mode: SMI */
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#define LOAPIC_NMI 0x00000400 /* delivery mode: NMI */
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#define LOAPIC_EXT 0x00000700 /* delivery mode: ExtINT */
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#define LOAPIC_IDLE 0x00000000 /* delivery status: Idle */
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#define LOAPIC_PEND 0x00001000 /* delivery status: Pend */
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#define LOAPIC_HIGH 0x00000000 /* polarity: High */
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#define LOAPIC_LOW 0x00002000 /* polarity: Low */
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#define LOAPIC_REMOTE 0x00004000 /* remote IRR */
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#define LOAPIC_EDGE 0x00000000 /* trigger mode: Edge */
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#define LOAPIC_LEVEL 0x00008000 /* trigger mode: Level */
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#define LOAPIC_MASK 0x00010000 /* mask */
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/* Local APIC Spurious-Interrupt Register Bits */
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#define LOAPIC_ENABLE 0x100 /* APIC Enabled */
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#define LOAPIC_FOCUS_DISABLE 0x200 /* Focus Processor Checking */
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/* Local APIC Timer Bits */
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#define LOAPIC_TIMER_DIVBY_2 0x0 /* Divide by 2 */
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#define LOAPIC_TIMER_DIVBY_4 0x1 /* Divide by 4 */
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#define LOAPIC_TIMER_DIVBY_8 0x2 /* Divide by 8 */
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#define LOAPIC_TIMER_DIVBY_16 0x3 /* Divide by 16 */
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#define LOAPIC_TIMER_DIVBY_32 0x8 /* Divide by 32 */
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#define LOAPIC_TIMER_DIVBY_64 0x9 /* Divide by 64 */
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#define LOAPIC_TIMER_DIVBY_128 0xa /* Divide by 128 */
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#define LOAPIC_TIMER_DIVBY_1 0xb /* Divide by 1 */
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#define LOAPIC_TIMER_DIVBY_MASK 0xf /* mask bits */
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#define LOAPIC_TIMER_PERIODIC 0x00020000 /* Timer Mode: Periodic */
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/* Local Vector's lock-unlock macro used in loApicIntLock/Unlock */
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#define LOCKED_TIMER 0x01
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#define LOCKED_PMC 0x02
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#define LOCKED_LINT0 0x04
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#define LOCKED_LINT1 0x08
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#define LOCKED_ERROR 0x10
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#define LOCKED_THERMAL 0x20
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/* Interrupt Command Register: delivery mode and status */
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#define MODE_FIXED 0x0 /* delivery mode: Fixed */
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#define MODE_LOWEST 0x1 /* delivery mode: Lowest */
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#define MODE_SMI 0x2 /* delivery mode: SMI */
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#define MODE_NMI 0x4 /* delivery mode: NMI */
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#define MODE_INIT 0x5 /* delivery mode: INIT */
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#define MODE_STARTUP 0x6 /* delivery mode: StartUp */
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#define STATUS_PEND 0x1000 /* delivery status: Pend */
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/* MP Configuration Table Entries */
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#define MP_ENTRY_CPU 0 /* Entry Type: CPU */
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#define MP_ENTRY_BUS 1 /* Entry Type: BUS */
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#define MP_ENTRY_IOAPIC 2 /* Entry Type: IO APIC */
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#define MP_ENTRY_IOINTERRUPT 3 /* Entry Type: IO INT */
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#define MP_ENTRY_LOINTERRUPT 4 /* Entry Type: LO INT */
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/* Extended MP Configuration Table Entries */
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#define EXT_MP_ENTRY_SASM 128 /* Entry Type: System Address Space Map */
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#define EXT_MP_ENTRY_BHD 129 /* Entry Type: Bus Hierarchy Descriptor */
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#define EXT_MP_ENTRY_CBASM 130 /* Entry Type: Comp Address Space Modifier */
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/* MP Configuration Table CPU Flags */
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#define MP_CPU_FLAGS_BP 0x02
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/* IMCR related bits */
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#define IMCR_ADRS 0x22 /* IMCR addr reg */
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#define IMCR_DATA 0x23 /* IMCR data reg */
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#define IMCR_REG_SEL 0x70 /* IMCR reg select */
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#define IMCR_IOAPIC_ON 0x01 /* IMCR IOAPIC route enable */
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#define IMCR_IOAPIC_OFF 0x00 /* IMCR IOAPIC route disable */
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#ifndef _ASMLANGUAGE
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* MultiProcessor Specification version 1.4 */
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typedef struct /* MP Floating Pointer Structure */
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{
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char signature [4]; /* "_MP_" */
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UINT32 configTableAddr; /* address of the MP configuration table */
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UINT8 length; /* length of the floating pointer structure */
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UINT8 specRev; /* version number of the MP specification */
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UINT8 cksum; /* checksum of the pointer structure */
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UINT8 featureByte[5]; /* MP feature bytes 1 - 5 */
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} MP_FPS;
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typedef struct /* MP Configuration Table Header */
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{
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char mpSignature[4]; /* "PCMP" */
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UINT16 tableLength; /* length of the base configuration table */
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UINT8 specRevision; /* version number of the MP specification */
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UINT8 cksum; /* checksum of the base configuration table */
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char oemId[8]; /* string that identifies the manufacturer */
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char prodId[12]; /* string that identifies the product */
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UINT32 oemTablePtr; /* address to an OEM configuration table */
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UINT16 oemTableSize; /* size of the OEM configuration table */
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UINT16 entryCount; /* number of entries in the variable table */
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UINT32 localApicBaseAddr; /* address of the Local APIC */
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UINT16 extendedTableLength; /* length of the extended entries */
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UINT8 extendedTableCksum; /* checksum of the extended table entries */
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UINT8 reserved;
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} MP_HEADER;
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typedef struct /* MP Config Table Entry for CPU's */
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{
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UINT8 entryType; /* 0 identifies a processor entry */
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UINT8 localApicId; /* Local APIC ID number */
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UINT8 localApicVersion; /* Local APIC's version number */
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UINT8 cpuFlags; /* EN: usable, BP: boot-processor */
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UINT32 cpuSig; /* stepping, model, family of the CPU */
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UINT32 featureFlags; /* feature definition flag */
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UINT32 reserved[2];
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} MP_CPU;
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typedef struct /* MP Config Table Entry for IO APIC's */
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{
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UINT8 entryType; /* 2 identifies an IO APIC entry */
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UINT8 ioApicId; /* ID of this IO APIC */
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UINT8 ioApicVersion; /* version of this IO APIC */
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UINT8 ioApicFlags; /* usable or not */
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UINT32 ioApicBaseAddress; /* address of this IO APIC */
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} MP_IOAPIC;
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typedef struct
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{
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UINT8 entryType;
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UINT8 busId;
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UINT8 busType[6];
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} MP_BUS;
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typedef struct
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{
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UINT8 entryType;
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UINT8 interruptType;
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UINT16 interruptFlags;
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UINT8 sourceBusId;
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UINT8 sourceBusIrq;
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UINT8 destApicId;
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UINT8 destApicIntIn;
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} MP_INTERRUPT;
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typedef MP_INTERRUPT MP_IOINTERRUPT;
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typedef MP_INTERRUPT MP_LOINTERRUPT;
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/* logical ID to base address */
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#define LID_TO_BASE(apic) ((UINT32)mpApicAddrTable[apic])
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/* irq to bus irq */
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#define IRQ_TO_BIRQ(apic, irq) mpApicIrqToBusIrq(apic, irq)
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/* offset within sysInumTbl depends on the logical apic id */
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#define IRQ_OFFSET(apic) (mpApicBaseIrq[apic])
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/* number of required interrupt entries */
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#define NUM_REDIRECTION_ENTRIES(apic) (mpApicRedEntries[apic])
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#define NUM_IOAPICS (mpApicNioApic)
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#ifdef __cplusplus
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}
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#endif
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#include "mpApic.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* variable declarations */
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IMPORT UINT32 loApicBase; /* default Local APIC addr */
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IMPORT UINT32 ioApicBase; /* default IO APIC index addr */
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IMPORT UINT32 ioApicData; /* default IO APIC data addr */
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IMPORT UINT32 loApicId; /* local APIC Id */
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IMPORT UINT32 loApicVersion; /* local APIC Version */
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IMPORT UINT32 loApicMaxLvt; /* local APIC Max LVT */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT void loApicInit (void);
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IMPORT void loApicEnable (BOOL enable);
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IMPORT STATUS loApicIpi (INT32 apicId, INT32 shortHand, INT32 trigger,
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INT32 level, INT32 destMode, INT32 deliMode,
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INT32 vectorNo);
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#else
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IMPORT void loApicInit ();
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IMPORT void loApicEnable ();
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IMPORT STATUS loApicIpi ();
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#endif /* __STDC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* __INCloApich */
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