344 lines
17 KiB
C
344 lines
17 KiB
C
/* motCpmEnd.h - Motorola CPM core Ethernet interface header */
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/* Copyright 1996 - 2002, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01i,29apr10,pad Moved extern C statement after include statements.
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01h,12nov04,dtr Use PPC32 and CPU32 types instead of PPC860.
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01g,24jan02,rcs removed #include "drv/netif/if_cpm.h"
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01f,24jan02,rcs moved General SCC Mode Register definitions,
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SCC Ethernet Protocol Specific Mode Register definitions,
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SCC Ethernet Event and Mask Register definitions,
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SCC Ethernet Receive Buffer Descriptor definitions,
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SCC Ethernet Transmit Buffer Descriptor definitions,
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SCC Serial Comunications Controller,
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SCC device descriptor, and
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#include "drv/multi/ppc860Cpm.h" from h/drv/netif/if_cpm.h
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01e,08jan02,mil Backed out last update "Remove compilation warning".
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01d,22dec01,g_h Remove compilation warning
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01c,28aug98,dat changed all motCmp names to motCpm.
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01b,29jun98,cn fixed compiler errors for CPUs other than CPU32 or PPC860.
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01a,22jun98,cn created.
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*/
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/*
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This file contains definitions to support the end-style Network Driver
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for the Motorola CPM core Ethernet controller used in the M68EN360 and
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PPC800-series communications controllers. These definitions are compiler
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dependant, meaning that their values are based on the particular cpu
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being used.
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*/
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#ifndef __INCmotCpmEndh
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#define __INCmotCpmEndh
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#if ((CPU == PPC32) || (CPU == PPC860))
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#include "drv/multi/ppc860Cpm.h"
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#include "drv/multi/ppc860Siu.h"
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#else
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#include "drv/multi/m68360.h" /* default: use CPU32 include file */
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#endif /* CPU == PPC32 */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/*
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* the following may be redefined in the bsp to account for the actual
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* number of SCC devices in the system.
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*/
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#ifndef MAX_SCC_CHANNELS
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#define MAX_SCC_CHANNELS 4 /* max SCC number for Ethernet channels */
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#endif /* MAX_SCC_CHANNELS */
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#if ((CPU == PPC32) || (CPU == PPC860))
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#define CPM_DPR_SCC1(baseAddr) MPC860_DPR_SCC1 (baseAddr)
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#define CPM_GSMR_L1(baseAddr) GSMR_L1 (baseAddr)
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#define CPM_CIMR_SCC4 CIMR_SCC4
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#define CPM_CIMR(baseAddr) CIMR (baseAddr)
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#define CPM_CISR(baseAddr) CISR (baseAddr)
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#define CPM_CPCR(baseAddr) CPCR (baseAddr)
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#define END_OBJ_STRING "MPC860 Power-QUICC Enhanced Network Driver"
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#define MOT_DEV_NAME "cpm"
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#define MOT_DEV_NAME_LEN 4
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/* General SCC Mode Register definitions */
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#define SCC_GSMRL_HDLC 0x00000000 /* HDLC mode */
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#define SCC_GSMRL_APPLETALK 0x00000002 /* AppleTalk mode (LocalTalk) */
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#define SCC_GSMRL_SS7 0x00000003 /* SS7 mode (microcode) */
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#define SCC_GSMRL_UART 0x00000004 /* UART mode */
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#define SCC_GSMRL_PROFI_BUS 0x00000005 /* Profi-Bus mode (microcode) */
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#define SCC_GSMRL_ASYNC_HDLC 0x00000006 /* async HDLC mode (microcode)*/
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#define SCC_GSMRL_V14 0x00000007 /* V.14 mode */
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#define SCC_GSMRL_BISYNC 0x00000008 /* BISYNC mode */
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#define SCC_GSMRL_DDCMP 0x00000009 /* DDCMP mode (microcode) */
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#define SCC_GSMRL_ETHERNET 0x0000000c /* ethernet mode (SCC1 only) */
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#define SCC_GSMRL_ENT 0x00000010 /* enable transmitter */
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#define SCC_GSMRL_ENR 0x00000020 /* enable receiver */
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#define SCC_GSMRL_LOOPBACK 0x00000040 /* local loopback mode */
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#define SCC_GSMRL_ECHO 0x00000080 /* automatic echo mode */
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#define SCC_GSMRL_TENC 0x00000700 /* transmitter encoding method*/
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#define SCC_GSMRL_RENC 0x00003800 /* receiver encoding method */
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#define SCC_GSMRL_RDCR_X8 0x00004000 /* receive DPLL clock x8 */
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#define SCC_GSMRL_RDCR_X16 0x00008000 /* receive DPLL clock x16 */
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#define SCC_GSMRL_RDCR_X32 0x0000c000 /* receive DPLL clock x32 */
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#define SCC_GSMRL_TDCR_X8 0x00010000 /* transmit DPLL clock x8 */
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#define SCC_GSMRL_TDCR_X16 0x00020000 /* transmit DPLL clock x16 */
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#define SCC_GSMRL_TDCR_X32 0x00030000 /* transmit DPLL clock x32 */
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#define SCC_GSMRL_TEND 0x00040000 /* transmitter frame ending */
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#define SCC_GSMRL_TPP_00 0x00180000 /* Tx preamble pattern = 00 */
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#define SCC_GSMRL_TPP_10 0x00080000 /* Tx preamble pattern = 10 */
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#define SCC_GSMRL_TPP_01 0x00100000 /* Tx preamble pattern = 01 */
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#define SCC_GSMRL_TPP_11 0x00180000 /* Tx preamble pattern = 11 */
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#define SCC_GSMRL_TPL_NONE 0x00000000 /* no Tx preamble (default) */
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#define SCC_GSMRL_TPL_8 0x00200000 /* Tx preamble = 1 byte */
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#define SCC_GSMRL_TPL_16 0x00400000 /* Tx preamble = 2 bytes */
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#define SCC_GSMRL_TPL_32 0x00600000 /* Tx preamble = 4 bytes */
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#define SCC_GSMRL_TPL_48 0x00800000 /* Tx preamble = 6 bytes */
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#define SCC_GSMRL_TPL_64 0x00a00000 /* Tx preamble = 8 bytes */
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#define SCC_GSMRL_TPL_128 0x00c00000 /* Tx preamble = 16 bytes */
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#define SCC_GSMRL_TINV 0x01000000 /* DPLL transmit input invert */
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#define SCC_GSMRL_RINV 0x02000000 /* DPLL receive input invert */
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#define SCC_GSMRL_TSNC 0x0c000000 /* transmit sense */
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#define SCC_GSMRL_TCI 0x10000000 /* transmit clock invert */
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#define SCC_GSMRL_EDGE 0x60000000 /* adjustment edge +/- */
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#define SCC_GSMRH_RSYN 0x00000001 /* receive sync timing*/
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#define SCC_GSMRH_RTSM 0x00000002 /* RTS* mode */
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#define SCC_GSMRH_SYNL 0x0000000c /* sync length */
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#define SCC_GSMRH_TXSY 0x00000010 /* transmitter/receiver sync */
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#define SCC_GSMRH_RFW 0x00000020 /* Rx FIFO width */
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#define SCC_GSMRH_TFL 0x00000040 /* transmit FIFO length */
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#define SCC_GSMRH_CTSS 0x00000080 /* CTS* sampling */
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#define SCC_GSMRH_CDS 0x00000100 /* CD* sampling */
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#define SCC_GSMRH_CTSP 0x00000200 /* CTS* pulse */
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#define SCC_GSMRH_CDP 0x00000400 /* CD* pulse */
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#define SCC_GSMRH_TTX 0x00000800 /* transparent transmitter */
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#define SCC_GSMRH_TRX 0x00001000 /* transparent receiver */
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#define SCC_GSMRH_REVD 0x00002000 /* reverse data */
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#define SCC_GSMRH_TCRC 0x0000c000 /* transparent CRC */
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#define SCC_GSMRH_GDE 0x00010000 /* glitch detect enable */
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/* CPM - Communication Processor Module */
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/* SCC Ethernet Protocol Specific Mode Register definitions */
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#define SCC_ETHER_PSMR_NIB_13 0x0000 /* SFD 13 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_14 0x0002 /* SFD 14 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_15 0x0004 /* SFD 15 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_16 0x0006 /* SFD 16 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_21 0x0008 /* SFD 21 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_22 0x000a /* SFD 22 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_23 0x000c /* SFD 23 bits after TENA */
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#define SCC_ETHER_PSMR_NIB_24 0x000e /* SFD 24 bits after TENA */
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#define SCC_ETHER_PSMR_LCW 0x0100 /* late collision window */
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#define SCC_ETHER_PSMR_SIP 0x0200 /* sample input pins */
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#define SCC_ETHER_PSMR_LPB 0x0400 /* loopback operation */
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#define SCC_ETHER_PSMR_SBT 0x0800 /* stop backoff timer */
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#define SCC_ETHER_PSMR_BRO 0x0100 /* broadcast address */
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#define SCC_ETHER_PSMR_PRO 0x0200 /* promiscuous mode */
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#define SCC_ETHER_PSMR_CRC 0x0800 /* CRC selection */
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#define SCC_ETHER_PSMR_IAM 0x1000 /* individual address mode */
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#define SCC_ETHER_PSMR_RSH 0x2000 /* receive short frame */
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#define SCC_ETHER_PSMR_FC 0x4000 /* force collision */
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#define SCC_ETHER_PSMR_HBC 0x8000 /* heartbeat checking*/
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/* SCC Ethernet Event and Mask Register definitions */
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#define SCC_ETHER_SCCX_RXB 0x0001 /* buffer received event */
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#define SCC_ETHER_SCCX_TXB 0x0002 /* buffer transmitted event */
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#define SCC_ETHER_SCCX_BSY 0x0004 /* busy condition */
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#define SCC_ETHER_SCCX_RXF 0x0008 /* frame received event */
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#define SCC_ETHER_SCCX_TXE 0x0010 /* transmission error event */
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#define SCC_ETHER_SCCX_GRA 0x0080 /* graceful stop event */
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/* SCC Ethernet Receive Buffer Descriptor definitions */
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#define SCC_ETHER_RX_BD_CL 0x0001 /* collision condition */
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#define SCC_ETHER_RX_BD_OV 0x0002 /* overrun condition */
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#define SCC_ETHER_RX_BD_CR 0x0004 /* Rx CRC error */
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#define SCC_ETHER_RX_BD_SH 0x0008 /* short frame received */
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#define SCC_ETHER_RX_BD_NO 0x0010 /* Rx nonoctet aligned frame */
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#define SCC_ETHER_RX_BD_LG 0x0020 /* Rx frame length violation */
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#define SCC_ETHER_RX_BD_M 0x0100 /* miss bit for prom mode */
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#define SCC_ETHER_RX_BD_F 0x0400 /* buffer is first in frame */
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#define SCC_ETHER_RX_BD_L 0x0800 /* buffer is last in frame */
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#define SCC_ETHER_RX_BD_I 0x1000 /* interrupt on receive */
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#define SCC_ETHER_RX_BD_W 0x2000 /* last BD in ring */
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#define SCC_ETHER_RX_BD_E 0x8000 /* buffer is empty */
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/* SCC Ethernet Transmit Buffer Descriptor definitions */
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#define SCC_ETHER_TX_BD_CSL 0x0001 /* carrier sense lost */
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#define SCC_ETHER_TX_BD_UN 0x0002 /* underrun */
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#define SCC_ETHER_TX_BD_RC 0x003c /* retry count */
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#define SCC_ETHER_TX_BD_RL 0x0040 /* retransmission limit */
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#define SCC_ETHER_TX_BD_LC 0x0080 /* late collision */
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#define SCC_ETHER_TX_BD_HB 0x0100 /* heartbeat */
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#define SCC_ETHER_TX_BD_DEF 0x0200 /* defer indication */
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#define SCC_ETHER_TX_BD_TC 0x0400 /* auto transmit CRC */
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#define SCC_ETHER_TX_BD_L 0x0800 /* buffer is last in frame */
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#define SCC_ETHER_TX_BD_I 0x1000 /* interrupt on transmit */
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#define SCC_ETHER_TX_BD_W 0x2000 /* last BD in ring */
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#define SCC_ETHER_TX_BD_PAD 0x4000 /* auto pad short frames */
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#define SCC_ETHER_TX_BD_R 0x8000 /* buffer is ready */
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/* typedefs */
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/* SCC - Serial Comunications Controller */
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typedef struct /* SCC_ETHER_PROTO */
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{
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UINT32 c_pres; /* preset CRC */
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UINT32 c_mask; /* constant mask for CRC */
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volatile UINT32 crcec; /* CRC error counter */
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volatile UINT32 alec; /* alignment error counter */
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volatile UINT32 disfc; /* discard frame counter */
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UINT16 pads; /* short frame pad value */
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UINT16 ret_lim; /* retry limit threshold */
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volatile UINT16 ret_cnt; /* retry limit counter */
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UINT16 mflr; /* maximum frame length register */
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UINT16 minflr; /* minimum frame length register */
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UINT16 maxd1; /* max DMA1 length register */
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UINT16 maxd2; /* max DMA2 length register */
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volatile UINT16 maxd; /* Rx max DMA */
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volatile UINT16 dma_cnt; /* Rx DMA counter */
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volatile UINT16 max_b; /* max BD byte count */
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UINT16 gaddr1; /* group address filter 1 */
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UINT16 gaddr2; /* group address filter 2 */
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UINT16 gaddr3; /* group address filter 3 */
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UINT16 gaddr4; /* group address filter 4 */
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volatile UINT32 tbuf0_data0; /* save area 0 - current frame */
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volatile UINT32 tbuf0_data1; /* save area 1 - current frame */
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volatile UINT32 tbuf0_rba0; /* ? */
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volatile UINT32 tbuf0_crc; /* ? */
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volatile UINT16 tbuf0_bcnt; /* ? */
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UINT16 paddr1_h; /* physical address 1 (MSB) */
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UINT16 paddr1_m; /* physical address 1 */
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UINT16 paddr1_l; /* physical address 1 (LSB) */
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UINT16 p_per; /* persistence */
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volatile UINT16 rfbd_ptr; /* Rx first BD pointer */
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volatile UINT16 tfbd_ptr; /* Tx first BD pointer */
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volatile UINT16 tlbd_ptr; /* Tx last BD pointer */
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volatile UINT32 tbuf1_data0; /* save area 0 - next frame */
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volatile UINT32 tbuf1_data1; /* ? */
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volatile UINT32 tbuf1_rba0; /* ? */
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volatile UINT32 tbuf1_crc; /* ? */
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volatile UINT16 tbuf1_bcnt; /* ? */
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volatile UINT16 tx_len; /* Tx frame length counter */
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UINT16 iaddr1; /* individual address filter 1 */
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UINT16 iaddr2; /* individual address filter 2 */
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UINT16 iaddr3; /* individual address filter 3 */
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UINT16 iaddr4; /* individual address filter 4 */
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volatile UINT16 boff_cnt; /* backoff counter */
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UINT16 taddr_h; /* temp address (MSB) */
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UINT16 taddr_m; /* temp address */
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UINT16 taddr_l; /* temp address (LSB) */
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} SCC_ETHER_PROTO;
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/* SCC device descriptor */
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typedef struct /* SCC_ETHER_DEV */
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{
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int sccNum; /* number of SCC device */
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int txBdNum; /* number of transmit buf descriptors */
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int rxBdNum; /* number of receive buf descriptors */
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SCC_BUF * txBdBase; /* transmit BD base address */
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SCC_BUF * rxBdBase; /* receive BD base address */
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u_char * txBufBase; /* transmit buffer base address */
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u_char * rxBufBase; /* receive buffer base address */
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UINT32 txBufSize; /* transmit buffer size */
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UINT32 rxBufSize; /* receive buffer size */
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int txBdNext; /* next transmit BD to fill */
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int rxBdNext; /* next receive BD to read */
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volatile SCC * pScc; /* SCC parameter RAM */
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volatile SCC_REG * pSccReg; /* SCC registers */
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UINT32 intMask; /* interrupt acknowledge mask */
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} SCC_ETHER_DEV;
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#else /* default: use CPU32 definitions */
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#define SCC_ETHER_DEV SCC_DEV
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#define CPM_DPR_SCC1(baseAddr) M360_DPR_SCC1 (baseAddr)
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#define CPM_GSMR_L1(baseAddr) M360_CPM_GSMR_L1 (baseAddr)
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#define CPM_CIMR_SCC4 CPIC_CIXR_SCC4
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#define CPM_CIMR(baseAddr) M360_CPM_CIMR (baseAddr)
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#define CPM_CISR(baseAddr) M360_CPM_CISR (baseAddr)
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#define CPM_CPCR(baseAddr) M360_CPM_CR (baseAddr)
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#define END_OBJ_STRING "MC68EN360 QUICC Enhanced Network Driver"
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#define MOT_DEV_NAME "qu"
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#define MOT_DEV_NAME_LEN 3
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#endif /* CPU == PPC32 || PPC860 */
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/* bsp-specific routine to include */
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#if ((CPU == PPC32)|| (CPU == PPC860))
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#define SYS_ENET_ADDR_GET(address) \
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if (sysCpmEnetAddrGet != NULL) \
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if (sysCpmEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR) \
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{ \
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errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS); \
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return (NULL); \
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}
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#define SYS_ENET_ENABLE \
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if (sysCpmEnetEnable != NULL) \
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if (sysCpmEnetEnable (pDrvCtrl->unit) == ERROR) \
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return (ERROR);
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#define SYS_ENET_DISABLE \
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if (sysCpmEnetDisable != NULL) \
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sysCpmEnetDisable (pDrvCtrl->unit);
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#else /* default: use CPU32 definitions */
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#define SYS_ENET_ADDR_GET(address) \
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if (sys360EnetAddrGet != NULL) \
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if (sys360EnetAddrGet (pDrvCtrl->unit, (address)) == ERROR) \
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{ \
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errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS); \
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return (NULL); \
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}
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#define SYS_ENET_ENABLE \
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if (sys360EnetEnable != NULL) \
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if (sys360EnetEnable (pDrvCtrl->unit, pDrvCtrl->regBase) == ERROR) \
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return (ERROR);
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#define SYS_ENET_DISABLE \
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if (sys360EnetDisable != NULL) \
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sys360EnetDisable (pDrvCtrl->unit, pDrvCtrl->regBase);
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#endif /* CPU == PPC32 | PPC860*/
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/* globals */
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#if ((CPU == PPC32) || (CPU == PPC860))
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IMPORT STATUS sysCpmEnetEnable (int unit); /* enable ctrl */
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IMPORT void sysCpmEnetDisable (int unit); /* disable ctrl */
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IMPORT STATUS sysCpmEnetAddrGet (int unit, u_char * addr); /* get enet addr */
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#else /* default: use CPU32 prototypes */
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IMPORT STATUS sys360EnetEnable (int unit, UINT32 regBase); /* enable ctrl */
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IMPORT void sys360EnetDisable (int unit, UINT32 regBase); /* disable ctrl */
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IMPORT STATUS sys360EnetAddrGet (int unit, u_char * addr); /* get enet addr */
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#endif /* CPU == PPC32 || PPC860 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmotCpmEndh */
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