237 lines
8.7 KiB
C
237 lines
8.7 KiB
C
/* ibmMalDma.h - IBM Memory Access Layer (MAL) library header */
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/*
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*******************************************************************************
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This source and object code has been made available to you by IBM on an
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AS-IS basis.
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IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
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OF THIRD PARTY RIGHTS. IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
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FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES. IBM'S OR ITS LICENSOR'S
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DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
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AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE. No license
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under IBM patents or patent applications is to be implied by the copyright
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license.
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Any user of this software should understand that neither IBM nor its
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licensors will be responsible for any consequences resulting from the use
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of this software.
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Any person who transfers this source code or any derivative work must
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include the IBM copyright notice, this paragraph, and the preceding two
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paragraphs in the transferred software.
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Any person who transfers this object code or any derivative work must
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include the IBM copyright notice in the transferred software.
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COPYRIGHT I B M CORPORATION 2000
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LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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********************************************************************************
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\NOMANUAL
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*/
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/* Copyright 1984-2004 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01h,03sep04,mdo Documentation fixes for apigen
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01g,28may04,jln add MAL_RX_GROUP_HANDLER_RUNING
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01f,26aug03,jln change malLib.c to ibmMalDma.h;
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change ibmMalRxGroupHandlerEnable() API
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01e,07jul03,jln rename EMAC_RXCHAN_GROUP to MAL_RXCHAN_GROUP
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01d,11jun03,jln modified MAL_DATA structure, more comments.
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01c,16may01,mcg common driver for walnut (405GP), cedar (NPe405x)
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01b,15jan00,mcg added alignment requirement for buffer descriptor rings
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01a,18oct99,mcg created
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*/
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/*
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This file contains constants for the IBM Memory Access Layer core.
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The emacEnd driver is tightly coupling with this header file, if any change
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in the MAL data structure and APIs, the emacEnd.c should be recompiled.
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*/
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#ifndef INCibmMalDmah
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#define INCibmMalDmah
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MAL_NUM_TYPES 2
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#define MAL_TX_TYPE 0
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#define MAL_RX_TYPE 1
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#define MAL_MAX_CHANNELS 32 /* 32 for receive, 32 for transmit */
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/*
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* Reduced configurations of MAL are used for chips with fewer communication
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* cores inside.
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*/
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#define MAL_NO_INTS 0x00000000
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#define MAL_EOB_INT_EN 0x00000001
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#define MAL_DE_INT_EN 0x00000002
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#define MAL_SERR_INT_EN 0x00000004
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#define MAL_MAX_DESC 256 /* max descriptors per channel */
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#define MAL_MAX_DESC_TBL_SIZE (MAL_MAX_DESC * sizeof(MAL_BD))
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#define MAL_DESC_REQ_ALIGN (512*1024) /* 512KB */
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/* MAX RX channels in a board */
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#ifndef MAX_MAL_RX_CHANS
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#define MAX_MAL_RX_CHANS 4
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#endif
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/* MAL flags */
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#define MAL_RX_GROUP_ENABLE 0x0001
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#define MAL_RX_GROUP_POLL_ENABLE 0x0002
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#define MAL_RX_GROUP_HANDLER_RUNING 0x0004
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/* MAL Channel structure */
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typedef struct
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{
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UINT channelType; /* TX_TYPE or RX_TYPE */
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UINT channelNum; /* channel number (0 through 31) */
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UINT bufferSizeRX; /* receive buffer size if an RX channel */
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UINT channelIntMask; /* interrupt mask for this channel */
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VOIDFUNCPTR functionEOB; /* function for EOB int on this channel */
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UINT parmEOB; /* parameter for the above function */
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VOIDFUNCPTR functionDescErr; /* function for DE int on this channel */
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UINT parmDescErr; /* parameter for the above function */
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VOIDFUNCPTR functionSERR; /* function for MAL SERR int for this chn */
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UINT parmSERR; /* parameter for the above function */
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} MAL_CHANNEL;
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/*
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* MAL initialization structure. This information is passed to the MAL driver
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* in malInit().
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*/
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typedef struct
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{
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UINT dcrBaseReg;
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UINT validChannels[MAL_NUM_TYPES];
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UINT intLvlTxeob;
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UINT intVecTxeob;
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UINT intLvlRxeob;
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UINT intVecRxeob;
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UINT intLvlTxde;
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UINT intVecTxde;
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UINT intLvlRxde;
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UINT intVecRxde;
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UINT intLvlSerr;
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UINT intVecSerr;
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} MAL_INIT;
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/* Structure to group all EMAC_RX channels */
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typedef struct
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{
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int rotateIndex [MAX_MAL_RX_CHANS]; /* channel order to search */
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UINT rotateRx [MAX_MAL_RX_CHANS]; /* RX channels index in order */
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UINT chanNum; /* number of RX channels in group */
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UINT maxRxPktsPerInterrupt; /* Max RX packets in a interrupt */
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} MAL_RXCHAN_GROUP;
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/*
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* MAL driver control structure.
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*/
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typedef struct
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{
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MAL_INIT malInit;
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char *descTablesAlloc;
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char *descTables;
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UINT reserved1;
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MAL_CHANNEL malChannelArray[MAL_NUM_TYPES][MAL_MAX_CHANNELS];
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UINT malInitializedChannels[MAL_NUM_TYPES];
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UINT malFlags;
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UINT reserved2;
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MAL_RXCHAN_GROUP malRxChanGrp;
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UINT reserved3;
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UINT reserved4;
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} MAL_DATA;
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/*
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* MAL Buffer Descriptor Structure. The same structure is used for both
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* Transmit and Receive channels.
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*/
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typedef struct
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{
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USHORT statusControl; /* Shared between MAL and comm core */
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USHORT dataLen; /* Buffer byte count */
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char * bufferAdrs; /* Buffer address */
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} MAL_BD;
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/*
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* The status/control bits in the MAL buffer descriptor structure have different
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* meaning if the descriptor is used by a TX channel versus an RX channel.
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* Bits 0:5 are used to convey MAL control/status. Bits 6:15 are
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* used to convey the communication core's (EMAC for example) control/status.
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*/
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/* MAL TX Descriptor Control/Status bits */
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#define MAL_TX_CTRL_READY 0x8000 /* Packet ready to transmit */
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#define MAL_TX_CTRL_WRAP 0x4000 /* Last descriptor in the ring */
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#define MAL_TX_CTRL_CM 0x2000
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#define MAL_TX_CTRL_LAST 0x1000 /* Last buffer for this packet */
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#define MAL_TX_CTRL_INTR 0x0400 /* Intr when packet TX complete*/
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/* MAL RX Descriptor Control/Status bits */
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#define MAL_RX_CTRL_EMPTY 0x8000 /* Buffer empty, ready to RX */
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#define MAL_RX_CTRL_WRAP 0x4000 /* Last descriptor in the ring */
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#define MAL_RX_CTRL_CM 0x2000
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#define MAL_RX_CTRL_LAST 0x1000 /* Last buffer for this packet */
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#define MAL_RX_CTRL_FIRST 0x0800 /* 1st buffer for this packet */
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#define MAL_RX_CTRL_INTR 0x0400 /* Intr when packet RX complete*/
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/* Masks */
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#define MAL_MAL_CTRL_BITS 0xFC00 /* All descriptor bits for MAL */
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#define MAL_COMMAC_CTRL_BITS 0x03FF /* All descriptor bits for the */
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/* communications core */
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#define MAL_RX_ONE_BUFFER (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)
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/* External functions */
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#if defined(__STDC__) || defined(__cplusplus)
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void ibmMalReset (UINT dcrBaseReg);
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MAL_DATA * ibmMalInit (MAL_INIT *pMalInit);
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STATUS ibmMalChannelInit (MAL_DATA *pMalData, MAL_CHANNEL *pChannel);
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STATUS ibmMalChannelDelete (MAL_DATA *pMalData, UINT channelType, UINT channelNum);
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STATUS ibmMalChannelActivate (MAL_DATA *pMalData, UINT channelType, UINT channelNum);
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STATUS ibmMalChannelStop (MAL_DATA *pMalData, UINT channelType, UINT channelNum);
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STATUS ibmMalChannelIntMaskGet (MAL_DATA *pMalData, UINT channelType, UINT channelNum, UINT * intMask);
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STATUS ibmMalChannelIntMaskSet (MAL_DATA *pMalData, UINT channelType, UINT channelNum, UINT intMask);
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STATUS ibmMalChannelDescTblPtrGet (MAL_DATA *pMalData, UINT channelType, UINT channelNum,
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MAL_BD ** descTblAdrs);
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STATUS ibmMalShutDown (MAL_DATA * pMalData);
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void ibmMalRxGroupHandlerEnable (MAL_DATA *, BOOL, BOOL);
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#else
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void ibmMalReset ();
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MAL_DATA * ibmMalInit ();
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STATUS ibmMalChannelInit ();
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STATUS ibmMalChannelDelete ();
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STATUS ibmMalChannelActivate ();
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STATUS ibmMalChannelStop ();
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STATUS ibmMalChannelIntMaskGet ();
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STATUS ibmMalChannelIntMaskSet ();
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STATUS ibmMalChannelDescTblPtrGet ();
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STATUS ibmMalShutDown ();
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void ibmMalRxGroupHandlerEnable ();
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#endif /* defined(__STDC__) || defined(__cplusplus) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* INCibmMalDmah */
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