107 lines
3.3 KiB
C
107 lines
3.3 KiB
C
/* vxdbgPpcLibP.h - private PPC VxWorks debug library (VxDBG) header file */
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/*
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* Copyright (c) 2007-2008, 2010-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use of this
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* software may be licensed only pursuant to the terms of an applicable Wind
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* River license agreement.
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*/
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/*
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modification history
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--------------------
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01g,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
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SMP (CQ:WIND00253870).
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01f,29apr10,pad Moved extern C statement after include statements.
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01e,27aug08,jpb Renamed VSB header file
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01d,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01c,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
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01b,11oct07,rlp Added the VXDBG_INT_REGS_IS_LOCKED macro (CQ:WIND00107725).
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01a,01jun07,jmp Written
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*/
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#ifndef __INCvxdbgPpcLibPh
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#define __INCvxdbgPpcLibPh
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#include <vsbConfig.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* This macro returns the <level> parameter modified with the interrupt lock
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* level defined into the <value> parameter. The <level> parameter must be
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* previously get with either intCpuLock() or intRegsLock() API.
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*
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* We have to define a dummy VXDBG_INT_LOCK_LEVEL_COMPUTE macro since
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* _PPC_MSR_EE is not defined when we build the VxDBG code with CPU==PPC32.
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*/
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#ifdef _PPC_MSR_EE
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#ifdef _PPC_MSR_CE
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#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
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((level & ~(_PPC_MSR_EE | _PPC_MSR_CE)) | \
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(value & (_PPC_MSR_EE | _PPC_MSR_CE)))
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#else /* _PPC_MSR_CE */
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#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
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((level & ~_PPC_MSR_EE) | (value & _PPC_MSR_EE))
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#endif /* _PPC_MSR_CE */
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#else /* _PPC_MSR_EE */
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#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) (level)
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#endif /* _PPC_MSR_EE */
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#ifdef _WRS_CONFIG_SMP
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/*
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* return TRUE if interrupts are locked in specified register set.
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*
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* We have to define a dummy VXDBG_INT_REGS_IS_LOCKED macro since _PPC_MSR_EE
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* is not defined when we build the VxDBG code with CPU==PPC32.
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*/
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#ifdef _PPC_MSR_EE
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#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->msr & _PPC_MSR_EE) == \
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_PPC_MSR_EE) ? FALSE : TRUE)
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#else /* _PPC_MSR_EE */
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#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (FALSE)
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#endif /* _PPC_MSR_EE */
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/*
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* _WRS_VXDBG_CPU_CTRL_VARS_ALIGN sets the alignment constraint for
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* vxdbgCpuCtrlVars array.
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* The value must be:
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* a power of two no smaller than sizeof(vxdbgCpuCtrlVars), and
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* a multiple of the cache line size on every PPC variant that supports SMP.
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*/
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#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN 256
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#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT 8
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#ifdef _CPU_CACHE_ALIGN_SIZE
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/*
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* Validate _WRS_VXDBG_CPU_CTRL_VARS_ALIGN vs current build's
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* _CPU_CACHE_ALIGN_SIZE
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*
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* If any SMP-enabled variant fails this test, _WRS_VXDBG_CPU_CTRL_VARS_ALIGN
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* must be increased. Since this limit also applies to any subsequent arch-only
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* release against the same generic binary release, it may be desirable to
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* allow for growth.
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*/
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#if (_CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN)
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#error Must increase "_WRS_VXDBG_CPU_CTRL_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
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#endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN */
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#endif /* _CPU_CACHE_ALIGN_SIZE */
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#endif /* _WRS_CONFIG_SMP */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxdbgLibPh */
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