186 lines
6.6 KiB
C
186 lines
6.6 KiB
C
/* cacheMipsLib.h - MIPS cache library header file */
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/* Copyright (C) 1992-1993,1996,1999,2001-2003,2006-2008, 2010,
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* 2016 Wind River Systems, Inc. */
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01r,18feb16,g_x support cache and coherency combination and special
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CCA setting (VXW6-85311)
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01q,29apr10,pad Moved extern C statement after include statements.
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01p,22may08,slk add CFG_CCA_COHERENT for malta34k variant
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01o,09aug07,rlg Changes for the MIPS Library restructuring
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01n,23apr07,rlg fix for defect 87754
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01m,10jan06,pes Fix compiler warning.
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01l,27may03,jmt Modify after cache library review
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01k,07may03,jmt Add mti20kx family support
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01j,01oct02,jmt added tx79xx support and made mods for comments from
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design review
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01i,17may02,zmm Global au1000 name changes. SPR 77333.
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01i,14may02,jmt Added Tx49xx cache library support
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01h,13dec01,sru add prototype for Vr4131 cache lib
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01g,16jul01,ros add CofE comment
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01f,09jul01,mem Added generic MIPS cache op prototypes.
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01e,19jan99,dra added CW4000, CW4011, VR4100, VR5000 and VR5400 support.
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01d,15jul96,kkk added R4650 support
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01c,15oct93,cd added R4000 supoort.
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01b,22sep92,rrr added support for c++
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01a,07jul92,ajm created.
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*/
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#ifndef __INCcacheMipsLibh
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#define __INCcacheMipsLibh
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#include <vxWorks.h>
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#include <cacheLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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/* function declarations */
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IMPORT void * cacheMipsMalloc (size_t bytes);
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IMPORT STATUS cacheMipsFree (void * pBuf);
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IMPORT void * cacheMipsVirtToPhys (void * address);
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IMPORT void * cacheMipsPhysToVirt (void * address);
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IMPORT STATUS cacheMipsPipeFlush (void);
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IMPORT STATUS cacheMipsLibInit(CACHE_MODE instMode, CACHE_MODE dataMode);
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IMPORT STATUS cache4kcLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize);
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IMPORT STATUS cache20kxLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize,
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UINT32 sCacheSize, UINT32 sCacheLineSize,
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UINT32 tCacheSize, UINT32 tCacheLineSize);
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IMPORT STATUS cacheAuLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize);
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IMPORT STATUS cacheCW400xLibInit (CACHE_MODE instMode, CACHE_MODE dataMode);
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IMPORT STATUS cacheCW4011LibInit (CACHE_MODE instMode, CACHE_MODE dataMode);
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IMPORT STATUS cacheR32kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode);
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IMPORT STATUS cacheR33kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize);
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IMPORT STATUS cacheR3kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode);
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IMPORT STATUS cacheR4kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize,
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UINT32 sCacheSize, UINT32 sCacheLineSize);
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IMPORT STATUS cacheR5kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize,
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UINT32 sCacheSize, UINT32 sCacheLineSize);
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IMPORT STATUS cacheR7kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize,
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UINT32 sCacheSize, UINT32 sCacheLineSize,
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UINT32 tCacheSize, UINT32 tCacheLineSize);
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IMPORT STATUS cacheR10kLibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize,
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UINT32 sCacheSize, UINT32 sCacheLineSize);
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IMPORT STATUS cacheTx49LibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize);
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IMPORT STATUS cacheTx79LibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize);
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IMPORT STATUS cacheVr4131LibInit (CACHE_MODE instMode, CACHE_MODE dataMode,
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UINT32 iCacheSize, UINT32 iCacheLineSize,
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UINT32 dCacheSize, UINT32 dCacheLineSize,
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UINT32 sCacheSize, UINT32 sCacheLineSize);
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#endif /* _ASMLANGUAGE */
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#if defined (MIPSXX_sb1)
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/* cache configuration attributes */
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#define CFG_K0_MASK 0x07
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#define CFG_K0_EXCL_NOL2 0
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#define CFG_K0_SHARED_NOL2 1
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#define CFG_K0_UNCACHED 2
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#define CFG_K0_CACHEABLE 3
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#define CFG_K0_EXCL_COH 4
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#define CFG_K0_COHERENT 5
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#define CFG_K0_UNUSED 6
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#define CFG_K0_ACCEL 7
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#elif defined (MIPSXX_vr55xx)
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/* cache configuration attributes */
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#define CFG_CCA_RESERVED 0
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#define CFG_CCA_WRTTHRU_ALLOC 1
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#define CFG_CCA_UNCACHED 2
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#define CFG_CCA_WRITEBACK 3
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#define CFG_CCA_WRITETHRU 4
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#define CFG_CCA_WRITEBACK_UNGUARDED 5
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#define CFG_CCA_RESERVED2 6
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#define CFG_CCA_UNCACHED_ACCELERATED 7
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#elif defined (MIPSXX_rm9xxx)
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/* cache control config attributes */
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#define CFG_CCA_WRITETHRU 0
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#define CFG_CCA_WRTTHRU_ALLOC 1
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#define CFG_CCA_UNCACHED_BLK 2
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#define CFG_CCA_WRITEBACK 3
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#define CFG_CCA_COHERE_WRTBK_EXCL 4
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#define CFG_CCA_COHERE_WRTBK 5
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#define CFG_CCA_UNCACHED_NOBLK 6
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#define CFG_CCA_FAST_PACKET_CACHE 7
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#elif defined (MIPSXX_rm52xx)
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/* cache control config attributes */
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#define CFG_CCA_WRITETHRU 0
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#define CFG_CCA_WRTTHRU_ALLOC 1
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#define CFG_CCA_UNCACHED 2
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#define CFG_CCA_WRITEBACK 3
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#define CFG_CCA_RESERVED1 4
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#define CFG_CCA_RESERVED2 5
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#define CFG_CCA_RESERVED3 6
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#define CFG_CCA_RESERVED4 7
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#endif /* MIPSXX_sb1 */
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/* cache control attributes for pal */
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#define CFG_CCA_ALIAS_CACHEABLE 1
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#define CFG_CCA_UNCACHED 2
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#define CFG_CCA_CACHEABLE 3
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#define CFG_CCA_COHERENT 4
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#ifdef MIPSXX_cav_cn7xxx
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#define CFG_CCA_6 6
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#define CFG_CCA_7 7
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#endif /* MIPSXX_cav_cn7xxx */
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#define CFG_CCA_MASK 7
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcacheMipsLibh */
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