382 lines
13 KiB
C
382 lines
13 KiB
C
/* TiDCan.h - definitions for the Ti DCAN */
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/*
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* Copyright (c) 2012, 2014 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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25aug14,hcl fix Altera Soc Gen 5 channel number. (VXW6-83280)
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01a,30nov12,wqi written.
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*/
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/*
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DESCRIPTION
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This file contains the functions declarations, specific to the
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new CAN controller, that implement the interface defined
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in the wnCAN.h header file.
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*/
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#ifndef __INCtiDcanh
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#define __INCtiDcanh
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#include <vxWorks.h>
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#include <spinLockLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* max number of message objects for TI AM335X */
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#undef ALT_DEV_BOARD_CYCLONE_V
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#ifdef ALT_DEV_BOARD_CYCLONE_V
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# define TIDCAN_MAX_MSG_OBJ (128)
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#else
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# define TIDCAN_MAX_MSG_OBJ (64)
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#endif
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#define TI_CHN_VALID 0x01
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#define TI_CHN_INVALID 0x02
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/* CAN control register */
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#define TI_DCAN_CTL 0x00
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#define TI_DCAN_CTL_Init (1<<0)
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#define TI_DCAN_CTL_IE0 (1<<1)
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#define TI_DCAN_CTL_SIE (1<<2)
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#define TI_DCAN_CTL_EIE (1<<3)
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#define TI_DCAN_CTL_DAR (1<<5)
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#define TI_DCAN_CTL_CCE (1<<6)
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#define TI_DCAN_CTL_Test (1<<7)
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#define TI_DCAN_CTL_IDS (1<<8)
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#define TI_DCAN_CTL_ABO (1<<9)
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#define TI_DCAN_CTL_SWR (1<<15)
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#define TI_DCAN_CTL_InitDbg (1<<16)
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#define TI_DCAN_CTL_IE1 (1<<17)
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#define TI_DCAN_CTL_DE1 (1<<18)
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#define TI_DCAN_CTL_DE2 (1<<19)
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#define TI_DCAN_CTL_DE3 (1<<20)
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#define TI_DCAN_CTL_PDR (1<<24)
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#define TI_DCAN_CTL_WUBA (1<<25)
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#define TI_DCAN_CTL_PMD_E (0x5<<10)
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#define TI_DCAN_CTL_PMD_MASK (0xf<<10)
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/* error and status register */
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#define TI_DCAN_ES 0x04
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#define TI_DCAN_ES_PDA (1<<10)
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#define TI_DCAN_ES_WKUP (1<<9)
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#define TI_DCAN_ES_PER (1<<8)
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#define TI_DCAN_ES_BOFF (1<<7)
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#define TI_DCAN_ES_EWARN (1<<6)
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#define TI_DCAN_ES_EPASS (1<<5)
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#define TI_DCAN_ES_RXOK (1<<4)
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#define TI_DCAN_ES_TXOK (1<<3)
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/* last error code. */
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#define TI_DCAN_ES_LEC_MASK (7)
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#define TI_DCAN_ES_LEC_STUFF (1)
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#define TI_DCAN_ES_LEC_FORM (2)
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#define TI_DCAN_ES_LEC_ACK (3)
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#define TI_DCAN_ES_LEC_BIT1 (4)
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#define TI_DCAN_ES_LEC_BIT0 (5)
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#define TI_DCAN_ES_LEC_CRC (6)
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#define TI_DCAN_ES_LEC_OK (7)
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#define TI_DCAN_ERR_BOFF (1<<0) /* Bus-Off state */
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#define TI_DCAN_ERR_EPASS (1<<1) /* error passive state */
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#define TI_DCAN_ERR_PER (1<<2) /* parity error detected */
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#define TI_DCAN_ERR_EWARN (1<<3) /* warning state */
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#define TI_DCAN_ERR_PDA (1<<4) /* local power-down mode acknowledge */
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#define TI_DCAN_ERR_STUFF (1<<5) /* stuff error */
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#define TI_DCAN_ERR_FORM (1<<6) /* form error */
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#define TI_DCAN_ERR_ACK (1<<7) /* ack error */
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#define TI_DCAN_ERR_BIT1 (1<<8) /* bit1 error */
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#define TI_DCAN_ERR_BIT0 (1<<9) /* bit0 error */
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#define TI_DCAN_ERR_CRC (1<<10) /* CRC error */
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#define TI_DCAN_ERR_RXOK (1<<11) /* message Received */
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#define TI_DCAN_ERR_TXOK (1<<12) /* message Transmitted */
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#define TI_DCAN_ERR_WKUP (1<<13) /* wake up pending */
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/* bit timing register */
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#define TI_DCAN_BTR 0x0C
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#define TI_DCAN_BTR_BRP_SHIFT 0
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#define TI_DCAN_BTR_SJW_SHIFT 6
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#define TI_DCAN_BTR_TSeg1_SHIFT 8
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#define TI_DCAN_BTR_TSeg2_SHIFT 12
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#define DCAN_BTR_BRPE_SHIFT 16
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#define DCAN_BTR_BRP_MASK 0x3F
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#define DCAN_BTR_BRP_MASK_SHIFT 6
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#define DCAN_BTR_BRP_MAXVAL 0x3FF
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#define DCAN_BTR_BRP_SHIFT 0
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#define DCAN_BTR_SJW_MAXVAL 0x3
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#define DCAN_BTR_SJW_SHIFT 6
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#define DCAN_BTR_TSEG2_MAXVAL 0x7
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#define DCAN_BTR_TSEG2_SHIFT 12
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#define DCAN_BTR_TSEG1_MAXVAL 0xF
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#define DCAN_BTR_TSEG1_SHIFT 8
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/* the values stored in CANBTC should be adjusted */
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#define DCAN_BTR_ADJUST 1
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/* IFx Register */
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#define TI_DCAN_IF1CMD 0x100 /* IF1 Command Registers */
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#define TI_DCAN_IF2CMD 0x120 /* IF2 Command Registers */
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#define TI_DCAN_IFxCMD_WR (1<<23)
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#define TI_DCAN_IFxCMD_MASK (1<<22)
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#define TI_DCAN_IFxCMD_ARB (1<<21)
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#define TI_DCAN_IFxCMD_CTRL (1<<20)
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#define TI_DCAN_IFxCMD_CTRLINTPND (1<<19)
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#define TI_DCAN_IFxCMD_TXRNDT (1<<18)
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#define TI_DCAN_IFxCMD_DATAA (1<<17)
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#define TI_DCAN_IFxCMD_DATAB (1<<16)
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#define TI_DCAN_IFxCMD_BUSY (1<<15)
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#define TI_DCAN_IFxCMD_DMAACT (1<<14)
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#define TI_DCAN_IFxCMD_MSGNO_SHIFT 0
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#define TI_DCAN_IF1MSK 0x104
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#define TI_DCAN_IF2MSK 0x124
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#define TI_DCAN_IFxMSK_MXTD_SHIFT 31
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#define TI_DCAN_IFxMSK_MDIR_SHIFT 30
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#define TI_DCAN_IFxMSK_MASK_SHIFT 0
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#define TI_DCAN_IFxMSK_MXTD_MASK (((UINT32)1)<<31)
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#define TI_DCAN_IFxMSK_MDIR_MASK (1<<30)
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#define TI_DCAN_IFxMSK_MASK_MASK (0x1FFFFFFF)
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#define TI_DCAN_IFxMSK_NOEXT_MASK (0x1FFC0000)
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#define TI_DCAN_IF1ARB 0x108
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#define TI_DCAN_IF2ARB 0x128
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#define TI_DCAN_IFxARB_MSGVAL_SHIFT 31
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#define TI_DCAN_IFxARB_XTD_SHIFT 30
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#define TI_DCAN_IFxARB_DIR_SHIFT 29
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#define TI_DCAN_IFxARB_MSK_SHIFT_EXT 18
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#define TI_DCAN_IFxARB_MSK_SHIFT_STD 0
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#define TI_DCAN_IFxARB_MSGVAL_MASK (((UINT32)1)<<31)
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#define TI_DCAN_IFxARB_XTD_MASK (1<<30)
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#define TI_DCAN_IFxARB_DIR_MASK (1<<29)
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#define TI_DCAN_IFxARB_MSK_MASK_EXT (0x1FFFFFFF)
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#define TI_DCAN_IFxARB_MSK_MASK_STD (0x1FFC0000)
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#define TI_DCAN_IF1MCTL 0x10C
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#define TI_DCAN_IF2MCTL 0x12C
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#define TI_DCAN_IFxMCTL_NEWDAT_SHIFT 15
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#define TI_DCAN_IFxMCTL_MSGLST_SHIFT 14
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#define TI_DCAN_IFxMCTL_INTPND_SHIFT 13
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#define TI_DCAN_IFxMCTL_UMASK_SHIFT 12
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#define TI_DCAN_IFxMCTL_TXIE_SHIFT 11
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#define TI_DCAN_IFxMCTL_RXIE_SHIFT 10
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#define TI_DCAN_IFxMCTL_RMTEN_SHIFT 9
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#define TI_DCAN_IFxMCTL_TXRQST_SHIFT 8
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#define TI_DCAN_IFxMCTL_EOB_SHIFT 7
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#define TI_DCAN_IFxMCTL_DLC_SHIFT 0
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#define TI_DCAN_IFxMCTL_NEWDAT_MASK (1 << 15)
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#define TI_DCAN_IFxMCTL_MSGLST_MASK (1 << 14)
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#define TI_DCAN_IFxMCTL_INTPND_MASK (1 << 13)
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#define TI_DCAN_IFxMCTL_UMASK_MASK (1 << 12)
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#define TI_DCAN_IFxMCTL_TXIE_MASK (1 << 11)
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#define TI_DCAN_IFxMCTL_RXIE_MASK (1 << 10)
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#define TI_DCAN_IFxMCTL_RMTEN_MASK (1 << 9)
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#define TI_DCAN_IFxMCTL_TXRQST_MASK (1 << 8)
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#define TI_DCAN_IFxMCTL_EOB_MASK (1 << 7)
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#define TI_DCAN_IFxMCTL_DLC_MASK 0x0000000F
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#define TI_DCAN_IF1DATA 0x110 /* IF1 Data A Register */
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#define TI_DCAN_IF1DATB 0x114 /* IF1 Data B Register */
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#define TI_DCAN_IF2DATA 0x130 /* IF2 Data A Register */
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#define TI_DCAN_IF2DATB 0x134 /* IF2 Data B Register */
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#define TI_DCAN_INT 0x10 /* interrupt register */
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#define TI_DCAN_INT1_MASK (0x00FF0000)
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#define TI_DCAN_INT0_MASK (0x0000FFFF)
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#define TI_DCAN_ERRC 0x08 /* error counter register */
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#define TI_DCAN_TEST 0x14 /* test register */
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#define TI_DCAN_TEST_LBACK_SHIFT (1 << 4)
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#define TI_DCAN_TEST_EXLBACK_SHIFT (1 << 8)
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#define TI_DCAN_PERR 0x1C /* parity error code register */
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#define TI_DCAN_ABOTR 0x80 /* Auto-Bus-On time register */
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#define TI_DCAN_TXRQ_X 0x84 /* transmission request x register */
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#define TI_DCAN_TXRQ12 0x88 /* transmission request registers */
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#define TI_DCAN_TXRQ34 0x8C
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#define TI_DCAN_TXRQ56 0x90
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#define TI_DCAN_TXRQ78 0x94
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#define TI_DCAN_NWDAT_X 0x98 /* new data X register */
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#define TI_DCAN_NWDAT12 0x9C /* new data registers */
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#define TI_DCAN_NWDAT34 0xA0
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#define TI_DCAN_NWDAT56 0xA4
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#define TI_DCAN_NWDAT78 0xA8
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#define TI_DCAN_INTPND_X 0xAC /* interrupt pending x register */
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#define TI_DCAN_INTPND12 0xB0 /* interrupt pending registers */
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#define TI_DCAN_INTPND34 0xB4
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#define TI_DCAN_INTPND56 0xB8
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#define TI_DCAN_INTPND78 0xBC
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#define TI_DCAN_MSGVAL_X 0xC0 /* message valid X register */
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#define TI_DCAN_MSGVAL12 0xC4 /* message valid registers */
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#define TI_DCAN_MSGVAL34 0xC8
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#define TI_DCAN_MSGVAL56 0xCC
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#define TI_DCAN_MSGVAL78 0xD0
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#define TI_DCAN_INTMUX12 0xD8 /* interrupt multiplexer registers */
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#define TI_DCAN_INTMUX34 0xDC
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#define TI_DCAN_INTMUX56 0xE0
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#define TI_DCAN_INTMUX78 0xE4
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#define TI_DCAN_IF3OBS 0x140 /* IF3 observation register */
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#define TI_DCAN_IF3MSK 0x144 /* IF3 mask register */
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#define TI_DCAN_IF3ARB 0x148 /* IF3 arbitration register */
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#define TI_DCAN_IF3MCTL 0x14C /* IF3 message control register */
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#define TI_DCAN_IF3DATA 0x150 /* IF3 data A register */
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#define TI_DCAN_IF3DATB 0x154 /* IF3 data B register */
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#define TI_DCAN_IF3UPD12 0x160 /* IF3 update enable registers */
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#define TI_DCAN_IF3UPD34 0x164
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#define TI_DCAN_IF3UPD56 0x168
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#define TI_DCAN_IF3UPD78 0x16C
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#define TI_DCAN_TIOC 0x1E0 /* CAN TX IO control register */
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#define TI_DCAN_RT_TX_SHIFT (1<<3)
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#define TI_DCAN_RIOC 0x1E4 /* CAN RX IO control register */
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/* config options */
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#define TI_CFG_LOOPBACK 0x00000001 /* loopback mode enabled */
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#define TI_CFG_PARITY_ON 0x00000002 /* parity function enabled */
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#define TI_CFG_AUTO_BUS_ON 0x00000004 /* Auto-Bus-On enable */
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/* automatic retransmission of not successful messages enabled */
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#define TI_CFG_AUTO_RETRAN_ON 0x00000008
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#define TI_MSG_MAX_LEN 8
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#define TI_DCAN_SET 1
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#define TI_DCAN_CLR 0
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#define TI_DCAN_IFX_WRITE 0
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#define TI_DCAN_IFX_READ 1
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/* data structures for the controller */
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typedef struct dcanDev
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{
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/* register base for the AM335X DCAN */
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void * pDCANregs;
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/* global data for the AM335X device driver */
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UINT32 busErr;
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UINT32 busState;
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UINT32 intMask;
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UCHAR chanInt[TIDCAN_MAX_MSG_OBJ];
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/* Configuration options, set before TIDCAN_Init() is called */
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UINT32 cfgOptions;
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UINT32 intMsg;
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UINT32 intSys;
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UINT32 intErr;
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UINT32 freq;
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UCHAR rxChl;
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UCHAR txChl;
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UCHAR taChl;
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UCHAR ctrlID ;
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/* interrupt lock */
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spinlockIsr_t lock;
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}
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DCAN_DEV;
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/* used by channel allocate */
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struct _dcan_channeldata_
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{
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WNCAN_ChannelMode chnMode[TIDCAN_MAX_MSG_OBJ];
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WNCAN_ChannelType chnType[TIDCAN_MAX_MSG_OBJ];
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}
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DCAN_CHANNELDATA;
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typedef struct _am335x_dcanmsg_
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{
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/* IFX mask registers */
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UINT32 mxtd; /* mask extended mdentifier */
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UINT32 mdir; /* mask message direction */
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UINT32 msk; /* identifier mask */
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/* IFX arbitration registers */
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UINT32 msgVal; /* message valid */
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UINT32 xtd; /* extended identifier */
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UINT32 dir; /* message direction */
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/*
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* message identifier
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* [28:0] 29-bit identifier (extended frame)
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* [28:18] 11-bit identifier (standard frame).
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*
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*/
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UINT32 id;
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/* IFX message control registers */
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UINT32 newDat; /* new data */
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UINT32 msgLst; /* message lost */
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UINT32 intPnd; /* interrupt pending */
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UINT32 uMask; /* use acceptance mask */
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UINT32 txIE; /* transmit interrupt enable */
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UINT32 rxIE; /* receive interrupt enable */
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UINT32 rmtEn; /* remote enable */
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UINT32 txRqst; /* transmit request */
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UINT32 eob; /* end of the fifo buffer */
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UINT32 dlc; /* data length code */
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}
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AM335X_DCANMSG;
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/* cAN message object data structure */
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typedef struct _dcan_msg_obj_
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{
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UINT32 mask; /* IFX mask registers */
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UINT32 arbitration; /* IFX arbitration registers */
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UINT32 msgCtrl; /* IFX message control registers */
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/* IFx Data A and Data B Registers */
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UINT32 dataA; /* message dataA */
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UINT32 dataB; /* message dataB */
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AM335X_DCANMSG dcanmsg;
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} DCAN_MSG_OBJ;
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/* external globals for the controller */
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/* external functions for the controller */
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void DCAN_ISR (ULONG context);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCtiDcanh */
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