/* am335xCan.h - definitions for AM335X based CAN controller */

/*
 * Copyright (c) 2012, 2014 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01aug14,hcl  add Altera Soc Gen 5 support
01a,30nov12,wqi  written.
*/

/*
DESCRIPTION
This file contains definitions used only in am335xCan.c
and am335xCan_cfg.c
*/

#ifndef __INCam335xCanh
#define __INCam335xCanh

/* includes */

#include <dllLib.h>
#include <CAN/TiDCan.h>

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/* external WindNet CAN required functions */

/*
 * Since all AM335X devices are internal to the processor, only one
 * board can exist.
 */

#define MAX_NUM_AM335X_CAN_BOARDS (1)

#define BRD_NDX       (0)       /* only one board possible */

#ifdef ALT_DEV_BOARD_CYCLONE_V
#	define INUM_MSG0     164     	/* can0_mo_IRQ */
#	define INUM_SYS0     163       	/* can0_sts_IRQ */
#	define INUM_ERR0     166       	/* can0_ecc_uncorrected_IRQ */
#	define INUM_MSG1     168      	/* can1_mo_IRQ */
#	define INUM_SYS1     167       	/* can1_sts_IRQ */
#	define INUM_ERR1     170       	/* can1_ecc_uncorrected_IRQ */
#else
#	define INUM_MSG0     52        	/* DCAN0 interrupt0 */
#	define INUM_SYS0     53        	/* DCAN0 interrupt1 */
#	define INUM_ERR0     54        	/* DCAN0 Parity */
#	define INUM_MSG1     55        	/* DCAN1 interrupt0 */
#	define INUM_SYS1     56        	/* DCAN1 interrupt1 */
#	define INUM_ERR1     57        	/* DCAN1 Parity */
#endif /* ALT_DEV_BOARD_CYCLONE_V */

#define CFG_IMMR        0x80000000
#define MAX_FIFO_SIZE   32

/* the 1Mbps bitrate is the max bitrate */

#define AM335X_CAN_BTR_MAX      1000000

/* the time segment before the sample point */

#define AM335X_CAN_BTR_TSEG1    9

/* the time segment after the sample point */

#define AM335X_CAN_BTR_TSEG2    2

/* the synchronization jump width */

#define AM335X_CAN_BTR_SJW      1

/* the defalut bitrates */

#define AM335X_CAN_BTR_BRP_10K      200
#define AM335X_CAN_BTR_BRP_20K      100
#define AM335X_CAN_BTR_BRP_25K      80
#define AM335X_CAN_BTR_BRP_50K      40
#define AM335X_CAN_BTR_BRP_100K     20
#define AM335X_CAN_BTR_BRP_125K     16
#define AM335X_CAN_BTR_BRP_250K     8
#define AM335X_CAN_BTR_BRP_500K     4
#define AM335X_CAN_BTR_BRP_1M       2

/* typedefs */

/* we need an identifier for each individual AM335X controllers */

typedef enum
    {
    DCAN1_CTRL,
    DCAN2_CTRL
    }
    DCAN_CTRL_ID;

typedef struct _dcan_fifo_
    {
    DL_NODE      pNode;
    UCHAR        channelNum[MAX_FIFO_SIZE];
    UCHAR        bufferSize;
    } DCAN_FIFO;

/*
 * Define a type to record AM335X device instance.
 * Used to pass BSP configuration data to WNCAN.
 */

typedef struct
    {
    DCAN_CTRL_ID DCANcontrollerId;  /* AM335X controller Identifier. */
    void *       pDevBaseAddr;      /* base address of AM335X device */
    int          intNummsg;         /* interrupt number */
    int          intNumsys;         /* interrupt number */
    int          intNumerr;         /* interrupt number */

    UINT32       freq;              /* frequency */
    UINT32       cfgOptions;        /* config options */
    UCHAR        taChl;             /* the number of all channels */
    UCHAR        rxChl;             /* the number of receive channels */
    UCHAR        txChl;             /* the number of transmission channels */

    /* default bit timing setting */

    UCHAR        brp;
    UCHAR        sjw;
    UCHAR        tseg1;
    UCHAR        tseg2;

    }
    am335x_mscan_instance;

IMPORT STATUS am335xCan_init (am335x_mscan_instance * pDCANboardCfg);
IMPORT STATUS am335xCan_establishLinks (struct WNCAN_Device *);
IMPORT struct WNCAN_Device * am335xCan_open (UINT32, UINT32);
IMPORT STATUS am335xCan_close (struct WNCAN_Device *);

IMPORT STATUS CAN_FreeFifoRxChannel (struct WNCAN_Device *pDev,
                                     UCHAR channelNum);
IMPORT STATUS CAN_SetupFifoRxChannel (struct WNCAN_Device  *pDev,
                                      UCHAR * channelNum, UCHAR size,
                                      ULONG canID, BOOL ext,
                                      WNCAN_IntType intSetting, long mask);

IMPORT BOOL am335x_cfgGet_inUse (UINT32 brdNdx);
IMPORT void am335x_cfgSet_inUse (UINT32 brdNdx, BOOL val);
IMPORT BOOL am335x_cfgGet_allocated (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT void am335x_cfgSet_allocated (UINT32 brdNdx, UINT32 ctrlNdx,
                                     BOOL val);

IMPORT struct WNCAN_Board * am335x_cfgGet_canBoardPtr (UINT32 brdNdx);
IMPORT struct WNCAN_Device * am335x_cfgGet_canDevicePtr
                             (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT struct WNCAN_Controller * am335x_cfgGet_canControllerPtr
                                 (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT DCAN_DEV * am335x_cfgGet_mscanDevPtr
                  (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT WNCAN_ChannelMode * am335x_cfgGet_chModePtr
                           (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT WNCAN_ChannelMode * am335x_cfgGet_chTypePtr
                           (UINT32 brdNdx, UINT32 ctrlNdx);
IMPORT UINT32 am335x_cfgGet_NumControllers (void);

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __INCam335xCanh */