/* windArchLibP.h - private WIND header file for i86 */

/*
 * Copyright (c) 2018 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01a,18jul18,r_h  created for kernel page table isolation support (F10571)
*/

#ifndef __INCwindArchLibPh
#define __INCwindArchLibPh


#include <vsbConfig.h>
#include <private/adrSpaceLibP.h>
#ifdef _ASMLANGUAGE
#include <private/offsetMacrosP.h>
#endif

#ifdef __cplusplus
extern "C" {
#endif

#ifdef _WRS_CONFIG_KPTI

#ifdef _WRS_CONFIG_LP64
#define _WRS_WIND_RTP_VARS_ALIGN            512
#define _WRS_WIND_RTP_VARS_ALIGN_SHIFT        9
#define RTP_TRAMPOLINE_STACK_SIZE           192
#define TSS_MAX_COUNT                         1
#else
#define _WRS_WIND_RTP_VARS_ALIGN           1024
#define _WRS_WIND_RTP_VARS_ALIGN_SHIFT       10
#define RTP_TRAMPOLINE_STACK_SIZE            96
#define TSS_MAX_COUNT                         2
#endif

#define GDT_MAX_COUNT                        12

/* RTP region for 32-bit supervisor mode access */

#ifndef _WRS_CONFIG_LP64
#ifndef _ASMLANGUAGE
IMPORT  char *trampolineBaseAddr;
#endif /* _ASMLANGUAGE */
#define KERNEL_RTP_SUP_RGN_BASE	  trampolineBaseAddr
#define KERNEL_RTP_SUP_RGN_SIZE   0x00400000
#endif

#define RTP_SUP_RGN_CODE_ADDR     (KERNEL_RTP_SUP_RGN_BASE + 0x000000)
#define RTP_SUP_RGN_CODE_SIZE     0x2000
#define RTP_SUP_RGN_DATA_ADDR     (KERNEL_RTP_SUP_RGN_BASE + RTP_SUP_RGN_CODE_SIZE)
#define RTP_SUP_RGN_DATA_SIZE     (RTP_SUP_RGN_IDT_SIZE + RTP_SUP_RGN_VARS_SIZE)

/* space for 256 IDT entries, each entry is 16 bytes (4k total) */

#define RTP_SUP_RGN_IDT_ADDRESS   (RTP_SUP_RGN_DATA_ADDR)
#define RTP_SUP_RGN_IDT_SIZE      ((HIGH_VEC + 1) * 16)

/* 256 bytes for each CPU for WIND_RTP_VARS (up to 16k)  */

#define RTP_SUP_RGN_VARS_ADDR     (RTP_SUP_RGN_DATA_ADDR + RTP_SUP_RGN_IDT_SIZE)
#define RTP_SUP_RGN_VARS_SIZE     (_WRS_WIND_RTP_VARS_ALIGN * VX_MAX_SMP_CPUS)

#ifndef _ASMLANGUAGE

/*
 * per-CPU arch specific data accessible using the user-mode page table.
 * For x86 the total size (including the arch-independent part) is 512
 * bytes(64-bit mode) or 1024 bytes(32-bit mode), see
 * _WRS_WIND_RTP_VARS_ALIGN / _WRS_WIND_VARS_ALIGN.
 *
 * Note: unlike the windVarsArch, this is used for UP as well.
 */

typedef struct windRtpVarsArch
    {
    TSS    tss[TSS_MAX_COUNT];      /* 0x010 / 0x020: TSS */
#ifndef _WRS_CONFIG_LP64
    ULONG  tss_pad;                 /* ----- /      : for future use */
#endif
    ULONG  cr3Offset;               /* 0x22c / 0x088: offset to user mode CR3 */
    GDT    gdt[GDT_MAX_COUNT];      /* 0x230 / 0x090: GDT */
#ifdef _WRS_CONFIG_LP64
    ULONG  reserved[2];             /* ----- / 0x0f0: for future use */
#endif
    char   trampolineStack[RTP_TRAMPOLINE_STACK_SIZE];
                                    /* 0x290 / 0x100: trampoline stack */
    } WIND_RTP_VARS_ARCH;

#define _WRS_WIND_RTP_VARS_ARCH WIND_RTP_VARS_ARCH    cpu_archVars

#define _WRS_WIND_RTP_VARS_ARCH_ACCESS(ix, var) \
                           _WRS_WIND_RTP_VARS_ACCESS (ix, archVars.var)

#define RTP_SUP_RGN_GDT_ADDRESS(cpu)   \
                         (&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, gdt[0]))
#define RTP_SUP_RGN_TSS_ADDRESS(cpu)   \
                         (&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, tss[0]))

#ifndef _WRS_CONFIG_LP64
#define RTP_SUP_RGN_OSMTSS_ADDRESS(cpu)   \
                        (&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, tss[1]))
#endif

#endif /* _ASMLANGUAGE */

#endif /* _WRS_CONFIG_KPTI */


#ifdef __cplusplus
}
#endif

#endif /* __INCwindArchLibPh */