/* TiDCan.h - definitions for the Ti DCAN */ /* * Copyright (c) 2012, 2014 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* modification history -------------------- 25aug14,hcl fix Altera Soc Gen 5 channel number. (VXW6-83280) 01a,30nov12,wqi written. */ /* DESCRIPTION This file contains the functions declarations, specific to the new CAN controller, that implement the interface defined in the wnCAN.h header file. */ #ifndef __INCtiDcanh #define __INCtiDcanh #include #include #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /* max number of message objects for TI AM335X */ #undef ALT_DEV_BOARD_CYCLONE_V #ifdef ALT_DEV_BOARD_CYCLONE_V # define TIDCAN_MAX_MSG_OBJ (128) #else # define TIDCAN_MAX_MSG_OBJ (64) #endif #define TI_CHN_VALID 0x01 #define TI_CHN_INVALID 0x02 /* CAN control register */ #define TI_DCAN_CTL 0x00 #define TI_DCAN_CTL_Init (1<<0) #define TI_DCAN_CTL_IE0 (1<<1) #define TI_DCAN_CTL_SIE (1<<2) #define TI_DCAN_CTL_EIE (1<<3) #define TI_DCAN_CTL_DAR (1<<5) #define TI_DCAN_CTL_CCE (1<<6) #define TI_DCAN_CTL_Test (1<<7) #define TI_DCAN_CTL_IDS (1<<8) #define TI_DCAN_CTL_ABO (1<<9) #define TI_DCAN_CTL_SWR (1<<15) #define TI_DCAN_CTL_InitDbg (1<<16) #define TI_DCAN_CTL_IE1 (1<<17) #define TI_DCAN_CTL_DE1 (1<<18) #define TI_DCAN_CTL_DE2 (1<<19) #define TI_DCAN_CTL_DE3 (1<<20) #define TI_DCAN_CTL_PDR (1<<24) #define TI_DCAN_CTL_WUBA (1<<25) #define TI_DCAN_CTL_PMD_E (0x5<<10) #define TI_DCAN_CTL_PMD_MASK (0xf<<10) /* error and status register */ #define TI_DCAN_ES 0x04 #define TI_DCAN_ES_PDA (1<<10) #define TI_DCAN_ES_WKUP (1<<9) #define TI_DCAN_ES_PER (1<<8) #define TI_DCAN_ES_BOFF (1<<7) #define TI_DCAN_ES_EWARN (1<<6) #define TI_DCAN_ES_EPASS (1<<5) #define TI_DCAN_ES_RXOK (1<<4) #define TI_DCAN_ES_TXOK (1<<3) /* last error code. */ #define TI_DCAN_ES_LEC_MASK (7) #define TI_DCAN_ES_LEC_STUFF (1) #define TI_DCAN_ES_LEC_FORM (2) #define TI_DCAN_ES_LEC_ACK (3) #define TI_DCAN_ES_LEC_BIT1 (4) #define TI_DCAN_ES_LEC_BIT0 (5) #define TI_DCAN_ES_LEC_CRC (6) #define TI_DCAN_ES_LEC_OK (7) #define TI_DCAN_ERR_BOFF (1<<0) /* Bus-Off state */ #define TI_DCAN_ERR_EPASS (1<<1) /* error passive state */ #define TI_DCAN_ERR_PER (1<<2) /* parity error detected */ #define TI_DCAN_ERR_EWARN (1<<3) /* warning state */ #define TI_DCAN_ERR_PDA (1<<4) /* local power-down mode acknowledge */ #define TI_DCAN_ERR_STUFF (1<<5) /* stuff error */ #define TI_DCAN_ERR_FORM (1<<6) /* form error */ #define TI_DCAN_ERR_ACK (1<<7) /* ack error */ #define TI_DCAN_ERR_BIT1 (1<<8) /* bit1 error */ #define TI_DCAN_ERR_BIT0 (1<<9) /* bit0 error */ #define TI_DCAN_ERR_CRC (1<<10) /* CRC error */ #define TI_DCAN_ERR_RXOK (1<<11) /* message Received */ #define TI_DCAN_ERR_TXOK (1<<12) /* message Transmitted */ #define TI_DCAN_ERR_WKUP (1<<13) /* wake up pending */ /* bit timing register */ #define TI_DCAN_BTR 0x0C #define TI_DCAN_BTR_BRP_SHIFT 0 #define TI_DCAN_BTR_SJW_SHIFT 6 #define TI_DCAN_BTR_TSeg1_SHIFT 8 #define TI_DCAN_BTR_TSeg2_SHIFT 12 #define DCAN_BTR_BRPE_SHIFT 16 #define DCAN_BTR_BRP_MASK 0x3F #define DCAN_BTR_BRP_MASK_SHIFT 6 #define DCAN_BTR_BRP_MAXVAL 0x3FF #define DCAN_BTR_BRP_SHIFT 0 #define DCAN_BTR_SJW_MAXVAL 0x3 #define DCAN_BTR_SJW_SHIFT 6 #define DCAN_BTR_TSEG2_MAXVAL 0x7 #define DCAN_BTR_TSEG2_SHIFT 12 #define DCAN_BTR_TSEG1_MAXVAL 0xF #define DCAN_BTR_TSEG1_SHIFT 8 /* the values stored in CANBTC should be adjusted */ #define DCAN_BTR_ADJUST 1 /* IFx Register */ #define TI_DCAN_IF1CMD 0x100 /* IF1 Command Registers */ #define TI_DCAN_IF2CMD 0x120 /* IF2 Command Registers */ #define TI_DCAN_IFxCMD_WR (1<<23) #define TI_DCAN_IFxCMD_MASK (1<<22) #define TI_DCAN_IFxCMD_ARB (1<<21) #define TI_DCAN_IFxCMD_CTRL (1<<20) #define TI_DCAN_IFxCMD_CTRLINTPND (1<<19) #define TI_DCAN_IFxCMD_TXRNDT (1<<18) #define TI_DCAN_IFxCMD_DATAA (1<<17) #define TI_DCAN_IFxCMD_DATAB (1<<16) #define TI_DCAN_IFxCMD_BUSY (1<<15) #define TI_DCAN_IFxCMD_DMAACT (1<<14) #define TI_DCAN_IFxCMD_MSGNO_SHIFT 0 #define TI_DCAN_IF1MSK 0x104 #define TI_DCAN_IF2MSK 0x124 #define TI_DCAN_IFxMSK_MXTD_SHIFT 31 #define TI_DCAN_IFxMSK_MDIR_SHIFT 30 #define TI_DCAN_IFxMSK_MASK_SHIFT 0 #define TI_DCAN_IFxMSK_MXTD_MASK (((UINT32)1)<<31) #define TI_DCAN_IFxMSK_MDIR_MASK (1<<30) #define TI_DCAN_IFxMSK_MASK_MASK (0x1FFFFFFF) #define TI_DCAN_IFxMSK_NOEXT_MASK (0x1FFC0000) #define TI_DCAN_IF1ARB 0x108 #define TI_DCAN_IF2ARB 0x128 #define TI_DCAN_IFxARB_MSGVAL_SHIFT 31 #define TI_DCAN_IFxARB_XTD_SHIFT 30 #define TI_DCAN_IFxARB_DIR_SHIFT 29 #define TI_DCAN_IFxARB_MSK_SHIFT_EXT 18 #define TI_DCAN_IFxARB_MSK_SHIFT_STD 0 #define TI_DCAN_IFxARB_MSGVAL_MASK (((UINT32)1)<<31) #define TI_DCAN_IFxARB_XTD_MASK (1<<30) #define TI_DCAN_IFxARB_DIR_MASK (1<<29) #define TI_DCAN_IFxARB_MSK_MASK_EXT (0x1FFFFFFF) #define TI_DCAN_IFxARB_MSK_MASK_STD (0x1FFC0000) #define TI_DCAN_IF1MCTL 0x10C #define TI_DCAN_IF2MCTL 0x12C #define TI_DCAN_IFxMCTL_NEWDAT_SHIFT 15 #define TI_DCAN_IFxMCTL_MSGLST_SHIFT 14 #define TI_DCAN_IFxMCTL_INTPND_SHIFT 13 #define TI_DCAN_IFxMCTL_UMASK_SHIFT 12 #define TI_DCAN_IFxMCTL_TXIE_SHIFT 11 #define TI_DCAN_IFxMCTL_RXIE_SHIFT 10 #define TI_DCAN_IFxMCTL_RMTEN_SHIFT 9 #define TI_DCAN_IFxMCTL_TXRQST_SHIFT 8 #define TI_DCAN_IFxMCTL_EOB_SHIFT 7 #define TI_DCAN_IFxMCTL_DLC_SHIFT 0 #define TI_DCAN_IFxMCTL_NEWDAT_MASK (1 << 15) #define TI_DCAN_IFxMCTL_MSGLST_MASK (1 << 14) #define TI_DCAN_IFxMCTL_INTPND_MASK (1 << 13) #define TI_DCAN_IFxMCTL_UMASK_MASK (1 << 12) #define TI_DCAN_IFxMCTL_TXIE_MASK (1 << 11) #define TI_DCAN_IFxMCTL_RXIE_MASK (1 << 10) #define TI_DCAN_IFxMCTL_RMTEN_MASK (1 << 9) #define TI_DCAN_IFxMCTL_TXRQST_MASK (1 << 8) #define TI_DCAN_IFxMCTL_EOB_MASK (1 << 7) #define TI_DCAN_IFxMCTL_DLC_MASK 0x0000000F #define TI_DCAN_IF1DATA 0x110 /* IF1 Data A Register */ #define TI_DCAN_IF1DATB 0x114 /* IF1 Data B Register */ #define TI_DCAN_IF2DATA 0x130 /* IF2 Data A Register */ #define TI_DCAN_IF2DATB 0x134 /* IF2 Data B Register */ #define TI_DCAN_INT 0x10 /* interrupt register */ #define TI_DCAN_INT1_MASK (0x00FF0000) #define TI_DCAN_INT0_MASK (0x0000FFFF) #define TI_DCAN_ERRC 0x08 /* error counter register */ #define TI_DCAN_TEST 0x14 /* test register */ #define TI_DCAN_TEST_LBACK_SHIFT (1 << 4) #define TI_DCAN_TEST_EXLBACK_SHIFT (1 << 8) #define TI_DCAN_PERR 0x1C /* parity error code register */ #define TI_DCAN_ABOTR 0x80 /* Auto-Bus-On time register */ #define TI_DCAN_TXRQ_X 0x84 /* transmission request x register */ #define TI_DCAN_TXRQ12 0x88 /* transmission request registers */ #define TI_DCAN_TXRQ34 0x8C #define TI_DCAN_TXRQ56 0x90 #define TI_DCAN_TXRQ78 0x94 #define TI_DCAN_NWDAT_X 0x98 /* new data X register */ #define TI_DCAN_NWDAT12 0x9C /* new data registers */ #define TI_DCAN_NWDAT34 0xA0 #define TI_DCAN_NWDAT56 0xA4 #define TI_DCAN_NWDAT78 0xA8 #define TI_DCAN_INTPND_X 0xAC /* interrupt pending x register */ #define TI_DCAN_INTPND12 0xB0 /* interrupt pending registers */ #define TI_DCAN_INTPND34 0xB4 #define TI_DCAN_INTPND56 0xB8 #define TI_DCAN_INTPND78 0xBC #define TI_DCAN_MSGVAL_X 0xC0 /* message valid X register */ #define TI_DCAN_MSGVAL12 0xC4 /* message valid registers */ #define TI_DCAN_MSGVAL34 0xC8 #define TI_DCAN_MSGVAL56 0xCC #define TI_DCAN_MSGVAL78 0xD0 #define TI_DCAN_INTMUX12 0xD8 /* interrupt multiplexer registers */ #define TI_DCAN_INTMUX34 0xDC #define TI_DCAN_INTMUX56 0xE0 #define TI_DCAN_INTMUX78 0xE4 #define TI_DCAN_IF3OBS 0x140 /* IF3 observation register */ #define TI_DCAN_IF3MSK 0x144 /* IF3 mask register */ #define TI_DCAN_IF3ARB 0x148 /* IF3 arbitration register */ #define TI_DCAN_IF3MCTL 0x14C /* IF3 message control register */ #define TI_DCAN_IF3DATA 0x150 /* IF3 data A register */ #define TI_DCAN_IF3DATB 0x154 /* IF3 data B register */ #define TI_DCAN_IF3UPD12 0x160 /* IF3 update enable registers */ #define TI_DCAN_IF3UPD34 0x164 #define TI_DCAN_IF3UPD56 0x168 #define TI_DCAN_IF3UPD78 0x16C #define TI_DCAN_TIOC 0x1E0 /* CAN TX IO control register */ #define TI_DCAN_RT_TX_SHIFT (1<<3) #define TI_DCAN_RIOC 0x1E4 /* CAN RX IO control register */ /* config options */ #define TI_CFG_LOOPBACK 0x00000001 /* loopback mode enabled */ #define TI_CFG_PARITY_ON 0x00000002 /* parity function enabled */ #define TI_CFG_AUTO_BUS_ON 0x00000004 /* Auto-Bus-On enable */ /* automatic retransmission of not successful messages enabled */ #define TI_CFG_AUTO_RETRAN_ON 0x00000008 #define TI_MSG_MAX_LEN 8 #define TI_DCAN_SET 1 #define TI_DCAN_CLR 0 #define TI_DCAN_IFX_WRITE 0 #define TI_DCAN_IFX_READ 1 /* data structures for the controller */ typedef struct dcanDev { /* register base for the AM335X DCAN */ void * pDCANregs; /* global data for the AM335X device driver */ UINT32 busErr; UINT32 busState; UINT32 intMask; UCHAR chanInt[TIDCAN_MAX_MSG_OBJ]; /* Configuration options, set before TIDCAN_Init() is called */ UINT32 cfgOptions; UINT32 intMsg; UINT32 intSys; UINT32 intErr; UINT32 freq; UCHAR rxChl; UCHAR txChl; UCHAR taChl; UCHAR ctrlID ; /* interrupt lock */ spinlockIsr_t lock; } DCAN_DEV; /* used by channel allocate */ struct _dcan_channeldata_ { WNCAN_ChannelMode chnMode[TIDCAN_MAX_MSG_OBJ]; WNCAN_ChannelType chnType[TIDCAN_MAX_MSG_OBJ]; } DCAN_CHANNELDATA; typedef struct _am335x_dcanmsg_ { /* IFX mask registers */ UINT32 mxtd; /* mask extended mdentifier */ UINT32 mdir; /* mask message direction */ UINT32 msk; /* identifier mask */ /* IFX arbitration registers */ UINT32 msgVal; /* message valid */ UINT32 xtd; /* extended identifier */ UINT32 dir; /* message direction */ /* * message identifier * [28:0] 29-bit identifier (extended frame) * [28:18] 11-bit identifier (standard frame). * */ UINT32 id; /* IFX message control registers */ UINT32 newDat; /* new data */ UINT32 msgLst; /* message lost */ UINT32 intPnd; /* interrupt pending */ UINT32 uMask; /* use acceptance mask */ UINT32 txIE; /* transmit interrupt enable */ UINT32 rxIE; /* receive interrupt enable */ UINT32 rmtEn; /* remote enable */ UINT32 txRqst; /* transmit request */ UINT32 eob; /* end of the fifo buffer */ UINT32 dlc; /* data length code */ } AM335X_DCANMSG; /* cAN message object data structure */ typedef struct _dcan_msg_obj_ { UINT32 mask; /* IFX mask registers */ UINT32 arbitration; /* IFX arbitration registers */ UINT32 msgCtrl; /* IFX message control registers */ /* IFx Data A and Data B Registers */ UINT32 dataA; /* message dataA */ UINT32 dataB; /* message dataB */ AM335X_DCANMSG dcanmsg; } DCAN_MSG_OBJ; /* external globals for the controller */ /* external functions for the controller */ void DCAN_ISR (ULONG context); #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __INCtiDcanh */