/* mmuI86Lib.h - mmuI86Lib header for i86. */ /* Copyright 1984-2003 Wind River Systems, Inc. */ /* modification history -------------------- 01g,24jun04,zmm Ported from mmuPro32Lib.h version 01f to P5 MMU. 01f,12jun02,hdn added arch specific VM library APIs' prototype 01e,22aug01,hdn moved GDT and GDT_ENTRIES to regsI86.h 01d,13may98,hdn added PAGE_SIZE_XXX and _ASMLANGUAGE macros. 01c,07jan95,hdn added GDT and GDT_ENTRIES. 01b,01nov94,hdn added MMU_STATE_CACHEABLE_WT for Pentium. 01a,26jul93,hdn written based on mc68k's version. */ #ifndef __INCmmuI86Libh #define __INCmmuI86Libh #ifdef __cplusplus extern "C" { #endif #define PAGE_SIZE 0x1000 #define PAGE_BLOCK_SIZE 0x400000 #define PAGE_SIZE_4KB 0x1000 #define PAGE_SIZE_4MB 0x400000 #define N_PTES 1024 #define N_PDES 1024 #define DIRECTORY_BITS 0xffc00000 #define TABLE_BITS 0x003ff000 #define OFFSET_BITS_4KB 0x00000fff #define DIRECTORY_INDEX 22 #define TABLE_INDEX 12 #define PTE_TO_ADDR_4KB 0xfffff000 #define PTE_INVALID PTE_TO_ADDR_4KB #define PDE_INVALID PTE_INVALID #define ADDR_TO_PAGE 12 #define ADDR_TO_PAGEBASE 0xffc00000 #ifndef _ASMLANGUAGE typedef struct { unsigned present:1; unsigned rw:1; unsigned us:1; unsigned pwt:1; unsigned pcd:1; unsigned access:1; unsigned dirty:1; unsigned zero:2; unsigned avail:3; unsigned page:20; } PTE_FIELD; typedef union pte { PTE_FIELD field; unsigned int bits; } PTE; typedef struct mmuTransTblStruct { PTE *pDirectoryTable; INT32 pageSize; /* Fixed size 4K or 4M if !mixed */ BOOL mixed; /* TRUE if mixed size pages */ } MMU_TRANS_TBL; #define MMU_STATE_MASK_VALID 0x001 #define MMU_STATE_MASK_WRITABLE 0x002 #define MMU_STATE_MASK_USER 0x004 #define MMU_STATE_MASK_PROTECTION 0x006 #define MMU_STATE_MASK_WRITETHROUGH 0x008 #define MMU_STATE_MASK_WBACK 0x008 #define MMU_STATE_MASK_CACHEABLE 0x018 /* 0x018 was 0x10 in AE version */ #define MMU_STATE_MASK_GLOBAL 0x100 #define MMU_STATE_MASK_STATE 0x11f #define MMU_STATE_VALID 0x001 #define MMU_STATE_VALID_NOT 0x000 #define MMU_STATE_WRITABLE 0x002 #define MMU_STATE_WRITABLE_NOT 0x000 #define MMU_STATE_USER 0x004 #define MMU_STATE_USER_NOT 0x000 #define MMU_STATE_WRITETHROUGH 0x008 #define MMU_STATE_WBACK 0x000 #define MMU_STATE_COPYBACK 0x000 #define MMU_STATE_CACHEABLE_NOT 0x018 /* 0x18 was 0x10 in AE version */ #define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT #define MMU_STATE_CACHEABLE 0x000 #define MMU_STATE_GLOBAL 0x100 #define MMU_STATE_GLOBAL_NOT 0x000 #define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT) /* 0x0 */ #define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT) /* 0x4 */ #define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE) /* 0x2 */ #define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE) /* 0x6 */ /* wpOff is used to temporarily override supervisor write-protection. * When using wpOff, interrupts should * be locked because this disables write-protection system wide! * Before unlocking interrupts, be sure to do a wpOn(). */ #define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff) #define wpOn() vxCr0Set (vxCr0Get() | 0x00010000) /* function declarations */ #if defined(__STDC__) || defined(__cplusplus) extern STATUS mmuI86LibInit (int pageSize); extern STATUS mmuI86Enable (BOOL enable); extern void mmuI86On (); extern void mmuI86Off (); extern void mmuI86TLBFlush (); extern void mmuI86PdbrSet (MMU_TRANS_TBL *transTbl); extern void mmuI86Show (MMU_TRANS_TBL *transTbl, void * vaddr); extern MMU_TRANS_TBL *mmuI86PdbrGet (); #else /* __STDC__ */ extern STATUS mmuI86LibInit (); extern STATUS mmuI86Enable (); extern void mmuI86On (); extern void mmuI86Off (); extern void mmuI86TLBFlush (); extern void mmuI86PdbrSet (); extern void mmuI86Show (); extern MMU_TRANS_TBL *mmuI86PdbrGet (); #endif /* __STDC__ */ #endif /* _ASMLANGUAGE */ #ifdef __cplusplus } #endif #endif /* __INCmmuI86Libh */