original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,31 @@
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# Makefile - makefile for bsp/src/drv/video
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#
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# modification history
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# --------------------
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# 01f,15aug05,kkz Updating doc values
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# 01e,29apr05,kkz Updating for new doc directory
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# 01d,27may04,dgp change output dir and TOC structure (DOC_CHAPTER & DOC_DIR)
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# 01c,12mar02,dat SPR 72518 Drivers docs in separate directory
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# 01b,12oct01,tam added repackaging support
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# 01a,03may00,ms created from 01b of MakeSkel
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#
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# DESCRIPTION
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# This file contains the makefile rules for building the vx library
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#
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#*/
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TGT_DIR=$(WIND_BASE)/target
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DOC_FILES=ctB69000Vga.c vgaInit.c
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LIB_BASE_NAME=drv
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EXTRA_INCLUDE=-I$(TGT_DIR)/h/
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OBJS=
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include $(TGT_DIR)/h/make/rules.library
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CC_OPTIM=$(CC_OPTIM_DRIVER)
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include $(TGT_DIR)/h/make/defs.drivers
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@@ -0,0 +1,250 @@
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/* ctB69000Vga.c - a CHIPS B69000 initialization source module */
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/* Copyright 1984-2000 Wind River Systems, Inc. */
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#include "copyright_wrs.h"
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/*
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||||
modification history
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||||
--------------------
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||||
01a,26mar00,ms written.
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*/
|
||||
|
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/*
|
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DESCRIPTION
|
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The 69000 is the first product in the CHIPS family of portable graphics
|
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accelerator product line that integrates high performance memory technology
|
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for the graphics frame buffer. Based on the proven HiQVideo graphics
|
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accelerator core, the 69000 combines state-of-the-art flat panel controller
|
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capabilities with low power, high performance integrated memory. The result
|
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is the start of a high performance, low power, highly integrated solution for
|
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the premier family of portable graphics products.
|
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.IP "High Performance Integrated Memory"
|
||||
The 69000 is the first member of the HiQVideo family to provide integrated high
|
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performance synchronous DRAM (SDRAM) memory technology. Targeted at the
|
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mainstream notebook market, the 69000 incorporates 2MB of proprietary integrated
|
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SDRAM for the graphics/video frame buffer. The integrated SDRAM memory can
|
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support up to 83MHz operation, thus increasing the available memory bandwidth
|
||||
for the graphics subsystem. The result is support for additional high color /
|
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high resolution graphics modes combined with real-time video acceleration. This
|
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additional bandwidth also allows more flexibility in the other graphics
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functions intensely used in Graphical User Interfaces (GUIs) such as Microsoft
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Windows.
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|
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.IP "Frame-Based AGP Compatibility"
|
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The 69000 graphics is designed to be used with either 33MHz PCI, or with AGP as a
|
||||
frame-based AGP device, allowing it to be used with the AGP interface provided by
|
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the latest core logic chipsets.
|
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|
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.IP "HiQColor TM Technology"
|
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The 69000 integrates CHIPS breakthrough HiQColor technology. Based on the CHIPS
|
||||
proprietary TMED (Temporal Modulated Energy Distribution) algorithm, HiQColor
|
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technology is a unique process that allows the display of 16.7 million true
|
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colors on STN panels without using Frame Rate Control (FRC) or dithering. In
|
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addition, TMED also reduces the need for the panel tuning associated with
|
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current FRC-based algorithms. Independent of panel response, the TMED algorithm
|
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eliminates all of the flaws (such as shimmer, Mach banding, and other motion
|
||||
artifacts) normally associated with dithering and FRC. Combined with the new
|
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fast response, high-contrast, and low-crosstalk technology found in new STN
|
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panels, HiQColor technology enables the best display quality and color fidelity
|
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previously only available with TFT technology.
|
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|
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.IP "Versatile Panel Support"
|
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The HiQVideo family supports a wide variety of monochrome and color Single-
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Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD), standard and high-
|
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resolution, passive STN and active matrix TFT/MIM LCD, and EL panels. With
|
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HiQColor technology, up to 256 gray scales are supported on passive STN LCDs. Up
|
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to 16.7M different colors can be displayed on passive STN LCDs and up to 16.7M
|
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colors on 24- bit active matrix LCDs.
|
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|
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The 69000 offers a variety of programmable features to optimize display quality.
|
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Vertical centering and stretching are provided for handling modes with less than
|
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480 lines on 480-line panels. Horizontal and vertical stretching capabilities
|
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are also available for both text and graphics modes for optimal display of VGA
|
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text and graphics modes on 800x600, 1024x768 and 1280x1024 panels.
|
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|
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.IP "Television NTSC/PAL Flicker Free Output"
|
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The 69000 uses a flicker reduction process which makes text of all fonts and
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sizes readable by reducing the flicker and jumping lines on the display.
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.IP "HiQVideo T Multimedia Support"
|
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The 69000 uses independent multimedia capture and display systems on-chip.
|
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The capture system places data in display memory (usually off screen) and
|
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the display system places the data in a window on the screen.
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|
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.IP "Low Power Consumption"
|
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The 69000 uses a variety of advanced power management features to reduce power
|
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consumption of the display sub-system and to extend battery life. Optimized for
|
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3.3V operation, the 69000 internal logic, bus and panel interfaces operate at
|
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3.3V but can tolerate 5V operation.
|
||||
|
||||
.IP "Software Compatibility / Flexibility"
|
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The HiQVideo controllers are fully compatible with the VGA standard at both the
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register and BIOS levels. CHIPS and third-party vendors supply a fully VGA
|
||||
compatible BIOS, end-user utilities and drivers for common application programs.
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|
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.IP "Acceleration for All Panels and All Modes"
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The 69000 graphics engine is designed to support high performance graphics and
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video acceleration for all supported display resolutions, display types, and
|
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color modes. There is no compromise in performance operating in 8, 16, or 24 bpp
|
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color modes allowing true acceleration while displaying up to 16.7M colors.
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.LP
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.I USAGE
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This library provides initialization routines to configure CHIPS B69000 (VGA)
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in alphanumeric mode.
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The functions addressed here include:
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.IP " -"
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Initialization of CHIPS B69000 IC.
|
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|
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.LP
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||||
|
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.I USER INTERFACE
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|
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.CS
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STATUS ctB69000VgaInit
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(
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VOID
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)
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.CE
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This routine will initialize the VGA card if present in PCI connector,
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sets up register set in VGA 3+ mode and loads the font in plane 2.
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INCLUDE FILES: NONE.
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*/
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/* includes */
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#include "vxWorks.h"
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#include "sysLib.h"
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#include "drv/pci/pciConfigLib.h"
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#include "vgaInit.c"
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|
||||
/* defines */
|
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#define CTB69000VGA_VENID 0x102C
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#define CTB69000VGA_DEVID 0x00C0
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#define CTB69000VGA_XR_PORT 0x3D6 /* Extended Register Index Port */
|
||||
#define CTB69000VGA_XR_DATA_PORT 0x3D7 /* Extended Register Data Port */
|
||||
#define CTB69000VGA_FR_PORT 0x3D0 /* Flat Panel Index Port */
|
||||
#define CTB69000VGA_FR_DATA_PORT 0x3D1 /* Flat Panel Data Port */
|
||||
#define CTB69000VGA_MR_PORT 0x3D2 /* Multimedia Index Port */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* ctB69000VgaInit - initializes the B69000 chip and loads font in memory.
|
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*
|
||||
* This routine will initialize the VGA card if present in PCI connector,
|
||||
* sets up register set in VGA 3+ mode and loads the font in plane 2.
|
||||
*
|
||||
* RETURNS: OK/ERROR
|
||||
*/
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||||
|
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STATUS ctB69000VgaInit
|
||||
(
|
||||
void
|
||||
)
|
||||
{
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||||
int pciBus = 0;
|
||||
int pciDevice = 0;
|
||||
int pciFunc = 0;
|
||||
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||||
/* check PCI BASED - CHIPS B69000's presence on the bus */
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||||
if (pciFindDevice (CTB69000VGA_VENID, CTB69000VGA_DEVID, 0,
|
||||
&pciBus, &pciDevice, &pciFunc) != OK)
|
||||
{
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* enable mapped memory and IO addresses */
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||||
pciConfigOutLong (pciBus, pciDevice, pciFunc, 0x04, 0x7);
|
||||
|
||||
/*
|
||||
* Intialize CHIPS B69000 specific registers.
|
||||
*/
|
||||
|
||||
/* Extension Registers */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0005);
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vgaRegSet (CTB69000VGA_XR_PORT, 0xC006);
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||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x0308);
|
||||
|
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/* [0] = Paged; [1] = Linear Mapping; */
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vgaRegSet (CTB69000VGA_XR_PORT, 0x000A);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x010B);
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0x000E);
|
||||
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||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x0040);
|
||||
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0xBC63);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0080);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x0081);
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|
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/* Fout for DCLK0 = 25 Mhz */
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0xD1C0);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x1CC1);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x00C2);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x24C3);
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|
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/* Fout for DCLK1 = 28 Mhz */
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0x55C4);
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vgaRegSet (CTB69000VGA_XR_PORT, 0x09C5);
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0x00C6);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x24C7);
|
||||
|
||||
/* Fout for DCLK2 = Mhz */
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0x6BC8);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x3CC9);
|
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vgaRegSet (CTB69000VGA_XR_PORT, 0x00CA);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x21CB);
|
||||
|
||||
/* Fout for MCLK = 83 Mhz */
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x10CE);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x38CC);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x03CD);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x90CE);
|
||||
|
||||
/* Enable MCLK and DCLK synthesizers */
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x06CF);
|
||||
|
||||
/* Enable DAC, Palette, DCLK-Vco and MCLK-Vco */
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x0FD0);
|
||||
vgaRegSet (CTB69000VGA_XR_PORT, 0x01D1);
|
||||
|
||||
/* Flat Panel Registers */
|
||||
vgaRegSet (CTB69000VGA_FR_PORT, 0x0101);
|
||||
|
||||
/*
|
||||
* Intialize VGA compatible register set on B69000,
|
||||
* and download font in memory for alphanumeric mode.
|
||||
*/
|
||||
vgaInit ();
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,569 @@
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/* vgaInit.c - a VGA 3+ mode initialization source module */
|
||||
|
||||
/* Copyright 1984-2000 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,11may06,dgp doc: fix headings in library
|
||||
01a,26mar00,ms written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This library provides initialization routines to configure VGA in 3+
|
||||
alphanumeric mode.
|
||||
|
||||
The functions addressed here include:
|
||||
\ms
|
||||
\m -
|
||||
Initialization of the VGA specific register set.
|
||||
\me
|
||||
|
||||
USER INTERFACE
|
||||
\cs
|
||||
STATUS vgaInit
|
||||
(
|
||||
VOID
|
||||
)
|
||||
\ce
|
||||
|
||||
This routine will initialize the VGA specific register set to bring a VGA
|
||||
card in VGA 3+ mode and loads the font in plane 2.
|
||||
|
||||
REFERENCES
|
||||
.I Programmer's Guide to the EGA, VGA, and Super VGA Cards - Ferraro.
|
||||
.I Programmer's Guide to PC & PS/2 Video Systems - Richard Wilton.
|
||||
|
||||
INCLUDE FILES: NONE.
|
||||
*/
|
||||
|
||||
/* includes */
|
||||
#include "vxWorks.h"
|
||||
#include "sysLib.h"
|
||||
#include "drv/pci/pciConfigLib.h"
|
||||
#include "intLib.h"
|
||||
|
||||
/* include font */
|
||||
#include "vgaFont.c"
|
||||
|
||||
/* defines */
|
||||
#define VGA_FEATURE_CTRL 0x3DA /* Feature Control Register */
|
||||
#define VGA_MVGA_SR_PORT 0x3C2 /* Miscellaneous Output Port */
|
||||
#define VGA_DAC_PEL_MASK 0x3C6 /* Color Palette Pixel Mask Register */
|
||||
#define VGA_DAC_READ_INDEX 0x3C7 /* Color Palette Read-Mode Index Reg */
|
||||
#define VGA_DAC_STATE 0x3C7 /* Color Palette State Register */
|
||||
#define VGA_DAC_WRITE_INDEX 0x3C8 /* Color Palette Index Register */
|
||||
#define VGA_DAC_DATA_REG 0x3C9 /* Color Palette Data Register */
|
||||
#define VGA_AR_PORT 0x3C0 /* Attribute Controller Index Port */
|
||||
#define VGA_CR_PORT 0x3D4 /* CRT Controller Index Port */
|
||||
#define VGA_GR_PORT 0x3CE /* Graphics Controller Index Port */
|
||||
#define VGA_SR_PORT 0x3C4 /* Sequencer Index Port */
|
||||
#define VGA_SR_DATA_PORT 0x3C5 /* Sequencer Data Port */
|
||||
|
||||
/* forward declarations */
|
||||
LOCAL VOID vgaRegSet (int ioPort, short value);
|
||||
LOCAL STATUS vgaDnldFont (char * font, int len);
|
||||
STATUS vgaInit (void);
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* vgaRegSet - sets the given vga register with given value.
|
||||
*
|
||||
* This routine sets the given vga register with given value.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
|
||||
LOCAL VOID vgaRegSet
|
||||
(
|
||||
int ioPort,
|
||||
short value
|
||||
)
|
||||
{
|
||||
sysOutByte (ioPort, (char) (value & 0xFF));
|
||||
sysOutByte (ioPort + 1, (char) (value >> 8));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* vgaDnldFont - writes given font in plane 2.
|
||||
*
|
||||
* This routine downloads the user specified font in bit plane 2 of VGA planes.
|
||||
*
|
||||
* RETURNS: OK/ERROR
|
||||
*/
|
||||
|
||||
LOCAL STATUS vgaDnldFont
|
||||
(
|
||||
char * font,
|
||||
int len
|
||||
)
|
||||
{
|
||||
int i, j, bytesPerChar;
|
||||
int intKey;
|
||||
unsigned char * vidPtr = (unsigned char *) 0xA0000;
|
||||
|
||||
|
||||
if ((bytesPerChar = len/CHARPERFONT) > MAXBYTESPERCH)
|
||||
return ERROR;
|
||||
|
||||
intKey = intLock();
|
||||
|
||||
/* sequencer is put to reset */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0100);
|
||||
/* write only to plane 2 */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0402);
|
||||
/* sequential addressing */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0704);
|
||||
/* out of reset */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0300);
|
||||
|
||||
/* read plane 2 only */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0204);
|
||||
/* disable even-odd */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0005);
|
||||
/* 0xA0000 */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0006);
|
||||
|
||||
intUnlock (intKey);
|
||||
|
||||
/* Downloading a font into bit plane # 2 */
|
||||
i = 0;
|
||||
j = 0;
|
||||
while(i < FONTDATAMAX) {
|
||||
if (j < bytesPerChar)
|
||||
{
|
||||
*vidPtr++ = vgaFont[i];
|
||||
i++;
|
||||
j++;
|
||||
}
|
||||
else
|
||||
{
|
||||
vidPtr += (MAXBYTESPERCH - bytesPerChar);
|
||||
j = 0;
|
||||
}
|
||||
}
|
||||
/* Downloading over */
|
||||
|
||||
intKey = intLock();
|
||||
|
||||
/* sequencer is put to reset */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0100);
|
||||
/* write only to plane 0 & 1 */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0302);
|
||||
/* font 0 */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0003);
|
||||
/* odd-even addressing */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0304);
|
||||
/* out of reset */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0300);
|
||||
|
||||
/* read plane 0 only */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0004);
|
||||
/* even-odd */
|
||||
vgaRegSet (VGA_GR_PORT, 0x1005);
|
||||
/* 0xB8000 */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0E06);
|
||||
|
||||
intUnlock (intKey);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* vgaInit - initializes the VGA chip and loads font in memory.
|
||||
*
|
||||
* This routine will initialize the VGA specific register set to bring a VGA
|
||||
* card in VGA 3+ mode and loads the font in plane 2.
|
||||
*
|
||||
* RETURNS: OK/ERROR
|
||||
*/
|
||||
|
||||
STATUS vgaInit
|
||||
(
|
||||
void
|
||||
)
|
||||
{
|
||||
int intKey;
|
||||
|
||||
intKey = intLock ();
|
||||
|
||||
/* Sequencer Registers */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0100);
|
||||
vgaRegSet (VGA_SR_PORT, 0x0001);
|
||||
/* write only to plane 0 & 1 */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0302);
|
||||
vgaRegSet (VGA_SR_PORT, 0x0003);
|
||||
/* enable odd/even addressing + extended */
|
||||
vgaRegSet (VGA_SR_PORT, 0x0204);
|
||||
vgaRegSet (VGA_SR_PORT, 0x0007);
|
||||
|
||||
/* MSR: Select DCLK0, Enable RAM access and move I/O to 3Dx */
|
||||
sysOutByte (VGA_MVGA_SR_PORT, 0x67);
|
||||
|
||||
vgaRegSet (VGA_SR_PORT, 0x0300);
|
||||
|
||||
intUnlock (intKey);
|
||||
|
||||
/* CRT Controller Registers */
|
||||
vgaRegSet (VGA_CR_PORT, 0x0E11);
|
||||
|
||||
vgaRegSet (VGA_CR_PORT, 0x5F00);
|
||||
vgaRegSet (VGA_CR_PORT, 0x4F01);
|
||||
vgaRegSet (VGA_CR_PORT, 0x5002);
|
||||
vgaRegSet (VGA_CR_PORT, 0x8203);
|
||||
vgaRegSet (VGA_CR_PORT, 0x5504);
|
||||
vgaRegSet (VGA_CR_PORT, 0x8105);
|
||||
vgaRegSet (VGA_CR_PORT, 0xBF06);
|
||||
vgaRegSet (VGA_CR_PORT, 0x1F07);
|
||||
vgaRegSet (VGA_CR_PORT, 0x0008);
|
||||
vgaRegSet (VGA_CR_PORT, 0x4F09);
|
||||
vgaRegSet (VGA_CR_PORT, 0x0D0A);
|
||||
vgaRegSet (VGA_CR_PORT, 0x0E0B);
|
||||
vgaRegSet (VGA_CR_PORT, 0x000C);
|
||||
vgaRegSet (VGA_CR_PORT, 0x000D);
|
||||
vgaRegSet (VGA_CR_PORT, 0x070E);
|
||||
vgaRegSet (VGA_CR_PORT, 0x800F);
|
||||
vgaRegSet (VGA_CR_PORT, 0x9C10);
|
||||
|
||||
/* Protect Registers CR0-7 */
|
||||
vgaRegSet (VGA_CR_PORT, 0x8E11);
|
||||
|
||||
vgaRegSet (VGA_CR_PORT, 0x8F12);
|
||||
vgaRegSet (VGA_CR_PORT, 0x2813);
|
||||
vgaRegSet (VGA_CR_PORT, 0x1F14);
|
||||
vgaRegSet (VGA_CR_PORT, 0x9615);
|
||||
vgaRegSet (VGA_CR_PORT, 0xB916);
|
||||
vgaRegSet (VGA_CR_PORT, 0xA317);
|
||||
vgaRegSet (VGA_CR_PORT, 0xFF18);
|
||||
|
||||
vgaRegSet (VGA_CR_PORT, 0x4F70);
|
||||
|
||||
/* Attribute Controller Registers */
|
||||
sysInByte (VGA_FEATURE_CTRL);
|
||||
sysOutByte (VGA_AR_PORT, 0x00);
|
||||
sysOutByte (VGA_AR_PORT, 0x00);
|
||||
sysOutByte (VGA_AR_PORT, 0x01);
|
||||
sysOutByte (VGA_AR_PORT, 0x01);
|
||||
sysOutByte (VGA_AR_PORT, 0x02);
|
||||
sysOutByte (VGA_AR_PORT, 0x02);
|
||||
sysOutByte (VGA_AR_PORT, 0x03);
|
||||
sysOutByte (VGA_AR_PORT, 0x03);
|
||||
sysOutByte (VGA_AR_PORT, 0x04);
|
||||
sysOutByte (VGA_AR_PORT, 0x04);
|
||||
sysOutByte (VGA_AR_PORT, 0x05);
|
||||
sysOutByte (VGA_AR_PORT, 0x05);
|
||||
sysOutByte (VGA_AR_PORT, 0x06);
|
||||
sysOutByte (VGA_AR_PORT, 0x14);
|
||||
sysOutByte (VGA_AR_PORT, 0x07);
|
||||
sysOutByte (VGA_AR_PORT, 0x07);
|
||||
sysOutByte (VGA_AR_PORT, 0x08);
|
||||
sysOutByte (VGA_AR_PORT, 0x38);
|
||||
sysOutByte (VGA_AR_PORT, 0x09);
|
||||
sysOutByte (VGA_AR_PORT, 0x39);
|
||||
sysOutByte (VGA_AR_PORT, 0x0A);
|
||||
sysOutByte (VGA_AR_PORT, 0x3A);
|
||||
sysOutByte (VGA_AR_PORT, 0x0B);
|
||||
sysOutByte (VGA_AR_PORT, 0x3B);
|
||||
sysOutByte (VGA_AR_PORT, 0x0C);
|
||||
sysOutByte (VGA_AR_PORT, 0x3C);
|
||||
sysOutByte (VGA_AR_PORT, 0x0D);
|
||||
sysOutByte (VGA_AR_PORT, 0x3D);
|
||||
sysOutByte (VGA_AR_PORT, 0x0E);
|
||||
sysOutByte (VGA_AR_PORT, 0x3E);
|
||||
sysOutByte (VGA_AR_PORT, 0x0F);
|
||||
sysOutByte (VGA_AR_PORT, 0x3F);
|
||||
sysOutByte (VGA_AR_PORT, 0x10);
|
||||
sysOutByte (VGA_AR_PORT, 0x0C);
|
||||
sysOutByte (VGA_AR_PORT, 0x11);
|
||||
sysOutByte (VGA_AR_PORT, 0x00);
|
||||
sysOutByte (VGA_AR_PORT, 0x12);
|
||||
sysOutByte (VGA_AR_PORT, 0x0F);
|
||||
sysOutByte (VGA_AR_PORT, 0x13);
|
||||
sysOutByte (VGA_AR_PORT, 0x08);
|
||||
sysOutByte (VGA_AR_PORT, 0x14);
|
||||
sysOutByte (VGA_AR_PORT, 0x00);
|
||||
/* Enable Video */
|
||||
sysOutByte (VGA_AR_PORT, 0x20);
|
||||
|
||||
/* Graphics Controller Registers */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0000);
|
||||
vgaRegSet (VGA_GR_PORT, 0x0001);
|
||||
vgaRegSet (VGA_GR_PORT, 0x0002);
|
||||
vgaRegSet (VGA_GR_PORT, 0x0003);
|
||||
vgaRegSet (VGA_GR_PORT, 0x0004);
|
||||
vgaRegSet (VGA_GR_PORT, 0x1005);
|
||||
/* B8000-BFFFF */
|
||||
vgaRegSet (VGA_GR_PORT, 0x0E06);
|
||||
vgaRegSet (VGA_GR_PORT, 0x0007);
|
||||
vgaRegSet (VGA_GR_PORT, 0xFF08);
|
||||
|
||||
/* Palette Registers */
|
||||
sysOutByte (VGA_DAC_PEL_MASK, 0xFF);
|
||||
sysOutByte (VGA_DAC_WRITE_INDEX, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00); /* 0x00 - 0x0F */
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F); /* 0x00 - 0x0F */
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00); /* 0x10 - 0x1F */
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F); /* 0x10 - 0x1F */
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15); /* 0x20 - 0x2F */
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F); /* 0x20 - 0x2F */
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15); /* 0x30 - 0x3F */
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x00);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x2A);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x15);
|
||||
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F);
|
||||
sysOutByte (VGA_DAC_DATA_REG, 0x3F); /* 0x30 - 0x3F */
|
||||
|
||||
vgaDnldFont (vgaFont, FONTDATAMAX);
|
||||
|
||||
return OK;
|
||||
}
|
||||
Reference in New Issue
Block a user