original files of m241
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neelimap
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/* usb2Pgs.h - Generation 2 USB pegasus driver */
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/*
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* Copyright (c) 2008 - 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01c,30mar10,w_x Back port GEN2 class drivers for old VxWorks (WIND00192167)
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01b,22arp09,s_z Remove the gun compiler warning and code cleaning
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01a,12nov08,s_z written
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*/
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#ifndef __INCusb2Pgsh
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#define __INCusb2Pgsh
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/* includes */
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#include <vxWorks.h>
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#include <iosLib.h>
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#include <usb2/usb2Helper.h>
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#include <usb2/usb2End.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/* USB pegasus class specific requests */
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#define USB2_PGS_GET_REGISTER_VENDOR_RQ 0xF0 /* get register */
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#define USB2_PGS_SET_REGISTER_VENDOR_RQ 0xF1 /* set register */
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#define USB2_PGS_LINK_STATUS_OFFSET 0x05
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#define USB2_PGS_LINK_STATUS_MASK 0x01
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#define USB2_PGS_HEADER 0x02
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/* Pegasus Register Definition */
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#define USB2_PGS_RGS_ETHERNET_CTRL0 0x00 /* Ethernet Control 0 */
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#define USB2_PGS_RGS_ETHERNET_CTRL1 0x01 /* Ethernet Control 1 */
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#define USB2_PGS_RGS_ETHERNET_CTRL2 0x02 /* Ethernet Control 2 */
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#define USB2_PGS_MULTICAST_ADDR 0x08 /* Multicast Address 0 */
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#define USB2_PGS_ETHERNET_ID 0x10 /* Ethernet ID 0 */
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#define USB2_PGS_RGS_RXFIFO_CTRL 0x1D /* RX FIFO Control */
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#define USB2_PEGASUS_RGS_BIST 0x1E /* BIST */
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/* EEPROM Interface Registers */
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#define USB2_PGS_EEPROM_OFFSET 0x20 /* EEPROM Offset Reg */
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#define USB2_PGS_EEPROM_DATA 0x21 /* EEPROM Data Low Reg*/
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#define USB2_PGS_EEPROM_CONTROL 0x23 /* EEPROM Access Control Reg*/
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/* EEPROM Control Reg Bitmap definition */
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#define USB2_PGS_EEPROM_CONTROL_DONE (0x1 << 2) /* EEPROM Done*/
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#define USB2_PGS_EEPROM_CONTROL_READ (0x1 << 1) /* EEPROM write */
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#define USB2_PGS_EEPROM_CONTROL_WRITE (0x1 << 0) /* EEPROM read */
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/* MII Interface Transceiver Registers */
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#define USB2_PGS_MII_RGS_CONTROL 0x0 /* Control Reg */
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#define USB2_PGS_MII_RGS_STATUS 0x1 /* Status Reg */
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#define USB2_PGS_MII_RGS_PHY_ID1 0x2 /* PHY Identifier 1 Reg */
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#define USB2_PGS_MII_RGS_PHY_ID2 0x3 /* PHY Identifier 2 Reg */
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#define USB2_PGS_MII_RGS_NEGO_AD 0x4 /* Auto-Negotiation Advertisement */
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#define USB2_PGS_MII_RGS_NEGO_ABILITY 0x5 /* Auto-Negotiation Link Partnet Ability */
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#define USB2_PGS_MII_RGS_NEGO_EXP 0x6 /* Auto-Negotiation Expansion */
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/* PHY Access Register */
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#define USB2_PGS_RGS_PHY_ADDR 0x25 /* PHY Address */
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#define USB2_PGS_RGS_PHY_DATA 0x26 /* PHY Data Low */
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#define USB2_PGS_RGS_PHY_CTRL 0x28 /* PHY Access Control */
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/* PHY Access Control Register Bitmap defineition */
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#define USB2_PGS_PHY_CTRL_ADDR_MASK 0x1F
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#define USB2_PGS_PHY_CTRL_WRITE 0x20
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#define USB2_PGS_PHY_CTRL_READ 0x40
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#define USB2_PGS_PHY_CTRL_DONE 0x80
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#define USB2_PGS_RGS_WAKEUP_CTRL 0x78 /* Wakeup Control */
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#define USB2_PGS_RGS_INTERNAL_PHY_CTRL 0x7B /* Internal PHY Control */
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#define USB2_PGS_RGS_GPIO_10_CTRL 0x7E /* GPIO[1:0] Control */
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#define USB2_PGS_RGS_GPIO_32_CTRL 0x7F /* GPIO[3:2] Control */
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/* Pegasus Control Registers definition */
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#define PEGASUS_CTL0_INCLUDE_RXCRC 0x01
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#define PEGASUS_CTL0_ALLMULTI 0x02
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#define PEGASUS_CTL0_STOP_BACKOFF 0x04
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#define PEGASUS_CTL0_RXSTAT_APPEND 0x08
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#define PEGASUS_CTL0_WAKEON_ENB 0x10
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#define PEGASUS_CTL0_RXPAUSE_ENB 0x20
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#define PEGASUS_CTL0_RX_ENB 0x40
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#define PEGASUS_CTL0_TX_ENB 0x80
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#define PEGASUS_CTL1_HOMELAN 0x04
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#define PEGASUS_CTL1_RESETMAC 0x08
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#define PEGASUS_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */
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#define PEGASUS_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */
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#define PEGASUS_CTL1_DELAYHOME 0x40
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#define PEGASUS_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */
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#define PEGASUS_CTL2_RX_BADFRAMES 0x02
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#define PEGASUS_CTL2_RX_PROMISC 0x04
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#define PEGASUS_CTL2_LOOPBACK 0x08
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#define PEGASUS_CTL2_EEPROMWR_ENB 0x10
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#define PEGASUS_CTL2_EEPROM_LOAD 0x20
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/*
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* Define Vendor ID and Product ID which supported
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* by pegasus driver,add such devices into pgs list
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*/
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/* ADMtek */
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#define ADMTEK_ADM8515_PRODUCT_ID 0x8515
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#define ADMTEK_ADM8513_PRODUCT_ID 0x8513
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#define ADMTEK_ADM8511_PRODUCT_ID 0x8511
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/* Sohoware */
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#define SOHOWARE_NUB110_PRODUCT_ID 0x9110
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/* D-Link */
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#define DLINK_DSB650_PRODUCT_ID 0xABC1
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#define DLINK_DSB650TX1_PRODUCT_ID 0x4001
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#define DLINK_DSB650TX2_PRODUCT_ID 0x4002
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#define DLINK_DSB650TX12_PRODUCT_ID 0x4102
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#define DLINK_DSB650TXB_PRODUCT_ID 0x400B
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/* Belkin */
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#define BELKIN_F5D5050_PRODUCT_ID 0x0121
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/* Netgear */
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#define NETGEAR_FA101_PRODUCT_ID 0x1020
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/* IO Data */
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#define IODATA_ETTXS_PRODUCT_ID 0x0913
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/* 3COM */
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#define _3COM_3C460B_PRODUCT_ID 0x4601
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/* SIEMENS */
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#define SIEMENS_SPEEDSTREAM_PRODUCT_ID 0x1001
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/*
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* Define the max number of the pegasus devcie table, can be expanded
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* according the device
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*/
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#define USB2_PGS_MAX_DEVICE_NUMBER 32
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/* Forward declarations */
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extern void usb2PgsDeInit
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(
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void
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);
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extern STATUS usb2PgsInit
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(
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char * pName
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);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCusb2Pgsh */
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