original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,90 @@
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/* mcfPit.h - coldfire programmable interrupt timer device header */
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/*
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* Copyright (c) 2007 Wind River Systems, Inc.
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*
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||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
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||||
modification history
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||||
--------------------
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||||
01a,14nov07,rec created
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||||
*/
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||||
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||||
#ifndef __INCmcfPith
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#define __INCmcfPith
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/* register offsets */
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#define VXB_MCF_PIT_PCSR 0
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#define VXB_MCF_PIT_PMR 2
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#define VXB_MCF_PIT_PCNTR 4
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/* Register read/write macros */
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#ifndef MCF_PIT_REG_OFFSET
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#define MCF_PIT_REG_OFFSET 0x4000
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#endif
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#define MCF_PIT0_PCSR ((volatile UINT16*)(MCF_PIT0_BASE + \
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VXB_MCF_PIT_PCSR))
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#define MCF_PIT0_PMR ((volatile UINT16*)(MCF_PIT0_BASE + \
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VXB_MCF_PIT_PMR))
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#define MCF_PIT0_PCNTR ((volatile UINT16*)(MCF_PIT0_BASE + \
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VXB_MCF_PIT_PCNTR))
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#define MCF_PIT1_PCSR ((volatile UINT16*)(MCF_PIT1_BASE + \
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VXB_MCF_PIT_PCSR))
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#define MCF_PIT1_PMR ((volatile UINT16*)(MCF_PIT1_BASE + \
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VXB_MCF_PIT_PMR))
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#define MCF_PIT1_PCNTR ((volatile UINT16*)(MCF_PIT1_BASE + \
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VXB_MCF_PIT_PCNTR))
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#define MCF_PIT2_PCSR ((volatile UINT16*)(MCF_PIT2_BASE + \
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VXB_MCF_PIT_PCSR))
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#define MCF_PIT2_PMR ((volatile UINT16*)(MCF_PIT2_BASE + \
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VXB_MCF_PIT_PMR))
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#define MCF_PIT2_PCNTR ((volatile UINT16*)(MCF_PIT2_BASE + \
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VXB_MCF_PIT_PCNTR))
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#define MCF_PIT3_PCSR ((volatile UINT16*)(MCF_PIT3_BASE + \
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VXB_MCF_PIT_PCSR))
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#define MCF_PIT3_PMR ((volatile UINT16*)(MCF_PIT3_BASE + \
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VXB_MCF_PIT_PMR))
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#define MCF_PIT3_PCNTR ((volatile UINT16*)(MCF_PIT3_BASE + \
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VXB_MCF_PIT_PCNTR))
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#define MCF_PIT_PCSR(x) ((volatile UINT16*)((MCF_PIT0_BASE + \
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(x) * MCF_PIT_REG_OFFSET)))
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#define MCF_PIT_PMR(x) ((volatile UINT16*)((MCF_PIT0_BASE + \
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(x) * MCF_PIT_REG_OFFSET)))
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#define MCF_PIT_PCNTR(x) ((volatile UINT16*)((MCF_PIT0_BASE + \
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(x) * MCF_PIT_REG_OFFSET)))
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/* Bit definitions and macros for MCF_PIT_PCSR */
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#define MCF_PIT_PCSR_EN (0x0001)
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#define MCF_PIT_PCSR_RLD (0x0002)
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#define MCF_PIT_PCSR_PIF (0x0004)
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#define MCF_PIT_PCSR_PIE (0x0008)
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#define MCF_PIT_PCSR_OVW (0x0010)
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#define MCF_PIT_PCSR_HALTED (0x0020)
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#define MCF_PIT_PCSR_DOZE (0x0040)
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#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
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/* Bit definitions and macros for MCF_PIT_PMR */
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#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_PIT_PCNTR */
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#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
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#endif
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@@ -0,0 +1,56 @@
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/* vxbCn3xxxTimer.h - Cavium timer driver */
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/*
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||||
* Copyright (c) 2010 Wind River Systems, Inc.
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||||
*
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||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
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||||
|
||||
/*
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||||
modification history
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||||
--------------------
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||||
01a,19jul10,rlg created.
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*/
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||||
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#ifndef __INCvxbCn3xxxTimerh
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#define __INCvxbCn3xxxTimerh
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/*
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* address of core clock count register
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* number of cycles since release of reset
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* read only
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*/
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#define CAV_IPD_CLK_COUNT 0x80014f0000000338ull
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/* For 78XX COP0 uses FPA_CLK
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* Check cvmx-clock.h for more details
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*/
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#define CAV_FPA_CLK_COUNT 0x80012800000000F0ull
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/*
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* base address of timers
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*/
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#define CAV_CIU_TIMX 0x8001070000000480ull
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#define CAV_CIU_TIMX_SP 0x8
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#define CAV_CIU_TIMER(unit) \
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(CAV_CIU_TIMX + ((unit) * CAV_CIU_TIMX_SP ))
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#define CAV_CIU3_TIMX 0x8001010000010000ull
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#define CAV_CIU3_TIMX_SP 0x8
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#define CAV_CIU3_TIMER(unit) \
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(CAV_CIU3_TIMX + ((unit & 15) * CAV_CIU3_TIMX_SP ))
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/* BIT MASK AND SHIFT FOR TIMER REGISTERS */
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#define CAV_CIU_TIMER_MODE_SHIFT 36
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#define CAV_CIU_TIMER_MODE_MASK 0x0000000000000001ull
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#endif /* __INCvxbCn3xxxTimerh */
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@@ -0,0 +1,50 @@
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/* vxbCortexMSysTick.h - vxbus Cortex-M system tick timer header file */
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/*
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||||
* Copyright (c) 2012 Wind River Systems, Inc.
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||||
*
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||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
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||||
modification history
|
||||
--------------------
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||||
01a,19apr12,rec written.
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||||
*/
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||||
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||||
/*
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||||
DESCRIPTION
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||||
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||||
This file provides the Cortex-M timers specific definitions.
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||||
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||||
*/
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||||
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||||
#ifndef __INCvxbCortexMSysTickh
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||||
#define __INCvxbCortexMSysTickh
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||||
#ifdef __cplusplus
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extern "C" {
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||||
#endif
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#define CORTEXM_SYSTICK_NAME "CortexMSysTick"
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#define CORTEXM_SYST_CSR 0xE000E010 /* control and status */
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#define CORTEXM_SYST_CSR_ENABLE \
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0x00000001 /* 1 = enable */
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#define CORTEXM_SYST_CSR_TICKINT \
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0x00000002 /* Exception enable */
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||||
#define CORTEXM_SYST_CSR_CLKSOURCE \
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0x00000004 /* 1 = system clock, 0 = external */
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#define CORTEXM_SYST_CSR_COUNTFLAG \
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0x00010000 /* reload event - reset when read */
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#define CORTEXM_SYST_RVR 0xE000E014 /* reload value (24-bit) */
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#define CORTEXM_SYST_CVR 0xE000E018 /* current value (24-bit) */
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#define CORTEXM_SYST_CALIB 0xE000E01c /* calibration */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbCortexMSysTickh */
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@@ -0,0 +1,201 @@
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||||
/* vxbHpetLib.h - vxbus high performance event timer interfaces header file */
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||||
|
||||
/*
|
||||
* Copyright (c) 2007,2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
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||||
|
||||
/*
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||||
modification history
|
||||
--------------------
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||||
01b,30oct10,j_l Fix LP64 HPET register mapping (Fix for WIND00236223).
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||||
01a,07aug07,scm written.
|
||||
*/
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||||
|
||||
/*
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||||
DESCRIPTION
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||||
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||||
This library provides the high performance event timer (HPET) specific
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definitiions.
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||||
|
||||
*/
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||||
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#ifndef _INC_vxbHpetLibH
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#define _INC_vxbHpetLibH
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* IA-PC HPET - High Precision Event Timers
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*
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* On-Multiprocessing IA-32 platforms this gives us a
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* 64-bit free running up-counter for Time Stamping Applications.
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||||
*
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* This provides a time-base that is insensitive to clock frequency
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* drifts on individual CPU's on an N-way MP system.
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||||
*/
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||||
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||||
#define IA_TIMESTAMP_NAME "iaTimestamp"
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||||
/* The HPET LPC Bridge function resides in PCI Device:31, Function:0 */
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||||
#define LPC_BUSNO 0x00
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#define LPC_DEVNO 0x1F
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||||
#define LPC_FUNCNO 0x00
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#define LPC_GEN_CNTRL 0xD0 /* 6300ESB ICH General Control Reg */
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||||
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||||
#define LPC_RCBA_REG 0xF0 /* ICH7 Root Complex Base Addr Reg */
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||||
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||||
#define RCBA_ADDR_MSK 0xFFFFC000 /* ICH7 RCBA Address Mask */
|
||||
#define RCBA_ADDR_ENBL 0x00000001 /* ICH7 RCBA Enable Bit */
|
||||
#define RCBA_MEM_ADDR_RNG 0x4000 /* ICH7 RCBA Address Block */
|
||||
|
||||
#define HPTC_REG_OFFSET 0x00003404 /* ICH7 HPTC Register Offset */
|
||||
#define HPTC_REG_MSK 0xFFFFFFFE /* ICH7 HPTC Register Mask */
|
||||
#define HPTC_ADDR_ENBL 0x00000080 /* ICH7 HPTC Address Enable Bit */
|
||||
|
||||
/* This bit enables the ICH to decode the High Performance Event Timer
|
||||
* memory Address Range...
|
||||
*
|
||||
* The registers associated with these timers sre mapped to memory space
|
||||
* much like the I/O APIC. The timer register space is 1024 bytes.
|
||||
*/
|
||||
|
||||
#define HPET_ADDR_ENABLE 0x00020000
|
||||
|
||||
/* 1 of 4 possible memory address ranges for the High Performance
|
||||
* Event Timer functionality...
|
||||
*/
|
||||
|
||||
#define HPET_ADDR_SEL_MASK 0x00018000
|
||||
|
||||
#define HPET_ADDR_SEL_00 0xFED00000
|
||||
#define HPET_ADDR_SEL_01 0xFED01000
|
||||
#define HPET_ADDR_SEL_02 0xFED02000
|
||||
#define HPET_ADDR_SEL_03 0xFED03000
|
||||
|
||||
#define HPET_MEM_ADDR_RNG 0x4000
|
||||
|
||||
/* HPET Memory-mapped Register Offsets */
|
||||
|
||||
/* General Capabilities and ID Register
|
||||
* Offset: 000-007h, RO, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_GEN_CAP_OFF 0x0000
|
||||
|
||||
#define HPET_CNTR_PER_CAP_MSK 0xffffffff00000000
|
||||
#define HPET_VNDR_ID_CAP_MSK 0x00000000ffff0000
|
||||
#define HPET_LEG_RT_CAP_MSK 0x0000000000008000
|
||||
#define HPET_CNT_SZ_CAP_MSK 0x0000000000002000
|
||||
#define HPET_NUM_TIM_CAP_MSK 0x0000000000001f00
|
||||
#define HPET_REV_ID_CAP_MSK 0x00000000000000ff
|
||||
|
||||
/* General Configuration Register
|
||||
* Offset: 010-017h, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_GEN_CON_OFF 0x0010
|
||||
|
||||
#define HPET_LEG_RT_CNF_MSK 0x0000000000000002
|
||||
#define HPET_EN_CNF_MSK 0x0000000000000001
|
||||
|
||||
/* General Interrupt Status Register
|
||||
* Offset: 020-027h, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_GEN_INT_STS_OFF 0x0020
|
||||
|
||||
#define HPET_T02_INT_STS_MSK 0x0000000000000004
|
||||
#define HPET_T01_INT_STS_MSK 0x0000000000000002
|
||||
#define HPET_T00_INT_STS_MSK 0x0000000000000001
|
||||
|
||||
/* Main counter Value Register
|
||||
* Offset: 0F0-0F7h, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_MN_CNTR_OFF 0x00F0
|
||||
|
||||
/* Timer 0 Config/Capabilities Register
|
||||
* Offset: 100-107h, RW, 64-bit
|
||||
*
|
||||
* Timer 0 Comparator Value Register
|
||||
* Offset: 108-10Fh, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_T0_CONF_OFF 0x0100
|
||||
#define HPET_T0_COMP_OFF 0x0108
|
||||
|
||||
/* Timer 1 Config/Capabilities Register
|
||||
* Offset: 120-127h, RW, 64-bit
|
||||
*
|
||||
* Timer 1 Comparator Value Register
|
||||
* Offset: 128-12Fh, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_T1_CONF_OFF 0x0120
|
||||
#define HPET_T1_COMP_OFF 0x0128
|
||||
|
||||
/* Timer 2 Config/Capabilities Register
|
||||
* Offset: 140-147h, RW, 64-bit
|
||||
*
|
||||
* Timer 2 Comparator Value Register
|
||||
* Offset: 148-14Fh, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define HPET_T2_CONF_OFF 0x0140
|
||||
#define HPET_T2_COMP_OFF 0x0148
|
||||
|
||||
/* Timer Config/Capabilities Masks */
|
||||
|
||||
#define HPET_TIMERn_INT_ROUT_CAP_MSK 0xffffffff00000000
|
||||
#define HPET_TIMERn_FSB_INT_DEL_CAP_MSK 0x0000000000008000
|
||||
#define HPET_TIMERn_FSB_EN_CNF_MSK 0x0000000000004000
|
||||
#define HPET_TIMERn_INT_ROUT_CNF_MSK 0x0000000000003e00
|
||||
#define HPET_TIMERn_32MODE_CNF_MSK 0x0000000000000100
|
||||
#define HPET_TIMERn_VAL_SET_CNF_MSK 0x0000000000000040
|
||||
#define HPET_TIMERn_SIZE_CAP_MSK 0x0000000000000020
|
||||
#define HPET_TIMERn_PER_INT_CAP_MSK 0x0000000000000010
|
||||
#define HPET_TIMERn_TYPE_CNF_MSK 0x0000000000000008
|
||||
#define HPET_TIMERn_INT_ENB_CNF_MSK 0x0000000000000004
|
||||
#define HPET_TIMERn_INT_TYPE_CNF_MSK 0x0000000000000002
|
||||
|
||||
/* IA-32 dedicated SMP Timestamp defines used in vxbIntelTimestamp.c,
|
||||
* and elsewhere...
|
||||
*/
|
||||
|
||||
/* IA-32 SMP Timestamp based off of a 64-bit free running counter.
|
||||
* IA-32 will be using HPET Timer #0, using default address range
|
||||
* HPET_ADDR_SEL_00 (0xFED00000)...
|
||||
*/
|
||||
|
||||
#define HPET_TIMESTAMP (HPET_ADDR_SEL_00)
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
IMPORT ULONG hpetTimestampAddr;
|
||||
#define HP_TS_GEN_CAP (hpetTimestampAddr + HPET_GEN_CAP_OFF)
|
||||
#define HP_TS_GEN_CON (hpetTimestampAddr + HPET_GEN_CON_OFF)
|
||||
#define HP_TS_GEN_INT_STS (hpetTimestampAddr + HPET_GEN_INT_STS_OFF)
|
||||
#define HP_TS_MN_CNTR (hpetTimestampAddr + HPET_MN_CNTR_OFF)
|
||||
#define HP_TS_T0_CONF (hpetTimestampAddr + HPET_T0_CONF_OFF)
|
||||
#define HP_TS_T0_COMP (hpetTimestampAddr + HPET_T0_COMP_OFF)
|
||||
#else
|
||||
#define HP_TS_GEN_CAP (HPET_TIMESTAMP + HPET_GEN_CAP_OFF)
|
||||
#define HP_TS_GEN_CON (HPET_TIMESTAMP + HPET_GEN_CON_OFF)
|
||||
#define HP_TS_GEN_INT_STS (HPET_TIMESTAMP + HPET_GEN_INT_STS_OFF)
|
||||
#define HP_TS_MN_CNTR (HPET_TIMESTAMP + HPET_MN_CNTR_OFF)
|
||||
#define HP_TS_T0_CONF (HPET_TIMESTAMP + HPET_T0_CONF_OFF)
|
||||
#define HP_TS_T0_COMP (HPET_TIMESTAMP + HPET_T0_COMP_OFF)
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _INC_vxbHpetLibH */
|
||||
|
||||
@@ -0,0 +1,40 @@
|
||||
/* vxbI8253Timer.h - i8253 timer device header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,25aug10,j_l Change default i8253 counter mode to mode 2 (WIND00221408).
|
||||
01a,02feb10,cwl created. (WIND00196333)
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbI8253Timerh
|
||||
#define __INCvxbI8253Timerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* operation modes for timer I8253 */
|
||||
|
||||
#define VXB_I8253_COUNTER_MODE0 0x0
|
||||
#define VXB_I8253_COUNTER_MODE1 0x02
|
||||
#define VXB_I8253_COUNTER_MODE2 0x04
|
||||
#define VXB_I8253_COUNTER_MODE3 0x06
|
||||
#define VXB_I8253_COUNTER_MODE4 0x08
|
||||
#define VXB_I8253_COUNTER_MODE5 0x0A
|
||||
#define VXB_I8253_COUNTER_MODE_DEFAULT VXB_I8253_COUNTER_MODE2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCvxbI8253Timerh */
|
||||
|
||||
@@ -0,0 +1,430 @@
|
||||
/* vxbIaHpetTimer.h - header for the Intel High Precision Event Timer (HPET) */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2011, 2013, 2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,31jan14,jb VXW6-1845 - Error in HPET reading
|
||||
01h,28jan14,jb VXW6-25700 - patch for WIND00406770 does not fix the problem
|
||||
in aux timer
|
||||
01g,25apr13,rbc WIND00414401 - Changes to support Unified BSP.
|
||||
01f,18mar13,jb WIND00406770 - iaHpetTimerInt() -> wrong calculation of next
|
||||
timeout
|
||||
01e,07oct11,sem WIND00310639 - Remove timer drift. Revise oneshot API.
|
||||
01d,02aug11,sem Fix HPET interrupts - WIND00287725
|
||||
01c,22jul11,sem Update timestamp name define
|
||||
01b,14jul11,sem Update 64-bit counter read
|
||||
01a,05may11,sem initial version
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbIaHpetTimerh
|
||||
#define __INCvxbIaHpetTimerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IA HPET - High Precision Event Timers
|
||||
*
|
||||
* On IA platforms this gives us a
|
||||
* 64-bit free running up-counter for Time Stamping Applications.
|
||||
*
|
||||
* This provides a time-base that is insensitive to clock frequency
|
||||
* drifts on individual CPU's on an N-way MP system.
|
||||
*/
|
||||
|
||||
#define IA_TIMESTAMP_NAME "iaTimestamp"
|
||||
|
||||
#ifndef IA_HPET_TIMER_NAME
|
||||
#define IA_HPET_TIMER_NAME "iaHpetTimerDev"
|
||||
#endif /* IA_HPET_TIMER_NAME */
|
||||
|
||||
#define IA_HPET_TIMER_CLK_FREQ 14318179
|
||||
|
||||
/* HPET timer IDs */
|
||||
|
||||
#define IA_HPET_TIMER0 0x0 /* Timer 0 Id */
|
||||
#define IA_HPET_TIMER1 0x1 /* Timer 1 Id */
|
||||
#define IA_HPET_TIMER2 0x2 /* Timer 2 Id */
|
||||
#define IA_HPET_TIMER3 0x3 /* Timer 3 Id */
|
||||
#define IA_HPET_TIMER4 0x4 /* Timer 4 Id */
|
||||
#define IA_HPET_TIMER5 0x5 /* Timer 5 Id */
|
||||
#define IA_HPET_TIMER6 0x6 /* Timer 6 Id */
|
||||
#define IA_HPET_TIMER7 0x7 /* Timer 7 Id */
|
||||
#define IA_HPET_TIMER_MAX 0x8 /* Max timer Ids */
|
||||
|
||||
/* HPET timer operational modes */
|
||||
|
||||
#ifdef _WRS_CONFIG_PWR_MGMT
|
||||
|
||||
/* Maintain Power Mgmt functionality */
|
||||
|
||||
#define IA_HPET_TIMER_MODE_PERIODIC 0x00 /* Periodic timer */
|
||||
#define IA_HPET_TIMER_MODE_ONESHOT32 0x01 /* 32-bit one-shot timer */
|
||||
#define IA_HPET_TIMER_MODE_ONESHOT64 0x02 /* 64-bit one-shot timer */
|
||||
|
||||
#else
|
||||
|
||||
#define IA_HPET_TIMER_MODE_PERIODIC 0x01 /* Periodic timer */
|
||||
#define IA_HPET_TIMER_MODE_HW_PERIODIC 0x03 /* Timer supports H/W periodic */
|
||||
/* mode */
|
||||
#define IA_HPET_TIMER_MODE_ONESHOT32 0x04 /* 32-bit one-shot timer */
|
||||
#define IA_HPET_TIMER_MODE_ONESHOT64 0x08 /* 64-bit one-shot timer */
|
||||
|
||||
#endif /* _WRS_CONFIG_PWR_MGMT */
|
||||
|
||||
/* interrupt routing for HPET comparators */
|
||||
|
||||
#define INT_NUM_IA_HPET_TIMER0 0x14 /* Timer 0 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER1 0x15 /* Timer 1 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER2 0x16 /* Timer 2 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER3 0x17 /* Timer 3 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER4 0x18 /* Timer 4 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER5 0x19 /* Timer 5 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER6 0x1A /* Timer 6 interrupt */
|
||||
#define INT_NUM_IA_HPET_TIMER7 0x1B /* Timer 7 interrupt */
|
||||
|
||||
/* The HPET LPC Bridge function resides in PCI Device:31, Function:0 */
|
||||
|
||||
#define LPC_BUSNO 0x00
|
||||
#define LPC_DEVNO 0x1F
|
||||
#define LPC_FUNCNO 0x00
|
||||
#define LPC_DID_6300ESB 0x25A1
|
||||
#define LPC_DID_ICH5 0x24D0
|
||||
#define LPC_GEN_CNTRL 0xD0 /* 6300ESB ICH General Control */
|
||||
/* Reg */
|
||||
|
||||
#define LPC_RCBA_REG 0xF0 /* ICH7 Root Complex Base Addr */
|
||||
/* Reg */
|
||||
|
||||
#define RCBA_REG_BASE 1
|
||||
#define RCBA_ADDR_MSK 0xFFFFC000 /* ICH7 RCBA Address Mask */
|
||||
#define RCBA_ADDR_ENBL 0x00000001 /* ICH7 RCBA Enable Bit */
|
||||
#define RCBA_MEM_ADDR_RNG 0x4000 /* ICH7 RCBA Address Block */
|
||||
|
||||
#define IA_HPETTC_REG_OFFSET 0x00003404 /* ICH7 HPTC Register Offset */
|
||||
#define IA_HPETTC_REG_MSK 0xFFFFFFFE /* ICH7 HPTC Register Mask */
|
||||
#define IA_HPETTC_ADDR_ENBL 0x00000080 /* ICH7 HPTC Address Enable Bit */
|
||||
|
||||
/*
|
||||
* This bit enables the ICH to decode the High Performance Event Timer
|
||||
* memory Address Range...
|
||||
*
|
||||
* The registers associated with these timers are mapped to memory space
|
||||
* much like the I/O APIC. The timer register space is 1024 bytes.
|
||||
*/
|
||||
|
||||
#define IA_HPET_ADDR_ENABLE 0x00020000
|
||||
|
||||
/*
|
||||
* 1 of 4 possible memory address ranges for the High Performance
|
||||
* Event Timer functionality...
|
||||
*/
|
||||
|
||||
#define IA_HPET_ADDR_SEL_MASK 0x00018000
|
||||
|
||||
#define IA_HPET_ADDR_SEL_00 0xFED00000
|
||||
#define IA_HPET_ADDR_SEL_01 0xFED01000
|
||||
#define IA_HPET_ADDR_SEL_02 0xFED02000
|
||||
#define IA_HPET_ADDR_SEL_03 0xFED03000
|
||||
|
||||
#define IA_HPET_MEM_ADDR_RNG 0x4000
|
||||
|
||||
/* HPET Memory-mapped Register Offsets */
|
||||
|
||||
/*
|
||||
* General Capabilities and ID Register
|
||||
* Offset: 000-007h, RO, 64-bit
|
||||
*/
|
||||
|
||||
#define IA_HPET_GEN_CAP_OFF 0x0000
|
||||
|
||||
#define IA_HPET_CNTR_PER_CAP_MSK 0xffffffff00000000
|
||||
#define IA_HPET_VNDR_ID_CAP_MSK 0x00000000ffff0000
|
||||
#define IA_HPET_LEG_RT_CAP_MSK 0x0000000000008000
|
||||
#define IA_HPET_CNT_SZ_CAP_MSK 0x0000000000002000
|
||||
#define IA_HPET_NUM_TIM_CAP_MSK 0x0000000000001f00
|
||||
#define IA_HPET_REV_ID_CAP_MSK 0x00000000000000ff
|
||||
|
||||
/*
|
||||
* General Configuration Register
|
||||
* Offset: 010-017h, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define IA_HPET_GEN_CON_OFF 0x0010
|
||||
|
||||
#define IA_HPET_LEG_RT_CNF_MSK 0x0000000000000002
|
||||
#define IA_HPET_EN_CNF_MSK 0x0000000000000001
|
||||
|
||||
/*
|
||||
* General Interrupt Status Register
|
||||
* Offset: 020-027h, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define IA_HPET_INT_STS_OFF 0x0020
|
||||
|
||||
#define IA_HPET_T00_INT_STS_MSK 0x0000000000000001
|
||||
#define IA_HPET_T01_INT_STS_MSK 0x0000000000000002
|
||||
#define IA_HPET_T02_INT_STS_MSK 0x0000000000000004
|
||||
|
||||
/*
|
||||
* Main counter Value Register
|
||||
* Offset: 0F0-0F7h, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define IA_HPET_MN_CNTR_OFF 0x00F0
|
||||
|
||||
/*
|
||||
* Timer Config/Capabilities Registers
|
||||
* Offset: 20h, relative to each register
|
||||
*/
|
||||
|
||||
#define IA_HPET_TIMER_CONF_OFF 0x0020
|
||||
|
||||
/*
|
||||
* Timer Comparator Registers
|
||||
* Offset: 20h, relative to each comparator
|
||||
*/
|
||||
|
||||
#define IA_HPET_TIMER_COMP_OFF 0x0020
|
||||
|
||||
/*
|
||||
* Timer MSI Configuration Registers
|
||||
* Offset: 20h, relative to each comparator
|
||||
*/
|
||||
|
||||
#define IA_HPET_TIMER_MSI_OFF 0x0020
|
||||
|
||||
/*
|
||||
* Timer Config/Capabilities Register
|
||||
* Offset: 100-107h, RW, 64-bit
|
||||
*
|
||||
* Timer Comparator Value Register
|
||||
* Offset: 108-10Fh, RW, 64-bit
|
||||
*
|
||||
* Timer MSI Config Value Register
|
||||
* Offset: 110-10Fh, RW, 64-bit
|
||||
*/
|
||||
|
||||
#define IA_HPET_T0_CONF_OFF 0x0100
|
||||
#define IA_HPET_T0_COMP_OFF 0x0108
|
||||
#define IA_HPET_T0_MSI_OFF 0x0110
|
||||
|
||||
#define IA_HPET_T1_CONF_OFF 0x0120
|
||||
#define IA_HPET_T1_COMP_OFF 0x0128
|
||||
#define IA_HPET_T1_MSI_OFF 0x0130
|
||||
|
||||
#define IA_HPET_T2_CONF_OFF 0x0140
|
||||
#define IA_HPET_T2_COMP_OFF 0x0148
|
||||
#define IA_HPET_T2_MSI_OFF 0x0150
|
||||
|
||||
#define IA_HPET_T3_CONF_OFF 0x0160
|
||||
#define IA_HPET_T3_COMP_OFF 0x0168
|
||||
#define IA_HPET_T3_MSI_OFF 0x0170
|
||||
|
||||
#define IA_HPET_T4_CONF_OFF 0x0180
|
||||
#define IA_HPET_T4_COMP_OFF 0x0188
|
||||
#define IA_HPET_T4_MSI_OFF 0x0180
|
||||
|
||||
#define IA_HPET_T5_CONF_OFF 0x01a0
|
||||
#define IA_HPET_T5_COMP_OFF 0x01a8
|
||||
#define IA_HPET_T5_MSI_OFF 0x01b0
|
||||
|
||||
#define IA_HPET_T6_CONF_OFF 0x01c0
|
||||
#define IA_HPET_T6_COMP_OFF 0x01c8
|
||||
#define IA_HPET_T6_MSI_OFF 0x01d0
|
||||
|
||||
#define IA_HPET_T7_CONF_OFF 0x01e0
|
||||
#define IA_HPET_T7_COMP_OFF 0x01e8
|
||||
#define IA_HPET_T7_MSI_OFF 0x01f0
|
||||
|
||||
/* Timer Config/Capabilities Masks */
|
||||
|
||||
#define IA_HPET_TIMERn_INT_ROUT_CAP_MSK 0xffffffff00000000
|
||||
#define IA_HPET_TIMERn_MSI_INT_DEL_CAP_MSK 0x0000000000008000
|
||||
#define IA_HPET_TIMERn_MSI_EN_CNF_MSK 0x0000000000004000
|
||||
#define IA_HPET_TIMERn_INT_ROUT_CNF_MSK 0x0000000000003e00
|
||||
#define IA_HPET_TIMERn_32MODE_CNF_MSK 0x0000000000000100
|
||||
#define IA_HPET_TIMERn_VAL_SET_CNF_MSK 0x0000000000000040
|
||||
#define IA_HPET_TIMERn_SIZE_CAP_MSK 0x0000000000000020
|
||||
#define IA_HPET_TIMERn_PER_INT_CAP_MSK 0x0000000000000010
|
||||
#define IA_HPET_TIMERn_TYPE_CNF_MSK 0x0000000000000008
|
||||
#define IA_HPET_TIMERn_INT_ENB_CNF_MSK 0x0000000000000004
|
||||
#define IA_HPET_TIMERn_INT_TYPE_CNF_MSK 0x0000000000000002
|
||||
|
||||
/*
|
||||
* IA Timestamp based off of a 64-bit free running counter
|
||||
* using default address range HPET_ADDR_SEL_00 (0xFED00000).
|
||||
* This address should be obtained from ACPI tables, however
|
||||
* the associated ACPI tables are initialized after the HPET timer
|
||||
* driver is instantiated by VxBus.
|
||||
*/
|
||||
|
||||
#define IA_HPET_BASE_ADDR (IA_HPET_ADDR_SEL_00)
|
||||
#define IA_HPET_REG_BASE (IA_HPET_GEN_CAP_OFF)
|
||||
|
||||
#ifndef _WRS_CONFIG_LP64
|
||||
IMPORT UINT vxbIaHpetBaseAddr;
|
||||
|
||||
/* HPET register definitions */
|
||||
|
||||
#define IA_HPET_GEN_CAP (IA_HPET_BASE_ADDR + IA_HPET_GEN_CAP_OFF)
|
||||
#define IA_HPET_GEN_CON (IA_HPET_BASE_ADDR + IA_HPET_GEN_CON_OFF)
|
||||
#define IA_HPET_INT_STS (IA_HPET_BASE_ADDR + IA_HPET_INT_STS_OFF)
|
||||
#define IA_HPET_MN_CNTR (IA_HPET_BASE_ADDR + IA_HPET_MN_CNTR_OFF)
|
||||
|
||||
#define IA_HPET_T0_CONF (IA_HPET_BASE_ADDR + IA_HPET_T0_CONF_OFF)
|
||||
#define IA_HPET_T0_COMP (IA_HPET_BASE_ADDR + IA_HPET_T0_COMP_OFF)
|
||||
#define IA_HPET_T0_MSI (IA_HPET_BASE_ADDR + IA_HPET_T0_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T1_CONF (IA_HPET_BASE_ADDR + IA_HPET_T1_CONF_OFF)
|
||||
#define IA_HPET_T1_COMP (IA_HPET_BASE_ADDR + IA_HPET_T1_COMP_OFF)
|
||||
#define IA_HPET_T1_MSI (IA_HPET_BASE_ADDR + IA_HPET_T1_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T2_CONF (IA_HPET_BASE_ADDR + IA_HPET_T2_CONF_OFF)
|
||||
#define IA_HPET_T2_COMP (IA_HPET_BASE_ADDR + IA_HPET_T2_COMP_OFF)
|
||||
#define IA_HPET_T2_MSI (IA_HPET_BASE_ADDR + IA_HPET_T2_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T3_CONF (IA_HPET_BASE_ADDR + IA_HPET_T3_CONF_OFF)
|
||||
#define IA_HPET_T3_COMP (IA_HPET_BASE_ADDR + IA_HPET_T3_COMP_OFF)
|
||||
#define IA_HPET_T3_MSI (IA_HPET_BASE_ADDR + IA_HPET_T3_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T4_CONF (IA_HPET_BASE_ADDR + IA_HPET_T4_CONF_OFF)
|
||||
#define IA_HPET_T4_COMP (IA_HPET_BASE_ADDR + IA_HPET_T4_COMP_OFF)
|
||||
#define IA_HPET_T4_MSI (IA_HPET_BASE_ADDR + IA_HPET_T4_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T5_CONF (IA_HPET_BASE_ADDR + IA_HPET_T5_CONF_OFF)
|
||||
#define IA_HPET_T5_COMP (IA_HPET_BASE_ADDR + IA_HPET_T5_COMP_OFF)
|
||||
#define IA_HPET_T5_MSI (IA_HPET_BASE_ADDR + IA_HPET_T5_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T6_CONF (IA_HPET_BASE_ADDR + IA_HPET_T6_CONF_OFF)
|
||||
#define IA_HPET_T6_COMP (IA_HPET_BASE_ADDR + IA_HPET_T6_COMP_OFF)
|
||||
#define IA_HPET_T6_MSI (IA_HPET_BASE_ADDR + IA_HPET_T6_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T7_CONF (IA_HPET_BASE_ADDR + IA_HPET_T7_CONF_OFF)
|
||||
#define IA_HPET_T7_COMP (IA_HPET_BASE_ADDR + IA_HPET_T7_COMP_OFF)
|
||||
#define IA_HPET_T7_MSI (IA_HPET_BASE_ADDR + IA_HPET_T7_MSI_OFF)
|
||||
|
||||
#else
|
||||
|
||||
IMPORT ULONG vxbIaHpetBaseAddr;
|
||||
|
||||
#define IA_HPET_GEN_CAP (vxbIaHpetBaseAddr + IA_HPET_GEN_CAP_OFF)
|
||||
#define IA_HPET_GEN_CON (vxbIaHpetBaseAddr + IA_HPET_GEN_CON_OFF)
|
||||
#define IA_HPET_INT_STS (vxbIaHpetBaseAddr + IA_HPET_INT_STS_OFF)
|
||||
#define IA_HPET_MN_CNTR (vxbIaHpetBaseAddr + IA_HPET_MN_CNTR_OFF)
|
||||
|
||||
#define IA_HPET_T0_CONF (vxbIaHpetBaseAddr + IA_HPET_T0_CONF_OFF)
|
||||
#define IA_HPET_T0_COMP (vxbIaHpetBaseAddr + IA_HPET_T0_COMP_OFF)
|
||||
#define IA_HPET_T0_MSI (vxbIaHpetBaseAddr + IA_HPET_T0_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T1_CONF (vxbIaHpetBaseAddr + IA_HPET_T1_CONF_OFF)
|
||||
#define IA_HPET_T1_COMP (vxbIaHpetBaseAddr + IA_HPET_T1_COMP_OFF)
|
||||
#define IA_HPET_T1_MSI (vxbIaHpetBaseAddr + IA_HPET_T1_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T2_CONF (vxbIaHpetBaseAddr + IA_HPET_T2_CONF_OFF)
|
||||
#define IA_HPET_T2_COMP (vxbIaHpetBaseAddr + IA_HPET_T2_COMP_OFF)
|
||||
#define IA_HPET_T2_MSI (vxbIaHpetBaseAddr + IA_HPET_T2_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T3_CONF (vxbIaHpetBaseAddr + IA_HPET_T3_CONF_OFF)
|
||||
#define IA_HPET_T3_COMP (vxbIaHpetBaseAddr + IA_HPET_T3_COMP_OFF)
|
||||
#define IA_HPET_T3_MSI (vxbIaHpetBaseAddr + IA_HPET_T3_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T4_CONF (vxbIaHpetBaseAddr + IA_HPET_T4_CONF_OFF)
|
||||
#define IA_HPET_T4_COMP (vxbIaHpetBaseAddr + IA_HPET_T4_COMP_OFF)
|
||||
#define IA_HPET_T4_MSI (vxbIaHpetBaseAddr + IA_HPET_T4_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T5_CONF (vxbIaHpetBaseAddr + IA_HPET_T5_CONF_OFF)
|
||||
#define IA_HPET_T5_COMP (vxbIaHpetBaseAddr + IA_HPET_T5_COMP_OFF)
|
||||
#define IA_HPET_T5_MSI (vxbIaHpetBaseAddr + IA_HPET_T5_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T6_CONF (vxbIaHpetBaseAddr + IA_HPET_T6_CONF_OFF)
|
||||
#define IA_HPET_T6_COMP (vxbIaHpetBaseAddr + IA_HPET_T6_COMP_OFF)
|
||||
#define IA_HPET_T6_MSI (vxbIaHpetBaseAddr + IA_HPET_T6_MSI_OFF)
|
||||
|
||||
#define IA_HPET_T7_CONF (vxbIaHpetBaseAddr + IA_HPET_T7_CONF_OFF)
|
||||
#define IA_HPET_T7_COMP (vxbIaHpetBaseAddr + IA_HPET_T7_COMP_OFF)
|
||||
#define IA_HPET_T7_MSI (vxbIaHpetBaseAddr + IA_HPET_T7_MSI_OFF)
|
||||
|
||||
#endif /* !_WRS_CONFIG_LP64 */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#define IA_HPET_GEN_READ64(addr, value) (value = (*(volatile UINT64 *)addr))
|
||||
#define IA_HPET_GEN_WRITE64(addr, value) ((*(volatile UINT64 *)addr) = value)
|
||||
#define IA_HPET_GEN_READ32(addr, value) (value = (*(volatile UINT32 *)addr))
|
||||
#define IA_HPET_GEN_WRITE32(addr, value) ((*(volatile UINT32 *)addr) = value)
|
||||
|
||||
#define IA_HPET_TIMERn_READ64(base, id, value) (value = *(volatile UINT64 *)\
|
||||
(base + id * 0x20))
|
||||
#define IA_HPET_TIMERn_WRITE64(base, id, value) (*(volatile UINT64 *)\
|
||||
(base + id * 0x20) = value)
|
||||
#define IA_HPET_TIMERn_READ32(base, id, value) (value = *(volatile UINT32 *)\
|
||||
(base + id * 0x20))
|
||||
#define IA_HPET_TIMERn_WRITE32(base, id, value) (*(volatile UINT32 *)\
|
||||
(base + id * 0x20) = value)
|
||||
|
||||
LOCAL __inline__ UINT64 iaHpetRead64 (void)
|
||||
{
|
||||
UINT64 value;
|
||||
|
||||
value = *(volatile UINT64 *)IA_HPET_MN_CNTR;
|
||||
|
||||
#ifndef _WRS_CONFIG_LP64
|
||||
if (((*(volatile UINT64 *)IA_HPET_MN_CNTR) & 0x00000000ffffffffULL) <
|
||||
(value & 0x00000000ffffffffULL))
|
||||
value = *(volatile UINT64 *)IA_HPET_MN_CNTR;
|
||||
#endif
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/* macros */
|
||||
|
||||
#define IA_HPET_READ32(value) value = *(volatile UINT32 *)IA_HPET_MN_CNTR
|
||||
#define IA_HPET_READ64(value) value = iaHpetRead64()
|
||||
|
||||
#undef HPET_DEBUG
|
||||
|
||||
#if defined (HPET_DEBUG)
|
||||
IMPORT void earlyPrint (char * outString);
|
||||
#endif /* HPET_DEBUG */
|
||||
|
||||
IMPORT BOOL vxbDelayTimerFreeRunning;
|
||||
|
||||
IMPORT STATUS sysMmuMapAdd();
|
||||
|
||||
IMPORT UINT8 *sysInumTbl; /* IRQ vs intNum table */
|
||||
|
||||
IMPORT unsigned int vxCpuLoApicId (void);
|
||||
|
||||
/* prototypes */
|
||||
|
||||
IMPORT void vxbIaHpetTimerDrvRegister (void);
|
||||
|
||||
IMPORT STATUS iaHpetOneShotEnable (VXB_DEVICE_ID pInst,
|
||||
UINT32 timerId,
|
||||
UINT64 timeoutTs,
|
||||
void *pIsr,
|
||||
UINT32 arg);
|
||||
IMPORT UINT64 iaHpetOneShotDisable (VXB_DEVICE_ID pInst, UINT32 timerId);
|
||||
IMPORT UINT64 iaHpetTimerBaseGet (VXB_DEVICE_ID pInst, UINT32 timerId);
|
||||
IMPORT UINT64 iaHpetTimerPeriodGet (VXB_DEVICE_ID pInst, UINT32 timerId);
|
||||
IMPORT UINT32 iaHpetTimerFreqGet (VXB_DEVICE_ID pInst, UINT32 timerId);
|
||||
IMPORT void iaHpetTimerCfgShow (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCvxbIaHpetTimerh */
|
||||
@@ -0,0 +1,54 @@
|
||||
/* vxbIntelTimestampP.h - private Intel Architecture timestamp header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,02aug11,j_l WIND00255353: created
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbIntelTimestampPh
|
||||
#define __INCvxbIntelTimestampPh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* structure holding timestamp details */
|
||||
|
||||
struct iaTimestampData
|
||||
{
|
||||
struct vxbTimerFunctionality timerFunc; /*
|
||||
* functionality of the timer
|
||||
* used by the
|
||||
* application/timer library
|
||||
*/
|
||||
UINT32 divider; /* */
|
||||
VXB_DEVICE_ID pInst; /* instance pointer */
|
||||
spinlockIsr_t lock; /* spin lock for protection */
|
||||
BOOL timerInitialized;/* timer initialized flag */
|
||||
UINT32 timestampBase; /* timestamp base value */
|
||||
WDOG_ID wdId; /* watchdog id */
|
||||
BOOL hpetUsed; /* indicate whether HPET is used */
|
||||
};
|
||||
|
||||
/* structure to be used in watchdog timer function */
|
||||
|
||||
struct iaTimestampWdData
|
||||
{
|
||||
UINT32 initialCount; /* initial count */
|
||||
struct iaTimestampData * pTimerData; /* timestamp data */
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbIntelTimestampPh */
|
||||
@@ -0,0 +1,57 @@
|
||||
|
||||
/* vxbK70Timer.h - vxbus Freescale K70 timer header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,20jun13,mpc written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This file provides the ARM Cortex-M Freescale K70 timer specific definitions.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbK70Timerh
|
||||
#define __INCvxbK70Timerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define K70_TIMER_NAME "vxbK70Timer"
|
||||
|
||||
/* register offset */
|
||||
|
||||
#define K70_PIT_MCR 0x0 /* PIT Module Control Register offset */
|
||||
|
||||
#define K70_PIT_LDVAL 0x0 /* Timer Load Value Register offset */
|
||||
|
||||
#define K70_PIT_CVAL 0x4 /* Current Timer Value Register offset */
|
||||
|
||||
#define K70_PIT_TCTRL 0x8 /* Timer Control Register offset */
|
||||
|
||||
#define K70_PIT_TFLG 0xc /* Timer Flag Register offset */
|
||||
|
||||
#define K70_PIT_TCTRL_TIE 0x2 /* Timer Interrupt Enable */
|
||||
#define K70_PIT_TCTRL_TEN 0x1 /* Timer Enable */
|
||||
|
||||
#define K70_PIT_TFLG_TIF 0x1 /* Timer Interrupt Flag */
|
||||
|
||||
#define K70_PIT_MCR_FRZ 0x1 /* Freeze in debug */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbK70Timerh */
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
/* vxbOmap35xxTimer.h - vxbus OMAP35xx timer interfaces header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008-2011, 2015 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
14jan15,swu added support for AM437x. (US51994)
|
||||
01d,13jul11,clx add dm81xx timer support
|
||||
01c,07oct10,rec add tickless-idle support functions
|
||||
01b,02mar09,m_h Cleanup
|
||||
01a,08jul08,m_h written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This file provides the OMAP timers specific definitions.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbOmap35xxTimerh
|
||||
#define __INCvxbOmap35xxTimerh
|
||||
|
||||
#include <vxBusLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Maximum number of timers */
|
||||
#define OMAP35XX_MAX_TIMERS 12
|
||||
|
||||
/*
|
||||
* These base addresses are used for purposes of identifying which timer is
|
||||
* being used
|
||||
*/
|
||||
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER1 0x48318000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER2 0x49032000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER3 0x49034000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER4 0x49036000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER5 0x49038000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER6 0x4903A000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER7 0x4903C000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER8 0x4903E000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER9 0x49040000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER10 0x48086000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER11 0x48088000
|
||||
#define OMAP35XX_BASE_ADDR_GPTIMER12 0x48304000
|
||||
|
||||
#define OMAP35XX_BASE_ADDR_CM_CLKOUT_CTRL 0x48004D70
|
||||
|
||||
|
||||
/* GP Timer offsets */
|
||||
|
||||
#define OMAP35XX_TIMER_TIOCP_CFG_OFFSET 0x010
|
||||
#define OMAP35XX_TIMER_TISTAT_OFFSET 0x014
|
||||
#define OMAP35XX_TIMER_TISR_OFFSET 0x018
|
||||
#define OMAP35XX_TIMER_TIER_OFFSET 0x01C
|
||||
#define OMAP35XX_TIMER_TWER_OFFSET 0x020
|
||||
#define OMAP35XX_TIMER_TCLR_OFFSET 0x024
|
||||
#define OMAP35XX_TIMER_TCRR_OFFSET 0x028
|
||||
#define OMAP35XX_TIMER_TLDR_OFFSET 0x02C
|
||||
#define OMAP35XX_TIMER_TTGR_OFFSET 0x030
|
||||
#define OMAP35XX_TIMER_TWPS_OFFSET 0x034
|
||||
#define OMAP35XX_TIMER_TMAR_OFFSET 0x038
|
||||
#define OMAP35XX_TIMER_TCAR1_OFFSET 0x03C
|
||||
#define OMAP35XX_TIMER_TSICR_OFFSET 0x040
|
||||
#define OMAP35XX_TIMER_TCAR2_OFFSET 0x044
|
||||
#define OMAP35XX_TIMER_TPIR_OFFSET 0x048
|
||||
#define OMAP35XX_TIMER_TNIR_OFFSET 0x04C
|
||||
#define OMAP35XX_TIMER_TCVR_OFFSET 0x050
|
||||
#define OMAP35XX_TIMER_TOCR_OFFSET 0x054
|
||||
#define OMAP35XX_TIMER_TOWR_OFFSET 0x058
|
||||
|
||||
/* DM81xx GP Timer offsets */
|
||||
|
||||
#define DM81XX_TIMER_IRQSTATUS_OFFSET 0x028
|
||||
#define DM81XX_TIMER_IRQSTATUS_SET_OFFSET 0x02C
|
||||
#define DM81XX_TIMER_IRQWAKEEN_OFFSET 0x034
|
||||
#define DM81XX_TIMER_TIOCP_CFG_OFFSET 0x010
|
||||
#define DM81XX_TIMER_TCLR_OFFSET 0x038
|
||||
#define DM81XX_TIMER_TCRR_OFFSET 0x03C
|
||||
#define DM81XX_TIMER_TLDR_OFFSET 0x040
|
||||
#define DM81XX_TIMER_TTGR_OFFSET 0x044
|
||||
#define DM81XX_TIMER_TWPS_OFFSET 0x048
|
||||
#define DM81XX_TIMER_TMAR_OFFSET 0x04C
|
||||
#define DM81XX_TIMER_TCAR1_OFFSET 0x050
|
||||
#define DM81XX_TIMER_TSICR_OFFSET 0x054
|
||||
#define DM81XX_TIMER_TCAR2_OFFSET 0x058
|
||||
|
||||
#define TIMER_W_PEND_TCLR 0x1
|
||||
#define TIMER_W_PEND_TCRR 0x2
|
||||
#define TIMER_W_PEND_TLDR 0x4
|
||||
#define TIMER_W_PEND_TTGR 0x8
|
||||
#define TIMER_W_PEND_TMAR 0x10
|
||||
#define TIMER_W_PEND_TPIR 0x20
|
||||
#define TIMER_W_PEND_TNIR 0x40
|
||||
#define TIMER_W_PEND_TCVR 0x80
|
||||
#define TIMER_W_PEND_TOCR 0x100
|
||||
#define TIMER_W_PEND_TOWR 0x200
|
||||
|
||||
#define TIMER_POSTED 0x4
|
||||
|
||||
#define OMAP35XX_TIMER_ID_OFFSET (0x0)
|
||||
|
||||
/* AM437x Timer ID */
|
||||
|
||||
#define AM437X_DMTIMER_ID (0x4FFF0301)
|
||||
#define AM437X_DMTIMER_1MS_ID (0x15)
|
||||
|
||||
/* AM335x Timer ID */
|
||||
|
||||
#define AM335X_DMTIMER_ID (0x40001000)
|
||||
#define AM335X_DMTIMER_1MS_ID (0x15)
|
||||
|
||||
/* AM389x Timer ID */
|
||||
|
||||
#define AM389X_DMTIMER_ID (0x4FFF1301)
|
||||
|
||||
/* prototypes */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
IMPORT void omap35xxOneShotEnable (VXB_DEVICE_ID pInst, UINT32 nTicks);
|
||||
IMPORT UINT32 omap35xxOneShotDisable (VXB_DEVICE_ID pInst);
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbOmap35xxTimerh */
|
||||
@@ -0,0 +1,134 @@
|
||||
|
||||
/* vxbStm32fTimer.h - vxbus STM32F20x/STM32F21x timer header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute or otherwise make use of this software
|
||||
* may be licensed only pursuant to the terms of an applicable Wind River
|
||||
* license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,26apr12,rec written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This file provides the ARM Cortex-M STM32F20x/STM32F21x General Purpose timer
|
||||
specific definitions
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbStm32fTimerh
|
||||
#define __INCvxbStm32fTimerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define STM32F_TIMER_NAME "vxbStm32fTimer"
|
||||
|
||||
/* Control Register 1 */
|
||||
#define STM32FTIM_CR1 0x0000 /* Register offset */
|
||||
#define STM32FTIM_CR1CEN 0x00000001 /* Counter enable */
|
||||
#define STM32FTIM_CR1UDIS 0x00000002 /* Update disable */
|
||||
#define STM32FTIM_CR1URS 0x00000004 /* Update request src, 1=overflow only*/
|
||||
#define STM32FTIM_CR1OPM 0x00000008 /* One pules mode */
|
||||
#define STM32FTIM_CR1DIR 0x00000010 /* Direction, 1=down */
|
||||
#define STM32FTIM_CR1CMSMSK 0x00000060 /* Center-aligned mask (leave zero) */
|
||||
#define STM32FTIM_CR1ARPE 0x00000080 /* Auto-reload preload enable */
|
||||
#define STM32FTIM_CR1CKDMSK 0x00000300 /* Clock division mask */
|
||||
#define STM32FTIM_CR1CKD1X 0x00000000 /* Clock division 1x */
|
||||
#define STM32FTIM_CR1CKD2X 0x00000100 /* Clock division 2x */
|
||||
#define STM32FTIM_CR1CKD4x 0x00000200 /* Clock division 4x */
|
||||
|
||||
/* Control Register 2 */
|
||||
#define STM32FTIM_CR2 0x0004 /* Register offset */
|
||||
#define STM32FTIM_CR2CCDS 0x00000008 /* Capture/compare DMA selection */
|
||||
#define STM32FTIM_CR2MMSMSK 0x00000070 /* Master mode selection mask */
|
||||
#define STM32FTIM_CR2TI1S 0x00000080 /* TI1 selection */
|
||||
|
||||
/* Slave Mode Control Register */
|
||||
#define STM32FTIM_SMCR 0x0008 /* Register offset */
|
||||
#define STM32FTIM_SMCRSMSMSK 0x00000003 /* Slave mode select mask */
|
||||
#define STM32FTIM_SMCRTSMSK 0x00000070 /* Trigger selection mask */
|
||||
#define STM32FTIM_SMCRMSMMSK 0x00000080 /* Master/slave mode */
|
||||
#define STM32FTIM_SMCRETFMSK 0x00000F00 /* External trigger filter mask */
|
||||
#define STM32FTIM_SMCRETPSOFF 0x00000000 /* External trigger prescaler OFF */
|
||||
#define STM32FTIM_SMCRETPS2 0x00001000 /* External trigger prescale /2 */
|
||||
#define STM32FTIM_SMCRETPS4 0x00002000 /* External trigger prescale /4 */
|
||||
#define STM32FTIM_SMCRETPS8 0x00003000 /* External trigger prescale /8 */
|
||||
#define STM32FTIM_SMCRECE 0x00004000 /* External clock enable */
|
||||
#define STM32FTIM_SMCRETP 0x00008000 /* External trigger polarity 1=low>hi */
|
||||
|
||||
/* DMA/Interrupt Enable Register */
|
||||
#define STM32FTIM_DIER 0x0000C /* Register offset */
|
||||
#define STM32FTIM_DIERUIE 0x00000001 /* Update interrupt enable */
|
||||
#define STM32FTIM_DIERCC1IE 0x00000002 /* Capture/Compare 1 interrupt enable */
|
||||
#define STM32FTIM_DIERCC2IE 0x00000004 /* Capture/Compare 2 interrupt enable */
|
||||
#define STM32FTIM_DIERCC3IE 0x00000008 /* Capture/Compare 3 interrupt enable */
|
||||
#define STM32FTIM_DIERCC4IE 0x00000010 /* Capture/Compare 4 interrupt enable */
|
||||
#define STM32FTIM_DIERTIE 0x00000040 /* Trigger interrupt enable */
|
||||
#define STM32FTIM_DIERUDE 0x00000100 /* Update DMA request enble */
|
||||
#define STM32FTIM_DIERCC1DE 0x00000200 /* Capture/Compare 1 DMA req enable */
|
||||
#define STM32FTIM_DIERCC2DE 0x00000400 /* Capture/Compare 2 DMA req enable */
|
||||
#define STM32FTIM_DIERCC3DE 0x00000800 /* Capture/Compare 3 DMA req enable */
|
||||
#define STM32FTIM_DIERCC4DE 0x00001000 /* Capture/Compare 4 DMA req enable */
|
||||
#define STM32FTIM_DIERTDE 0x00004000 /* Trigger DMA request enable */
|
||||
|
||||
/* Timer Status Register */
|
||||
#define STM32FTIM_SR 0x0010 /* Register offset */
|
||||
#define STM32FTIM_SRUIF 0x00000001 /* Update interrupt flag */
|
||||
#define STM32FTIM_SRCC1IF 0x00000002 /* Capture/compare 1 interrupt flag */
|
||||
#define STM32FTIM_SRCC2IF 0x00000004 /* Capture/compare 2 interrupt flag */
|
||||
#define STM32FTIM_SRCC3IF 0x00000008 /* Capture/compare 3 interrupt flag */
|
||||
#define STM32FTIM_SRCC4IF 0x00000010 /* Capture/compare 4 interrupt flag */
|
||||
#define STM32FTIM_SRTIF 0x00000040 /* Trigger interrupt flag */
|
||||
#define STM32FTIM_SRCC1OF 0x00000200 /* Capture/compare 1 overcapture flag */
|
||||
#define STM32FTIM_SRCC2OF 0x00000400 /* Capture/compare 2 overcapture flag */
|
||||
#define STM32FTIM_SRCC3OF 0x00000800 /* Capture/compare 3 overcapture flag */
|
||||
#define STM32FTIM_SRCC4OF 0x00001000 /* Capture/compare 4 overcapture flag */
|
||||
|
||||
/* Event Generation Register */
|
||||
#define STM32FTIM_EGR 0x0014 /* Register offset */
|
||||
#define STM32FTIM_EGRUG 0x00000001 /* Update generation */
|
||||
#define STM32FTIM_EGRCC1G 0x00000002 /* Capture/comare 1 generation */
|
||||
#define STM32FTIM_EGRCC2G 0x00000004 /* Capture/comare 2 generation */
|
||||
#define STM32FTIM_EGRCC3G 0x00000008 /* Capture/comare 3 generation */
|
||||
#define STM32FTIM_EGRCC4G 0x00000010 /* Capture/comare 4 generation */
|
||||
#define STM32FTIM_EGRTG 0x00000040 /* Trigger generation */
|
||||
|
||||
/* Timer Count Register (32-bit) */
|
||||
#define STM32FTIM_CNT 0x0024 /* Register offset */
|
||||
|
||||
/* Prescaler Register */
|
||||
#define STM32FTIM_PSC 0x0028 /* Register offset */
|
||||
#define STM32FTIM_PSCMSK 0x0000FFFF /* Prescaler mask */
|
||||
|
||||
/* Auto-reload Register (32-bits) */
|
||||
#define STM32FTIM_ARR 0x002C /* Register offset */
|
||||
|
||||
/*
|
||||
* The following registers are used in capture/compare mode only.
|
||||
* This feature is unsupported.
|
||||
*/
|
||||
|
||||
/* Capture Compare Mode Register 1 */
|
||||
#define STM32FTIM_CCMR1 0x0018 /* Register offset */
|
||||
|
||||
/* Capture Compare Mode Register 2 */
|
||||
#define STM32FTIM_CCMR2 0x001C /* Register offset */
|
||||
|
||||
/* Capture Compare Mode Interrupt Enable Register */
|
||||
#define STM32FTIM_CCER 0x0020 /* Register offset */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbStm32fTimerh */
|
||||
Reference in New Issue
Block a user