original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,616 @@
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/* fslSoc913x.h - Freescale BSC913X SOC header */
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/*
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* Copyright (c) 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01a,30may13,ylu Created.
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*/
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/*
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* This file contains I/O addresses and related constants for the
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* FreeScale QorIQ BSC913X series platform.
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*/
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#ifndef __INCfslsoc913xh
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#define __INCfslsoc913xh
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef _ASMLANGUAGE
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# define CAST(x)
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#else /* _ASMLANGUAGE */
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typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
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typedef volatile INT32 VINT32; /* volatile unsigned word */
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typedef volatile INT16 VINT16; /* volatile unsigned halfword */
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typedef volatile INT8 VINT8; /* volatile unsigned byte */
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
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typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
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# define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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/* Base Address of Memory Mapped Registers */
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#define MP_MAGIC_RBV 0xfeedfeed
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#define MP_MAGIC_CACHE_FLUSHED 0xD07ED07E
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#define M85XX_ALTCBAR(base) (CAST(VUINT32 *)((base) + 0x08))
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#define M85XX_ALTCAR(base) (CAST(VUINT32 *)((base) + 0x10))
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#define M85XX_BPTR(base) (CAST(VUINT32 *)((base) + 0x20))
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#define BPTR_EN 0x80000000
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#define CPU1CHECK (vxHid1Get() & 0x1)
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/*
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* Shift 36bit physical address to 24 bit ie lowest 4k predefined as 0xffc
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* We only every use 32 bit for this so shift by 8 not 12
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*/
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#define BPTR_BOOT_PAGE_SHIFT 12
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/* PA CCSBAR */
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#define CCSBAR_RESET 0xff700000
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#define CCSBAR 0xff700000
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#define CCSR_SIZE 0x00100000
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/* SC3850 CCSBAR */
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#define DSP_CCSBAR_RESET 0xff600000
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#define DSP_CCSBAR 0xff600000
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#define CCSR_SIZE 0x00100000
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/* Vectors */
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/*
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* Extra Duarts are available in Simics. This allows for each CPU in
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* an AMP system to have its own dedicated console port. Note that because
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* these are duarts, there are two serial devices available for each interrupt
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* line. But since two CPUs cannot share a device on the same interrupt, this
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* requires that we create six additional duarts. To keep things consistent,
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* these are set up like the two stock duarts. Thus, twelve additional
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* serial ports are created, potentially allowing for two ports to be
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* dedicated to each CPU.
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*/
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/* EPIC defines */
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#define EPIC_EX_IRQ_NUM 12
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#define EPIC_IN_IRQ_NUM 64
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#define EPIC_GT_IRQ_NUM 4
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#define EPIC_MSG_IRQ_NUM 8
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#define EPIC_SMSG_IRQ_NUM 8
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#define EPIC_IPI_IRQ_NUM 4
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#define EPIC_EX_REG_BASE 0x50000
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#define EPIC_IN_REG_BASE 0x50200
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#define EPIC_GT_A_REG_BASE 0x41120
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#define EPIC_GT_B_REG_BASE 0x42120
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#define EPIC_MSG_REG_BASE 0x51600
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#define EPIC_SMSG_REG_BASE 0x51c00
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#define EPIC_IPI_REG_BASE 0x410a0
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#define EPIC_EX_REG_INTERVAL 0x20
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#define EPIC_IN_REG_INTERVAL 0x20
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#define EPIC_GT_REG_INTERVAL 0x40
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#define EPIC_MSG_REG_INTERVAL 0x20
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#define EPIC_SMSG_REG_INTERVAL 0x20
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#define EPIC_IPI_REG_INTERVAL 0x10
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/* Interrupt vectors */
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#undef EPIC_USB1_INT_VEC
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#undef EPIC_USB1_INT_NUM
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#define EPIC_USB1_INT_NUM 24
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#define EPIC_USB1_INT_VEC (EPIC_USB1_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DUART_INT_VEC
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#undef EPIC_DUART_INT_NUM
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#define EPIC_DUART_INT_NUM 0x2
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#define EPIC_DUART_INT_VEC ( EPIC_DUART_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_I2C_INT_NUM
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#undef EPIC_I2C_INT_VEC
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#define EPIC_I2C_INT_NUM 0x1
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#define EPIC_I2C_INT_VEC ( EPIC_I2C_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC1TX_INT_NUM
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#undef EPIC_TSEC1TX_INT_VEC
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#define EPIC_TSEC1TX_INT_NUM 10
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#define EPIC_TSEC1TX_INT_VEC ( EPIC_TSEC1TX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC1RX_INT_NUM
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#undef EPIC_TSEC1RX_INT_VEC
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#define EPIC_TSEC1RX_INT_NUM 11
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#define EPIC_TSEC1RX_INT_VEC ( EPIC_TSEC1RX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC1ERR_INT_NUM
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#undef EPIC_TSEC1ERR_INT_VEC
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#define EPIC_TSEC1ERR_INT_NUM 12
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#define EPIC_TSEC1ERR_INT_VEC ( EPIC_TSEC1ERR_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC2TX_INT_NUM
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#undef EPIC_TSEC2TX_INT_VEC
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#define EPIC_TSEC2TX_INT_NUM 17
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#define EPIC_TSEC2TX_INT_VEC ( EPIC_TSEC2TX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC2RX_INT_NUM
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#undef EPIC_TSEC2RX_INT_VEC
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#define EPIC_TSEC2RX_INT_NUM 18
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#define EPIC_TSEC2RX_INT_VEC ( EPIC_TSEC2RX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC2ERR_INT_NUM
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#undef EPIC_TSEC2ERR_INT_VEC
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#define EPIC_TSEC2ERR_INT_NUM 19
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#define EPIC_TSEC2ERR_INT_VEC ( EPIC_TSEC2ERR_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_DMA1_CHAN0_INT_NUM
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#undef EPIC_DMA1_CHAN0_INT_VEC
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#define EPIC_DMA1_CHAN0_INT_NUM 46
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#define EPIC_DMA1_CHAN0_INT_VEC (EPIC_DMA1_CHAN0_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#define EPIC_DMA1_CHAN1_INT_NUM 47
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#define EPIC_DMA1_CHAN1_INT_VEC (EPIC_DMA1_CHAN1_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#define EPIC_DMA1_CHAN2_INT_NUM 48
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#define EPIC_DMA1_CHAN2_INT_VEC (EPIC_DMA1_CHAN2_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#define EPIC_DMA1_CHAN3_INT_NUM 49
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#define EPIC_DMA1_CHAN3_INT_VEC (EPIC_DMA1_CHAN3_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_USB_INT_NUM
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#undef EPIC_USB_INT_VEC
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#define EPIC_USB_INT_NUM 24
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#define EPIC_USB_INT_VEC (EPIC_USB_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SPI_INT_NUM
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#undef EPIC_SPI_INT_VEC
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#define EPIC_SPI_INT_NUM 6
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#define EPIC_SPI_INT_VEC (EPIC_SPI_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SPI1_INT_NUM
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#undef EPIC_SPI1_INT_VEC
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#define EPIC_SPI1_INT_NUM 7
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#define EPIC_SPI1_INT_VEC (EPIC_SPI_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN0_INT_NUM
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#undef EPIC_DMA2_CHAN0_INT_VEC
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#define EPIC_DMA2_CHAN0_INT_NUM 50
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#define EPIC_DMA2_CHAN0_INT_VEC (EPIC_DMA2_CHAN0_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN1_INT_NUM
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#undef EPIC_DMA2_CHAN1_INT_VEC
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#define EPIC_DMA2_CHAN1_INT_NUM 51
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#define EPIC_DMA2_CHAN1_INT_VEC (EPIC_DMA2_CHAN1_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN2_INT_NUM
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#undef EPIC_DMA2_CHAN2_INT_VEC
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#define EPIC_DMA2_CHAN2_INT_NUM 52
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#define EPIC_DMA2_CHAN2_INT_VEC (EPIC_DMA2_CHAN2_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN3_INT_NUM
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#undef EPIC_DMA2_CHAN3_INT_VEC
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#define EPIC_DMA2_CHAN3_INT_NUM 53
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#define EPIC_DMA2_CHAN3_INT_VEC (EPIC_DMA2_CHAN3_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_I2C_INT_NUM
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#undef EPIC_I2C_INT_VEC
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#define EPIC_I2C_INT_NUM 1
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#define EPIC_I2C_INT_VEC (EPIC_I2C_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SDHC_INT_NUM
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#undef EPIC_SDHC_INT_VEC
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#define EPIC_SDHC_INT_NUM 25
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#define EPIC_SDHC_INT_VEC (EPIC_SDHC_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SEC_INT_NUM
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#undef EPIC_SEC_INT_VEC
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#define EPIC_SEC_INT_NUM 41
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#define EPIC_SEC_INT_VEC (EPIC_SEC_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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/* OpenPIC timer vectors */
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#define OPENPIC_TIMERA0_INT_VEC 0x4C
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#define OPENPIC_TIMERA1_INT_VEC 0x4D
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#define OPENPIC_TIMERA2_INT_VEC 0x4E
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#define OPENPIC_TIMERA3_INT_VEC 0x4F
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#define OPENPIC_TIMERB0_INT_VEC 0x50
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#define OPENPIC_TIMERB1_INT_VEC 0x51
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#define OPENPIC_TIMERB2_INT_VEC 0x52
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#define OPENPIC_TIMERB3_INT_VEC 0x53
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/* PCIe */
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/* PCI Express Host Controller */
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/* ATMU register defines */
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#define PCI_WINDOW_ENABLE_BIT 0x80000000
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#define PCI_SNOOP_ENABLE 0x40000000
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#define PCI_PREFETCHABLE 0x20000000
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/* outbound window attributes */
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#define PCI_OUT_ATTR_RTT_MEM 0x00040000
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#define PCI_OUT_ATTR_RTT_IO 0x00080000
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#define PCI_OUT_ATTR_WTT_MEM 0x00004000
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#define PCI_OUT_ATTR_WTT_IO 0x00008000
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#define PCI_ATTR_WS_4K 0x0000000B
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#define PCI_ATTR_WS_8K 0x0000000C
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#define PCI_ATTR_WS_16K 0x0000000D
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#define PCI_ATTR_WS_32K 0x0000000E
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#define PCI_ATTR_WS_64K 0x0000000F
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#define PCI_ATTR_WS_128K 0x00000010
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#define PCI_ATTR_WS_256K 0x00000011
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#define PCI_ATTR_WS_512K 0x00000012
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#define PCI_ATTR_WS_1M 0x00000013
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#define PCI_ATTR_WS_2M 0x00000014
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#define PCI_ATTR_WS_4M 0x00000015
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#define PCI_ATTR_WS_8M 0x00000016
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#define PCI_ATTR_WS_16M 0x00000017
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#define PCI_ATTR_WS_32M 0x00000018
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#define PCI_ATTR_WS_64M 0x00000019
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#define PCI_ATTR_WS_128M 0x0000001A
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#define PCI_ATTR_WS_256M 0x0000001B
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#define PCI_ATTR_WS_512M 0x0000001C
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#define PCI_ATTR_WS_1G 0x0000001D
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#define PCI_ATTR_WS_2G 0x0000001E
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#define PCI_ATTR_WS_4G 0x0000001F
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#define PCI_ATTR_WS_8G 0x00000020
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#define PCI_ATTR_WS_16G 0x00000021
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#define PCI_ATTR_WS_32G 0x00000022
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#define PCI_ATTR_WS_64G 0x00000023
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/* Inbound window attributes */
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#define PCI_IN_ATTR_TGI_LM 0x00000000
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#define PCI_IN_ATTR_RTT_LM_READ_NO_SNOOP 0x00040000
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#define PCI_IN_ATTR_RTT_LM_READ_SNOOP 0x00050000
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#define PCI_IN_ATTR_RTT_LM_READ_UNLOCK_L2_CACHE_LINE 0x00070000
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#define PCI_IN_ATTR_RTT_LM_WRITE_NO_SNOOP 0x00004000
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#define PCI_IN_ATTR_RTT_LM_WRITE_SNOOP 0x00005000
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#define PCI_IN_ATTR_RTT_LM_WRITE_ALLOC_L2_CACHE_LINE 0x00006000
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#define PCI_IN_ATTR_RTT_LM_WRITE_ALLOC_LOCK_L2_CACHE_LINE 0x00007000
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/* Local Access Windows Regster Offsets from CCSBAR */
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#define M85XX_LAWBAR0(base) (CAST(VUINT32 *)((base) + 0xc08))
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#define M85XX_LAWAR0(base) (CAST(VUINT32 *)((base) + 0xc10))
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#define M85XX_LAWBAR1(base) (CAST(VUINT32 *)((base) + 0xc28))
|
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#define M85XX_LAWAR1(base) (CAST(VUINT32 *)((base) + 0xc30))
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#define M85XX_LAWBAR2(base) (CAST(VUINT32 *)((base) + 0xc48))
|
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#define M85XX_LAWAR2(base) (CAST(VUINT32 *)((base) + 0xc50))
|
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#define M85XX_LAWBAR3(base) (CAST(VUINT32 *)((base) + 0xc68))
|
||||
#define M85XX_LAWAR3(base) (CAST(VUINT32 *)((base) + 0xc70))
|
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#define M85XX_LAWBAR4(base) (CAST(VUINT32 *)((base) + 0xc88))
|
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#define M85XX_LAWAR4(base) (CAST(VUINT32 *)((base) + 0xc90))
|
||||
|
||||
#define M85XX_LAWBAR5(base) (CAST(VUINT32 *)((base) + 0xca8))
|
||||
#define M85XX_LAWAR5(base) (CAST(VUINT32 *)((base) + 0xcb0))
|
||||
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||||
#define M85XX_LAWBAR6(base) (CAST(VUINT32 *)((base) + 0xcc8))
|
||||
#define M85XX_LAWAR6(base) (CAST(VUINT32 *)((base) + 0xcd0))
|
||||
|
||||
#define M85XX_LAWBAR7(base) (CAST(VUINT32 *)((base) + 0xce8))
|
||||
#define M85XX_LAWAR7(base) (CAST(VUINT32 *)((base) + 0xcf0))
|
||||
|
||||
#define M85XX_LAWBAR8(base) (CAST(VUINT32 *)((base) + 0xd08))
|
||||
#define M85XX_LAWAR8(base) (CAST(VUINT32 *)((base) + 0xd10))
|
||||
|
||||
#define M85XX_LAWBAR9(base) (CAST(VUINT32 *)((base) + 0xd28))
|
||||
#define M85XX_LAWAR9(base) (CAST(VUINT32 *)((base) + 0xd30))
|
||||
|
||||
#define M85XX_LAWBAR10(base) (CAST(VUINT32 *)((base) + 0xd48))
|
||||
#define M85XX_LAWAR10(base) (CAST(VUINT32 *)((base) + 0xd50))
|
||||
|
||||
#define M85XX_LAWBAR11(base) (CAST(VUINT32 *)((base) + 0xd68))
|
||||
#define M85XX_LAWAR11(base) (CAST(VUINT32 *)((base) + 0xd70))
|
||||
|
||||
#define M85XX_LAW_CNT 12
|
||||
#define M85XX_LAW_SIZE 0x20
|
||||
#define LAWBAR_ADRS_SHIFT 12
|
||||
|
||||
#define LAWAR_ENABLE 0x80000000
|
||||
#define LAWAR_TGTIF_PCIEX2 0x00200000
|
||||
#define LAWAR_TGTIF_LBC 0x00400000
|
||||
#define LAWAR_TGTIF_RAPIDIO 0x00C00000
|
||||
#define LAWAR_TGTIF_RAPIDIO2 0x00D00000
|
||||
#define LAWAR_TGTIF_DDRSDRAM 0x00F00000
|
||||
|
||||
#define LAWAR_TGTIF_M3 0x00D00000
|
||||
#define LAWAR_TGTIF_M2 0x00300000
|
||||
#define LAWAR_TGTIF 0x01F00000 /* Target ID */
|
||||
|
||||
#define QORIQ_TGTID_PCIE1 0x02 /* PCI Express1 */
|
||||
#define QORIQ_TGTID_PCIE2 0x01 /* PCI Express2 */
|
||||
#define QORIQ_TGTID_PCIE3 0x03 /* PCI Express3 */
|
||||
|
||||
/* LAWAR SIZE Settings */
|
||||
|
||||
#define LAWAR_SIZE_4KB 0x0000000B
|
||||
#define LAWAR_SIZE_8KB 0x0000000C
|
||||
#define LAWAR_SIZE_16KB 0x0000000D
|
||||
#define LAWAR_SIZE_32KB 0x0000000E
|
||||
#define LAWAR_SIZE_64KB 0x0000000F
|
||||
#define LAWAR_SIZE_128KB 0x00000010
|
||||
#define LAWAR_SIZE_256KB 0x00000011
|
||||
#define LAWAR_SIZE_512KB 0x00000012
|
||||
#define LAWAR_SIZE_1MB 0x00000013
|
||||
#define LAWAR_SIZE_2MB 0x00000014
|
||||
#define LAWAR_SIZE_4MB 0x00000015
|
||||
#define LAWAR_SIZE_8MB 0x00000016
|
||||
#define LAWAR_SIZE_16MB 0x00000017
|
||||
#define LAWAR_SIZE_32MB 0x00000018
|
||||
#define LAWAR_SIZE_64MB 0x00000019
|
||||
#define LAWAR_SIZE_128MB 0x0000001A
|
||||
#define LAWAR_SIZE_256MB 0x0000001B
|
||||
#define LAWAR_SIZE_512MB 0x0000001C
|
||||
#define LAWAR_SIZE_1GB 0x0000001D
|
||||
#define LAWAR_SIZE_2GB 0x0000001E
|
||||
|
||||
/* Integrated Flash Controller (IFC) Registers */
|
||||
|
||||
#define IFC (CCSBAR + IFC_OFFSET)
|
||||
#define IFC_OFFSET 0x1E000
|
||||
|
||||
#define IFC_CSPR0 0x010
|
||||
#define IFC_CSPR1 0x01C
|
||||
#define IFC_CSPR2 0x028
|
||||
#define IFC_CSPR3 0x034
|
||||
#define IFC_AMASK0 0x0A0
|
||||
#define IFC_AMASK1 0x0AC
|
||||
#define IFC_AMASK2 0x0B8
|
||||
#define IFC_AMASK3 0x0C4
|
||||
#define IFC_CSOR0 0x130
|
||||
#define IFC_CSOR1 0x13C
|
||||
#define IFC_CSOR2 0x148
|
||||
#define IFC_CSOR3 0x154
|
||||
#define IFC_FTIM0_CS0 0x1C0
|
||||
#define IFC_FTIM1_CS0 0x1C4
|
||||
#define IFC_FTIM2_CS0 0x1C8
|
||||
#define IFC_FTIM3_CS0 0x1CC
|
||||
#define IFC_FTIM0_CS1 0x1F0
|
||||
#define IFC_FTIM1_CS1 0x1F4
|
||||
#define IFC_FTIM2_CS1 0x1F8
|
||||
#define IFC_FTIM3_CS1 0x1FC
|
||||
#define IFC_FTIM0_CS2 0x220
|
||||
#define IFC_FTIM1_CS2 0x224
|
||||
#define IFC_FTIM2_CS2 0x228
|
||||
#define IFC_FTIM3_CS2 0x22C
|
||||
#define IFC_FTIM0_CS3 0x250
|
||||
#define IFC_FTIM1_CS3 0x254
|
||||
#define IFC_FTIM2_CS3 0x258
|
||||
#define IFC_FTIM3_CS3 0x25C
|
||||
#define IFC_GCR 0x40C
|
||||
|
||||
/* DDR */
|
||||
/* Offsets for DDR registers */
|
||||
|
||||
#define DDR1_OFFSET 0x2000
|
||||
#define DDR2_OFFSET 0x10000
|
||||
#define DDRBA (CCSBAR | DDR1_OFFSET)
|
||||
|
||||
#define DDR1_BASE (CCSBAR | DDR1_OFFSET)
|
||||
#define DDR2_BASE (DSP_CCSBAR | DDR2_OFFSET)
|
||||
|
||||
#define CS0_BNDS 0x000
|
||||
#define CS1_BNDS 0x008
|
||||
#define CS2_BNDS 0x010
|
||||
#define CS3_BNDS 0x018
|
||||
#define CS0_CONFIG 0x080
|
||||
#define CS1_CONFIG 0x084
|
||||
#define CS2_CONFIG 0x088
|
||||
#define CS3_CONFIG 0x08C
|
||||
#define CS0_CONFIG_2 0x0c0
|
||||
#define CS1_CONFIG_2 0x0c4
|
||||
#define CS2_CONFIG_2 0x0c8
|
||||
#define CS3_CONFIG_2 0x0CC
|
||||
#define TIMING_CFG_3 0x100
|
||||
#define TIMING_CFG_0 0x104
|
||||
#define TIMING_CFG_1 0x108
|
||||
#define TIMING_CFG_2 0x10C
|
||||
#define DDR_SDRAM_CFG 0x110
|
||||
#define DDR_SDRAM_CFG_2 0x114
|
||||
#define DDR_SDRAM_MODE_CFG 0x118
|
||||
#define DDR_SDRAM_MODE_CFG_2 0x11c
|
||||
#define DDR_SDRAM_MD_CNTL 0x120
|
||||
#define DDR_SDRAM_INTERVAL 0x124
|
||||
#define DDR_DATA_INIT 0x128
|
||||
#define DDR_SDRAM_CLK_CTRL 0x130
|
||||
#define DDR_INIT_ADDR 0x148
|
||||
#define DDR_INIT_EXT_ADDRESS 0x14C
|
||||
#define TIMING_CFG_4 0x160
|
||||
#define TIMING_CFG_5 0x164
|
||||
#define DDR_DDR_ZQ_CNTL 0x170
|
||||
#define DDR_DDR_WRLVL_CNTL 0x174
|
||||
#define DDR_DDRDSR_1 0xB20
|
||||
#define DDR_DDRDSR_2 0xB24
|
||||
#define DDR_DDRCDR_1 0xB28
|
||||
#define DDR_DDRCDR_2 0xB2C
|
||||
#define DDR_DDR_IP_REV1 0xBF8
|
||||
#define DDR_DDR_IP_REV2 0xBFC
|
||||
#define DATA_ERR_INJECT_HI 0xE00
|
||||
#define DATA_ERR_INJECT_LO 0xE04
|
||||
#define ECC_ERR_INJECT 0xE08
|
||||
#define CAPTURE_DATA_HI 0xE20
|
||||
#define CAPTURE_DATA_LO 0xE24
|
||||
#define CAPTURE_ECC 0xE28
|
||||
#define ERR_DETECT 0xE40
|
||||
#define ERR_DISABLE 0xE44
|
||||
#define ERR_INT_EN 0xE48
|
||||
#define CAPTURE_ATTRIBUTES 0xE4c
|
||||
#define CAPTURE_ADDRESS 0xE50
|
||||
#define ERR_SBE 0xE58
|
||||
|
||||
#define DDR_IO_OVCR 0x000E0F24
|
||||
|
||||
/* DMA */
|
||||
|
||||
#define DMA1_REGBASE (CCSBAR + 0x21100)
|
||||
#define DMA_CHAN_OFFSET 0x80
|
||||
#define DMA_CHAN_NUM 4
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define I2C_BUS1_BASE (CCSBAR + 0x3000)
|
||||
#define I2C_BUS2_BASE (CCSBAR + 0x3100)
|
||||
|
||||
/* USB */
|
||||
|
||||
#define USB1_BASE (CCSBAR + 0x22000)
|
||||
#define USB2_BASE (CCSBAR + 0x23000)
|
||||
|
||||
/* eSPI */
|
||||
|
||||
#define SPI_REG_BASE (CCSBAR + 0x7000)
|
||||
#define SPI1_REG_BASE (CCSBAR + 0x6000)
|
||||
|
||||
/* ETSEC */
|
||||
|
||||
#define ETSEC0_GROUP0_BASE (CCSBAR + 0xB0000)
|
||||
#define ETSEC1_GROUP0_BASE (CCSBAR + 0xB1000)
|
||||
#define ETSEC2_GROUP0_BASE (CCSBAR + 0xB2000)
|
||||
|
||||
/* MDIO */
|
||||
|
||||
#define ETSEC0_MDIO_BASE (CCSBAR + 0x24000)
|
||||
#define ETSEC1_MDIO_BASE (CCSBAR + 0x25000)
|
||||
#define ETSEC2_MDIO_BASE (CCSBAR + 0x26000)
|
||||
|
||||
/* UART */
|
||||
|
||||
#define UART0_BASE (CCSBAR + 0x4500)
|
||||
#define UART1_BASE (CCSBAR + 0x4600)
|
||||
#define DUART_REG_ADDR_INTERVAL 1
|
||||
|
||||
/* TIMER */
|
||||
|
||||
#define T4_OPENPIC_TIMER1_BASE (CCSBAR + 0x0410F0)
|
||||
#define T4_OPENPIC_TIMER2_BASE (CCSBAR + 0x0420F0)
|
||||
|
||||
/* SDHC */
|
||||
|
||||
#define SDHC_BASE (CCSBAR + 0x2E000)
|
||||
#define SD_DATA 0x80000000
|
||||
#define SDHC_CD 0x40000000
|
||||
#define SDHC_WP 0x20000000
|
||||
|
||||
/* GPIO Registers */
|
||||
|
||||
#define GPIO_BASE (CCSBAR + 0xF000)
|
||||
#define GPDIR (GPIO_BASE + 0xC00)
|
||||
#define GPODR (GPIO_BASE + 0xC04)
|
||||
#define GPDAT (GPIO_BASE + 0xC08)
|
||||
#define GPIER (GPIO_BASE + 0xC0C)
|
||||
#define GPIMR (GPIO_BASE + 0xC10)
|
||||
#define GPICR (GPIO_BASE + 0xC14)
|
||||
|
||||
/* ECM Registers */
|
||||
|
||||
#define ECM_OFFSET 0x1000
|
||||
#define ECMBA (CCSBAR + ECM_OFFSET)
|
||||
|
||||
#define EEB_ABCR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0x0))
|
||||
#define EEB_DBCR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0x8))
|
||||
#define EEB_PCR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0x10))
|
||||
#define EEB_REV1(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xBF8))
|
||||
#define EEB_REV2(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xBFC))
|
||||
#define EEB_EDR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE00))
|
||||
#define EEB_EER(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE08))
|
||||
#define EEB_EATR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE0C))
|
||||
#define EEB_ELADR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE10))
|
||||
#define EEB_EHADR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE14))
|
||||
|
||||
#define EEB_PCR_CORE1_ENABLE 0x02000000
|
||||
#define EEB_PCR_CORE0_ENABLE 0x01000000
|
||||
|
||||
/* EHCI registers */
|
||||
|
||||
#define EHCI_CAPLENGTH(base) ((base) + 0x00100)
|
||||
|
||||
#define EHCI_BURSTSIZE(base) ((base) + 0x00160)
|
||||
#define EHCI_TXTTFILLTUNING_L(base) ((base) + 0x00164)
|
||||
#define EHCI_TXTTFILLTUNING_H(base) ((base) + 0x00168)
|
||||
#define EHCI_CONFIGFLAG(base) ((base) + 0x00180)
|
||||
#define EHCI_PORTSC(base) ((base) + 0x00184)
|
||||
#define EHCI_USBMODE(base) ((base) + 0x001a8)
|
||||
|
||||
#define EHCI_SNOOP1(base) ((base) + 0x00400)
|
||||
#define EHCI_SNOOP2(base) ((base) + 0x00404)
|
||||
#define EHCI_AGE_CNT_THRESH(base) ((base) + 0x00408)
|
||||
#define EHCI_PRI_CTRL(base) ((base) + 0x0040c)
|
||||
#define EHCI_SI_CTRL(base) ((base) + 0x00410)
|
||||
#define EHCI_CONTROL(base) ((base) + 0x00500)
|
||||
|
||||
#define EHCI_USBMODE_IDLE 0x00000000
|
||||
#define EHCI_USBMODE_DEVICE 0x00000002
|
||||
#define EHCI_USBMODE_HOST 0x00000003
|
||||
|
||||
#define EHCI_PORTSC_ULPI 0x80000000
|
||||
|
||||
#define EHCI_SNOOP_SIZE_4K 0x0000000B
|
||||
#define EHCI_SNOOP_SIZE_8K 0x0000000C
|
||||
#define EHCI_SNOOP_SIZE_16K 0x0000000D
|
||||
#define EHCI_SNOOP_SIZE_32K 0x0000000E
|
||||
#define EHCI_SNOOP_SIZE_64K 0x0000000F
|
||||
#define EHCI_SNOOP_SIZE_128K 0x00000010
|
||||
#define EHCI_SNOOP_SIZE_256K 0x00000011
|
||||
#define EHCI_SNOOP_SIZE_512K 0x00000012
|
||||
#define EHCI_SNOOP_SIZE_1M 0x00000013
|
||||
#define EHCI_SNOOP_SIZE_2M 0x00000014
|
||||
#define EHCI_SNOOP_SIZE_4M 0x00000015
|
||||
#define EHCI_SNOOP_SIZE_8M 0x00000016
|
||||
#define EHCI_SNOOP_SIZE_16M 0x00000017
|
||||
#define EHCI_SNOOP_SIZE_32M 0x00000018
|
||||
#define EHCI_SNOOP_SIZE_64M 0x00000019
|
||||
#define EHCI_SNOOP_SIZE_128M 0x0000001A
|
||||
#define EHCI_SNOOP_SIZE_256M 0x0000001B
|
||||
#define EHCI_SNOOP_SIZE_512M 0x0000001C
|
||||
#define EHCI_SNOOP_SIZE_1G 0x0000001D
|
||||
#define EHCI_SNOOP_SIZE_2G 0x0000001E
|
||||
|
||||
#ifdef INCLUDE_AMP
|
||||
# define EHCI_SNOOP_SIZE EHCI_SNOOP_SIZE_512M
|
||||
#else /* INCLUDE_AMP */
|
||||
# define EHCI_SNOOP_SIZE EHCI_SNOOP_SIZE_1G
|
||||
#endif /* INCLUDE_AMP */
|
||||
|
||||
#define EHCI_CONTROL_USB_EN 0x00000004
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCfslsoc913xh */
|
||||
|
||||
@@ -0,0 +1,901 @@
|
||||
/* fslSocT4.h - Freescale T4XXX SOC header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2014, 2016 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
04feb16,p_x add CGA and CGB PLL definitions.
|
||||
22aug14,wyt add boot space translation registers.
|
||||
01k,09jul14,j_x add USB related macros.
|
||||
01j,14jan14,wyt add device base address macros.
|
||||
01i,18apr13,j_z add SRIO, RMAN base address macros.
|
||||
01h,06feb13,wyt add device base address macros.
|
||||
01g,31jan13,wyt wrap vxbReadxxx and vxbWritexxx.
|
||||
01f,27jan13,y_y Added eSPI macros.
|
||||
01e,21jan13,wyt fixed some macro defines.
|
||||
01d,09jan13,x_s removed QIXIS register set to t4240qds.h.
|
||||
01c,17dec12,x_s removed DDR configuration parameters.
|
||||
01b,05dec12,h_k removed SPR631_INIT_VAL.
|
||||
01a,30nov12,x_s Created from t4240qds.h.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains I/O addresses and related constants for the
|
||||
* FreeScale QorIQ T4xxx series platform.
|
||||
*/
|
||||
|
||||
#ifndef __INCfslsocT4h
|
||||
#define __INCfslsocT4h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define CCSBAR 0xFE000000
|
||||
#define CCSBAR_RESET 0xFE000000
|
||||
#define CCSBAR_COMMIT 0x80000000
|
||||
#define CCSRBARH_OFFSET 0x0
|
||||
#define CCSRBARL_OFFSET 0x4
|
||||
#define CCSRAR_OFFSET 0x8
|
||||
|
||||
/* 1. Vectors */
|
||||
/*
|
||||
* Extra Duarts are available in Simics. This allows for each CPU in
|
||||
* an AMP system to have its own dedicated console port. Note that because
|
||||
* these are duarts, there are two serial devices available for each interrupt
|
||||
* line. But since two CPUs cannot share a device on the same interrupt, this
|
||||
* requires that we create six additional duarts. To keep things consistent,
|
||||
* these are set up like the two stock duarts. Thus, twelve additional
|
||||
* serial ports are created, potentially allowing for two ports to be
|
||||
* dedicated to each CPU.
|
||||
*/
|
||||
|
||||
#undef EPIC_VEC_IN_IRQ0
|
||||
#define EPIC_VEC_IN_IRQ0 16
|
||||
|
||||
#define EPIC_DMA1_CHAN0_INT_VEC (EPIC_VEC_IN_IRQ0 + 12)
|
||||
#define EPIC_DMA1_CHAN1_INT_VEC (EPIC_VEC_IN_IRQ0 + 13)
|
||||
#define EPIC_DMA1_CHAN2_INT_VEC (EPIC_VEC_IN_IRQ0 + 14)
|
||||
#define EPIC_DMA1_CHAN3_INT_VEC (EPIC_VEC_IN_IRQ0 + 15)
|
||||
#define EPIC_DMA2_CHAN0_INT_VEC (EPIC_VEC_IN_IRQ0 + 16)
|
||||
#define EPIC_DMA2_CHAN1_INT_VEC (EPIC_VEC_IN_IRQ0 + 17)
|
||||
#define EPIC_DMA2_CHAN2_INT_VEC (EPIC_VEC_IN_IRQ0 + 18)
|
||||
#define EPIC_DMA2_CHAN3_INT_VEC (EPIC_VEC_IN_IRQ0 + 19)
|
||||
|
||||
#undef EPIC_DUART_INT_VEC
|
||||
#define EPIC_DUART_INT_VEC (EPIC_VEC_IN_IRQ0 + 20)
|
||||
#undef EPIC_DUART2_INT_VEC
|
||||
#define EPIC_DUART2_INT_VEC (EPIC_VEC_IN_IRQ0 + 21)
|
||||
#define EPIC_DI2C1_INT_VEC (EPIC_VEC_IN_IRQ0 + 22)
|
||||
#define EPIC_DI2C2_INT_VEC (EPIC_VEC_IN_IRQ0 + 23)
|
||||
#define EPIC_USB0_INT_VEC (EPIC_VEC_IN_IRQ0 + 28)
|
||||
#define EPIC_SDHC_INT_VEC (EPIC_VEC_IN_IRQ0 + 32)
|
||||
#define EPIC_ESPI_INT_VEC (EPIC_VEC_IN_IRQ0 + 37)
|
||||
#define EPIC_SATA1_INT_VEC (EPIC_VEC_IN_IRQ0 + 52)
|
||||
#define EPIC_SATA2_INT_VEC (EPIC_VEC_IN_IRQ0 + 53)
|
||||
#define EPIC_DMA1_CHAN4_INT_VEC (EPIC_VEC_IN_IRQ0 + 60)
|
||||
#define EPIC_DMA1_CHAN5_INT_VEC (EPIC_VEC_IN_IRQ0 + 61)
|
||||
#define EPIC_DMA1_CHAN6_INT_VEC (EPIC_VEC_IN_IRQ0 + 62)
|
||||
#define EPIC_DMA1_CHAN7_INT_VEC (EPIC_VEC_IN_IRQ0 + 63)
|
||||
#define EPIC_DMA2_CHAN4_INT_VEC (EPIC_VEC_IN_IRQ0 + 64)
|
||||
#define EPIC_DMA2_CHAN5_INT_VEC (EPIC_VEC_IN_IRQ0 + 65)
|
||||
#define EPIC_DMA2_CHAN6_INT_VEC (EPIC_VEC_IN_IRQ0 + 66)
|
||||
#define EPIC_DMA2_CHAN7_INT_VEC (EPIC_VEC_IN_IRQ0 + 67)
|
||||
|
||||
#define EPIC_QMAN_PORTAL0_INT_VEC 104
|
||||
#define EPIC_QMAN_PORTAL1_INT_VEC 106
|
||||
#define EPIC_QMAN_PORTAL2_INT_VEC 108
|
||||
#define EPIC_QMAN_PORTAL3_INT_VEC 110
|
||||
#define EPIC_QMAN_PORTAL4_INT_VEC 112
|
||||
#define EPIC_QMAN_PORTAL5_INT_VEC 114
|
||||
#define EPIC_QMAN_PORTAL6_INT_VEC 116
|
||||
#define EPIC_QMAN_PORTAL7_INT_VEC 118
|
||||
#define EPIC_QMAN_PORTAL8_INT_VEC 120
|
||||
#define EPIC_QMAN_PORTAL9_INT_VEC 122
|
||||
#define EPIC_QMAN_PORTAL10_INT_VEC 124
|
||||
#define EPIC_QMAN_PORTAL11_INT_VEC 126
|
||||
#define EPIC_QMAN_PORTAL12_INT_VEC 128
|
||||
#define EPIC_QMAN_PORTAL13_INT_VEC 130
|
||||
#define EPIC_QMAN_PORTAL14_INT_VEC 132
|
||||
#define EPIC_QMAN_PORTAL15_INT_VEC 134
|
||||
#define EPIC_QMAN_PORTAL16_INT_VEC 136
|
||||
#define EPIC_QMAN_PORTAL17_INT_VEC 138
|
||||
#define EPIC_QMAN_PORTAL18_INT_VEC 140
|
||||
#define EPIC_QMAN_PORTAL19_INT_VEC 142
|
||||
#define EPIC_QMAN_PORTAL20_INT_VEC 144
|
||||
#define EPIC_QMAN_PORTAL21_INT_VEC 146
|
||||
#define EPIC_QMAN_PORTAL22_INT_VEC 148
|
||||
#define EPIC_QMAN_PORTAL23_INT_VEC 150
|
||||
|
||||
#define EPIC_BMAN_PORTAL0_INT_VEC 105
|
||||
#define EPIC_BMAN_PORTAL1_INT_VEC 107
|
||||
#define EPIC_BMAN_PORTAL2_INT_VEC 109
|
||||
#define EPIC_BMAN_PORTAL3_INT_VEC 111
|
||||
#define EPIC_BMAN_PORTAL4_INT_VEC 113
|
||||
#define EPIC_BMAN_PORTAL5_INT_VEC 115
|
||||
#define EPIC_BMAN_PORTAL6_INT_VEC 117
|
||||
#define EPIC_BMAN_PORTAL7_INT_VEC 119
|
||||
#define EPIC_BMAN_PORTAL8_INT_VEC 121
|
||||
#define EPIC_BMAN_PORTAL9_INT_VEC 123
|
||||
#define EPIC_BMAN_PORTAL10_INT_VEC 125
|
||||
#define EPIC_BMAN_PORTAL11_INT_VEC 127
|
||||
#define EPIC_BMAN_PORTAL12_INT_VEC 129
|
||||
#define EPIC_BMAN_PORTAL13_INT_VEC 131
|
||||
#define EPIC_BMAN_PORTAL14_INT_VEC 133
|
||||
#define EPIC_BMAN_PORTAL15_INT_VEC 135
|
||||
#define EPIC_BMAN_PORTAL16_INT_VEC 137
|
||||
#define EPIC_BMAN_PORTAL17_INT_VEC 139
|
||||
#define EPIC_BMAN_PORTAL18_INT_VEC 141
|
||||
#define EPIC_BMAN_PORTAL19_INT_VEC 143
|
||||
#define EPIC_BMAN_PORTAL20_INT_VEC 145
|
||||
#define EPIC_BMAN_PORTAL21_INT_VEC 147
|
||||
#define EPIC_BMAN_PORTAL22_INT_VEC 149
|
||||
#define EPIC_BMAN_PORTAL23_INT_VEC 151
|
||||
|
||||
/* OpenPIC timer vectors */
|
||||
|
||||
#define OPENPIC_TIMERA0_INT_VEC 200
|
||||
#define OPENPIC_TIMERB0_INT_VEC 204
|
||||
|
||||
/* GPIO vector */
|
||||
|
||||
#define GPIO_INT_VEC 55
|
||||
|
||||
/* USB vectors */
|
||||
|
||||
#define EPIC_USB1_INT_VEC (28 + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_USB2_INT_VEC (29 + EPIC_VEC_IN_IRQ0)
|
||||
|
||||
/* 2. PCI defines */
|
||||
/* SOC T4XXX supports four PCIe controllers */
|
||||
|
||||
/*
|
||||
|
||||
CPU Addr PCI Addr ( PCI1 or PCI2)
|
||||
PCI_LOCAL_MEM_BUS -------------------------- PCI_MSTR_MEM_BUS
|
||||
- -
|
||||
- -
|
||||
PCI_LOCAL_MEM_BUS + -------------------------- PCI_MSTR_MEM_BUS +
|
||||
PCI_LOCAL_MEM_SIZE - - PCI_MSTR_MEM_SIZE
|
||||
- -
|
||||
- ----- PCI Bridge (for PCI1 only)
|
||||
- - configuration regs
|
||||
- -
|
||||
CPU_PCI_MEM_ADRS (PCIEX1) -------------------------- PCI_MEM_ADRS
|
||||
CPU_PCI_MEM_ADRS2(PCIEX2) - - PCI_MEM_ADRS2
|
||||
CPU_PCI_MEM_ADRS3(PCIEX3) -------------------------- PCI_MEM_ADRS3
|
||||
- -
|
||||
CPU_PCI_MEMIO_ADRS -------------------------- PCI_MEMIO_ADRS
|
||||
CPU_PCI_MEMIO_ADRS2 - - PCI_MEMIO_ADRS2
|
||||
CPU_PCI_MEMIO_ADRS3 - - PCI_MEMIO_ADRS3
|
||||
- -
|
||||
CPU_PCI_IO_ADRS (PCIEX1) -------------------------- PCI_IO_ADRS
|
||||
CPU_PCI_IO_ADRS2(PCIEX2) - - PCI_IO_ADRS2
|
||||
CPU_PCI_IO_ADRS3(PCIEX3) - - PCI_IO_ADRS3
|
||||
- -
|
||||
CPU_PCI_IO_ADRS (PCIEX1)+-------------------------- PCI_IO_ADRS +
|
||||
CPU_PCI_IO_ADRS2(PCIEX2)+ PCI_IO_ADRS2 +
|
||||
CPU_PCI_IO_ADRS2(PCIEX3) PCI_IO_ADRS3
|
||||
CPU_PCI_IO_SIZE - - PCI_IO_SIZE
|
||||
- -
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI based addresses
|
||||
* Note: the LAW_BASE values have been chosen to coincide
|
||||
* with those used by U-Boot on the T4DS board.
|
||||
*/
|
||||
|
||||
#define T4_PCIEX1_BASE (CCSBAR + 0x240000) /* PCI-EX slot 0 */
|
||||
#define T4_PCIEX2_BASE (CCSBAR + 0x250000) /* PCI-EX slot 1 */
|
||||
#define T4_PCIEX3_BASE (CCSBAR + 0x260000) /* PCI-EX slot 2 */
|
||||
#define T4_PCIEX4_BASE (CCSBAR + 0x270000) /* PCI-EX slot 3 */
|
||||
|
||||
/*
|
||||
* The T4 processor has four PCIe bridges, each bridges's interrupt supports
|
||||
* two mechanisms, INTx emulation and Message Signaled Interrupt (MSI) mode.
|
||||
* The bridge provide four Virtual Wires(INTA, INTB, INTC and INTD) for
|
||||
* signaling interrupts across a Link. When the bridge works on INTx emulation
|
||||
* mode, the virtual Wires INTA are routed to dedicated internal
|
||||
* interrupts (24, 25, 26, and 27) in the MPIC, the others INTx are logically
|
||||
* combined with the IRQn signals so that they share the external interrupts.
|
||||
* If the bridge interrupts works on MSI mode, interrupts generated from
|
||||
* the EP device will be routed to the MSIIR register in the PIC, virtual Wires
|
||||
* INTx will not be triggered.
|
||||
*
|
||||
* The follow configuration is fit for INTx emulation mode, the INTA interrupts
|
||||
* work as expected, but INTB, INTC and INTD may not.
|
||||
*/
|
||||
|
||||
#define EPIC_VEC_PCIE1_INTA (EPIC_VEC_IN_IRQ0 + 24)
|
||||
#define EPIC_VEC_PCIE2_INTA (EPIC_VEC_IN_IRQ0 + 25)
|
||||
#define EPIC_VEC_PCIE3_INTA (EPIC_VEC_IN_IRQ0 + 26)
|
||||
#define EPIC_VEC_PCIE4_INTA (EPIC_VEC_IN_IRQ0 + 27)
|
||||
|
||||
#define PCIEX1_XINT1_LVL (EPIC_VEC_PCIE1_INTA)
|
||||
#define PCIEX1_XINT2_LVL (EPIC_VEC_EXT_IRQ0 + 1)
|
||||
#define PCIEX1_XINT3_LVL (EPIC_VEC_EXT_IRQ0 + 2)
|
||||
#define PCIEX1_XINT4_LVL (EPIC_VEC_EXT_IRQ0 + 3)
|
||||
|
||||
#define PCIEX2_XINT1_LVL (EPIC_VEC_PCIE2_INTA)
|
||||
#define PCIEX2_XINT2_LVL (EPIC_VEC_EXT_IRQ0 + 5)
|
||||
#define PCIEX2_XINT3_LVL (EPIC_VEC_EXT_IRQ0 + 6)
|
||||
#define PCIEX2_XINT4_LVL (EPIC_VEC_EXT_IRQ0 + 7)
|
||||
|
||||
#define PCIEX3_XINT1_LVL (EPIC_VEC_PCIE3_INTA)
|
||||
#define PCIEX3_XINT2_LVL (EPIC_VEC_EXT_IRQ0 + 9)
|
||||
#define PCIEX3_XINT3_LVL (EPIC_VEC_EXT_IRQ0 + 10)
|
||||
#define PCIEX3_XINT4_LVL (EPIC_VEC_EXT_IRQ0 + 11)
|
||||
|
||||
#define PCIEX4_XINT1_LVL (EPIC_VEC_PCIE4_INTA)
|
||||
#define PCIEX4_XINT2_LVL (EPIC_VEC_EXT_IRQ0 + 0)
|
||||
#define PCIEX4_XINT3_LVL (EPIC_VEC_EXT_IRQ0 + 4)
|
||||
#define PCIEX4_XINT4_LVL (EPIC_VEC_EXT_IRQ0 + 8)
|
||||
|
||||
#define EPIC_USB1_INT_VEC (28 + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_USB2_INT_VEC (29 + EPIC_VEC_IN_IRQ0)
|
||||
|
||||
/* 3. Local Access Windows Regster Offsets from CCSBAR */
|
||||
/* Used for Flash ROM */
|
||||
|
||||
#define T4_LAWBARH0 (CCSBAR + 0xc00)
|
||||
#define T4_LAWBARL0 (CCSBAR + 0xc04)
|
||||
#define T4_LAWAR0 (CCSBAR + 0xc08)
|
||||
|
||||
#define T4_LAWBARH1 (CCSBAR + 0xc10)
|
||||
#define T4_LAWBARL1 (CCSBAR + 0xc14)
|
||||
#define T4_LAWAR1 (CCSBAR + 0xc18)
|
||||
|
||||
#define T4_LAWBARH2 (CCSBAR + 0xc20)
|
||||
#define T4_LAWBARL2 (CCSBAR + 0xc24)
|
||||
#define T4_LAWAR2 (CCSBAR + 0xc28)
|
||||
|
||||
#define T4_LAWBARH3 (CCSBAR + 0xc30)
|
||||
#define T4_LAWBARL3 (CCSBAR + 0xc34)
|
||||
#define T4_LAWAR3 (CCSBAR + 0xc38)
|
||||
|
||||
#define T4_LAWBARH4 (CCSBAR + 0xc40)
|
||||
#define T4_LAWBARL4 (CCSBAR + 0xc44)
|
||||
#define T4_LAWAR4 (CCSBAR + 0xc48)
|
||||
|
||||
#define T4_LAWBARH5 (CCSBAR + 0xc50)
|
||||
#define T4_LAWBARL5 (CCSBAR + 0xc54)
|
||||
#define T4_LAWAR5 (CCSBAR + 0xc58)
|
||||
|
||||
#define T4_LAWBARH6 (CCSBAR + 0xc60)
|
||||
#define T4_LAWBARL6 (CCSBAR + 0xc64)
|
||||
#define T4_LAWAR6 (CCSBAR + 0xc68)
|
||||
|
||||
#define T4_LAWBARH7 (CCSBAR + 0xc70)
|
||||
#define T4_LAWBARL7 (CCSBAR + 0xc74)
|
||||
#define T4_LAWAR7 (CCSBAR + 0xc78)
|
||||
|
||||
#define T4_LAWBARH8 (CCSBAR + 0xc80)
|
||||
#define T4_LAWBARL8 (CCSBAR + 0xc84)
|
||||
#define T4_LAWAR8 (CCSBAR + 0xc88)
|
||||
|
||||
#define T4_LAWBARH9 (CCSBAR + 0xc90)
|
||||
#define T4_LAWBARL9 (CCSBAR + 0xc94)
|
||||
#define T4_LAWAR9 (CCSBAR + 0xc98)
|
||||
|
||||
#define T4_LAWBARH10 (CCSBAR + 0xca0)
|
||||
#define T4_LAWBARL10 (CCSBAR + 0xca4)
|
||||
#define T4_LAWAR10 (CCSBAR + 0xca8)
|
||||
|
||||
#define T4_LAWBARH11 (CCSBAR + 0xcb0)
|
||||
#define T4_LAWBARL11 (CCSBAR + 0xcb4)
|
||||
#define T4_LAWAR11 (CCSBAR + 0xcb8)
|
||||
|
||||
#define T4_LAWBARH30 (CCSBAR + 0xde0)
|
||||
#define T4_LAWBARL30 (CCSBAR + 0xde4)
|
||||
#define T4_LAWAR30 (CCSBAR + 0xde8)
|
||||
|
||||
#define T4_LAWBARH31 (CCSBAR + 0xdf0)
|
||||
#define T4_LAWBARL31 (CCSBAR + 0xdf4)
|
||||
#define T4_LAWAR31 (CCSBAR + 0xdf8)
|
||||
|
||||
#define T4_LAWBARH8_RESET (CCSBAR_RESET + 0xc80)
|
||||
#define T4_LAWBARL8_RESET (CCSBAR_RESET + 0xc84)
|
||||
#define T4_LAWAR8_RESET (CCSBAR_RESET + 0xc88)
|
||||
|
||||
|
||||
#define LAWBAR_ADRS_SHIFT 0
|
||||
#define LAWAR_ENABLE 0x80000000
|
||||
#define LAWAR_TGTIF_PCIEX1 0x00000000
|
||||
#define LAWAR_TGTIF_PCIEX2 0x00100000
|
||||
#define LAWAR_TGTIF_PCIEX3 0x00200000
|
||||
#define LAWAR_TGTIF_PCIEX4 0x00300000
|
||||
#define LAWAR_TGTIF_RAPIDIO 0x00800000
|
||||
#define LAWAR_TGTIF_RAPIDIO2 0x00900000
|
||||
#define LAWAR_TGTIF_DDRSDRAM 0x01000000
|
||||
#define LAWAR_TGTIF_DDRSDRAM2 0x01100000
|
||||
#define LAWAR_TGTIF_DDRSDRAM3 0x01200000
|
||||
#define LAWAR_TGTIF_MEM_INTRL 0x01400000
|
||||
#define LAWAR_TGTIF_BMAN 0x01800000
|
||||
#define LAWAR_TGTIF_DCSR 0x01D00000
|
||||
#define LAWAR_TGTIF_RESERVE 0x01E00000
|
||||
#define LAWAR_TGTIF_IFC 0x01F00000
|
||||
#define LAWAR_TGTIF_QMAN 0x03C00000
|
||||
|
||||
/* LAWAR SIZE Settings */
|
||||
|
||||
#define LAWAR_SIZE_4KB 0x0000000B
|
||||
#define LAWAR_SIZE_8KB 0x0000000C
|
||||
#define LAWAR_SIZE_16KB 0x0000000D
|
||||
#define LAWAR_SIZE_32KB 0x0000000E
|
||||
#define LAWAR_SIZE_64KB 0x0000000F
|
||||
#define LAWAR_SIZE_128KB 0x00000010
|
||||
#define LAWAR_SIZE_256KB 0x00000011
|
||||
#define LAWAR_SIZE_512KB 0x00000012
|
||||
#define LAWAR_SIZE_1MB 0x00000013
|
||||
#define LAWAR_SIZE_2MB 0x00000014
|
||||
#define LAWAR_SIZE_4MB 0x00000015
|
||||
#define LAWAR_SIZE_8MB 0x00000016
|
||||
#define LAWAR_SIZE_16MB 0x00000017
|
||||
#define LAWAR_SIZE_32MB 0x00000018
|
||||
#define LAWAR_SIZE_64MB 0x00000019
|
||||
#define LAWAR_SIZE_128MB 0x0000001A
|
||||
#define LAWAR_SIZE_256MB 0x0000001B
|
||||
#define LAWAR_SIZE_512MB 0x0000001C
|
||||
#define LAWAR_SIZE_1GB 0x0000001D
|
||||
#define LAWAR_SIZE_2GB 0x0000001E
|
||||
|
||||
/* 4. Integrated Flash Controller (IFC) Registers */
|
||||
|
||||
#define T4_IFC_BASE (CCSBAR + 0x124000)
|
||||
#define T4_IFC_REV (T4_IFC_BASE + 0x0000)
|
||||
#define T4_IFC_CSPR0_EXT (T4_IFC_BASE + 0x000c)
|
||||
#define T4_IFC_CSPR0 (T4_IFC_BASE + 0x0010)
|
||||
#define T4_IFC_CSPR1_EXT (T4_IFC_BASE + 0x0018)
|
||||
#define T4_IFC_CSPR1 (T4_IFC_BASE + 0x001c)
|
||||
#define T4_IFC_CSPR2_EXT (T4_IFC_BASE + 0x0024)
|
||||
#define T4_IFC_CSPR2 (T4_IFC_BASE + 0x0028)
|
||||
#define T4_IFC_CSPR3_EXT (T4_IFC_BASE + 0x0030)
|
||||
#define T4_IFC_CSPR3 (T4_IFC_BASE + 0x0034)
|
||||
#define T4_IFC_CSPR4_EXT (T4_IFC_BASE + 0x003c)
|
||||
#define T4_IFC_CSPR4 (T4_IFC_BASE + 0x0040)
|
||||
#define T4_IFC_CSPR5_EXT (T4_IFC_BASE + 0x0048)
|
||||
#define T4_IFC_CSPR5 (T4_IFC_BASE + 0x004c)
|
||||
#define T4_IFC_CSPR6_EXT (T4_IFC_BASE + 0x0054)
|
||||
#define T4_IFC_CSPR6 (T4_IFC_BASE + 0x0058)
|
||||
#define T4_IFC_CSPR7_EXT (T4_IFC_BASE + 0x0060)
|
||||
#define T4_IFC_CSPR7 (T4_IFC_BASE + 0x0064)
|
||||
#define T4_IFC_AMASK0 (T4_IFC_BASE + 0x00a0)
|
||||
#define T4_IFC_AMASK1 (T4_IFC_BASE + 0x00ac)
|
||||
#define T4_IFC_AMASK2 (T4_IFC_BASE + 0x00b8)
|
||||
#define T4_IFC_AMASK3 (T4_IFC_BASE + 0x00c4)
|
||||
#define T4_IFC_AMASK4 (T4_IFC_BASE + 0x00d0)
|
||||
#define T4_IFC_AMASK5 (T4_IFC_BASE + 0x00dc)
|
||||
#define T4_IFC_AMASK6 (T4_IFC_BASE + 0x00e8)
|
||||
#define T4_IFC_AMASK7 (T4_IFC_BASE + 0x00f4)
|
||||
#define T4_IFC_CSOR0 (T4_IFC_BASE + 0x0130)
|
||||
#define T4_IFC_CSOR0_EXT (T4_IFC_BASE + 0x0134)
|
||||
#define T4_IFC_CSOR1 (T4_IFC_BASE + 0x013c)
|
||||
#define T4_IFC_CSOR1_EXT (T4_IFC_BASE + 0x0140)
|
||||
#define T4_IFC_CSOR2 (T4_IFC_BASE + 0x0148)
|
||||
#define T4_IFC_CSOR2_EXT (T4_IFC_BASE + 0x014c)
|
||||
#define T4_IFC_CSOR3 (T4_IFC_BASE + 0x0154)
|
||||
#define T4_IFC_CSOR3_EXT (T4_IFC_BASE + 0x0158)
|
||||
#define T4_IFC_CSOR4 (T4_IFC_BASE + 0x0160)
|
||||
#define T4_IFC_CSOR4_EXT (T4_IFC_BASE + 0x0164)
|
||||
#define T4_IFC_CSOR5 (T4_IFC_BASE + 0x016c)
|
||||
#define T4_IFC_CSOR5_EXT (T4_IFC_BASE + 0x0170)
|
||||
#define T4_IFC_CSOR6 (T4_IFC_BASE + 0x0178)
|
||||
#define T4_IFC_CSOR6_EXT (T4_IFC_BASE + 0x017c)
|
||||
#define T4_IFC_CSOR7 (T4_IFC_BASE + 0x0184)
|
||||
#define T4_IFC_CSOR7_EXT (T4_IFC_BASE + 0x0188)
|
||||
#define T4_IFC_FTIM0_CS0 (T4_IFC_BASE + 0x01c0)
|
||||
#define T4_IFC_FTIM1_CS0 (T4_IFC_BASE + 0x01c4)
|
||||
#define T4_IFC_FTIM2_CS0 (T4_IFC_BASE + 0x01c8)
|
||||
#define T4_IFC_FTIM3_CS0 (T4_IFC_BASE + 0x01cc)
|
||||
#define T4_IFC_FTIM0_CS1 (T4_IFC_BASE + 0x01f0)
|
||||
#define T4_IFC_FTIM1_CS1 (T4_IFC_BASE + 0x01f4)
|
||||
#define T4_IFC_FTIM2_CS1 (T4_IFC_BASE + 0x01f8)
|
||||
#define T4_IFC_FTIM3_CS1 (T4_IFC_BASE + 0x01fc)
|
||||
#define T4_IFC_FTIM0_CS2 (T4_IFC_BASE + 0x0220)
|
||||
#define T4_IFC_FTIM1_CS2 (T4_IFC_BASE + 0x0224)
|
||||
#define T4_IFC_FTIM2_CS2 (T4_IFC_BASE + 0x0228)
|
||||
#define T4_IFC_FTIM3_CS2 (T4_IFC_BASE + 0x022c)
|
||||
#define T4_IFC_FTIM0_CS3 (T4_IFC_BASE + 0x0250)
|
||||
#define T4_IFC_FTIM1_CS3 (T4_IFC_BASE + 0x0254)
|
||||
#define T4_IFC_FTIM2_CS3 (T4_IFC_BASE + 0x0258)
|
||||
#define T4_IFC_FTIM3_CS3 (T4_IFC_BASE + 0x025c)
|
||||
#define T4_IFC_FTIM0_CS4 (T4_IFC_BASE + 0x0280)
|
||||
#define T4_IFC_FTIM1_CS4 (T4_IFC_BASE + 0x0284)
|
||||
#define T4_IFC_FTIM2_CS4 (T4_IFC_BASE + 0x0288)
|
||||
#define T4_IFC_FTIM3_CS4 (T4_IFC_BASE + 0x028c)
|
||||
#define T4_IFC_FTIM0_CS5 (T4_IFC_BASE + 0x02b0)
|
||||
#define T4_IFC_FTIM1_CS5 (T4_IFC_BASE + 0x02b4)
|
||||
#define T4_IFC_FTIM2_CS5 (T4_IFC_BASE + 0x02b8)
|
||||
#define T4_IFC_FTIM3_CS5 (T4_IFC_BASE + 0x02bc)
|
||||
#define T4_IFC_FTIM0_CS6 (T4_IFC_BASE + 0x02e0)
|
||||
#define T4_IFC_FTIM1_CS6 (T4_IFC_BASE + 0x02e4)
|
||||
#define T4_IFC_FTIM2_CS6 (T4_IFC_BASE + 0x02e8)
|
||||
#define T4_IFC_FTIM3_CS6 (T4_IFC_BASE + 0x02ec)
|
||||
#define T4_IFC_FTIM0_CS7 (T4_IFC_BASE + 0x0310)
|
||||
#define T4_IFC_FTIM1_CS7 (T4_IFC_BASE + 0x0314)
|
||||
#define T4_IFC_FTIM2_CS7 (T4_IFC_BASE + 0x0318)
|
||||
#define T4_IFC_FTIM3_CS7 (T4_IFC_BASE + 0x031c)
|
||||
#define T4_IFC_RB_STAT (T4_IFC_BASE + 0x0400)
|
||||
#define T4_IFC_GCR (T4_IFC_BASE + 0x040c)
|
||||
#define T4_IFC_CM_EVTER_STAT (T4_IFC_BASE + 0x0418)
|
||||
#define T4_IFC_CM_EVTER_EN (T4_IFC_BASE + 0x0424)
|
||||
#define T4_IFC_CM_EVTER_INTR_EN (T4_IFC_BASE + 0x0430)
|
||||
#define T4_IFC_CM_ERATTR0 (T4_IFC_BASE + 0x043c)
|
||||
#define T4_IFC_CM_ERATTR1 (T4_IFC_BASE + 0x0440)
|
||||
#define T4_IFC_CCR (T4_IFC_BASE + 0x044c)
|
||||
#define T4_IFC_CSR (T4_IFC_BASE + 0x0450)
|
||||
#define T4_IFC_NCFGR (T4_IFC_BASE + 0x1000)
|
||||
#define T4_IFC_NAND_FCR0 (T4_IFC_BASE + 0x1014)
|
||||
#define T4_IFC_NAND_FCR1 (T4_IFC_BASE + 0x1018)
|
||||
#define T4_IFC_ROW0 (T4_IFC_BASE + 0x103c)
|
||||
#define T4_IFC_COL0 (T4_IFC_BASE + 0x1044)
|
||||
#define T4_IFC_ROW1 (T4_IFC_BASE + 0x104c)
|
||||
#define T4_IFC_COL1 (T4_IFC_BASE + 0x1054)
|
||||
#define T4_IFC_ROW2 (T4_IFC_BASE + 0x105c)
|
||||
#define T4_IFC_COL2 (T4_IFC_BASE + 0x1064)
|
||||
#define T4_IFC_ROW3 (T4_IFC_BASE + 0x106c)
|
||||
#define T4_IFC_COL3 (T4_IFC_BASE + 0x1074)
|
||||
#define T4_IFC_NAND_BC (T4_IFC_BASE + 0x1108)
|
||||
#define T4_IFC_NAND_FIR0 (T4_IFC_BASE + 0x1110)
|
||||
#define T4_IFC_NAND_FIR1 (T4_IFC_BASE + 0x1114)
|
||||
#define T4_IFC_NAND_FIR2 (T4_IFC_BASE + 0x1118)
|
||||
#define T4_IFC_NAND_CSEL (T4_IFC_BASE + 0x115c)
|
||||
#define T4_IFC_NANDSEQ_STRT (T4_IFC_BASE + 0x1164)
|
||||
#define T4_IFC_NAND_EVTER_STAT (T4_IFC_BASE + 0x116c)
|
||||
#define T4_IFC_PGRDCMPL_EVT_STAT (T4_IFC_BASE + 0x1174)
|
||||
#define T4_IFC_NAND_EVTER_EN (T4_IFC_BASE + 0x1180)
|
||||
#define T4_IFC_NAND_EVTER_INTR_EN (T4_IFC_BASE + 0x118c)
|
||||
#define T4_IFC_NAND_ERATTR0 (T4_IFC_BASE + 0x1198)
|
||||
#define T4_IFC_NAND_ERATTR1 (T4_IFC_BASE + 0x119c)
|
||||
#define T4_IFC_NAND_FSR (T4_IFC_BASE + 0x11e0)
|
||||
#define T4_IFC_ECCSTAT0 (T4_IFC_BASE + 0x11e8)
|
||||
#define T4_IFC_ECCSTAT1 (T4_IFC_BASE + 0x11ec)
|
||||
#define T4_IFC_ECCSTAT2 (T4_IFC_BASE + 0x11f0)
|
||||
#define T4_IFC_ECCSTAT3 (T4_IFC_BASE + 0x11f4)
|
||||
#define T4_IFC_NANDCR (T4_IFC_BASE + 0x1278)
|
||||
#define T4_IFC_NAND_AUTOBOOT_TRGR (T4_IFC_BASE + 0x1284)
|
||||
#define T4_IFC_NAND_MDR (T4_IFC_BASE + 0x128c)
|
||||
#define T4_IFC_NOR_EVTER_STAT (T4_IFC_BASE + 0x1400)
|
||||
#define T4_IFC_NOR_EVTER_EN (T4_IFC_BASE + 0x140c)
|
||||
#define T4_IFC_NOR_EVTER_INTR_EN (T4_IFC_BASE + 0x1418)
|
||||
#define T4_IFC_NOR_ERATTR0 (T4_IFC_BASE + 0x1424)
|
||||
#define T4_IFC_NOR_ERATTR1 (T4_IFC_BASE + 0x1428)
|
||||
#define T4_IFC_NOR_ERATTR2 (T4_IFC_BASE + 0x142c)
|
||||
#define T4_IFC_NORCR (T4_IFC_BASE + 0x1440)
|
||||
#define T4_IFC_GPCM_EVTER_STAT (T4_IFC_BASE + 0x1800)
|
||||
#define T4_IFC_GPCM_EVTER_EN (T4_IFC_BASE + 0x180c)
|
||||
#define T4_IFC_GPCM_EVTER_INTR_EN (T4_IFC_BASE + 0x1818)
|
||||
#define T4_IFC_GPCM_ERATTR0 (T4_IFC_BASE + 0x1824)
|
||||
#define T4_IFC_GPCM_ERATTR1 (T4_IFC_BASE + 0x1828)
|
||||
#define T4_IFC_GPCM_ERATTR2 (T4_IFC_BASE + 0x182c)
|
||||
#define T4_IFC_GPCM_STAT (T4_IFC_BASE + 0x1830)
|
||||
|
||||
/* 4. DDR */
|
||||
/* Offsets for DDR registers */
|
||||
|
||||
#define T4_DDR1_BASE (CCSBAR + 0x8000)
|
||||
#define T4_DDR2_BASE (CCSBAR + 0x9000)
|
||||
#define T4_DDR3_BASE (CCSBAR + 0xA000)
|
||||
|
||||
#define T4_CS0_BNDS 0x000
|
||||
#define T4_CS1_BNDS 0x008
|
||||
#define T4_CS2_BNDS 0x010
|
||||
#define T4_CS3_BNDS 0x018
|
||||
#define T4_CS0_CONFIG 0x080
|
||||
#define T4_CS1_CONFIG 0x084
|
||||
#define T4_CS2_CONFIG 0x088
|
||||
#define T4_CS3_CONFIG 0x08C
|
||||
#define T4_TIMING_CFG_3 0x100
|
||||
#define T4_TIMING_CFG_0 0x104
|
||||
#define T4_TIMING_CFG_1 0x108
|
||||
#define T4_TIMING_CFG_2 0x10C
|
||||
#define T4_DDR_SDRAM_CFG 0x110
|
||||
#define T4_DDR_SDRAM_CFG_2 0x114
|
||||
#define T4_DDR_SDRAM_MODE_CFG 0x118
|
||||
#define T4_DDR_SDRAM_MODE_CFG_2 0x11c
|
||||
#define T4_DDR_SDRAM_MD_CNTL 0x120
|
||||
#define T4_DDR_SDRAM_INTERVAL 0x124
|
||||
#define T4_DDR_DATA_INIT 0x128
|
||||
#define T4_DDR_SDRAM_CLK_CTRL 0x130
|
||||
#define T4_TIMING_CFG_4 0x160
|
||||
#define T4_TIMING_CFG_5 0x164
|
||||
#define T4_DDR_ZQ_CNTL 0x170
|
||||
#define T4_DDR_WRLVL_CNTL 0x174
|
||||
#define T4_DDR_SR_CNTR 0x17C
|
||||
#define T4_DDR_WRLVL_CNTL_2 0x190
|
||||
#define T4_DDR_WRLVL_CNTL_3 0x194
|
||||
#define T4_DDRx_DDR_SDRAM_MODE_3 0x200
|
||||
#define T4_DDRx_DDR_SDRAM_MODE_4 0x204
|
||||
#define T4_DDRx_DDR_SDRAM_MODE_5 0x208
|
||||
#define T4_DDRx_DDR_SDRAM_MODE_6 0x20C
|
||||
#define T4_DDRx_DDR_SDRAM_MODE_7 0x210
|
||||
#define T4_DDRx_DDR_SDRAM_MODE_8 0x214
|
||||
|
||||
#define T4_DDRCDR_1 0xB28
|
||||
#define T4_DDRCDR_2 0xB2C
|
||||
|
||||
#define T4_DDR_DATA_ERR_INJECT_HI 0xe00
|
||||
#define T4_DDR_DATA_ERR_INJECT_LO 0xe04
|
||||
#define T4_DDR_ECC_ERR_INJECT 0xe08
|
||||
#define T4_DDR_CAPTURE_DATA_HI 0xe20
|
||||
#define T4_DDR_CAPTURE_DATA_LO 0xe24
|
||||
#define T4_DDR_CAPTURE_ECC 0xe28
|
||||
#define T4_DDR_ERR_DETECT 0xe40
|
||||
#define T4_DDR_ERR_DISABLE 0xe44
|
||||
#define T4_DDR_ERR_INT_EN 0xe48
|
||||
#define T4_DDR_CAPTURE_ATTRIBUTES 0xe4c
|
||||
#define T4_DDR_CAPTURE_ADDRESS 0xe50
|
||||
#define T4_DDR_ERR_SBE 0xe58
|
||||
|
||||
/* 5. DMA */
|
||||
|
||||
#define T4_DMA1_BASE (CCSBAR + 0x100100)
|
||||
#define T4_DMA2_BASE (CCSBAR + 0x101100)
|
||||
|
||||
/* 6. I2C */
|
||||
|
||||
#define T4_I2C1_BASE (CCSBAR + 0x118000)
|
||||
#define T4_I2C2_BASE (CCSBAR + 0x118100)
|
||||
#define T4_I2C3_BASE (CCSBAR + 0x119000)
|
||||
#define T4_I2C4_BASE (CCSBAR + 0x119100)
|
||||
|
||||
/* 7. USB */
|
||||
|
||||
#define T4_USB1_BASE (CCSBAR + 0x210000)
|
||||
#define T4_USB2_BASE (CCSBAR + 0x211000)
|
||||
|
||||
/* 8. eSPI */
|
||||
|
||||
#define T4_ESPI1_BASE (CCSBAR + 0x110000)
|
||||
|
||||
/* 9. MEMAC */
|
||||
|
||||
#define T4_MEMAC1_BASE (CCSBAR + 0x4E0000)
|
||||
#define T4_MEMAC2_BASE (CCSBAR + 0x4E2000)
|
||||
#define T4_MEMAC3_BASE (CCSBAR + 0x4E4000)
|
||||
#define T4_MEMAC4_BASE (CCSBAR + 0x4E6000)
|
||||
#define T4_MEMAC5_BASE (CCSBAR + 0x4E8000)
|
||||
#define T4_MEMAC6_BASE (CCSBAR + 0x4EA000)
|
||||
#define T4_MEMAC7_BASE (CCSBAR + 0x4F0000)
|
||||
#define T4_MEMAC8_BASE (CCSBAR + 0x4F2000)
|
||||
#define T4_MEMAC9_BASE (CCSBAR + 0x5E0000)
|
||||
#define T4_MEMAC10_BASE (CCSBAR + 0x5E2000)
|
||||
#define T4_MEMAC11_BASE (CCSBAR + 0x5E4000)
|
||||
#define T4_MEMAC12_BASE (CCSBAR + 0x5E6000)
|
||||
#define T4_MEMAC13_BASE (CCSBAR + 0x5E8000)
|
||||
#define T4_MEMAC14_BASE (CCSBAR + 0x5EA000)
|
||||
#define T4_MEMAC15_BASE (CCSBAR + 0x5F0000)
|
||||
#define T4_MEMAC16_BASE (CCSBAR + 0x5F2000)
|
||||
|
||||
/* 10. MDIO */
|
||||
|
||||
#define T4_MDIO1_BASE (CCSBAR + 0x4FC000)
|
||||
#define T4_MDIO2_BASE (CCSBAR + 0x4FD000)
|
||||
#define T4_MDIO3_BASE (CCSBAR + 0x5FC000)
|
||||
#define T4_MDIO4_BASE (CCSBAR + 0x5FD000)
|
||||
|
||||
/* 11. FMAN */
|
||||
|
||||
#define T4_FMAN1_BASE (CCSBAR + 0x400000)
|
||||
#define T4_FMAN2_BASE (CCSBAR + 0x500000)
|
||||
|
||||
/* 12. QMAN */
|
||||
|
||||
#define T4_QMAN1_BASE (CCSBAR + 0x318000)
|
||||
|
||||
/* 13. BMAN */
|
||||
|
||||
#define T4_BMAN1_BASE (CCSBAR + 0x31A000)
|
||||
|
||||
/* 14. UART */
|
||||
|
||||
#define T4_DUART1_BASE (CCSBAR + 0x11C500)
|
||||
#define T4_DUART2_BASE (CCSBAR + 0x11C600)
|
||||
#define T4_DUART3_BASE (CCSBAR + 0x11D500)
|
||||
#define T4_DUART4_BASE (CCSBAR + 0x11D600)
|
||||
|
||||
/* 15. TIMER */
|
||||
|
||||
#define T4_OPENPIC_TIMER1_BASE (CCSBAR + 0x0410F0)
|
||||
#define T4_OPENPIC_TIMER2_BASE (CCSBAR + 0x0420F0)
|
||||
|
||||
/* 16. SDHC */
|
||||
|
||||
#define T4_SDHC1_BASE (CCSBAR + 0x114000)
|
||||
|
||||
/* 17. SATA */
|
||||
|
||||
#define T4_SATA1_BASE (CCSBAR + 0x220000)
|
||||
#define T4_SATA2_BASE (CCSBAR + 0x221000)
|
||||
|
||||
/* 18. SRIO */
|
||||
|
||||
#define T4_SRIO_BASE (CCSBAR + 0xC0000)
|
||||
|
||||
/* 19. RMAN */
|
||||
|
||||
#define T4_RMAN_BASE (CCSBAR + 0x1E0000)
|
||||
|
||||
/* EHCI registers */
|
||||
|
||||
#define T4_EHCI_CAPLENGTH(base) ((base) + 0x00100)
|
||||
#define T4_EHCI_BURSTSIZE(base) ((base) + 0x00160)
|
||||
#define T4_EHCI_TXTTFILLTUNING(base)((base) + 0x00164)
|
||||
#define T4_EHCI_CONFIGFLAG(base) ((base) + 0x00180)
|
||||
#define T4_EHCI_PORTSC(base) ((base) + 0x00184)
|
||||
#define T4_EHCI_USBMODE(base) ((base) + 0x001a8)
|
||||
#define T4_EHCI_SNOOP1(base) ((base) + 0x00400)
|
||||
#define T4_EHCI_SNOOP2(base) ((base) + 0x00404)
|
||||
#define T4_EHCI_AGE_CNT_THRESH(base)((base) + 0x00408)
|
||||
#define T4_EHCI_PRI_CTRL(base) ((base) + 0x0040c)
|
||||
#define T4_EHCI_SI_CTRL(base) ((base) + 0x00410)
|
||||
#define T4_EHCI_CONTROL(base) ((base) + 0x00500)
|
||||
|
||||
#define EHCI_USBMODE_IDLE 0x00000000
|
||||
#define EHCI_USBMODE_DEVICE 0x00000002
|
||||
#define EHCI_USBMODE_HOST 0x00000003
|
||||
|
||||
#define EHCI_PORTSC_ULPI 0x80000000
|
||||
#define EHCI_PORTSC_UTMI 0x00000000
|
||||
|
||||
#define EHCI_SNOOP_SIZE_4K 0x0000000B
|
||||
#define EHCI_SNOOP_SIZE_8K 0x0000000C
|
||||
#define EHCI_SNOOP_SIZE_16K 0x0000000D
|
||||
#define EHCI_SNOOP_SIZE_32K 0x0000000E
|
||||
#define EHCI_SNOOP_SIZE_64K 0x0000000F
|
||||
#define EHCI_SNOOP_SIZE_128K 0x00000010
|
||||
#define EHCI_SNOOP_SIZE_256K 0x00000011
|
||||
#define EHCI_SNOOP_SIZE_512K 0x00000012
|
||||
#define EHCI_SNOOP_SIZE_1M 0x00000013
|
||||
#define EHCI_SNOOP_SIZE_2M 0x00000014
|
||||
#define EHCI_SNOOP_SIZE_4M 0x00000015
|
||||
#define EHCI_SNOOP_SIZE_8M 0x00000016
|
||||
#define EHCI_SNOOP_SIZE_16M 0x00000017
|
||||
#define EHCI_SNOOP_SIZE_32M 0x00000018
|
||||
#define EHCI_SNOOP_SIZE_64M 0x00000019
|
||||
#define EHCI_SNOOP_SIZE_128M 0x0000001A
|
||||
#define EHCI_SNOOP_SIZE_256M 0x0000001B
|
||||
#define EHCI_SNOOP_SIZE_512M 0x0000001C
|
||||
#define EHCI_SNOOP_SIZE_1G 0x0000001D
|
||||
#define EHCI_SNOOP_SIZE_2G 0x0000001E
|
||||
|
||||
#ifdef INCLUDE_AMP
|
||||
# define EHCI_SNOOP_SIZE EHCI_SNOOP_SIZE_512M
|
||||
#else /* INCLUDE_AMP */
|
||||
# define EHCI_SNOOP_SIZE EHCI_SNOOP_SIZE_1G
|
||||
#endif /* INCLUDE_AMP */
|
||||
|
||||
#define EHCI_PRI_EN 0x00000008
|
||||
|
||||
#define EHCI_CONTROL_UTMI_PHY_EN 0x00000200
|
||||
#define EHCI_CONTROL_USB_EN 0x00000004
|
||||
|
||||
/* USB PHY */
|
||||
|
||||
#define T4_USB1_PHY_BASE (CCSBAR + 0x214004)
|
||||
#define T4_USB2_PHY_BASE (CCSBAR + 0x214080)
|
||||
|
||||
#define T4_USB_PHY_CTLR(base) ((base) + 0x00)
|
||||
#define T4_USB_PHY_VBUS_CFG(base) ((base) + 0x04)
|
||||
#define T4_USB_PHY_STS(base) ((base) + 0x0c)
|
||||
|
||||
#define T4_USB_PHY_PLL_PRG1 (CCSBAR + 0x214000 + 0x60)
|
||||
#define T4_USB_PHY_PLL_PRG2 (CCSBAR + 0x214000 + 0x64)
|
||||
#define T4_USB_PHY_PLL_PRG3 (CCSBAR + 0x214000 + 0x68)
|
||||
#define T4_USB_PHY_PLL_PRG4 (CCSBAR + 0x214000 + 0x6c)
|
||||
|
||||
#define PLL_PRG1_INIT_VALUE 0x000083E8
|
||||
#define PLL_PRG2_INIT_VALUE 0x00252013
|
||||
#define USB_PORT_ENABLE 0x00000001
|
||||
#define PHY_PLL_VALID 0x00000001
|
||||
#define PHY_VBUS_ENABLE 0x00000002
|
||||
#define PHY_VBUS_VALID 0x00000002
|
||||
#define PLL_PRG1_QUAN_MASK (0x01 << 3)
|
||||
#define PLL_PRG1_SDM_MASK (0x01 << 2)
|
||||
#define USB_PHY_EN_OVERRIDE 0x00000001
|
||||
|
||||
/* clocking */
|
||||
|
||||
#define T4_CLKC1CSR (CCSBAR + 0xE1000)
|
||||
#define T4_CLKCG1HWACSR (CCSBAR + 0xE1010)
|
||||
#define T4_CLKC2CSR (CCSBAR + 0xE1020)
|
||||
#define T4_CLKCG2HWACSR (CCSBAR + 0xE1030)
|
||||
#define T4_CLKC3CSR (CCSBAR + 0xE1040)
|
||||
#define T4_CLKCG3HWACSR (CCSBAR + 0xE1050)
|
||||
#define T4_CLKC4CSR (CCSBAR + 0xE1060)
|
||||
#define T4_CLKCG4HWACSR (CCSBAR + 0xE1070)
|
||||
#define T4_CLKCG5HWACSR (CCSBAR + 0xE1090)
|
||||
#define T4_PLLC1GSR (CCSBAR + 0xE1800)
|
||||
#define T4_PLLC2GSR (CCSBAR + 0xE1820)
|
||||
#define T4_PLLC3GSR (CCSBAR + 0xE1840)
|
||||
#define T4_PLLC4GSR (CCSBAR + 0xE1860)
|
||||
#define T4_PLLC5GSR (CCSBAR + 0xE1880)
|
||||
#define T4_CLKPCSR (CCSBAR + 0xE1A00)
|
||||
#define T4_PLLPGSR (CCSBAR + 0xE1C00)
|
||||
#define T4_PLLDGSR (CCSBAR + 0xE1C20)
|
||||
|
||||
/* Thread PH10 status and control registers - bits are 1 << CPU index */
|
||||
|
||||
#define T4_TPH10SR3 (CCSBAR + 0xE2000)
|
||||
#define T4_TPH10SR2 (CCSBAR + 0xE2004)
|
||||
#define T4_TPH10SR1 (CCSBAR + 0xE2008)
|
||||
#define T4_TPH10SR0 (CCSBAR + 0xE200C)
|
||||
#define T4_TPH10SETR3 (CCSBAR + 0xE2010)
|
||||
#define T4_TPH10SETR2 (CCSBAR + 0xE2014)
|
||||
#define T4_TPH10SETR1 (CCSBAR + 0xE2018)
|
||||
#define T4_TPH10SETR0 (CCSBAR + 0xE201C)
|
||||
#define T4_TPH10CLRR3 (CCSBAR + 0xE2020)
|
||||
#define T4_TPH10CLRR2 (CCSBAR + 0xE2024)
|
||||
#define T4_TPH10CLRR1 (CCSBAR + 0xE2028)
|
||||
#define T4_TPH10CLRR0 (CCSBAR + 0xE202C)
|
||||
#define T4_TPH10PSR3 (CCSBAR + 0xE2030)
|
||||
#define T4_TPH10PSR2 (CCSBAR + 0xE2034)
|
||||
#define T4_TPH10PSR1 (CCSBAR + 0xE2038)
|
||||
#define T4_TPH10PSR0 (CCSBAR + 0xE203C)
|
||||
#define T4_TWAITSR3 (CCSBAR + 0xE2040)
|
||||
#define T4_TWAITSR2 (CCSBAR + 0xE2044)
|
||||
#define T4_TWAITSR1 (CCSBAR + 0xE2048)
|
||||
#define T4_TWAITSR0 (CCSBAR + 0xE204C)
|
||||
|
||||
/* Processor reset register */
|
||||
|
||||
#define T4_EPICPRR (CCSBAR + 0x41098)
|
||||
|
||||
/* Feature Reporting Register (FRR) */
|
||||
|
||||
#define T4_EPICFRR (CCSBAR + 0x41000)
|
||||
|
||||
/* Processor initialization register */
|
||||
|
||||
#define T4_EPICPIR (CCSBAR + 0x41090)
|
||||
#define T4_EPICWHOAMI (CCSBAR + 0x40090)
|
||||
|
||||
/*
|
||||
* CPU-private current task priority and end-of-interrupt registers
|
||||
* (used for CPU reset)
|
||||
*/
|
||||
|
||||
#define T4_EPICCTPRn(n) (CCSBAR + 0x60080 + (n)*0x1000)
|
||||
#define T4_EPICEOIn(n) (CCSBAR + 0x600b0 + (n)*0x1000)
|
||||
#define EPIC_CTPR_MAX 15 /* maximum priority (mask) */
|
||||
#define RESET_EOI_NUM 15 /* EOIs to send RM:31.5.1.3 */
|
||||
|
||||
#define T4_PVR (CCSBAR + 0xE00A0)
|
||||
#define T4_SVR (CCSBAR + 0xE00A4)
|
||||
|
||||
#define T4_BRR (CCSBAR + 0xE00E4)
|
||||
#define T4_BSTRH (CCSBAR + 0x20)
|
||||
#define T4_BSTRL (CCSBAR + 0x24)
|
||||
#define T4_BSTAR (CCSBAR + 0x28)
|
||||
|
||||
/* Core reset status register */
|
||||
|
||||
#define T4_CRSTSR(n) (CCSBAR + 0xE0400 + (n)*4)
|
||||
#define CRSTSR_RST_WRT 0x08000000
|
||||
#define CRSTSR_RST_MPIC 0x00800000
|
||||
#define CRSTSR_RST_CORE 0x00080000
|
||||
#define CRSTSR_READY 0x00008000
|
||||
#define CRSTSR_RST_HRST 0x00000002
|
||||
#define CRSTSR_RST_PORST 0x00000001
|
||||
|
||||
/* Reset configuration word status registers (0 <= n < 16) */
|
||||
|
||||
#define T4_RCWSR(n) (CCSBAR + 0xE0100 + (n)*4)
|
||||
#define MEM_PLL_RAT_MSK 0x003E0000
|
||||
#define MEM_PLL_RAT_SFT 17
|
||||
#define MEM_PLL_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(0)) & MEM_PLL_RAT_MSK) >> MEM_PLL_RAT_SFT)
|
||||
|
||||
#define SYS_PLL_RAT_MSK 0x3E000000
|
||||
#define SYS_PLL_RAT_SFT 25
|
||||
#define SYS_PLL_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(0)) & SYS_PLL_RAT_MSK) >> SYS_PLL_RAT_SFT)
|
||||
|
||||
#define CGA_PLL1_RAT_MSK 0x0000003F
|
||||
#define CGA_PLL1_RAT_SFT 0
|
||||
#define CGA_PLL1_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(0)) & CGA_PLL1_RAT_MSK) >> CGA_PLL1_RAT_SFT)
|
||||
|
||||
#define CGA_PLL2_RAT_MSK 0x3F000000
|
||||
#define CGA_PLL2_RAT_SFT 24
|
||||
#define CGA_PLL2_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(1)) & CGA_PLL2_RAT_MSK) >> CGA_PLL2_RAT_SFT)
|
||||
|
||||
#define CGA_PLL3_RAT_MSK 0x003F0000
|
||||
#define CGA_PLL3_RAT_SFT 16
|
||||
#define CGA_PLL3_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(1)) & CGA_PLL3_RAT_MSK) >> CGA_PLL3_RAT_SFT)
|
||||
|
||||
#define CGB_PLL1_RAT_MSK 0x00003F00
|
||||
#define CGB_PLL1_RAT_SFT 8
|
||||
#define CGB_PLL1_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(1)) & CGB_PLL1_RAT_MSK) >> CGB_PLL1_RAT_SFT)
|
||||
|
||||
#define CGB_PLL2_RAT_MSK 0x0000003F
|
||||
#define CGB_PLL2_RAT_SFT 0
|
||||
#define CGB_PLL2_RAT \
|
||||
((T4_CSR_READ_32(T4_RCWSR(1)) & CGB_PLL2_RAT_MSK) >> CGB_PLL2_RAT_SFT)
|
||||
|
||||
#define CCN_PLL_RAT_MSK(n) (0x3E000000 >> (8 * n))
|
||||
#define CCN_PLL_RAT_SFT(n) (25 - (8 * n))
|
||||
#define CCN_PLL_RAT(n) \
|
||||
((T4_CSR_READ_32(T4_RCWSR(2)) & CCN_PLL_RAT_MSK(n)) >> CCN_PLL_RAT_SFT(n))
|
||||
|
||||
#define CN_PLL_SEL_MSK(n) (0xF0000000 >> (4 * n))
|
||||
#define CN_PLL_SEL_SFT(n) (28 - (4 * n))
|
||||
#define CN_PLL_SEL(n) \
|
||||
((T4_CSR_READ_32(T4_RCWSR(3)) & CN_PLL_SEL_MSK(n)) >> CN_PLL_SEL_SFT(n))
|
||||
|
||||
#define SRDS_PRTCL ((T4_CSR_READ_32(T4_RCWSR(4)) & 0xfc000000) >> 26)
|
||||
|
||||
/* Timebase enable register */
|
||||
|
||||
#define T4_CTBENR (CCSBAR + 0xE21A0)
|
||||
|
||||
#define T4_RSTCR (CCSBAR + 0xE00B0)
|
||||
|
||||
/* Branch Unit Control and Status Register (BUCSR) bit defines */
|
||||
|
||||
#define _PPC_BUCSR_FI 0x200 /* Invalidate branch cache */
|
||||
#define _PPC_BUCSR_E 0x1 /* Enable branch prediction */
|
||||
|
||||
/* MMU and CACHE defines used in romInit.s */
|
||||
|
||||
#ifndef MMU_STATE_IPROT
|
||||
# define MMU_STATE_IPROT 0x40000000
|
||||
#endif /* MMU_STATE_IPROT */
|
||||
|
||||
#define MMU_ROM_ACCESS (_MMU_TLB_ATTR_W | \
|
||||
_MMU_TLB_ATTR_M | \
|
||||
_MMU_TLB_ATTR_G)
|
||||
|
||||
#define MMU_UNCACHED (_MMU_TLB_ATTR_I | \
|
||||
_MMU_TLB_ATTR_G)
|
||||
#define MMU_CACHED _MMU_TLB_ATTR_M
|
||||
|
||||
#define MMU_IO_ACCESS MMU_UNCACHED /* WIMGE bits for IO */
|
||||
|
||||
#define T4_CSR_READ_8(x) \
|
||||
vxbRead8 ((void *)VXB_HANDLE_ORDERED , (UINT8 *)(x))
|
||||
|
||||
#define T4_CSR_WRITE_8(x, y) \
|
||||
vxbWrite8 ((void *)VXB_HANDLE_ORDERED , (UINT8 *)(x), (y))
|
||||
|
||||
#define T4_CSR_READ_16(x) \
|
||||
vxbRead16 ((void *)VXB_HANDLE_ORDERED , (UINT16 *)(x))
|
||||
|
||||
#define T4_CSR_WRITE_16(x, y) \
|
||||
vxbWrite16 ((void *)VXB_HANDLE_ORDERED , (UINT16 *)(x), (y))
|
||||
|
||||
#define T4_CSR_SWAP_READ_16(x) \
|
||||
vxbRead16 ((void *)VXB_HANDLE_SWAP(VXB_HANDLE_ORDERED ), (UINT16 *)(x))
|
||||
|
||||
#define T4_CSR_SWAP_WRITE_16(x, y) \
|
||||
vxbWrite16 ((void *)VXB_HANDLE_SWAP(VXB_HANDLE_ORDERED ), (UINT16 *)(x), (y))
|
||||
|
||||
#define T4_CSR_READ_32(x) \
|
||||
vxbRead32 ((void *)VXB_HANDLE_ORDERED , (UINT32 *)(x))
|
||||
|
||||
#define T4_CSR_WRITE_32(x, y) \
|
||||
vxbWrite32 ((void *)VXB_HANDLE_ORDERED , (UINT32 *)(x), (y))
|
||||
|
||||
#define T4_CSR_SWAP_READ_32(x) \
|
||||
vxbRead32 ((void *)VXB_HANDLE_SWAP(VXB_HANDLE_ORDERED ), (UINT32 *)(x))
|
||||
|
||||
#define T4_CSR_SWAP_WRITE_32(x, y) \
|
||||
vxbWrite32 ((void *)VXB_HANDLE_SWAP(VXB_HANDLE_ORDERED ), (UINT32 *)(x), (y))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCfslsocT4h */
|
||||
|
||||
@@ -0,0 +1,543 @@
|
||||
/* fsl_Kinetis.h - SOC specific header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,02aug13,yjw Created
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains register definitions specifc to the Kinetis series SOC.
|
||||
|
||||
SEE ALSO:
|
||||
\tb "Freescale K70 Sub-Family Reference Manual"
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCfsl_Kinetish
|
||||
#define __INCfsl_Kinetish
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Peripheral memory map */
|
||||
|
||||
#define KINETIS_AIPS0PERIPH_BASE 0x40000000
|
||||
#define KINETIS_AIPS1PERIPH_BASE 0x40080000
|
||||
|
||||
/* UART registers bases */
|
||||
|
||||
#define KINETIS_UART0_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006A000)
|
||||
#define KINETIS_UART1_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006B000)
|
||||
#define KINETIS_UART2_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006C000)
|
||||
#define KINETIS_UART3_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006D000)
|
||||
#define KINETIS_UART4_BASE (KINETIS_AIPS1PERIPH_BASE + 0x0006A000)
|
||||
#define KINETIS_UART5_BASE (KINETIS_AIPS1PERIPH_BASE + 0x0006B000)
|
||||
|
||||
/* ENET register base */
|
||||
|
||||
#define KINETIS_ENET_BASE (KINETIS_AIPS1PERIPH_BASE + 0x00040000)
|
||||
|
||||
/* PIT register base */
|
||||
|
||||
#define KINETIS_PIT_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00037000)
|
||||
|
||||
/* Clock gates for the modules inside the MCU */
|
||||
|
||||
/* UARTs */
|
||||
|
||||
#define SIM_SCGC1_UART4_MASK 0x00000400
|
||||
#define SIM_SCGC1_UART5_MASK 0x00000800
|
||||
#define SIM_SCGC1_UART0_MASK 0x00000400
|
||||
#define SIM_SCGC4_UART1_MASK 0x00000800
|
||||
#define SIM_SCGC4_UART2_MASK 0x00001000
|
||||
#define SIM_SCGC4_UART3_MASK 0x00002000
|
||||
|
||||
/* Ports */
|
||||
|
||||
#define SIM_SCGC5_PORTA_MASK 0x00000200
|
||||
#define SIM_SCGC5_PORTB_MASK 0x00000400
|
||||
#define SIM_SCGC5_PORTC_MASK 0x00000800
|
||||
#define SIM_SCGC5_PORTD_MASK 0x00001000
|
||||
#define SIM_SCGC5_PORTE_MASK 0x00002000
|
||||
|
||||
/* ENET */
|
||||
|
||||
#define SIM_SCGC2_ENET_MASK 0x00000001
|
||||
|
||||
/* PIT */
|
||||
|
||||
#define SIM_SCGC6_PIT_MASK 0x00800000
|
||||
|
||||
/* DDR */
|
||||
|
||||
#define SIM_SCGC3_DDR_MASK 0x00004000
|
||||
|
||||
/* OSC1 */
|
||||
|
||||
#define SIM_SCGC1_OSC1_MASK 0x00000020
|
||||
|
||||
/* MPU */
|
||||
|
||||
#define SIM_SCGC7_MPU_MASK 0x00000004
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define SIM_SCGC4_IIC0_MASK (1 << 6)
|
||||
|
||||
/* System Integration Module (SIM) register map */
|
||||
|
||||
struct kinetis_sim_regs {
|
||||
UINT32 sopt1; /* System Options Register 1 */
|
||||
UINT32 rsv0[1024];
|
||||
UINT32 sopt2; /* System Options Register 2 */
|
||||
UINT32 rsv1;
|
||||
UINT32 sopt4; /* System Options Register 4 */
|
||||
UINT32 sopt5; /* System Options Register 5 */
|
||||
UINT32 sopt6; /* System Options Register 6 */
|
||||
UINT32 sopt7; /* System Options Register 7 */
|
||||
UINT32 rsv2[2];
|
||||
UINT32 sdid; /* System Device Identification Register */
|
||||
UINT32 scgc[7]; /* Clock Gating Regs 1...7 */
|
||||
UINT32 clkdiv1; /* System Clock Divider Register 1 */
|
||||
UINT32 clkdiv2; /* System Clock Divider Register 2 */
|
||||
UINT32 fcfg1; /* Flash Configuration Register 1 */
|
||||
UINT32 fcfg2; /* Flash Configuration Register 2 */
|
||||
UINT32 uidh; /* Unique Identification Register High */
|
||||
UINT32 uidmh; /* Unique Identification Register Mid-High */
|
||||
UINT32 uidml; /* Unique Identification Register Mid Low */
|
||||
UINT32 uidl; /* Unique Identification Register Low */
|
||||
UINT32 clkdiv3; /* System Clock Divider Register 3 */
|
||||
UINT32 clkdiv4; /* System Clock Divider Register 4 */
|
||||
UINT32 mcr; /* Misc Control Register */
|
||||
};
|
||||
|
||||
/* SIM registers base */
|
||||
|
||||
#define KINETIS_SIM_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00047000)
|
||||
#define KINETIS_SIM ((volatile struct kinetis_sim_regs *) \
|
||||
KINETIS_SIM_BASE)
|
||||
|
||||
/* System Clock Divider Register 1 */
|
||||
|
||||
/* Clock 1 output divider value */
|
||||
|
||||
#define KINETIS_SIM_CLKDIV1_OUTDIV1_BITS 28
|
||||
|
||||
/* Clock 2 output divider value */
|
||||
|
||||
#define KINETIS_SIM_CLKDIV1_OUTDIV2_BITS 24
|
||||
|
||||
/* Clock 3 output divider value */
|
||||
|
||||
#define KINETIS_SIM_CLKDIV1_OUTDIV3_BITS 20
|
||||
|
||||
/* Clock 4 output divider value */
|
||||
|
||||
#define KINETIS_SIM_CLKDIV1_OUTDIV4_BITS 16
|
||||
|
||||
/* Misc Control Register (SIM_MCR) */
|
||||
|
||||
/* Pin enable for all DDR I/O */
|
||||
|
||||
#define KINETIS_SIM_MCR_DDRPEN_MSK (1 << 2)
|
||||
|
||||
/* DDR configuration select */
|
||||
|
||||
#define KINETIS_SIM_MCR_DDRCFG_BITS 5
|
||||
|
||||
/* DDR2 Full Strength */
|
||||
|
||||
#define KINETIS_SIM_MCR_DDRCFG_DDR2FULL (6 << KINETIS_SIM_MCR_DDRCFG_BITS)
|
||||
|
||||
/* Multipurpose Clock Generator (MCG) register map */
|
||||
|
||||
struct kinetis_mcg_regs {
|
||||
UINT8 c1; /* MCG Control 1 Register */
|
||||
UINT8 c2; /* MCG Control 2 Register */
|
||||
UINT8 c3; /* MCG Control 3 Register */
|
||||
UINT8 c4; /* MCG Control 4 Register */
|
||||
UINT8 c5; /* MCG Control 5 Register */
|
||||
UINT8 c6; /* MCG Control 6 Register */
|
||||
UINT8 status; /* MCG Status Register */
|
||||
UINT8 rsv0;
|
||||
UINT8 atc; /* MCG Auto Trim Control Register */
|
||||
UINT8 rsv1;
|
||||
UINT8 atcvh; /* MCG Auto Trim Compare Value High Register */
|
||||
UINT8 atcvl; /* MCG Auto Trim Compare Value Low Register */
|
||||
UINT8 c7; /* MCG Control 7 Register */
|
||||
UINT8 c8; /* MCG Control 8 Register */
|
||||
UINT8 rsv2;
|
||||
UINT8 c10; /* MCG Control 10 Register */
|
||||
UINT8 c11; /* MCG Control 11 Register */
|
||||
UINT8 c12; /* MCG Control 12 Register */
|
||||
UINT8 status2; /* MCG Status 2 Register */
|
||||
};
|
||||
|
||||
/* MCG registers base */
|
||||
|
||||
#define KINETIS_MCG_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00064000)
|
||||
#define KINETIS_MCG ((volatile struct kinetis_mcg_regs *) \
|
||||
KINETIS_MCG_BASE)
|
||||
|
||||
/* Clock rate at the EXTAL0 input */
|
||||
|
||||
#define KINETIS_OSC0_RATE 50000000
|
||||
|
||||
/* Use external reference clock from Ethernet PHY as main MCG input */
|
||||
|
||||
#define KINETIS_MCG_PLLREFSEL 0 /* OSC0 */
|
||||
|
||||
/*
|
||||
* The EXTAL rate divided by the divisor value (2**10 = 1024) specified by this
|
||||
* constant should be as close to the 32..40 kHz range as possible.
|
||||
*/
|
||||
|
||||
#define KINETIS_MCG_FRDIV_POW 10
|
||||
|
||||
/* Core/system clock divider: 120/1 = 120 MHz */
|
||||
|
||||
#define KINETIS_CCLK_DIV 1
|
||||
|
||||
/* Peripheral clock divider: 120/2 = 60 MHz */
|
||||
|
||||
#define KINETIS_PCLK_DIV 2
|
||||
|
||||
/* FlexBus clock divider: 120/3 = 40 MHz */
|
||||
|
||||
#define KINETIS_FLEXBUS_CLK_DIV 3
|
||||
|
||||
/* Flash clock divider: 120/5 = 24 MHz */
|
||||
|
||||
#define KINETIS_FLASH_CLK_DIV 5
|
||||
|
||||
/* PLL input divider: 50/5 = 10 MHz */
|
||||
|
||||
#define KINETIS_PLL_PRDIV 5
|
||||
|
||||
/* PLL multiplier: 10*24/2 = 120 MHz */
|
||||
|
||||
#define KINETIS_PLL_VDIV 24
|
||||
|
||||
/* PLL1 input divider: 50/5 = 10 MHz */
|
||||
|
||||
#define KINETIS_PLL1_PRDIV 5
|
||||
|
||||
/* PLL1 multiplier: 10*24/2 = 120 MHz */
|
||||
|
||||
#define KINETIS_PLL1_VDIV 24
|
||||
|
||||
/* Use PLL1 for MCGOUT */
|
||||
|
||||
#define KINETIS_MCGOUT_PLL1
|
||||
|
||||
#define KINETIS_PLL_PRDIV_MAX 8
|
||||
#define KINETIS_PLL_VDIV_MIN 16
|
||||
#define KINETIS_PLL_VDIV_MAX 47
|
||||
|
||||
#define KINETIS_PLL_REF_MIN (8 * 1000 * 1000) /* 8 MHz */
|
||||
#define KINETIS_PLL_REF_MAX (16 * 1000 * 1000) /* 16 MHz */
|
||||
|
||||
#define KINETIS_PLL_VCO_DIV 2 /* There is a /2 divider after VCO */
|
||||
|
||||
/* Clock rate on the input of the MCG (Multipurpose Clock Generator) */
|
||||
|
||||
#define KINETIS_MCG_PLLREFSEL 0
|
||||
#define KINETIS_MCG_PLL_IN_RATE KINETIS_OSC0_RATE
|
||||
|
||||
/* Set KINETIS_MCG_FREQ_RANGE according to the crystal oscillator */
|
||||
|
||||
#define KINETIS_MCG_FREQ_RANGE 1 /* 1 MHz to 8 MHz */
|
||||
|
||||
/*
|
||||
* Set KINETIS_MCG_FRDIV to the code for writing into the FRDIV bit field
|
||||
* of the MCG_C1 register.
|
||||
*/
|
||||
|
||||
#define KINETIS_MCG_FRDIV (KINETIS_MCG_FRDIV_POW - 5)
|
||||
|
||||
/* MCGOUTCLK rate */
|
||||
|
||||
#ifdef KINETIS_MCGOUT_PLL1
|
||||
#define KINETIS_MCGOUT_RATE \
|
||||
(KINETIS_MCG_PLL_IN_RATE / KINETIS_PLL1_PRDIV * KINETIS_PLL1_VDIV / \
|
||||
KINETIS_PLL_VCO_DIV)
|
||||
#else
|
||||
#define KINETIS_MCGOUT_RATE \
|
||||
(KINETIS_MCG_PLL_IN_RATE / KINETIS_PLL_PRDIV * KINETIS_PLL_VDIV / \
|
||||
KINETIS_PLL_VCO_DIV)
|
||||
#endif /* KINETIS_MCGOUT_PLL1 */
|
||||
|
||||
/* PLL1 output rate */
|
||||
|
||||
#define KINETIS_PLL1OUT_RATE \
|
||||
(KINETIS_MCG_PLL_IN_RATE / KINETIS_PLL1_PRDIV * KINETIS_PLL1_VDIV / \
|
||||
KINETIS_PLL_VCO_DIV)
|
||||
|
||||
/* Core/system clock rate */
|
||||
|
||||
#define KINETIS_CPU_RATE (KINETIS_MCGOUT_RATE / KINETIS_CCLK_DIV)
|
||||
|
||||
/* Peripheral clock rate */
|
||||
|
||||
#define KINETIS_PCLK_RATE (KINETIS_MCGOUT_RATE / KINETIS_PCLK_DIV)
|
||||
|
||||
/* FlexBus clock rate */
|
||||
|
||||
#define KINETIS_FLEXBUS_RATE (KINETIS_MCGOUT_RATE / KINETIS_FLEXBUS_CLK_DIV)
|
||||
|
||||
/* Flash clock rate */
|
||||
|
||||
#define KINETIS_FLASH_RATE (KINETIS_MCGOUT_RATE / KINETIS_FLASH_CLK_DIV)
|
||||
|
||||
#ifdef CONFIG_KINETIS_DDR
|
||||
|
||||
/* DDR clock rate */
|
||||
|
||||
#define KINETIS_DDR_RATE KINETIS_PLL1OUT_RATE
|
||||
#endif /* CONFIG_KINETIS_DDR */
|
||||
|
||||
/* MCG registers */
|
||||
|
||||
/* MCG Control 1 Register */
|
||||
|
||||
#define KINETIS_MCG_C1_FRDIV_BITS 3
|
||||
|
||||
/* Clock Source Select bits (CLKS) */
|
||||
|
||||
#define KINETIS_MCG_C1_CLKS_BITS 6
|
||||
#define KINETIS_MCG_C1_CLKS_MSK (3 << KINETIS_MCG_C1_CLKS_BITS)
|
||||
#define KINETIS_MCG_C1_CLKS_FLLPLL_MSK (0 << KINETIS_MCG_C1_CLKS_BITS)
|
||||
#define KINETIS_MCG_C1_CLKS_INT_REF_MSK (1 << KINETIS_MCG_C1_CLKS_BITS)
|
||||
#define KINETIS_MCG_C1_CLKS_EXT_REF_MSK (2 << KINETIS_MCG_C1_CLKS_BITS)
|
||||
|
||||
/* MCG Control 2 Register */
|
||||
|
||||
/* Frequency Range Select bits */
|
||||
|
||||
#define KINETIS_MCG_C2_RANGE0_BITS 4
|
||||
|
||||
/*
|
||||
* External Reference Select for OSC0
|
||||
* 0 = External reference clock requested.
|
||||
* 1 = Oscillator requested.
|
||||
*/
|
||||
|
||||
#define KINETIS_MCG_C2_EREFS0_MSK (1 << 2)
|
||||
|
||||
/* Configure crystal oscillator for high-gain operation */
|
||||
|
||||
#define KINETIS_MCG_C2_HGO_MSK (1 << 3)
|
||||
|
||||
/* MCG Control 5 Register */
|
||||
|
||||
/* PLL External Reference Divider */
|
||||
|
||||
#define KINETIS_MCG_C5_PRDIV_BITS 0
|
||||
|
||||
/* PLL Stop Enable */
|
||||
|
||||
#define KINETIS_MCG_C5_PLLSTEN_MSK (1 << 5)
|
||||
|
||||
/* PLL0 Clock Enable */
|
||||
|
||||
#define KINETIS_MCG_C5_PLLCLKEN_MSK (1 << 6)
|
||||
|
||||
/* PLL External Reference Select (for K70@120MHz) */
|
||||
|
||||
#define KINETIS_MCG_C5_PLLREFSEL_BIT 7
|
||||
#define KINETIS_MCG_C5_PLLREFSEL_MSK (1 << KINETIS_MCG_C5_PLLREFSEL_BIT)
|
||||
|
||||
/* MCG Control 6 Register */
|
||||
|
||||
/* VCO Divider */
|
||||
|
||||
#define KINETIS_MCG_C6_VDIV_BITS 0
|
||||
|
||||
/* PLL Select */
|
||||
|
||||
#define KINETIS_MCG_C6_PLLS_MSK (1 << 6)
|
||||
|
||||
/* MCG Control 7 Register */
|
||||
|
||||
/* MCG OSC Clock Select */
|
||||
|
||||
#define KINETIS_MCG_C7_OSCSEL_MSK (1 << 0)
|
||||
|
||||
/* MCG Control 10 Register */
|
||||
|
||||
/* Frequency Range1 Select */
|
||||
|
||||
#define KINETIS_MCG_C10_RANGE1_BITS 4
|
||||
|
||||
/*
|
||||
* External Reference Select for OSC1
|
||||
* 0 = External reference clock requested.
|
||||
* 1 = Oscillator requested.
|
||||
*/
|
||||
|
||||
#define KINETIS_MCG_C10_EREFS1_MSK (1 << 2)
|
||||
|
||||
/* MCG Control 11 Register */
|
||||
|
||||
/* PLL1 External Reference Divider */
|
||||
|
||||
#define KINETIS_MCG_C11_PRDIV_BITS 0
|
||||
|
||||
/* PLL Clock Select: PLL0 or PLL1 */
|
||||
|
||||
#define KINETIS_MCG_C11_PLLCS_MSK (1 << 4)
|
||||
|
||||
/* PLL1 Stop Enable */
|
||||
|
||||
#define KINETIS_MCG_C11_PLLSTEN1_MSK (1 << 5)
|
||||
|
||||
/* PLL1 Clock Enable */
|
||||
|
||||
#define KINETIS_MCG_C11_PLLCLKEN1_MSK (1 << 6)
|
||||
|
||||
/* PLL1 External Reference Select (for K70@120MHz) */
|
||||
|
||||
#define KINETIS_MCG_C11_PLLREFSEL1_BIT 7
|
||||
#define KINETIS_MCG_C11_PLLREFSEL1_MSK (1 << KINETIS_MCG_C11_PLLREFSEL1_BIT)
|
||||
|
||||
/* MCG Control 12 Register */
|
||||
|
||||
/* VCO1 Divider */
|
||||
|
||||
#define KINETIS_MCG_C12_VDIV1_BITS 0
|
||||
|
||||
/* MCG Status Register */
|
||||
|
||||
/* Oscillator 0 initialization */
|
||||
|
||||
#define KINETIS_MCG_S_OSCINIT0_MSK (1 << 1)
|
||||
|
||||
/* Clock Mode Status */
|
||||
|
||||
#define KINETIS_MCG_S_CLKST_MSK (3 << 2)
|
||||
#define KINETIS_MCG_S_CLKST_FLL (0 << 2)
|
||||
#define KINETIS_MCG_S_CLKST_INT_REF (1 << 2)
|
||||
#define KINETIS_MCG_S_CLKST_EXT_REF (2 << 2)
|
||||
#define KINETIS_MCG_S_CLKST_PLL (3 << 2)
|
||||
|
||||
/* Internal Reference Status */
|
||||
|
||||
#define KINETIS_MCG_S_IREFST_MSK (1 << 4)
|
||||
|
||||
/* PLL Select Status */
|
||||
|
||||
#define KINETIS_MCG_S_PLLST_MSK (1 << 5)
|
||||
|
||||
/* Indicates whether the PLL has acquired lock */
|
||||
|
||||
#define KINETIS_MCG_S_LOCK_MSK (1 << 6)
|
||||
|
||||
/* MCG Status 2 Register */
|
||||
|
||||
/* This bit indicates whether PLL1 has acquired lock */
|
||||
|
||||
#define KINETIS_MCG_S2_LOCK1_MSK (1 << 6)
|
||||
|
||||
/* Oscillator 1 initialization */
|
||||
|
||||
#define KINETIS_MCG_S2_OSCINIT1_MSK (1 << 1)
|
||||
|
||||
/* OSC registers base */
|
||||
|
||||
#define KINETIS_OSC0_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00065000)
|
||||
#define KINETIS_OSC1_BASE (KINETIS_AIPS0PERIPH_BASE + 0x000E5000)
|
||||
|
||||
/* Oscillator (OSC) registers */
|
||||
|
||||
/* OSC_CR register */
|
||||
|
||||
/* External Reference Enable */
|
||||
|
||||
#define KINETIS_OSC_CR_EREFSTEN_MSK (1 << 5)
|
||||
|
||||
/* External Reference Stop Enable */
|
||||
|
||||
#define KINETIS_OSC_CR_ERCLKEN_MSK (1 << 7)
|
||||
|
||||
|
||||
/* Miscellaneous Control Module (MCM) register map */
|
||||
|
||||
struct kinetis_mcm_regs {
|
||||
UINT32 rsv0[2];
|
||||
UINT16 plasc; /* Crossbar switch (AXBS) slave configuration */
|
||||
UINT16 plamc; /* Crossbar switch (AXBS) master configuration */
|
||||
UINT32 cr; /* Control register */
|
||||
};
|
||||
|
||||
/* MCM registers base */
|
||||
|
||||
#define KINETIS_MCM_BASE 0xE0080000
|
||||
#define KINETIS_MCM ((volatile struct kinetis_mcm_regs *) \
|
||||
KINETIS_MCM_BASE)
|
||||
|
||||
/* Watchdog timer (WDOG) register map */
|
||||
|
||||
struct kinetis_wdt_regs {
|
||||
UINT16 stctrlh; /* Status and Control Register High */
|
||||
UINT16 stctrll; /* Status and Control Register Low */
|
||||
UINT16 tovalh; /* Time-out Value Register High */
|
||||
UINT16 tovall; /* Time-out Value Register Low */
|
||||
UINT16 winh; /* Window Register High */
|
||||
UINT16 winl; /* Window Register Low */
|
||||
UINT16 refresh; /* Refresh Register */
|
||||
UINT16 unlock; /* Unlock Register */
|
||||
UINT16 tmrouth; /* Timer Output Register High */
|
||||
UINT16 tmroutl; /* Timer Output Register Low */
|
||||
UINT16 rstcnt; /* Reset Count Register */
|
||||
UINT16 presc; /* Prescaler Register */
|
||||
};
|
||||
|
||||
/* Watchdog Timer registers base */
|
||||
|
||||
#define KINETIS_WDT_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00052000)
|
||||
#define KINETIS_WDT ((volatile struct kinetis_wdt_regs *) \
|
||||
KINETIS_WDT_BASE)
|
||||
|
||||
#define KINETIS_WDT_UNLOCK_KEY1 0xC520
|
||||
#define KINETIS_WDT_UNLOCK_KEY2 0xD928
|
||||
|
||||
#define KINETIS_WDT_ENABLE (1 << 0)
|
||||
|
||||
/* GPIO port register map */
|
||||
|
||||
#define PORTA_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x49000 + (4 * (n)))
|
||||
#define PORTB_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x4a000 + (4 * (n)))
|
||||
#define PORTC_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x4b000 + (4 * (n)))
|
||||
#define PORTD_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x4c000 + (4 * (n)))
|
||||
#define PORTE_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x4d000 + (4 * (n)))
|
||||
#define PORTF_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x4e000 + (4 * (n)))
|
||||
|
||||
#define PORT_PCR_MUX(alt) (alt << 8)
|
||||
|
||||
#define KINETIS_PORT_BASE(n) (KINETIS_AIPS0PERIPH_BASE + \
|
||||
0x49000 + (0x1000 * (n)))
|
||||
|
||||
#define KINETIS_GPIO_MODULE_BASE(n) (0x400ff000 + (0x40 * (n)))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCfsl_Kinetish */
|
||||
@@ -0,0 +1,669 @@
|
||||
/* fsl_KinetisMem.h - Freescale Kinetis memory subsystem header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,30jul13,yjw Created
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains register definitions specifc to the freescale Kinetis
|
||||
flash and SDRAM memory interface registers.
|
||||
|
||||
SEE ALSO:
|
||||
\tb K70 Sub-Family Reference Manual
|
||||
*/
|
||||
|
||||
#ifndef __INCfsl_KinetisMemh
|
||||
#define __INCfsl_KinetisMemh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Flash Memory Module (FTFE) register map */
|
||||
|
||||
struct kinetis_ftfe_regs {
|
||||
UINT8 fstat; /* Flash Status Register */
|
||||
UINT8 fcnfg; /* Flash Configuration Register */
|
||||
UINT8 fsec; /* Flash Security Register */
|
||||
UINT8 fopt; /* Flash Option Register */
|
||||
|
||||
/* Flash Common Command Object Registers (3:0) */
|
||||
UINT8 fccob3;
|
||||
UINT8 fccob2;
|
||||
UINT8 fccob1;
|
||||
UINT8 fccob0;
|
||||
|
||||
/* Flash Common Command Object Registers (7:4) */
|
||||
UINT8 fccob7;
|
||||
UINT8 fccob6;
|
||||
UINT8 fccob5;
|
||||
UINT8 fccob4;
|
||||
|
||||
/* Flash Common Command Object Registers (0xB:8) */
|
||||
UINT8 fccobB;
|
||||
UINT8 fccobA;
|
||||
UINT8 fccob9;
|
||||
UINT8 fccob8;
|
||||
};
|
||||
|
||||
/* FTFE registers base */
|
||||
|
||||
#define KINETIS_AIPS0PERIPH_BASE 0x40000000
|
||||
#define KINETIS_FTFE_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00020000)
|
||||
#define KINETIS_FTFE ((volatile struct kinetis_ftfe_regs *)KINETIS_FTFE_BASE)
|
||||
|
||||
/* Flash Status Register (FSTAT)*/
|
||||
|
||||
#define KINETIS_FTFE_FSTAT_CCIF 0x80
|
||||
#define KINETIS_FTFE_FSTAT_RDCOLERR 0x40
|
||||
#define KINETIS_FTFE_FSTAT_ACCERR 0x20
|
||||
#define KINETIS_FTFE_FSTAT_FPVIOL 0x10
|
||||
#define KINETIS_FTFE_FSTAT_MGSTAT0 0x01
|
||||
|
||||
/* Flash configuration register (FCNFG)*/
|
||||
|
||||
#define KINETIS_FTFE_FCNFG_CCIE 0x80
|
||||
#define KINETIS_FTFE_FCNFG_RDCOLLIE 0x40
|
||||
#define KINETIS_FTFE_FCNFG_ERSAREQ 0x20
|
||||
#define KINETIS_FTFE_FCNFG_ERSSUSP 0x10
|
||||
#define KINETIS_FTFE_FCNFG_RAMRDY 0x02
|
||||
#define KINETIS_FTFE_FCNFG_EEERDY 0x01
|
||||
|
||||
/* Flash security register (FSEC) */
|
||||
|
||||
#define KINETIS_FTFE_FSEC_KEYEN 0xC0
|
||||
#define KINETIS_FTFE_FSEC_FSLACC 0x0C
|
||||
#define KINETIS_FTFE_FSEC_SEC 0x03
|
||||
|
||||
/* Flash operation commands */
|
||||
|
||||
#define KINETIS_FTFE_VERIFY_BLOCK 0x00
|
||||
#define KINETIS_FTFE_VERIFY_SECTION 0x01
|
||||
#define KINETIS_FTFE_PROGRAM_CHECK 0x02
|
||||
#define KINETIS_FTFE_READ_RESOURCE 0x03
|
||||
#define KINETIS_FTFE_PROGRAM_LONGWORD 0x06
|
||||
#define KINETIS_FTFE_PROGRAM_PHRASE 0x07
|
||||
#define KINETIS_FTFE_ERASE_BLOCK 0x08
|
||||
#define KINETIS_FTFE_ERASE_SECTOR 0x09
|
||||
#define KINETIS_FTFE_PROGRAM_SECTION 0x0B
|
||||
#define KINETIS_FTFE_VERIFY_ALL_BLOCK 0x40
|
||||
#define KINETIS_FTFE_READ_ONCE 0x41
|
||||
#define KINETIS_FTFE_PROGRAM_ONCE 0x43
|
||||
#define KINETIS_FTFE_ERASE_ALL_BLOCK 0x44
|
||||
#define KINETIS_FTFE_SECURITY_BY_PASS 0x45
|
||||
#define KINETIS_FTFE_PFLASH_SWAP 0x46
|
||||
#define KINETIS_FTFE_PROGRAM_PARTITION 0x80
|
||||
#define KINETIS_FTFE_SET_EERAM 0x81
|
||||
|
||||
/* Flash Memory Controller (FMC) register map */
|
||||
|
||||
struct kinetis_fmc_regs {
|
||||
UINT32 pfapr; /* Flash Access Protection Register */
|
||||
UINT32 pfb01cr; /* Flash Bank 01 Control Register */
|
||||
UINT32 pfb23cr; /* Flash Bank 23 Control Register */
|
||||
};
|
||||
|
||||
/* FMC registers base */
|
||||
#define KINETIS_FMC_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0001F000)
|
||||
#define KINETIS_FMC ((volatile struct kinetis_fmc_regs *)KINETIS_FMC_BASE)
|
||||
|
||||
/* PFAPR Bit Fields */
|
||||
|
||||
#define FMC_PFAPR_M0AP_MASK 0x00000003
|
||||
#define FMC_PFAPR_M1AP_MASK 0x0000000C
|
||||
#define FMC_PFAPR_M2AP_MASK 0x00000030
|
||||
#define FMC_PFAPR_M3AP_MASK 0x000000C0
|
||||
#define FMC_PFAPR_M4AP_MASK 0x00000300
|
||||
#define FMC_PFAPR_M5AP_MASK 0x00000C00
|
||||
#define FMC_PFAPR_M6AP_MASK 0x00003000
|
||||
#define FMC_PFAPR_M0PFD_MASK 0x00010000
|
||||
#define FMC_PFAPR_M1PFD_MASK 0x00020000
|
||||
#define FMC_PFAPR_M2PFD_MASK 0x00040000
|
||||
#define FMC_PFAPR_M3PFD_MASK 0x00080000
|
||||
#define FMC_PFAPR_M4PFD_MASK 0x00100000
|
||||
#define FMC_PFAPR_M5PFD_MASK 0x00200000
|
||||
#define FMC_PFAPR_M6PFD_MASK 0x00400000
|
||||
#define FMC_PFAPR_M7PFD_MASK 0x00800000
|
||||
|
||||
/* PFB01CR Bit Fields */
|
||||
|
||||
#define FMC_PFB01CR_B01SEBE_MASK 0x00000001
|
||||
#define FMC_PFB01CR_B01IPE_MASK 0x00000002
|
||||
#define FMC_PFB01CR_B01DPE_MASK 0x00000004
|
||||
#define FMC_PFB01CR_B01ICE_MASK 0x00000008
|
||||
#define FMC_PFB01CR_B01DCE_MASK 0x00000010
|
||||
#define FMC_PFB01CR_CRC_MASK 0x000000E0
|
||||
#define FMC_PFB01CR_B01MW_MASK 0x00060000
|
||||
#define FMC_PFB01CR_S_B_INV_MASK 0x00080000
|
||||
#define FMC_PFB01CR_CINV_WAY_MASK 0x00F00000
|
||||
#define FMC_PFB01CR_CLCK_WAY_MASK 0x0F000000
|
||||
#define FMC_PFB01CR_B01RWSC_MASK 0xF0000000
|
||||
|
||||
/* PFB23CR Bit Fields */
|
||||
|
||||
#define FMC_PFB23CR_B23SEBE_MASK 0x00000001
|
||||
#define FMC_PFB23CR_B23IPE_MASK 0x00000002
|
||||
#define FMC_PFB23CR_B23DPE_MASK 0x00000004
|
||||
#define FMC_PFB23CR_B23ICE_MASK 0x00000008
|
||||
#define FMC_PFB23CR_B23DCE_MASK 0x00000010
|
||||
#define FMC_PFB23CR_B23MW_MASK 0x00060000
|
||||
#define FMC_PFB23CR_B23RWSC_MASK 0xF0000000
|
||||
|
||||
/* TAGVD Bit Fields */
|
||||
|
||||
#define FMC_TAGVD_valid_MASK 0x00000001
|
||||
#define FMC_TAGVD_tag_MASK 0x000FFFC0
|
||||
|
||||
/* DATA_UM Bit Fields */
|
||||
|
||||
#define FMC_DATA_UM_data_MASK 0xFFFFFFFF
|
||||
|
||||
/* DATA_MU Bit Fields */
|
||||
|
||||
#define FMC_DATA_MU_data_MASK 0xFFFFFFFF
|
||||
|
||||
/* DATA_ML Bit Fields */
|
||||
|
||||
#define FMC_DATA_ML_data_MASK 0xFFFFFFFF
|
||||
|
||||
/* DATA_LM Bit Fields */
|
||||
|
||||
#define FMC_DATA_LM_data_MASK 0xFFFFFFFF
|
||||
|
||||
/* Pointer to the beginning of flash */
|
||||
|
||||
#define KINETIS_NVM_PTR ((UINT8 *)0x0)
|
||||
|
||||
/* Address of the flash programming acceleration RAM */
|
||||
|
||||
#define FLASH_PROG_ACCEL_BASE 0x14000000
|
||||
#define FLASH_PROG_ACCEL_PTR ((UINT8 *)FLASH_PROG_ACCEL_BASE)
|
||||
|
||||
/*
|
||||
* Size in bytes of the flash programming acceleration RAM
|
||||
*/
|
||||
|
||||
#define FLASH_PROG_ACCEL_SIZE (16 * 1024)
|
||||
|
||||
/*
|
||||
* Size of the bottom half of the flash programming acceleration RAM
|
||||
* that may be used for flash programming.
|
||||
*/
|
||||
|
||||
#define FLASH_PROG_ACCEL_HALF (FLASH_PROG_ACCEL_SIZE / 2)
|
||||
|
||||
/* Size of a sector in the MCU internal flash is 4 Kbytes (K70) */
|
||||
|
||||
#define FLASH_SECTOR_SIZE (4 * 1024)
|
||||
|
||||
/*
|
||||
* Offset of the byte in flash that loads into the FSEC register on reset
|
||||
*/
|
||||
#define KINETIS_FLASH_FSEC_OFFSET 0x40C
|
||||
|
||||
#define CONFIG_KINETIS_DDR
|
||||
#define CONFIG_KINETIS_DDR_SYNC /* DDR synchronous mode */
|
||||
|
||||
/*
|
||||
* DDR1/2/LP SDRAM Memory Controller (DDRMC) register map
|
||||
*/
|
||||
struct kinetis_ddr_regs {
|
||||
UINT32 cr[64]; /* Control Registers */
|
||||
UINT32 rsv0[32]; /* Reserved */
|
||||
UINT32 rcr; /* RCR Control Register */
|
||||
UINT32 rsv1[10]; /* Reserved */
|
||||
UINT32 pad_ctrl; /* I/O Pad Control Register */
|
||||
};
|
||||
|
||||
/*
|
||||
* DDRMC registers base
|
||||
*/
|
||||
#define KINETIS_DDR_BASE (KINETIS_AIPS1PERIPH_BASE + 0x0002E000)
|
||||
#define KINETIS_DDR ((volatile struct kinetis_ddr_regs *) \
|
||||
KINETIS_DDR_BASE)
|
||||
|
||||
/* DDR size is 128 Mbytes */
|
||||
#define KINETIS_MCM_CR_DDRSIZE_128MB (1 << 20)
|
||||
|
||||
/*
|
||||
* DRAM Port 0 configuration
|
||||
*/
|
||||
#define KINETIS_DDR_RP0 1
|
||||
#define KINETIS_DDR_WP0 1
|
||||
#define KINETIS_DDR_P0RDCNT 32
|
||||
#define KINETIS_DDR_P0WRCNT 32
|
||||
#define KINETIS_DDR_P0ORD 1
|
||||
#define KINETIS_DDR_P0PRI0 3
|
||||
#define KINETIS_DDR_P0PRI1 3
|
||||
#define KINETIS_DDR_P0PRI2 3
|
||||
#define KINETIS_DDR_P0PRI3 3
|
||||
#define KINETIS_DDR_P0PRIRLX 100
|
||||
|
||||
/*
|
||||
* DRAM Port 1 configuration
|
||||
*/
|
||||
#define KINETIS_DDR_RP1 1
|
||||
#define KINETIS_DDR_WP1 1
|
||||
#define KINETIS_DDR_P1RDCNT 32
|
||||
#define KINETIS_DDR_P1WRCNT 32
|
||||
#define KINETIS_DDR_P1ORD 1
|
||||
#define KINETIS_DDR_P1PRI0 2
|
||||
#define KINETIS_DDR_P1PRI1 2
|
||||
#define KINETIS_DDR_P1PRI2 2
|
||||
#define KINETIS_DDR_P1PRI3 2
|
||||
#define KINETIS_DDR_P1PRIRLX 100
|
||||
|
||||
/*
|
||||
* DRAM Port 2 configuration
|
||||
*/
|
||||
#define KINETIS_DDR_RP2 1
|
||||
#define KINETIS_DDR_WP2 1
|
||||
#define KINETIS_DDR_P2RDCNT 32
|
||||
#define KINETIS_DDR_P2WRCNT 32
|
||||
#define KINETIS_DDR_P2ORD 2
|
||||
#define KINETIS_DDR_P2PRI0 1
|
||||
#define KINETIS_DDR_P2PRI1 1
|
||||
#define KINETIS_DDR_P2PRI3 1
|
||||
#define KINETIS_DDR_P2PRI2 1
|
||||
#define KINETIS_DDR_P2PRIRLX 100
|
||||
|
||||
/*
|
||||
* Port types: synchronous, asynchronous.
|
||||
* See DDR registers bit fields: CR40[P0TYP], CR42[P1TYP], CR44[P2TYP].
|
||||
*/
|
||||
#define KINETIS_DDR_PORT_ASYNC 0
|
||||
#define KINETIS_DDR_PORT_SYNC 3
|
||||
|
||||
/*
|
||||
* Actual port types
|
||||
*/
|
||||
#ifdef CONFIG_KINETIS_DDR_SYNC
|
||||
#define KINETIS_DDR_P0TYP KINETIS_DDR_PORT_SYNC
|
||||
#define KINETIS_DDR_P1TYP KINETIS_DDR_PORT_SYNC
|
||||
#define KINETIS_DDR_P2TYP KINETIS_DDR_PORT_SYNC
|
||||
#else
|
||||
#define KINETIS_DDR_P0TYP KINETIS_DDR_PORT_ASYNC
|
||||
#define KINETIS_DDR_P1TYP KINETIS_DDR_PORT_ASYNC
|
||||
#define KINETIS_DDR_P2TYP KINETIS_DDR_PORT_ASYNC
|
||||
#endif /* CONFIG_KINETIS_DDR_SYNC */
|
||||
|
||||
/*
|
||||
* Other SDRAM configuration options
|
||||
*/
|
||||
#define KINETIS_DDR_INITAREF 2
|
||||
#define KINETIS_DDR_TINIT 49
|
||||
#define KINETIS_DDR_TCCD 2
|
||||
#define KINETIS_DDR_WRLAT 2
|
||||
#define KINETIS_DDR_LATGATE 5
|
||||
#define KINETIS_DDR_LATLIN 6
|
||||
#define KINETIS_DDR_TRASMIN 6
|
||||
#define KINETIS_DDR_TRC 9
|
||||
#define KINETIS_DDR_TRRD 2
|
||||
#define KINETIS_DDR_TBINT 2
|
||||
#define KINETIS_DDR_TMRD 2
|
||||
#define KINETIS_DDR_TRTP 2
|
||||
#define KINETIS_DDR_TRP 3
|
||||
#define KINETIS_DDR_TWTR 2
|
||||
#define KINETIS_DDR_TRASMAX 10500 /* 70000 ns */
|
||||
#define KINETIS_DDR_TMOD 2
|
||||
#define KINETIS_DDR_TCKESR 3
|
||||
#define KINETIS_DDR_CLKPW 3
|
||||
#define KINETIS_DDR_TDAL 5
|
||||
#define KINETIS_DDR_TWR 3
|
||||
#define KINETIS_DDR_TRASDI 2
|
||||
#define KINETIS_DDR_TDLL 200
|
||||
#define KINETIS_DDR_TRPAB 3
|
||||
#define KINETIS_DDR_TCPD 50
|
||||
#define KINETIS_DDR_TFAW 7
|
||||
#define KINETIS_DDR_TREF 1170 /* 7.8 us */
|
||||
#define KINETIS_DDR_TRFC 50
|
||||
#define KINETIS_DDR_TXSR 200
|
||||
#define KINETIS_DDR_TPDEX 2
|
||||
#define KINETIS_DDR_TXSNR 50
|
||||
#define KINETIS_DDR_CKSRX 3
|
||||
#define KINETIS_DDR_CKSRE 3
|
||||
#define KINETIS_DDR_APREBIT 10
|
||||
#define KINETIS_DDR_COLSIZ 1
|
||||
#define KINETIS_DDR_ADDPINS 2
|
||||
#define KINETIS_DDR_CMDAGE 255
|
||||
#define KINETIS_DDR_AGECNT 255
|
||||
#define KINETIS_DDR_R2WSAME 2
|
||||
#define KINETIS_DDR_RDDTENBAS 2
|
||||
#define KINETIS_DDR_PHYRDLAT 6
|
||||
#define KINETIS_DDR_PYWRLTBS 2
|
||||
#define KINETIS_DDR_CTRLUPDMX 968
|
||||
#define KINETIS_DDR_PHYUPDTY1 968
|
||||
#define KINETIS_DDR_PHYUPDTY0 968
|
||||
#define KINETIS_DDR_PHYUPDTY3 968
|
||||
#define KINETIS_DDR_PHYUPDTY2 968
|
||||
#define KINETIS_DDR_WRLATADJ 2
|
||||
#define KINETIS_DDR_RDLATADJ 3
|
||||
#define KINETIS_DDR_PHYUPDRESP 968
|
||||
#define KINETIS_DDR_CLKENDLY 1
|
||||
#define KINETIS_DDR_CMDDLY 2
|
||||
|
||||
/*
|
||||
* Micron MT47H[...] DDR2 SDRAM memory chip configuration registers
|
||||
*/
|
||||
/*
|
||||
* Mode Register (MR)
|
||||
*/
|
||||
#define MT47H_MR_WR_BITS 9
|
||||
/* CAS Latency (CL) */
|
||||
#define MT47H_MR_CL_BITS 4
|
||||
/* Burst Length */
|
||||
#define MT47H_MR_BL_BITS 0
|
||||
/* Burst Length = 4 */
|
||||
#define MT47H_MR_BL_4 (2 << MT47H_MR_BL_BITS)
|
||||
/*
|
||||
* Extended Mode Register
|
||||
*/
|
||||
/* Enables the 75 Ohms resistor */
|
||||
#define MT47H_EMR_RTT_75_MSK (1 << 2)
|
||||
/* Enables the 150 Ohms resistor */
|
||||
#define MT47H_EMR_RTT_150_MSK (1 << 6)
|
||||
|
||||
/*
|
||||
* SDRAM configuration options
|
||||
*/
|
||||
/* Write Recovery (WR) = 2 */
|
||||
#define SDRAM_MR_WR 2
|
||||
/* CAS Latency (CL) */
|
||||
#define SDRAM_MR_CL 3
|
||||
/* Burst Length */
|
||||
#define SDRAM_MR_BL MT47H_MR_BL_4
|
||||
|
||||
/*
|
||||
* DDR2 memory chip 16-bit registers
|
||||
*/
|
||||
/* Mode Register (MR) */
|
||||
#define KINETIS_DDR_MR0DAT0 \
|
||||
(((SDRAM_MR_WR - 1) << MT47H_MR_WR_BITS) | \
|
||||
(SDRAM_MR_CL << MT47H_MR_CL_BITS) | \
|
||||
SDRAM_MR_BL)
|
||||
/* Extended Mode Register (EMR) */
|
||||
#define KINETIS_DDR_MR1DAT0 MT47H_EMR_RTT_75_MSK
|
||||
/* Extended Mode Register 2 (EMR2) */
|
||||
#define KINETIS_DDR_MR2DAT0 0
|
||||
/* Extended Mode Register 3 (EMR3) */
|
||||
#define KINETIS_DDR_MR3DAT0 0
|
||||
|
||||
/*
|
||||
* DDR Control Register 0 (DDR_CR00)
|
||||
*/
|
||||
|
||||
/* DDR2 */
|
||||
#define KINETIS_DDR_CR00_DDRCLS_DDR2 (4 << 8)
|
||||
#define KINETIS_DDR_CR00_START_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 2 (DDR_CR02)
|
||||
*/
|
||||
#define KINETIS_DDR_CR02_INITAREF_BITS 24
|
||||
#define KINETIS_DDR_CR02_TINIT_BITS 0
|
||||
/*
|
||||
* DDR Control Register 3 (DDR_CR03)
|
||||
*/
|
||||
#define KINETIS_DDR_CR03_TCCD_BITS 24
|
||||
#define KINETIS_DDR_CR03_WRLAT_BITS 16
|
||||
#define KINETIS_DDR_CR03_LATGATE_BITS 8
|
||||
#define KINETIS_DDR_CR03_LATLIN_BITS 0
|
||||
/*
|
||||
* DDR Control Register 4 (DDR_CR04)
|
||||
*/
|
||||
#define KINETIS_DDR_CR04_TRASMIN_BITS 24
|
||||
#define KINETIS_DDR_CR04_TRC_BITS 16
|
||||
#define KINETIS_DDR_CR04_TRRD_BITS 8
|
||||
#define KINETIS_DDR_CR04_TBINT_BITS 0
|
||||
/*
|
||||
* DDR Control Register 5 (DDR_CR05)
|
||||
*/
|
||||
#define KINETIS_DDR_CR05_TMRD_BITS 24
|
||||
#define KINETIS_DDR_CR05_TRTP_BITS 16
|
||||
#define KINETIS_DDR_CR05_TRP_BITS 8
|
||||
#define KINETIS_DDR_CR05_TWTR_BITS 0
|
||||
/*
|
||||
* DDR Control Register 6 (DDR_CR06)
|
||||
*/
|
||||
#define KINETIS_DDR_CR06_TRASMAX_BITS 8
|
||||
#define KINETIS_DDR_CR06_TMOD_BITS 0
|
||||
/*
|
||||
* DDR Control Register 7 (DDR_CR07)
|
||||
*/
|
||||
#define KINETIS_DDR_CR07_CCAPEN_MSK (1 << 24)
|
||||
#define KINETIS_DDR_CR07_TCKESR_BITS 8
|
||||
#define KINETIS_DDR_CR07_CLKPW_BITS 0
|
||||
/*
|
||||
* DDR Control Register 8 (DDR_CR08)
|
||||
*/
|
||||
#define KINETIS_DDR_CR08_TDAL_BITS 24
|
||||
#define KINETIS_DDR_CR08_TWR_BITS 16
|
||||
#define KINETIS_DDR_CR08_TRASDI_BITS 8
|
||||
#define KINETIS_DDR_CR08_TRAS_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 9 (DDR_CR09)
|
||||
*/
|
||||
#define KINETIS_DDR_CR09_BSTLEN_BITS 24
|
||||
#define KINETIS_DDR_CR09_BSTLEN_4W (2 << KINETIS_DDR_CR09_BSTLEN_BITS)
|
||||
#define KINETIS_DDR_CR09_TDLL_BITS 0
|
||||
/*
|
||||
* DDR Control Register 10 (DDR_CR10)
|
||||
*/
|
||||
#define KINETIS_DDR_CR10_TRPAB_BITS 24
|
||||
#define KINETIS_DDR_CR10_TCPD_BITS 8
|
||||
#define KINETIS_DDR_CR10_TFAW_BITS 0
|
||||
/*
|
||||
* DDR Control Register 11 (DDR_CR11)
|
||||
*/
|
||||
#define KINETIS_DDR_CR11_TREFEN_MSK (1 << 24)
|
||||
/*
|
||||
* DDR Control Register 12 (DDR_CR12)
|
||||
*/
|
||||
#define KINETIS_DDR_CR12_TREF_BITS 16
|
||||
#define KINETIS_DDR_CR12_TRFC_BITS 0
|
||||
/*
|
||||
* DDR Control Register 14 (DDR_CR14)
|
||||
*/
|
||||
#define KINETIS_DDR_CR14_TXSR_BITS 16
|
||||
#define KINETIS_DDR_CR14_TPDEX_BITS 0
|
||||
/*
|
||||
* DDR Control Register 15 (DDR_CR15)
|
||||
*/
|
||||
#define KINETIS_DDR_CR15_TXSNR_BITS 0
|
||||
/*
|
||||
* DDR Control Register 16 (DDR_CR16)
|
||||
*/
|
||||
#define KINETIS_DDR_CR16_QKREF_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 20 (DDR_CR20)
|
||||
*/
|
||||
#define KINETIS_DDR_CR20_CKSRX_BITS 16
|
||||
#define KINETIS_DDR_CR20_CKSRE_BITS 8
|
||||
/*
|
||||
* DDR Control Register 21 (DDR_CR21)
|
||||
*/
|
||||
#define KINETIS_DDR_CR21_MR1DAT0_BITS 16
|
||||
#define KINETIS_DDR_CR21_MR0DAT0_BITS 0
|
||||
/*
|
||||
* DDR Control Register 22 (DDR_CR22)
|
||||
*/
|
||||
#define KINETIS_DDR_CR22_MR3DAT0_BITS 16
|
||||
#define KINETIS_DDR_CR22_MR2DAT0_BITS 0
|
||||
/*
|
||||
* DDR Control Register 25 (DDR_CR25)
|
||||
*/
|
||||
#define KINETIS_DDR_CR25_APREBIT_BITS 24
|
||||
#define KINETIS_DDR_CR25_COLSIZ_BITS 16
|
||||
#define KINETIS_DDR_CR25_ADDPINS_BITS 8
|
||||
#define KINETIS_DDR_CR25_BNK8_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 26 (DDR_CR26)
|
||||
*/
|
||||
#define KINETIS_DDR_CR26_BNKSPT_MSK (1 << 24)
|
||||
#define KINETIS_DDR_CR26_ADDCOL_MSK (1 << 16)
|
||||
#define KINETIS_DDR_CR26_CMDAGE_BITS 8
|
||||
#define KINETIS_DDR_CR26_AGECNT_BITS 0
|
||||
/*
|
||||
* DDR Control Register 27 (DDR_CR27)
|
||||
*/
|
||||
#define KINETIS_DDR_CR27_SWPEN_MSK (1 << 24)
|
||||
#define KINETIS_DDR_CR27_RWEN_MSK (1 << 16)
|
||||
#define KINETIS_DDR_CR27_PRIEN_MSK (1 << 8)
|
||||
#define KINETIS_DDR_CR27_PLEN_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 28 (DDR_CR28)
|
||||
*/
|
||||
#define KINETIS_DDR_CR28_CSMAP_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 30 (DDR_CR30)
|
||||
*/
|
||||
#define KINETIS_DDR_CR30_INTSTAT_DRAMINIT_MSK (1 << 10)
|
||||
#define KINETIS_DDR_CR30_RSYNCRF_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 34 (DDR_CR34)
|
||||
*/
|
||||
#define KINETIS_DDR_CR34_ODTWRCS_MSK (1 << 8)
|
||||
#define KINETIS_DDR_CR34_ODTRDC_MSK (1 << 0)
|
||||
/*
|
||||
* DDR Control Register 37 (DDR_CR37)
|
||||
*/
|
||||
#define KINETIS_DDR_CR37_R2WSAME_BITS 8
|
||||
/*
|
||||
* DDR Control Register 38 (DDR_CR38)
|
||||
*/
|
||||
#define KINETIS_DDR_CR38_P0WRCNT_BITS 16
|
||||
/*
|
||||
* DDR Control Register 39 (DDR_CR39)
|
||||
*/
|
||||
#define KINETIS_DDR_CR39_WP0_BITS 24
|
||||
#define KINETIS_DDR_CR39_RP0_BITS 16
|
||||
#define KINETIS_DDR_CR39_P0RDCNT_BITS 0
|
||||
/*
|
||||
* DDR Control Register 40 (DDR_CR40)
|
||||
*/
|
||||
#define KINETIS_DDR_CR40_P1WRCNT_BITS 8
|
||||
#define KINETIS_DDR_CR40_P0TYP_BITS 0
|
||||
/*
|
||||
* DDR Control Register 41 (DDR_CR41)
|
||||
*/
|
||||
#define KINETIS_DDR_CR41_WP1_BITS 24
|
||||
#define KINETIS_DDR_CR41_RP1_BITS 16
|
||||
#define KINETIS_DDR_CR41_P1RDCNT_BITS 0
|
||||
/*
|
||||
* DDR Control Register 42 (DDR_CR42)
|
||||
*/
|
||||
#define KINETIS_DDR_CR42_P2WRCNT_BITS 8
|
||||
#define KINETIS_DDR_CR42_P1TYP_BITS 0
|
||||
/*
|
||||
* DDR Control Register 43 (DDR_CR43)
|
||||
*/
|
||||
#define KINETIS_DDR_CR43_WP2_BITS 24
|
||||
#define KINETIS_DDR_CR43_RP2_BITS 16
|
||||
#define KINETIS_DDR_CR43_P2RDCNT_BITS 0
|
||||
/*
|
||||
* DDR Control Register 44 (DDR_CR44)
|
||||
*/
|
||||
#define KINETIS_DDR_CR44_P2TYP_BITS 0
|
||||
/*
|
||||
* DDR Control Register 45 (DDR_CR45)
|
||||
*/
|
||||
#define KINETIS_DDR_CR45_P0PRI3_BITS 24
|
||||
#define KINETIS_DDR_CR45_P0PRI2_BITS 16
|
||||
#define KINETIS_DDR_CR45_P0PRI1_BITS 8
|
||||
#define KINETIS_DDR_CR45_P0PRI0_BITS 0
|
||||
/*
|
||||
* DDR Control Register 46 (DDR_CR46)
|
||||
*/
|
||||
#define KINETIS_DDR_CR46_P1PRI0_BITS 24
|
||||
#define KINETIS_DDR_CR46_P0PRIRLX_BITS 8
|
||||
#define KINETIS_DDR_CR46_P0ORD_BITS 0
|
||||
/*
|
||||
* DDR Control Register 47 (DDR_CR47)
|
||||
*/
|
||||
#define KINETIS_DDR_CR47_P1ORD_BITS 24
|
||||
#define KINETIS_DDR_CR47_P1PRI3_BITS 16
|
||||
#define KINETIS_DDR_CR47_P1PRI2_BITS 8
|
||||
#define KINETIS_DDR_CR47_P1PRI1_BITS 0
|
||||
/*
|
||||
* DDR Control Register 48 (DDR_CR48)
|
||||
*/
|
||||
#define KINETIS_DDR_CR48_P2PRI1_BITS 24
|
||||
#define KINETIS_DDR_CR48_P2PRI0_BITS 16
|
||||
#define KINETIS_DDR_CR48_P1PRIRLX_BITS 0
|
||||
/*
|
||||
* DDR Control Register 49 (DDR_CR49)
|
||||
*/
|
||||
#define KINETIS_DDR_CR49_P2ORD_BITS 16
|
||||
#define KINETIS_DDR_CR49_P2PRI3_BITS 8
|
||||
#define KINETIS_DDR_CR49_P2PRI2_BITS 0
|
||||
/*
|
||||
* DDR Control Register 50 (DDR_CR50)
|
||||
*/
|
||||
#define KINETIS_DDR_CR50_P2PRIRLX_BITS 0
|
||||
/*
|
||||
* DDR Control Register 52 (DDR_CR52)
|
||||
*/
|
||||
#define KINETIS_DDR_CR52_RDDTENBAS_BITS 24
|
||||
#define KINETIS_DDR_CR52_PHYRDLAT_BITS 8
|
||||
#define KINETIS_DDR_CR52_PYWRLTBS_BITS 0
|
||||
/*
|
||||
* DDR Control Register 53 (DDR_CR53)
|
||||
*/
|
||||
#define KINETIS_DDR_CR53_CTRLUPDMX_BITS 16
|
||||
/*
|
||||
* DDR Control Register 54 (DDR_CR54)
|
||||
*/
|
||||
#define KINETIS_DDR_CR54_PHYUPDTY1_BITS 16
|
||||
#define KINETIS_DDR_CR54_PHYUPDTY0_BITS 0
|
||||
/*
|
||||
* DDR Control Register 55 (DDR_CR55)
|
||||
*/
|
||||
#define KINETIS_DDR_CR55_PHYUPDTY3_BITS 16
|
||||
#define KINETIS_DDR_CR55_PHYUPDTY2_BITS 0
|
||||
/*
|
||||
* DDR Control Register 56 (DDR_CR56)
|
||||
*/
|
||||
#define KINETIS_DDR_CR56_WRLATADJ_BITS 24
|
||||
#define KINETIS_DDR_CR56_RDLATADJ_BITS 16
|
||||
#define KINETIS_DDR_CR56_PHYUPDRESP_BITS 0
|
||||
/*
|
||||
* DDR Control Register 57 (DDR_CR57)
|
||||
*/
|
||||
#define KINETIS_DDR_CR57_ODTALTEN_MSK (1 << 24)
|
||||
#define KINETIS_DDR_CR57_CLKENDLY_BITS 16
|
||||
#define KINETIS_DDR_CR57_CMDDLY_BITS 0
|
||||
/*
|
||||
* RCR Control Register (DDR_RCR)
|
||||
*/
|
||||
#define KINETIS_DDR_RCR_RST_MSK (1 << 30)
|
||||
/*
|
||||
* I/O Pad Control Register (DDR_PAD_CTRL)
|
||||
*/
|
||||
/* Required to enable ODT and configure ODT resistor value in the pad */
|
||||
#define KINETIS_DDR_PAD_CTRL_PAD_ODT_CS0_BITS 24
|
||||
/* 75 Ohms */
|
||||
#define KINETIS_DDR_PAD_CTRL_CS0_75 \
|
||||
(1 << KINETIS_DDR_PAD_CTRL_PAD_ODT_CS0_BITS)
|
||||
/* SPARE_DLY_CTRL[1:0] is used to control the delay chain #0 */
|
||||
#define KINETIS_DDR_PAD_CTRL_SPARE_DLY_CTRL_BITS 0
|
||||
/* 10 buffers */
|
||||
#define KINETIS_DDR_PAD_CTRL_DELAY_10BUF \
|
||||
(3 << KINETIS_DDR_PAD_CTRL_SPARE_DLY_CTRL_BITS)
|
||||
/* This bit should always be written into PAD_CTRL (undocumented feature) */
|
||||
#define KINETIS_DDR_PAD_CTRL_FIXED_MSK (1 << 9)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCfsl_KinetisMemh */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,285 @@
|
||||
/* omapIRQ.h - Interrupt IRQ definitions for LogicPD OMAP35x */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,07oct10,dbr Add interrupts defs for GPIO
|
||||
01c,05oct10,dbr add interrupts defs for I2C
|
||||
01b,20sep10,rdl add support for MPU PRCM interrupts
|
||||
01a,11aug10,chs port to LogicPD board
|
||||
*/
|
||||
|
||||
/*
|
||||
This file contains definitions for mapping Interrupts on the LogicPD OMAP35x
|
||||
board.
|
||||
|
||||
See Also OMAP35xx Applications Processor Technical Reference Manual,
|
||||
Texas Instruments.
|
||||
*/
|
||||
|
||||
#ifndef __INComapIRQh
|
||||
#define __INComapIRQh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Interrupt priority */
|
||||
|
||||
#define OMAP_INT_PRI_UART_1 3 /* UART 1 */
|
||||
#define OMAP_INT_PRI_UART_2 3 /* UART 2 */
|
||||
#define OMAP_INT_PRI_UART_3 3 /* UART 3 */
|
||||
#define OMAP_INT_PRI_I2C_1 4 /* I2C 1 */
|
||||
#define OMAP_INT_PRI_I2C_2 4 /* I2C 2 */
|
||||
#define OMAP_INT_PRI_I2C_3 4 /* I2C 3 */
|
||||
#define OMAP_INT_PRI_TIMER_1 0 /* timer 1 */
|
||||
#define OMAP_INT_PRI_TIMER_2 6 /* timer 2 */
|
||||
#define OMAP_INT_PRI_TIMER_3 8 /* timer 3 */
|
||||
#define OMAP_INT_PRI_ENET 4 /* ethernet interrupt(GPIO-E) */
|
||||
#define OMAP_INT_PRI_MAIL_U0_MPU 9 /* mailbox interrupt */
|
||||
#define OMAP_INT_PRI_IVA2_MMU 9 /* iva2 subsystem interrupt */
|
||||
#define OMAP_INT_PRI_MHCI 10 /* mhci */
|
||||
#define OMAP_INT_PRI_GPIO_1 7 /* GPIO module 1 */
|
||||
#define OMAP_INT_PRI_GPIO_2 7 /* GPIO module 2 */
|
||||
#define OMAP_INT_PRI_GPIO_3 7 /* GPIO module 3 */
|
||||
#define OMAP_INT_PRI_GPIO_4 7 /* GPIO module 4 */
|
||||
#define OMAP_INT_PRI_GPIO_5 7 /* GPIO module 5 */
|
||||
#define OMAP_INT_PRI_GPIO_6 7 /* GPIO module 6 */
|
||||
|
||||
/* IRQ numbers */
|
||||
|
||||
#define OMAP_M_IRQ_0 0
|
||||
#define OMAP_M_IRQ_1 1
|
||||
#define OMAP_M_IRQ_2 2
|
||||
#define OMAP_M_IRQ_3 3
|
||||
#define OMAP_M_IRQ_4 4
|
||||
#define OMAP_M_IRQ_5 5
|
||||
#define OMAP_M_IRQ_6 6
|
||||
#define OMAP_M_IRQ_7 7
|
||||
#define OMAP_M_IRQ_8 8
|
||||
#define OMAP_M_IRQ_9 9
|
||||
#define OMAP_M_IRQ_10 10
|
||||
#define OMAP_M_IRQ_11 11
|
||||
#define OMAP_M_IRQ_12 12
|
||||
#define OMAP_M_IRQ_13 13
|
||||
#define OMAP_M_IRQ_14 14
|
||||
#define OMAP_M_IRQ_15 15
|
||||
#define OMAP_M_IRQ_16 16
|
||||
#define OMAP_M_IRQ_17 17
|
||||
#define OMAP_M_IRQ_18 18
|
||||
#define OMAP_M_IRQ_19 19
|
||||
#define OMAP_M_IRQ_20 20
|
||||
#define OMAP_M_IRQ_21 21
|
||||
#define OMAP_M_IRQ_22 22
|
||||
#define OMAP_M_IRQ_23 23
|
||||
#define OMAP_M_IRQ_24 24
|
||||
#define OMAP_M_IRQ_25 25
|
||||
#define OMAP_M_IRQ_26 26
|
||||
#define OMAP_M_IRQ_27 27
|
||||
#define OMAP_M_IRQ_28 28
|
||||
#define OMAP_M_IRQ_29 29
|
||||
#define OMAP_M_IRQ_30 30
|
||||
#define OMAP_M_IRQ_31 31
|
||||
#define OMAP_M_IRQ_32 32
|
||||
#define OMAP_M_IRQ_33 33
|
||||
#define OMAP_M_IRQ_34 34
|
||||
#define OMAP_M_IRQ_35 35
|
||||
#define OMAP_M_IRQ_36 36
|
||||
#define OMAP_M_IRQ_37 37
|
||||
#define OMAP_M_IRQ_38 38
|
||||
#define OMAP_M_IRQ_39 39
|
||||
#define OMAP_M_IRQ_40 40
|
||||
#define OMAP_M_IRQ_41 41
|
||||
#define OMAP_M_IRQ_42 42
|
||||
#define OMAP_M_IRQ_43 43
|
||||
#define OMAP_M_IRQ_44 44
|
||||
#define OMAP_M_IRQ_45 45
|
||||
#define OMAP_M_IRQ_46 46
|
||||
#define OMAP_M_IRQ_47 47
|
||||
#define OMAP_M_IRQ_48 48
|
||||
#define OMAP_M_IRQ_49 49
|
||||
#define OMAP_M_IRQ_50 50
|
||||
#define OMAP_M_IRQ_51 51
|
||||
#define OMAP_M_IRQ_52 52
|
||||
#define OMAP_M_IRQ_53 53
|
||||
#define OMAP_M_IRQ_54 54
|
||||
#define OMAP_M_IRQ_55 55
|
||||
#define OMAP_M_IRQ_56 56
|
||||
#define OMAP_M_IRQ_57 57
|
||||
#define OMAP_M_IRQ_58 58
|
||||
#define OMAP_M_IRQ_59 59
|
||||
#define OMAP_M_IRQ_60 60
|
||||
#define OMAP_M_IRQ_61 61
|
||||
#define OMAP_M_IRQ_62 62
|
||||
#define OMAP_M_IRQ_63 63
|
||||
#define OMAP_M_IRQ_64 64
|
||||
#define OMAP_M_IRQ_65 65
|
||||
#define OMAP_M_IRQ_66 66
|
||||
#define OMAP_M_IRQ_67 67
|
||||
#define OMAP_M_IRQ_68 68
|
||||
#define OMAP_M_IRQ_69 69
|
||||
#define OMAP_M_IRQ_70 70
|
||||
#define OMAP_M_IRQ_71 71
|
||||
#define OMAP_M_IRQ_72 72
|
||||
#define OMAP_M_IRQ_73 73
|
||||
#define OMAP_M_IRQ_74 74
|
||||
#define OMAP_M_IRQ_75 75
|
||||
#define OMAP_M_IRQ_76 76
|
||||
#define OMAP_M_IRQ_77 77
|
||||
#define OMAP_M_IRQ_78 78
|
||||
#define OMAP_M_IRQ_79 79
|
||||
#define OMAP_M_IRQ_80 80
|
||||
#define OMAP_M_IRQ_81 81
|
||||
#define OMAP_M_IRQ_82 82
|
||||
#define OMAP_M_IRQ_83 83
|
||||
#define OMAP_M_IRQ_84 84
|
||||
#define OMAP_M_IRQ_85 85
|
||||
#define OMAP_M_IRQ_86 86
|
||||
#define OMAP_M_IRQ_87 87
|
||||
#define OMAP_M_IRQ_88 88
|
||||
#define OMAP_M_IRQ_89 89
|
||||
#define OMAP_M_IRQ_90 90
|
||||
#define OMAP_M_IRQ_91 91
|
||||
#define OMAP_M_IRQ_92 92
|
||||
#define OMAP_M_IRQ_93 93
|
||||
#define OMAP_M_IRQ_94 94
|
||||
#define OMAP_M_IRQ_95 95
|
||||
|
||||
#define OMAP_TOP_MPU_IRQ OMAP_M_IRQ_95 + 1
|
||||
|
||||
/* Interrupt Mappings to the MPU Subsystem */
|
||||
|
||||
#define OMAP_EMUINT OMAP_M_IRQ_0 /* MPU emulation(2) */
|
||||
#define OMAP_COMMTX OMAP_M_IRQ_1 /* MPU emulation(2) */
|
||||
#define OMAP_COMMRX OMAP_M_IRQ_2 /* MPU emulation(2) */
|
||||
#define OMAP_BENCH OMAP_M_IRQ_3 /* MPU emulation(2) */
|
||||
#define OMAP_MCBSP2_ST_IRQ OMAP_M_IRQ_4 /* Sidetone MCBSP2 overflow */
|
||||
#define OMAP_MCBSP3_ST_IRQ OMAP_M_IRQ_5 /* Sidetone MCBSP3 overflow */
|
||||
#define OMAP_SSM_ABORT_IRQ OMAP_M_IRQ_6 /* MPU subsys secure st-mach abrt */
|
||||
#define OMAP_SYS_NIRQ OMAP_M_IRQ_7 /* External source (active low) */
|
||||
#define OMAP_SMX_DBG_IRQ OMAP_M_IRQ_9 /* SMX error for debug */
|
||||
#define OMAP_SMX_APP_IRQ OMAP_M_IRQ_10 /* SMX error for application */
|
||||
#define OMAP_PRCM_MPU_IRQ OMAP_M_IRQ_11 /* PRCM module IRQ */
|
||||
#define OMAP_SDMA_IRQ0 OMAP_M_IRQ_12 /* System DMA request 0(3) */
|
||||
#define OMAP_SDMA_IRQ1 OMAP_M_IRQ_13 /* System DMA request 1(3) */
|
||||
#define OMAP_SDMA_IRQ2 OMAP_M_IRQ_14 /* System DMA request 2 */
|
||||
#define OMAP_SDMA_IRQ3 OMAP_M_IRQ_15 /* System DMA request 3 */
|
||||
#define OMAP_MCBSP1_IRQ OMAP_M_IRQ_16 /* McBSP module 1 IRQ (3) */
|
||||
#define OMAP_MCBSP2_IRQ OMAP_M_IRQ_17 /* McBSP module 2 IRQ (3) */
|
||||
#define OMAP_SR1_IRQ OMAP_M_IRQ_18 /* SmartReflex 1 */
|
||||
#define OMAP_SR2_IRQ OMAP_M_IRQ_19 /* SmartReflex 2 */
|
||||
#define OMAP_GPMC_IRQ OMAP_M_IRQ_20 /* General-purpose mem ctrlr */
|
||||
#define OMAP_SGX_IRQ OMAP_M_IRQ_21 /* 2D/3D graphics module */
|
||||
#define OMAP_MCBSP3_IRQ OMAP_M_IRQ_22 /* McBSP module 3(3) */
|
||||
#define OMAP_MCBSP4_IRQ OMAP_M_IRQ_23 /* McBSP module 4(3) */
|
||||
#define OMAP_CAOMAP_M_IRQ0 OMAP_M_IRQ_24 /* Camera interface request 0 */
|
||||
#define OMAP_DSS_IRQ OMAP_M_IRQ_25 /* Display subsystem module(3) */
|
||||
#define OMAP_MAIL_U0_MPU_IRQ OMAP_M_IRQ_26 /* Mailbox user 0 request */
|
||||
#define OMAP_MCBSP5_IRQ OMAP_M_IRQ_27 /* McBSP module 5 (3) */
|
||||
#define OMAP_IVA2_MMU_IRQ OMAP_M_IRQ_28 /* IVA2 MMU */
|
||||
#define OMAP_GPIO1_MPU_IRQ OMAP_M_IRQ_29 /* GPIO module 1(3) */
|
||||
#define OMAP_GPIO2_MPU_IRQ OMAP_M_IRQ_30 /* GPIO module 2(3) */
|
||||
#define OMAP_GPIO3_MPU_IRQ OMAP_M_IRQ_31 /* GPIO module 3(3) */
|
||||
#define OMAP_GPIO4_MPU_IRQ OMAP_M_IRQ_32 /* GPIO module 4(3) */
|
||||
#define OMAP_GPIO5_MPU_IRQ OMAP_M_IRQ_33 /* GPIO module 5(3) */
|
||||
#define OMAP_GPIO6_MPU_IRQ OMAP_M_IRQ_34 /* GPIO module 6(3) */
|
||||
#define OMAP_USIOMAP_M_IRQ OMAP_M_IRQ_35 /* USIM interrupt (HS devs)(4) */
|
||||
#define OMAP_WDT3_IRQ OMAP_M_IRQ_36 /* Watchdog timer module 3 ovrflow */
|
||||
#define OMAP_GPT1_IRQ OMAP_M_IRQ_37 /* General-purpose timer module 1 */
|
||||
#define OMAP_GPT2_IRQ OMAP_M_IRQ_38 /* General-purpose timer module 2 */
|
||||
#define OMAP_GPT3_IRQ OMAP_M_IRQ_39 /* General-purpose timer module 3 */
|
||||
#define OMAP_GPT4_IRQ OMAP_M_IRQ_40 /* General-purpose timer module 4 */
|
||||
#define OMAP_GPT5_IRQ OMAP_M_IRQ_41 /* General-purpose timer mod 5(3) */
|
||||
#define OMAP_GPT6_IRQ OMAP_M_IRQ_42 /* General-purpose timer mod 6(3) */
|
||||
#define OMAP_GPT7_IRQ OMAP_M_IRQ_43 /* General-purpose timer mod 7(3) */
|
||||
#define OMAP_GPT8_IRQ OMAP_M_IRQ_44 /* General-purpose timer mod 8(3) */
|
||||
#define OMAP_GPT9_IRQ OMAP_M_IRQ_45 /* General-purpose timer module 9 */
|
||||
#define OMAP_GPT10_IRQ OMAP_M_IRQ_46 /* General-purpose timer module 10 */
|
||||
#define OMAP_GPT11_IRQ OMAP_M_IRQ_47 /* General-purpose timer module 11 */
|
||||
#define OMAP_SPI4_IRQ OMAP_M_IRQ_48 /* McSPI module 4 */
|
||||
#define OMAP_SHA1MD5_IRQ2 OMAP_M_IRQ_49 /* SHA-1/MD5 crypto-acc 2(HS devs) */
|
||||
#define OMAP_FPKA_IRQREADY_N OMAP_M_IRQ_50 /* PKA crypto-accel (HS devs) */
|
||||
#define OMAP_SHA2MD5_IRQ OMAP_M_IRQ_51 /* SHA-2/MD5 crypto-accel1(HS devs */
|
||||
#define OMAP_RNG_IRQ OMAP_M_IRQ_52 /* RNG module (HS devices only) */
|
||||
#define OMAP_MG_IRQ OMAP_M_IRQ_53 /* MG function (3) */
|
||||
#define OMAP_MCBSP4_IRQ_TX OMAP_M_IRQ_54 /* McBSP module 4 transmit(3) */
|
||||
#define OMAP_MCBSP4_IRQ_RX OMAP_M_IRQ_55 /* McBSP module 4 receive(3) */
|
||||
#define OMAP_I2C1_IRQ OMAP_M_IRQ_56 /* I2C module 1 */
|
||||
#define OMAP_I2C2_IRQ OMAP_M_IRQ_57 /* I2C module 2 */
|
||||
#define OMAP_HDQ_IRQ OMAP_M_IRQ_58 /* HDQ/One-wire */
|
||||
#define OMAP_McBSP1_IRQ_TX OMAP_M_IRQ_59 /* McBSP module 1 transmit(3) */
|
||||
#define OMAP_McBSP1_IRQ_RX OMAP_M_IRQ_60 /* McBSP module 1 receive(3) */
|
||||
#define OMAP_I2C3_IRQ OMAP_M_IRQ_61 /* I2C module 3 */
|
||||
#define OMAP_McBSP2_IRQ_TX OMAP_M_IRQ_62 /* McBSP module 2 transmit(3) */
|
||||
#define OMAP_McBSP2_IRQ_RX OMAP_M_IRQ_63 /* McBSP module 2 receive(3) */
|
||||
#define OMAP_FPKA_IRQRERROR_N OMAP_M_IRQ_64 /* PKA crypto-accel (HS devs) */
|
||||
#define OMAP_SPI1_IRQ OMAP_M_IRQ_65 /* McSPI module 1 */
|
||||
#define OMAP_SPI2_IRQ OMAP_M_IRQ_66 /* McSPI module 2 */
|
||||
#define OMAP_UART1_IRQ OMAP_M_IRQ_72 /* UART module 1 */
|
||||
#define OMAP_UART2_IRQ OMAP_M_IRQ_73 /* UART module 2 */
|
||||
#define OMAP_UART3_IRQ OMAP_M_IRQ_74 /* UART module 3 (& infrared)(3) */
|
||||
#define OMAP_PBIAS_IRQ OMAP_M_IRQ_75 /* Merged itrpt for PBIASlite1 & 2 */
|
||||
#define OMAP_OHCI_IRQ OMAP_M_IRQ_76 /* OHCI ctrlr HSUSB MP Host Intrpt */
|
||||
#define OMAP_EHCI_IRQ OMAP_M_IRQ_77 /* EHCI ctrlr HSUSB MP Host Intrpt */
|
||||
#define OMAP_TLL_IRQ OMAP_M_IRQ_78 /* HSUSB MP TLL Interrupt */
|
||||
#define OMAP_PARTHASH_IRQ OMAP_M_IRQ_79 /* SHA2/MD5 crypto-accel 1 HS devs */
|
||||
#define OMAP_MCBSP5_IRQ_TX OMAP_M_IRQ_81 /* McBSP module 5 transmit(3) */
|
||||
#define OMAP_MCBSP5_IRQ_RX OMAP_M_IRQ_82 /* McBSP module 5 receive(3) */
|
||||
#define OMAP_MMC1_IRQ OMAP_M_IRQ_83 /* MMC/SD module 1 */
|
||||
#define OMAP_MS_IRQ OMAP_M_IRQ_84 /* MS-PRO module */
|
||||
#define OMAP_MMC2_IRQ OMAP_M_IRQ_86 /* MMC/SD module 2 */
|
||||
#define OMAP_MPU_ICR_IRQ OMAP_M_IRQ_87 /* MPU ICR */
|
||||
#define OMAP_MCBSP3_IRQ_TX OMAP_M_IRQ_89 /* McBSP module 3 transmit(3) */
|
||||
#define OMAP_MCBSP3_IRQ_RX OMAP_M_IRQ_90 /* McBSP module 3 receive(3) */
|
||||
#define OMAP_SPI3_IRQ OMAP_M_IRQ_91 /* McSPI module 3 */
|
||||
#define OMAP_HSUSB_MC_NINT OMAP_M_IRQ_92 /* High-Speed USB OTG controller */
|
||||
#define OMAP_HSUSB_DMA_NINT OMAP_M_IRQ_93 /* High-Speed USB OTG DMA ctrlr */
|
||||
#define OMAP_MMC3_IRQ OMAP_M_IRQ_94 /* MMC/SD module 3 */
|
||||
#define OMAP_GPT12_IRQ OMAP_M_IRQ_95 /* General-purpose timer module 12 */
|
||||
|
||||
#define OMAP_LAN9115_IRQ OMAP_GPIO5_MPU_IRQ
|
||||
|
||||
|
||||
/* MPU PRCM interrupts */
|
||||
|
||||
#define OMAP_MPU_PRCM_WKUP_IRQ (OMAP_TOP_MPU_IRQ + 0)
|
||||
#define OMAP_MPU_PRCM_RESERVED_IRQ (OMAP_TOP_MPU_IRQ + 1)
|
||||
#define OMAP_MPU_PRCM_EVGENON_IRQ (OMAP_TOP_MPU_IRQ + 2)
|
||||
#define OMAP_MPU_PRCM_EVGENOFF_IRQ (OMAP_TOP_MPU_IRQ + 3)
|
||||
#define OMAP_MPU_PRCM_TRANSITION_IRQ (OMAP_TOP_MPU_IRQ + 4)
|
||||
#define OMAP_MPU_PRCM_CORE_DPLL_IRQ (OMAP_TOP_MPU_IRQ + 5)
|
||||
#define OMAP_MPU_PRCM_PERIPH_DPLL_IRQ (OMAP_TOP_MPU_IRQ + 6)
|
||||
#define OMAP_MPU_PRCM_MPU_DPLL_IRQ (OMAP_TOP_MPU_IRQ + 7)
|
||||
#define OMAP_MPU_PRCM_IVA2_DPLL_IRQ (OMAP_TOP_MPU_IRQ + 8)
|
||||
#define OMAP_MPU_PRCM_IO_IRQ (OMAP_TOP_MPU_IRQ + 9)
|
||||
#define OMAP_MPU_PRCM_VP1_OPPCHANGEDONE_IRQ (OMAP_TOP_MPU_IRQ + 10)
|
||||
#define OMAP_MPU_PRCM_VP1_MINVDD_IRQ (OMAP_TOP_MPU_IRQ + 11)
|
||||
#define OMAP_MPU_PRCM_VP1_MAXVDD_IRQ (OMAP_TOP_MPU_IRQ + 12)
|
||||
#define OMAP_MPU_PRCM_VP1_NOSMPSACK_IRQ (OMAP_TOP_MPU_IRQ + 13)
|
||||
#define OMAP_MPU_PRCM_VP1_EQVALUE_IRQ (OMAP_TOP_MPU_IRQ + 14)
|
||||
#define OMAP_MPU_PRCM_VP1_TRANXDONE_IRQ (OMAP_TOP_MPU_IRQ + 15)
|
||||
#define OMAP_MPU_PRCM_VP2_OPPCHANGEDONE_IRQ (OMAP_TOP_MPU_IRQ + 16)
|
||||
#define OMAP_MPU_PRCM_VP2_MINVDD_IRQ (OMAP_TOP_MPU_IRQ + 17)
|
||||
#define OMAP_MPU_PRCM_VP2_MAXVDD_IRQ (OMAP_TOP_MPU_IRQ + 18)
|
||||
#define OMAP_MPU_PRCM_VP2_NOSMPSACK_IRQ (OMAP_TOP_MPU_IRQ + 19)
|
||||
#define OMAP_MPU_PRCM_VP2_EQVALUE_IRQ (OMAP_TOP_MPU_IRQ + 20)
|
||||
#define OMAP_MPU_PRCM_VP2_TRANXDONE_IRQ (OMAP_TOP_MPU_IRQ + 21)
|
||||
#define OMAP_MPU_PRCM_VC_SAERR_IRQ (OMAP_TOP_MPU_IRQ + 22)
|
||||
#define OMAP_MPU_PRCM_VC_RAERR_IRQ (OMAP_TOP_MPU_IRQ + 23)
|
||||
#define OMAP_MPU_PRCM_VC_TIMEOUTERR_IRQ (OMAP_TOP_MPU_IRQ + 24)
|
||||
#define OMAP_MPU_PRCM_SND_PERIPH_DPLL_RECAL_IRQ (OMAP_TOP_MPU_IRQ + 25)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INComapIRQh */
|
||||
@@ -0,0 +1,462 @@
|
||||
/* omap35xxSmartReflex.h - OMAP35x Smart Reflex header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2010, 2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,24mar11,rdl WIND00262928: BSP specific macro definitions in driver headers
|
||||
01j,07feb11,rec fix DPLL3_MNM2MSK value
|
||||
01i,11jan11,rdl add definitions for some masks, fix offset bug
|
||||
01h,06dec10,rdl fix some macro problems with SR
|
||||
01g,22nov10,rdl add voltage processor offsets
|
||||
01f,12nov10,rec DPLL1 unit test changes
|
||||
01e,10nov10,rec test fixes - correct DPLL3_MNM2MSK constant
|
||||
01d,09nov10,rdl add SR registers
|
||||
01c,19oct10,rec fix compiler warning
|
||||
01b,26oct10,rdl add macros for efuse values needed by SmartReflex
|
||||
01a,30Aug10,rec created
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains memory, I/O address and related Smart Reflex and DPLL
|
||||
* constants for the OMAP35x chip.
|
||||
*
|
||||
* See Also OMAP35xx Applications Processor NDA Technical Reference Manual,
|
||||
* Texas Instruments.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _INC_OMAP35XXSMARTREFLEX_H
|
||||
#define _INC_OMAP35XXSMARTREFLEX_H
|
||||
|
||||
/* SmartReflex constants for the OMAP35xx */
|
||||
|
||||
#define SR_CLK 100 /* khz */
|
||||
#define ACCUMDATA_WINDOW 5 /* ms Smart Reflex window period */
|
||||
#define ERRWEIGHT 0x07
|
||||
#define ERRMINLIMIT 0xF9
|
||||
|
||||
/* DPLL Jitter Correction values in khz (TRM table 4-39) */
|
||||
|
||||
#define DPLL_JITTER_00750 0x3
|
||||
#define DPLL_JITTER_01000 0x4
|
||||
#define DPLL_JITTER_01250 0x5
|
||||
#define DPLL_JITTER_01500 0x6
|
||||
#define DPLL_JITTER_01750 0x7
|
||||
#define DPLL_JITTER_07500 0xb
|
||||
#define DPLL_JITTER_10000 0xc
|
||||
#define DPLL_JITTER_12500 0xc
|
||||
#define DPLL_JITTER_15000 0xe
|
||||
#define DPLL_JITTER_17500 0xf
|
||||
|
||||
/*
|
||||
* definitions for setting up the DPLL register tables in hwconf
|
||||
* (see TRM 4.7.6.1)
|
||||
*
|
||||
* Register fields are scattered among various registers in the register set.
|
||||
* Most vxBus devices would use a base address that defines a standard set
|
||||
* of device registers. Accesses to the register set would be relative to
|
||||
* that base. TI didn't lay the hardware out that way however. Accesses
|
||||
* performed to setup the hardware is done using a table. Entries within the
|
||||
* table provide register address, field mask, and value required to setup
|
||||
* each voltage setpoint. More than one table entry is required for each
|
||||
* setpoint.
|
||||
*
|
||||
* There are three types of register records, a register setting record used
|
||||
* to modify the value of a register, a register condition record used
|
||||
* to test a register field and spin until the hardware responds, and an
|
||||
* end of record marker.
|
||||
*
|
||||
* The list of entries associated with each setpoint is terminated
|
||||
* with an REG_SETTING_END_MARKER record. The macros below are used to
|
||||
* construct table entries.
|
||||
*/
|
||||
|
||||
#define REG_SETTING_END_MARKER 0, 0, 0, REG_SETTING_END
|
||||
|
||||
#define DPLL1_MNVAL(m,n) ((m << 8) | n )
|
||||
#define DPLL1_MNMSK 0x7ff7f
|
||||
#define DPLL1_M2VAL(m2) (m2)
|
||||
#define DPLL1_M2MSK 0x1f
|
||||
#define DPLL1_FRESELMSK 0xf0
|
||||
#define DPLL1_JITTER(j) (j << 4)
|
||||
#define DPLL1_RAMPMSK 0x300
|
||||
#define DPLL1_RAMP(r) (r << 8)
|
||||
#define DPLL1_ENABLE 7
|
||||
#define DPLL1_BYPASS 5
|
||||
#define DPLL1_BYPASSED 0
|
||||
#define DPLL1_LOCKED 1
|
||||
|
||||
/* register configuration settings for DPPL1 {address, mask, value, jitter} */
|
||||
|
||||
#define DPLL1REGCFG(m,n,m2,j) \
|
||||
{(UINT32 *)OMAP35XX_CM_CLKSEL1_PLL_MPU, DPLL1_MNMSK, DPLL1_MNVAL(m,n), \
|
||||
PLL_REG_VALUE}, \
|
||||
{(UINT32 *)OMAP35XX_CM_CLKSEL2_PLL_MPU, DPLL1_M2MSK, DPLL1_M2VAL(m2), \
|
||||
PLL_REG_VALUE}, \
|
||||
{(UINT32 *)OMAP35XX_CM_CLKEN_PLL_MPU, DPLL1_FRESELMSK | DPLL1_ENABLE, \
|
||||
DPLL1_JITTER(j) | DPLL1_BYPASS, PLL_REG_VALUE},\
|
||||
{(UINT32 *)OMAP35XX_CM_IDLEST_PLL_MPU, DPLL1_LOCKED, DPLL1_BYPASSED, \
|
||||
PLL_CONDITION}, \
|
||||
{(UINT32 *)OMAP35XX_CM_CLKEN_PLL_MPU, DPLL1_RAMPMSK | DPLL1_ENABLE, \
|
||||
DPLL1_RAMP(2) | DPLL1_ENABLE, PLL_REG_VALUE}, \
|
||||
{(UINT32 *)OMAP35XX_CM_IDLEST_PLL_MPU, DPLL1_LOCKED, DPLL1_LOCKED, \
|
||||
PLL_CONDITION},\
|
||||
{REG_SETTING_END_MARKER}
|
||||
|
||||
#define DPLL3_MNM2VAL(m,n,m2) ((m << 16) | (n << 8) | (m2 << 27))
|
||||
#define DPLL3_MNM2MSK 0x000080ff
|
||||
#define DPLL3_FRESELMSK 0xf0
|
||||
#define DPLL3_JITTER(j) (j << 4)
|
||||
#define DPLL3_RAMPMSK 0x300
|
||||
#define DPLL3_RAMP(r) (r << 8)
|
||||
#define DPLL3_M2VAL(m2) (m2 << 27) /* only M2 changed for this dpll */
|
||||
#define DPLL3_M2MSK 0x07ffffff
|
||||
|
||||
/*
|
||||
* Register configuration settings for DPPL3
|
||||
*
|
||||
* Two macros are defined. Once changes only M2 while the other changes
|
||||
* the multipliers and dividers also.
|
||||
*
|
||||
*/
|
||||
|
||||
#define DPLL3REGCFG(m,n,m2,j) \
|
||||
{(UINT32 *)OMAP35XX_CM_CLKSEL1_PLL, DPLL3_MNM2MSK, DPLL3_MNM2VAL(m,n,m2), \
|
||||
PLL_REG_VALUE}, \
|
||||
{REG_SETTING_END_MARKER}
|
||||
|
||||
#define DPLL3M2REGCFG(m2) \
|
||||
{(UINT32 *)OMAP35XX_CM_CLKSEL1_PLL, DPLL3_M2MSK, DPLL3_M2VAL(m2), \
|
||||
PLL_REG_VALUE}, \
|
||||
{REG_SETTING_END_MARKER}
|
||||
|
||||
#define NUMBER_POWER_DOMAINS 2
|
||||
#define MPU_DOMAIN 0
|
||||
#define CORE_DOMAIN 1
|
||||
#define VDD_DEVICE 0
|
||||
#define DPLL_DEVICE 1
|
||||
|
||||
/* constants for computing clock switch latency */
|
||||
|
||||
#define DPLL_LATENCY(refFreq, rate) \
|
||||
(((((refFreq / 1000000 << 8) >> 9) + 1) * 9) >> 8) >0 ? \
|
||||
((((refFreq / 1000000 << 8) >> 9) + 1) * 9) >> 8 : 1
|
||||
|
||||
/* number of Smart Reflex units */
|
||||
|
||||
#define SR_UNITS 2
|
||||
|
||||
/* offsets between SR1 and SR2 */
|
||||
|
||||
#define SR1_OFFSET 0x0000
|
||||
#define SR2_OFFSET 0x2000
|
||||
|
||||
/* Smart reflex address offsets (from OMAP35xTRM 4.14.3 P660) */
|
||||
|
||||
#define SRCONFIG 0x00
|
||||
#define SRSTATUS 0x04
|
||||
#define SENVAL 0x08
|
||||
#define SENMIN 0x0C
|
||||
#define SENMAX 0x10
|
||||
#define SENAVG 0x14
|
||||
#define AVGWEIGHT 0x18
|
||||
#define NVALUERECIPROCAL 0x1C
|
||||
#define SENERROR 0x20
|
||||
#define ERRCONFIG 0x24
|
||||
|
||||
/* SRCONFIG register definitions */
|
||||
|
||||
/* TRM equation-2 (TRM 4.10.5.4.3) */
|
||||
|
||||
#define SRCONFIG_ACCUMDATA_MSK (0xFFC << 22)
|
||||
#define SRCONFIG_ACCUMDATA_POS 22
|
||||
#define SRCONFIG_ACCUMDATA_VAL (ACCUMDATA_WINDOW * SR_CLK)
|
||||
#define SRCONFIG_ACCUMDATA (SRCONFIG_ACCUMDATA_VAL << \
|
||||
SRCONFIG_ACCUMDATA_POS)
|
||||
#define SRCONFIG_ACCUMDATA_R(val) ((val >> \
|
||||
SRCONFIG_ACCUMDATA_POS) & 0x3FF)
|
||||
|
||||
/* TRM equation-1 (TRM 4.10.5.4.3) */
|
||||
|
||||
#define SRCONFIG_SRCLKLENGTH_MSK (0x3FF << 12)
|
||||
#define SRCONFIG_SRCLKLENGTH_POS 12
|
||||
#define SR_ALWON_FCLK (sysPrmClk/1000)
|
||||
#define SRCONFIG_SRCLKLENGTH_VAL (SR_ALWON_FCLK/(2 * SR_CLK))
|
||||
|
||||
/*
|
||||
* Clock setting (TRM 4.12.6.4, cookbook 14.2.2.1 i)
|
||||
* Setting the clock consists of configuring the internal clock frequency
|
||||
* of the SmartReflex module and the state of the functional clock when
|
||||
* the module switches to inactive state, and then enabling the
|
||||
* functional clock from the PRCM module of the device. The internal clock
|
||||
* frequency configuration depends on the frequency of SR_ALWON_FCLK and
|
||||
* can be calculated from Equation 2.
|
||||
*
|
||||
* For example, if SR_ALWON_FCLK has a frequency of 38.4 MHz, and
|
||||
* the target SR_CLK frequency is 100 kHz, SRCLKLENGTH is set to 192 (0x0C0)
|
||||
* SRn.SRCONFIG[21:12] SRCLKLENGTH Calculated from Equation 1
|
||||
*/
|
||||
|
||||
#define SRCONFIG_SRCLKLENGTH ((sysClkFreqGet()/1000)/(2 * SR_CLK) \
|
||||
<< SRCONFIG_SRCLKLENGTH_POS)
|
||||
#define SRCONFIG_SRCLKLENGTH_R(val) ((val >> \
|
||||
SRCONFIG_SRCLKLENGTH_POS) & 0x3FF)
|
||||
|
||||
#define SRENABLE_POS 11 /* 1 = enable */
|
||||
#define SRENABLE (1 << SRENABLE_POS)
|
||||
|
||||
#define SENENABLE_POS 10 /* 1 = enable */
|
||||
#define SENENABLE (1 << SENENABLE_POS)
|
||||
|
||||
#define ERRORGENERATORENABLE_POS 9 /* 1 = Enable error generator */
|
||||
#define ERRORGENERATORENABLE (1 << ERRORGENERATORENABLE_POS)
|
||||
|
||||
#define MINMAXAVGENABLE_POS 8 /* 1 = Enable minmax avg detector*/
|
||||
#define MINMAXAVGENABLE (1 << MINMAXAVGENABLE_POS)
|
||||
|
||||
#define SENNENABLE_POS 5 /* Selects different SenN modes */
|
||||
#define SENNENABLE_MSK (0x3 << SENNENABLE_POS)
|
||||
#define SENNENABLE(val) ((val & 0x3) << SENNENABLE_POS)
|
||||
#define SENNENABLE_R(val) ((val >> SENNENABLE_POS) & 0x3)
|
||||
#define SENNENABLE_DIS_VAL 0 /* Disables all SenN sensors */
|
||||
#define SENNENABLE_NM3EN_VAL 1 /* SenN-M3 enabled */
|
||||
#define SENNENABLE_NM4EN_VAL 2 /* SenN-M4 enabled */
|
||||
#define SENNENABLE_NM5EN_VAL 3 /* SenN-M5 enabled */
|
||||
|
||||
#define SENPENABLE_POS 3 /* Selects different SenN modes */
|
||||
#define SENPENABLE_MSK (0x3 << SENPENABLE_POS)
|
||||
#define SENPENABLE(val) ((val & 0x3) << SENPENABLE_POS)
|
||||
#define SENPENABLE_R(val) ((val >> SENPENABLE_POS) & 0x3)
|
||||
#define SENPENABLE_DIS_VAL 0 /* Disables all SenN sensors */
|
||||
#define SENPENABLE_NM3EN_VAL 1 /* SenN-M3 enabled */
|
||||
#define SENPENABLE_NM4EN_VAL 2 /* SenN-M4 enabled */
|
||||
#define SENPENABLE_NM5EN_VAL 3 /* SenN-M5 enabled */
|
||||
|
||||
#define SRDELAYCTRL_POS 2 /*characterization mode (set 1)*/
|
||||
#define SRDELAYCTRL (1 << SRDELAYCTRL_POS)
|
||||
|
||||
#define SRCLKCTRL_POS 0 /* CLKCTRL Div down SenN and SenP */
|
||||
#define SRCLKCTRL(val) (val << SRCLKCTRL_POS)
|
||||
#define SRCLKCTRL_R(val) ((val >> SRCLKCTRL_POS) & 0x3)
|
||||
#define SRCLKCTRL_VAL4 0 /* Divide by 4 */
|
||||
#define SRCLKCTRL_VAL8 1 /* Divide by 8 */
|
||||
#define SRCLKCTRL_VAL16 2 /* Divide by 16 */
|
||||
#define SRCLKCTRL_VAL32 3 /* Divide by 32 */
|
||||
|
||||
/* SRSTATUS register definitions */
|
||||
|
||||
#define AVGERRVALID_POS 3 /* 1 = SenAvg register valid */
|
||||
#define AVGERRVALID(regVal) ((regVal & \
|
||||
(1 << AVGERRVALID_POS)) != 0)
|
||||
#define MINMAXAVGVALID_POS 2 /* 1 = SenVal,Min,Max,Avg valid */
|
||||
#define MINMAXAVGVALID(regVal) ((regVal & \
|
||||
(1 << MINMAXAVGVALID_POS)) != 0)
|
||||
#define ERRORGENERATORVALID_POS 1 /* 1 = SenErr register valid */
|
||||
#define ERRORGENERATORVALID(regVal) ((regVal & \
|
||||
(1 << ERRORGENERATORVALID_POS)) \
|
||||
!= 0)
|
||||
#define MINMAXAVGACCUMFINAL_POS 0 /* 1= SenVal,Min,Max,Avg valid */
|
||||
#define MINMAXAVGACCUMFINAL(regVal) ((regVal & \
|
||||
(1 << MINMAXAVGACCUMFINAL_POS)) \
|
||||
!= 0)
|
||||
|
||||
/* SENVAL register definitions */
|
||||
|
||||
#define SENPVAL(regVal) ((regVal >> 16) & 0xffff)
|
||||
#define SENNVAL(regVal) (regVal & 0xffff)
|
||||
|
||||
/* SENMIN register definitions */
|
||||
|
||||
#define SENPMIN(regVal) ((regVal >> 16) & 0xffff)
|
||||
#define SENNMIN(regVal) (regVal & 0xffff)
|
||||
|
||||
/* SENMAX register definitions */
|
||||
|
||||
#define SENPMAX(regVal) ((regVal >> 16) & 0xffff)
|
||||
#define SENNMAX(regVal) (regVal & 0xffff)
|
||||
|
||||
/* SENAVG register definitions */
|
||||
|
||||
#define SENPAVG(regVal) ((regVal >> 16) & 0xffff)
|
||||
#define SENNAVG(regVal) (regVal & 0xffff)
|
||||
|
||||
/* AVGWEIGHT register definitions */
|
||||
|
||||
#define SENPAVGWEIGHT(regVal) ((regVal >> 2) & 0x3)
|
||||
#define SENNAVGWEIGHT(regVal) (regVal & 0x3)
|
||||
|
||||
/* NVALUERECIPROCAL register definitions (used for reading values) */
|
||||
|
||||
#define SENPGAIN(regVal) ((regVal >> 20) & 0xf)
|
||||
#define SENNGAIN(regVal) ((regVal >> 16) & 0x3)
|
||||
#define RNSENP(regVal) ((regVal >> 8) & 0xff)
|
||||
#define RNSENN(regVal) (regVal & 0xff)
|
||||
|
||||
/* SENERROR register definitions (used for reading values) */
|
||||
|
||||
#define SRFUSEVALUE(regVal) ((regVal >> 16) & 0xff)
|
||||
#define SRAVGERROR(regVal) ((regVal >> 8) & 0xff)
|
||||
#define SRSENERROR(regVal) (regVal & 0xff)
|
||||
|
||||
/* ERRCONFIG - error configuration register */
|
||||
|
||||
#define VPBOUNDINTEN_POS 31 /* 1 = VP bounded interrupt enable */
|
||||
#define VPBOUNDINTEN (1 << VPBOUNDINTEN_POS)
|
||||
|
||||
#define VPBOUNDINTST_POS 30 /* 1 = Interrupt is pending */
|
||||
#define VPBOUNDINTST_R (1 << VPBOUNDINTST_POS)
|
||||
#define VPBOUNDINTST(regVal) ((regVal & (1 << VPBOUNDINTST_POS)) != 0)
|
||||
#define VPBOUNDINCTLR(regAdr) (*regAdr |= (1 << VPBOUNDINTST_POS)
|
||||
|
||||
#define MCUACCUMINTEN_POS 29 /* 1 = MCU Accum interrupt enable */
|
||||
#define MCUACCUMINTEN (1 << MCUACCUMINTEN_POS)
|
||||
#define MCUACCUMINTST_POS 28 /* 1 = Interrupt is pending */
|
||||
#define MCUACCUMINTST(regVal) ((regVal & (1 << MCUACCUMINTST_POS)) != 0)
|
||||
#define MCUACCUMINCTLR(regAdr) (*regAdr |= (1 << MCUACCUMINTST_POS)
|
||||
|
||||
#define MCUVALIDINTEN_POS 27 /* 1 = Enable MCU Valid Interrupt */
|
||||
#define MCUVALIDINTEN (1 << MCUVALIDINTEN_POS)
|
||||
|
||||
#define MCUVALIDINTST_POS 26 /* 1 = Interrupt is pending */
|
||||
#define MCUVALIDINTST(regVal) ((regVal & (1 << MCUVALIDINTST_POS)) != 0)
|
||||
#define MCUVALIDINTCLR(regAdr) (*regAdr |= (1 << MCUVALIDINTST_POS)
|
||||
|
||||
#define MCUBOUNDINTEN_POS 25 /* 1 = Enable MCU bound interrupt */
|
||||
#define MCUBOUNDINTEN (1 << MCUBOUNDINTEN_POS)
|
||||
|
||||
#define MCUBOUNDINTST_POS 24 /* 1 = Interrupt is pending */
|
||||
#define MCUBOUNDINTST(regVal) ((regVal & (1 << MCUBOUNDINTST_POS)) != 0)
|
||||
#define MCUBOUNDINCTLR(regAdr) (*regAdr |= (1 << MCUBOUNDINTST_POS)
|
||||
|
||||
#define MCUDISACKINTEN_POS 23 /* 1 = Enable MCU Disable Ack Int */
|
||||
#define MCUDISACKINTEN (1 << MCUDISACKINTEN_POS)
|
||||
|
||||
#define MCUDISACKINTST_POS 22 /* 1 = Interrupt is pending */
|
||||
#define MCUDISACKINTST_R (1 << MCUDISACKINTST_POS)
|
||||
#define MCUDISACKINTST(regVal) ((regVal & (1 << MCUDISACKINTST_POS)) != 0)
|
||||
|
||||
#define SRCLOCKACTIVITY_POS 20 /* Clock activity selection bits [21,20] */
|
||||
#define SRCLOCKACTIVITY_VAL(regVal) ((regVal >> SRCLOCKACTIVITY_POS) & 3)
|
||||
#define SRCLOCKACTIVITY_GATED 0x0 /* clocks can be gated */
|
||||
#define SRCLOCKACTIVITY_ACTIVE1 0x1 /* clock must be kept active and the */
|
||||
/* interface clock can be cut off */
|
||||
#define SRCLOCKACTIVITY_ACTIVE2 0x2 /* clock must be kept active and the */
|
||||
/* interface clock can be cut off */
|
||||
#define SRCLOCKACTIVITY_ACTIVE3 0x3 /* clock must be kept active and the */
|
||||
/* interface clock can be cut off */
|
||||
#define SRCLOCKACTIVITY SRCLOCKACTIVITY_VAL(SRCLOCKACTIVITY_GATED) /* def */
|
||||
|
||||
#define ERRWEIGHT_POS 16 /* avg sensor error weight [18..16]*/
|
||||
#define ERRWEIGHT_VAL(regVal) ((regVal & 0x7) << ERRWEIGHT_POS)
|
||||
#define ERRWEIGHT_VAL_R(regVal) ((regVal >> ERRWEIGHT_POS) & 0x7)
|
||||
#define ERRWEIGHT_MASK (0x7 << ERRWEIGHT_POS)
|
||||
|
||||
#define ERRMAXLIMIT_POS 8 /* High limit of sensor erro [15..8] */
|
||||
#define ERRMAXLIMIT_VAL(regVal) ((regVal & 0xff) << ERRMAXLIMIT_POS)
|
||||
#define ERRMAXLIMIT_VAL_R(regVal) ((regVal >> ERRMAXLIMIT_POS) & 0xff)
|
||||
#define ERRMAXLIMIT_MASK (0xFF << ERRMAXLIMIT_POS)
|
||||
|
||||
#define ERRMINLIMIT_POS 0 /* Low limit of sensor error [7..0] */
|
||||
#define ERRMINLIMIT_VAL(regVal) ((regVal & 0xff) << ERRMINLIMIT_POS)
|
||||
#define ERRMINLIMIT_VAL_R(regVal) ((regVal >> ERRMINLIMIT_POS) & 0xff)
|
||||
#define ERRMINLIMIT_MASK (0xFF << ERRMINLIMIT_POS)
|
||||
|
||||
|
||||
/* number of Voltage Processor units */
|
||||
|
||||
#define VP_UNITS 2
|
||||
|
||||
/* offsets of SR1 and SR2 */
|
||||
|
||||
#define VP1_OFFSET 0xB0
|
||||
#define VP2_OFFSET 0xD0
|
||||
|
||||
/* voltage processor register offsets (rel. to OMAP35XX_PRM_VPn_CONFIG) */
|
||||
|
||||
#define PRM_VP_CONFIG 0x00
|
||||
#define PRM_VP_VSTEPMIN 0x04
|
||||
#define PRM_VP_VSTEPMAX 0x08
|
||||
#define PRM_VP_VLIMITTO 0x0C
|
||||
#define PRM_VP_VOLTAGE 0x10
|
||||
#define PRM_VP_STATUS 0x14
|
||||
|
||||
/* VP_CONFIG fields TRM table 4-480 */
|
||||
|
||||
#define VPENABLE 1
|
||||
#define VPENABLE_MSK 1
|
||||
#define VPFORCEUPDATE 2
|
||||
#define VPFORCEUPDATE_MSK 2
|
||||
#define VPINITVDD 4
|
||||
#define VPINITVDD_MSK 4
|
||||
#define VPTIMEOUT 8
|
||||
#define VPTIMEOUT_MSK 8
|
||||
#define VPINITVOLTAGE(v) (v << 8)
|
||||
#define VPINITVOLTAGE_MSK 0x0000ff00
|
||||
#define VPERRORGAIN(g) (g << 16)
|
||||
#define VPERRORGAIN_MSK 0x00ff0000
|
||||
#define VPERROFFSET(o) (o << 24)
|
||||
#define VPERROFFSET_MSK 0xff000000
|
||||
|
||||
/* VP_VSTEPMIN TRM table 4-482 */
|
||||
|
||||
#define VPVSTEPMIN(v) (v)
|
||||
#define VPVSTEPMIN_MSK 0x0000ff
|
||||
#define VPSMPSWAITTIMEMIN(v) (v << 8)
|
||||
#define VPSMPSWAITTIMEMIN_MSK 0xffff00
|
||||
|
||||
/* VP_VSTEPMAX TRM table 4-484 */
|
||||
|
||||
#define VPVSTEPMAX(v) (v)
|
||||
#define VPVSTEPMAX_MSK 0x0000ff
|
||||
#define VPSMPSWAITTIMEMAX(v) (v << 8)
|
||||
#define VPSMPSWAITTIMEMAX_MSK 0xffff00
|
||||
|
||||
/* VP_VLIMITTO TRM table 4-486 */
|
||||
|
||||
#define VPVLIMITTO(v) (v)
|
||||
#define VPVLIMITTO_MSK 0x0000ffff
|
||||
#define VPVVDDMIN(v) (v << 16)
|
||||
#define VPVVDDMIN_MSK 0x00ff0000
|
||||
#define VPVVDDMAX(v) (v << 24)
|
||||
#define VPVVDDMAX_MSK 0xff000000
|
||||
|
||||
/* VP_VOLTAG TRM table 4-488 */
|
||||
|
||||
#define VPVOLTAGE (v) (v)
|
||||
#define VPVOLTAGE_MSK 0xff
|
||||
|
||||
/* VP_STATUS TRM table 4-490 */
|
||||
|
||||
#define VPSTATUS_MSK 0x1
|
||||
|
||||
/*
|
||||
* These are register definitions for the EFuses needed in SmartReflex
|
||||
* calculations.
|
||||
*/
|
||||
|
||||
#define OMAP35XX_SCM_GENERAL (OMAP35XX_L4_SYSCTRL + 0x270)
|
||||
|
||||
#define OMAP35XX_OPP1_VDD1 (OMAP35XX_SCM_GENERAL + 0x110)
|
||||
#define OMAP35XX_OPP2_VDD1 (OMAP35XX_SCM_GENERAL + 0x114)
|
||||
#define OMAP35XX_OPP3_VDD1 (OMAP35XX_SCM_GENERAL + 0x118)
|
||||
#define OMAP35XX_OPP4_VDD1 (OMAP35XX_SCM_GENERAL + 0x11C)
|
||||
#define OMAP35XX_OPP5_VDD1 (OMAP35XX_SCM_GENERAL + 0x120)
|
||||
|
||||
#define OMAP35XX_OPP1_VDD2 (OMAP35XX_SCM_GENERAL + 0x124)
|
||||
#define OMAP35XX_OPP2_VDD2 (OMAP35XX_SCM_GENERAL + 0x128)
|
||||
#define OMAP35XX_OPP3_VDD2 (OMAP35XX_SCM_GENERAL + 0x12C)
|
||||
|
||||
#define OMAP35XX_FUSE_SR (OMAP35XX_SCM_GENERAL + 0x130)
|
||||
|
||||
#define OMAP35XX_PRCM_SR_REGS 0x480C9000
|
||||
|
||||
#endif /* _INC_OMAP35XXSMARTREFLEX_H */
|
||||
@@ -0,0 +1,103 @@
|
||||
/* stm32f2xx.h - SOC specific header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,02jul12,rec fix USART base addresses
|
||||
01b,02may12,rec Moved to hwif/soc. Split into lower level files.
|
||||
01a,21mar12,jmz Created
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains register definitions specifc to the stm32f2xxx series SOC.
|
||||
|
||||
SEE ALSO:
|
||||
\tb RM0033 Reference manual - STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
|
||||
advanced ARM-based 32-bit MCUs
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCstm32f2xxh
|
||||
#define __INCstm32f2xxh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* macros to manipulate registers */
|
||||
|
||||
#define STM32F2XX_REG_READ(address) \
|
||||
*(volatile UINT32 *)(address)
|
||||
|
||||
#define STM32F2XX_REG_WRITE(address, value) \
|
||||
*(volatile UINT32 *)(address) = (UINT32)(value)
|
||||
|
||||
#define STM32F2XX_SHORT_REG_WRITE(address, value) \
|
||||
*(volatile UINT16*)(address) = value
|
||||
|
||||
#define STM32F2XX_SHORT_REG_READ(address) \
|
||||
(*(volatile UINT16*)(address))
|
||||
|
||||
/* Region allocation for General-purpose I/O (GPIO) registers */
|
||||
|
||||
#define STM32F2XX_GPIO_BASE 0x40020000
|
||||
|
||||
/* Region allocation for Reset and Clock Control (RCC) registers */
|
||||
|
||||
#define STM32F2XX_RCC_BASE 0x40023800
|
||||
|
||||
/* Region allocation for Flash Memory Interface (FMI) registers */
|
||||
|
||||
#define STM32F2XX_FMI_BASE 0x40023C00
|
||||
|
||||
/* Region allocation for Flexible Static Memory Controller (FSMC) registers */
|
||||
|
||||
#define STM32F2XX_FSMC_BASE 0xA0000000
|
||||
|
||||
/*
|
||||
* Region allocation for Universal Synchronous Asynchronous Receiver Transmitter
|
||||
* (USART) registers
|
||||
*/
|
||||
|
||||
#define STM32F2XX_USART1_BASE 0x40011000
|
||||
#define STM32F2XX_USART2_BASE 0x40004400
|
||||
#define STM32F2XX_USART3_BASE 0x40004800
|
||||
#define STM32F2XX_UART4_BASE 0x40004C00
|
||||
#define STM32F2XX_UART5_BASE 0x40005000
|
||||
#define STM32F2XX_USART6_BASE 0x40011400
|
||||
|
||||
/* Region allocation for General Purpose Timer (GPT) registers */
|
||||
|
||||
#define STM32F2XX_TIM1_BASE 0x40001000
|
||||
#define STM32F2XX_TIM2_BASE 0x40000000
|
||||
#define STM32F2XX_TIM3_BASE 0x40000400
|
||||
#define STM32F2XX_TIM4_BASE 0x40000800
|
||||
#define STM32F2XX_TIM5_BASE 0x40000C00
|
||||
#define STM32F2XX_TIM6_BASE 0x40001000
|
||||
#define STM32F2XX_TIM7_BASE 0x40001400
|
||||
#define STM32F2XX_TIM8_BASE 0x40010400
|
||||
#define STM32F2XX_TIM9_BASE 0x40014000
|
||||
#define STM32F2XX_TIM10_BASE 0x40014400
|
||||
#define STM32F2XX_TIM11_BASE 0x40014800
|
||||
#define STM32F2XX_TIM12_BASE 0x40001800
|
||||
#define STM32F2XX_TIM13_BASE 0x40001C00
|
||||
#define STM32F2XX_TIM14_BASE 0x40002000
|
||||
|
||||
/* Region allocation for Ethernet Driver registers */
|
||||
|
||||
#define STM32F2XX_ETH_BASE 0x40028000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCstm32f2xxh */
|
||||
@@ -0,0 +1,174 @@
|
||||
/* stm32f2xxMem.h - STM32F20x/STM32F21x memory subsystem header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,16jul12,rec Flash memory bank address error
|
||||
01b,10may12,rec add flash registers
|
||||
01a,02may12,rec Created - Content extracted from stm32f2xx.h v01a
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains register definitions specifc to the STM32F20x/STM32F21x
|
||||
flash and static memory interface registers.
|
||||
|
||||
SEE ALSO:
|
||||
\tb RM0033 Reference manual STM32F205xx, STM32F207xx, STM32F215xx and
|
||||
STM32F217xx advanced ARM-based 32-bit MCUs, DEC 2011
|
||||
\tb PM0059 Programming manual STM32F205xx, STM32F207xx, STM32F215xx and
|
||||
STM32F217xx, Flash programming manual, MAY 2011
|
||||
*/
|
||||
|
||||
#ifndef __INCstm32f2xxMemh
|
||||
#define __INCstm32f2xxMemh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* FLASH Access Control Register */
|
||||
|
||||
#define STM32F2XX_FMI_ACR (STM32F2XX_FMI_BASE + 0x00)
|
||||
#define STM32F2XX_FMI_ACR_LATENCY0 0x00000000 /* 0 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY1 0x00000001 /* 1 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY2 0x00000002 /* 2 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY3 0x00000003 /* 3 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY4 0x00000004 /* 4 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY5 0x00000005 /* 5 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY6 0x00000006 /* 6 wait states */
|
||||
#define STM32F2XX_FMI_ACR_LATENCY7 0x00000007 /* 7 wait states */
|
||||
#define STM32F2XX_FMI_ACR_PRFTEN 0X00000100 /* Prefetch enable */
|
||||
#define STM32F2XX_FMI_ACR_ICEN 0X00000200 /* Instruction cache enable */
|
||||
#define STM32F2XX_FMI_ACR_DCEN 0X00000400 /* Data cache enable */
|
||||
#define STM32F2XX_FMI_ACR_ICRST 0X00000800 /* Instruction cache reset */
|
||||
#define STM32F2XX_FMI_ACR_DCRST 0X00001000 /* Data cache reset */
|
||||
|
||||
/* FLASH Key Register */
|
||||
|
||||
#define STM32F2XX_FMI_KEYR (STM32F2XX_FMI_BASE + 0x04)
|
||||
#define STM32F2XX_FMI_KEY1 0x45670123
|
||||
#define STM32F2XX_FMI_KEY2 0xCDEF89AB
|
||||
|
||||
/* FLASH Options Key Register */
|
||||
#define STM32F2XX_FMI_OPTKEYR (STM32F2XX_FMI_BASE + 0x08)
|
||||
#define STM32F2XX_FMI_OPTKEY1 0x08192A3B
|
||||
#define STM32F2XX_FMI_OPTKEY2 0x4C5D6E7F
|
||||
|
||||
/* FLASH Status Register */
|
||||
#define STM32F2XX_FMI_SR (STM32F2XX_FMI_BASE + 0x0C)
|
||||
#define STM32F2XX_FMI_SR_EOP 0x00000001 /* End of operation */
|
||||
#define STM32F2XX_FMI_SR_OPERR 0x00000002 /* Operation error */
|
||||
#define STM32F2XX_FMI_SR_WRPERR 0x00000010 /* Write protect error */
|
||||
#define STM32F2XX_FMI_SR_PGAERR 0x00000020 /* Programming alignment error*/
|
||||
#define STM32F2XX_FMI_SR_PGPERR 0x00000040 /* Programming parallism error*/
|
||||
#define STM32F2XX_FMI_SR_PGSERR 0x00000080 /* Programming sequence error */
|
||||
#define STM32F2XX_FMI_SR_BSY 0x00010000 /* Busy */
|
||||
|
||||
/* FLASH Control Register */
|
||||
#define STM32F2XX_FMI_CR (STM32F2XX_FMI_BASE + 0x10)
|
||||
#define STM32F2XX_FMI_CR_PG 0x00000001 /* Programming */
|
||||
#define STM32F2XX_FMI_CR_SER 0x00000002 /* Sector erase */
|
||||
#define STM32F2XX_FMI_CR_MER 0x00000004 /* Mass erase */
|
||||
#define STM32F2XX_FMI_CR_SNB(arg) (arg << 3) /* Sector number */
|
||||
#define STM32F2XX_FMI_CR_SMSK 0x00000078 /* Sector number mask */
|
||||
#define STM32F2XX_FMI_CR_PSIZE8 0x00000000 /* Program size 8*/
|
||||
#define STM32F2XX_FMI_CR_PSIZE16 0x00000100 /* Program size 16 */
|
||||
#define STM32F2XX_FMI_CR_PSIZE32 0x00000200 /* Program size 32 */
|
||||
#define STM32F2XX_FMI_CR_PSIZE64 0x00000300 /* Program size 64 */
|
||||
#define STM32F2XX_FMI_CR_PSIZEMSK 0x00000300 /* Program size mask */
|
||||
#define STM32F2XX_FMI_CR_STRT 0x00010000 /* Start */
|
||||
#define STM32F2XX_FMI_CR_EOPIE 0x01000000 /* End of op interrupt enable */
|
||||
#define STM32F2XX_FMI_CR_ERRIE 0x02000000 /* Error interrupt enable */
|
||||
#define STM32F2XX_FMI_CR_LOCK 0x80000000 /* Lock */
|
||||
|
||||
/* FLASH Options Control */
|
||||
#define STM32F2XX_FMI_OPTCR (STM32F2XX_FMI_BASE + 0x14)
|
||||
#define STM32F2XX_FMI_OPTCR_LOCK 0x00000001 /* Options lock */
|
||||
#define STM32F2XX_FMI_OPTCR_STRT 0x00000002 /* Option start */
|
||||
#define STM32F2XX_FMI_OPTCR_VBOR0 0x0000000C /* 1.8V..2.1V */
|
||||
#define STM32F2XX_FMI_OPTCR_VBOR1 0x00000008 /* 2.1V..2.4V */
|
||||
#define STM32F2XX_FMI_OPTCR_VBOR2 0x00000004 /* 2.4V..2.7V */
|
||||
#define STM32F2XX_FMI_OPTCR_VBOR3 0x00000000 /* 2.7V..3.6V */
|
||||
#define STM32F2XX_FMI_OPTCR_WDGSW 0x00000020 /* User option */
|
||||
#define STM32F2XX_FMI_OPTCR_RSTSTOP 0x00000040 /* User option */
|
||||
#define STM32F2XX_FMI_OPTCR_RSTSTBY 0x00000080 /* User option */
|
||||
#define STM32F2XX_FMI_OPTCR_RDP_OFF 0x0000AA00 /* No read protect */
|
||||
#define STM32F2XX_FMI_OPTCR_RDP_CHP 0x0000CC00 /* Chip read protect */
|
||||
#define STM32F2XX_FMI_OPTCR_RDP_MEM 0x00000000 /* Memory read protect */
|
||||
#define STM32F2XX_FMI_OPTCR_WEN(arg) (arg <<16) /* Write enable sector */
|
||||
|
||||
/* Flash sector base addresses */
|
||||
#define STM32F2XX_FLASHSECT00 0x08000000
|
||||
#define STM32F2XX_FLASHSECT01 0x08004000
|
||||
#define STM32F2XX_FLASHSECT02 0x08008000
|
||||
#define STM32F2XX_FLASHSECT03 0x0800C000
|
||||
#define STM32F2XX_FLASHSECT04 0x08010000
|
||||
#define STM32F2XX_FLASHSECT05 0x08020000
|
||||
#define STM32F2XX_FLASHSECT06 0x08040000
|
||||
#define STM32F2XX_FLASHSECT07 0x08060000
|
||||
#define STM32F2XX_FLASHSECT08 0x08080000
|
||||
#define STM32F2XX_FLASHSECT09 0x080A0000
|
||||
#define STM32F2XX_FLASHSECT10 0x080C0000
|
||||
#define STM32F2XX_FLASHSECT11 0x080E0000
|
||||
|
||||
/* Flash sector sizes */
|
||||
#define STM_SZ16K (16 * 1024)
|
||||
#define STM_SZ64K (64 * 1024)
|
||||
#define STM_SZ128K (128 * 1024)
|
||||
#define STM32F2XX_FLASHSECT_SZ00 STM_SZ16K
|
||||
#define STM32F2XX_FLASHSECT_SZ01 STM_SZ16K
|
||||
#define STM32F2XX_FLASHSECT_SZ02 STM_SZ16K
|
||||
#define STM32F2XX_FLASHSECT_SZ03 STM_SZ16K
|
||||
#define STM32F2XX_FLASHSECT_SZ04 STM_SZ64K
|
||||
#define STM32F2XX_FLASHSECT_SZ05 STM_SZ128K
|
||||
#define STM32F2XX_FLASHSECT_SZ06 STM_SZ128K
|
||||
#define STM32F2XX_FLASHSECT_SZ07 STM_SZ128K
|
||||
#define STM32F2XX_FLASHSECT_SZ08 STM_SZ128K
|
||||
#define STM32F2XX_FLASHSECT_SZ09 STM_SZ128K
|
||||
#define STM32F2XX_FLASHSECT_SZ10 STM_SZ128K
|
||||
#define STM32F2XX_FLASHSECT_SZ11 STM_SZ128K
|
||||
|
||||
|
||||
#define STM32F2XX_FSMC_BCR1 (STM32F2XX_FSMC_BASE + 0x0)
|
||||
#define STM32F2XX_FSMC_BTR1 (STM32F2XX_FSMC_BASE + 0x4)
|
||||
#define STM32F2XX_FSMC_BWTR1 (STM32F2XX_FSMC_BASE + 0x104)
|
||||
#define STM32F2XX_FSMC_BCR2 (STM32F2XX_FSMC_BASE + 0x8)
|
||||
#define STM32F2XX_FSMC_BTR2 (STM32F2XX_FSMC_BASE + 0xC)
|
||||
#define STM32F2XX_FSMC_BWTR2 (STM32F2XX_FSMC_BASE + 0x10C)
|
||||
#define STM32F2XX_FSMC_BCR3 (STM32F2XX_FSMC_BASE + 0x10)
|
||||
#define STM32F2XX_FSMC_BTR3 (STM32F2XX_FSMC_BASE + 0x14)
|
||||
#define STM32F2XX_FSMC_BWTR3 (STM32F2XX_FSMC_BASE + 0x114)
|
||||
#define STM32F2XX_FSMC_BCR4 (STM32F2XX_FSMC_BASE + 0x18)
|
||||
#define STM32F2XX_FSMC_BTR4 (STM32F2XX_FSMC_BASE + 0x1C)
|
||||
#define STM32F2XX_FSMC_BWTR4 (STM32F2XX_FSMC_BASE + 0x11C)
|
||||
#define STM32F2XX_FSMC_PCR2 (STM32F2XX_FSMC_BASE + 0x60)
|
||||
#define STM32F2XX_FSMC_PCR3 (STM32F2XX_FSMC_BASE + 0x80)
|
||||
#define STM32F2XX_FSMC_PCR4 (STM32F2XX_FSMC_BASE + 0xA0)
|
||||
#define STM32F2XX_FSMC_SR2 (STM32F2XX_FSMC_BASE + 0x64)
|
||||
#define STM32F2XX_FSMC_SR3 (STM32F2XX_FSMC_BASE + 0x84)
|
||||
#define STM32F2XX_FSMC_SR4 (STM32F2XX_FSMC_BASE + 0xA4)
|
||||
#define STM32F2XX_FSMC_PMEM2 (STM32F2XX_FSMC_BASE + 0x68)
|
||||
#define STM32F2XX_FSMC_PMEM3 (STM32F2XX_FSMC_BASE + 0x88)
|
||||
#define STM32F2XX_FSMC_PMEM4 (STM32F2XX_FSMC_BASE + 0xA8)
|
||||
#define STM32F2XX_FSMC_PATT2 (STM32F2XX_FSMC_BASE + 0x6C)
|
||||
#define STM32F2XX_FSMC_PATT3 (STM32F2XX_FSMC_BASE + 0x8C)
|
||||
#define STM32F2XX_FSMC_PATT4 (STM32F2XX_FSMC_BASE + 0xAC)
|
||||
#define STM32F2XX_FSMC_PIO4 (STM32F2XX_FSMC_BASE + 0xB0)
|
||||
#define STM32F2XX_FSMC_ECCR2 (STM32F2XX_FSMC_BASE + 0x74)
|
||||
#define STM32F2XX_FSMC_ECCR3 (STM32F2XX_FSMC_BASE + 0x94)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __INCstm32f2xxMemh */
|
||||
@@ -0,0 +1,107 @@
|
||||
|
||||
/* stm32f2xxRcc.h - STM32F20x/STM32F21x reset and clock control header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,03jul12,m_h APB1 bit definitions
|
||||
01b,24may12,jmz added bit field definitions for AHB1ENR and APB1ENR registers
|
||||
01a,02may12,rec Created - Content extracted from stm32f2xx.h v01a
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains register definitions specifc to the STM32F20x/STM32F21x
|
||||
reset and clock control interface registers.
|
||||
|
||||
SEE ALSO:
|
||||
\tb RM0033 Reference manual STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
|
||||
advanced ARM-based 32-bit MCUs, DEC 2011
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCstm32f2xxRcch
|
||||
#define __INCstm32f2xxRcch
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Base register definitions */
|
||||
|
||||
#define STM32F2XX_RCC_CR (STM32F2XX_RCC_BASE + 0x0)
|
||||
#define STM32F2XX_RCC_PLLCFGR (STM32F2XX_RCC_BASE + 0x4)
|
||||
#define STM32F2XX_RCC_CFGR (STM32F2XX_RCC_BASE + 0x8)
|
||||
#define STM32F2XX_RCC_CIR (STM32F2XX_RCC_BASE + 0xC)
|
||||
#define STM32F2XX_RCC_AHB1RSTR (STM32F2XX_RCC_BASE + 0x10)
|
||||
#define STM32F2XX_RCC_AHB2RSTR (STM32F2XX_RCC_BASE + 0x14)
|
||||
#define STM32F2XX_RCC_AHB3RSTR (STM32F2XX_RCC_BASE + 0x18)
|
||||
#define STM32F2XX_RCC_APB1RSTR (STM32F2XX_RCC_BASE + 0x20)
|
||||
#define STM32F2XX_RCC_APB2RSTR (STM32F2XX_RCC_BASE + 0x24)
|
||||
#define STM32F2XX_RCC_AHB1ENR (STM32F2XX_RCC_BASE + 0x30)
|
||||
#define STM32F2XX_RCC_AHB2ENR (STM32F2XX_RCC_BASE + 0x34)
|
||||
#define STM32F2XX_RCC_APB3ENR (STM32F2XX_RCC_BASE + 0x38)
|
||||
#define STM32F2XX_RCC_APB1ENR (STM32F2XX_RCC_BASE + 0x40)
|
||||
#define STM32F2XX_RCC_APB2ENR (STM32F2XX_RCC_BASE + 0x44)
|
||||
#define STM32F2XX_RCC_AHB1LPENR (STM32F2XX_RCC_BASE + 0x50)
|
||||
#define STM32F2XX_RCC_AHB2LPENR (STM32F2XX_RCC_BASE + 0x54)
|
||||
#define STM32F2XX_RCC_AHB3LPENR (STM32F2XX_RCC_BASE + 0x58)
|
||||
#define STM32F2XX_RCC_APB1LPENR (STM32F2XX_RCC_BASE + 0x60)
|
||||
#define STM32F2XX_RCC_APB2LPENR (STM32F2XX_RCC_BASE + 0x64)
|
||||
#define STM32F2XX_RCC_BDCR (STM32F2XX_RCC_BASE + 0x70)
|
||||
#define STM32F2XX_RCC_CSR (STM32F2XX_RCC_BASE + 0x74)
|
||||
#define STM32F2XX_RCC_SSCGR (STM32F2XX_RCC_BASE + 0x80)
|
||||
#define STM32F2XX_RCC_PLLI2SCFGR (STM32F2XX_RCC_BASE + 0x84)
|
||||
|
||||
/* Bit field definitions */
|
||||
|
||||
#define STM32F2XX_RCC_AHB1ENR_GPIOAEN (1<<0)
|
||||
#define STM32F2XX_RCC_AHB1ENR_GPIOBEN (1<<1)
|
||||
#define STM32F2XX_RCC_AHB1ENR_GPIOCEN (1<<2)
|
||||
#define STM32F2XX_RCC_AHB1ENR_GPIOGEN (1<<6)
|
||||
#define STM32F2XX_RCC_AHB1ENR_GPIOHEN (1<<7)
|
||||
#define STM32F2XX_RCC_AHB1ENR_GPIOIEN (1<<8)
|
||||
#define STM32F2XX_RCC_AHB1ENR_ETHMACEN (1<<25)
|
||||
#define STM32F2XX_RCC_AHB1ENR_ETHMACTXEN (1<<26)
|
||||
#define STM32F2XX_RCC_AHB1ENR_ETHMACRXEN (1<<27)
|
||||
|
||||
/* RCC APB1 periphial clock enable register */
|
||||
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM2EN (1<<0)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM3EN (1<<1)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM4EN (1<<2)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM5EN (1<<3)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM6EN (1<<4)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM7EN (1<<5)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM12EN (1<<6)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM13EN (1<<7)
|
||||
#define STM32F2XX_RCC_APB1ENR_TIM14EN (1<<8)
|
||||
#define STM32F2XX_RCC_APB1ENR_WWDGEN (1<<11)
|
||||
#define STM32F2XX_RCC_APB1ENR_SPI2EN (1<<14)
|
||||
#define STM32F2XX_RCC_APB1ENR_SPI3EN (1<<15)
|
||||
#define STM32F2XX_RCC_APB1ENR_USART2EN (1<<17)
|
||||
#define STM32F2XX_RCC_APB1ENR_USART3EN (1<<18)
|
||||
#define STM32F2XX_RCC_APB1ENR_USART4EN (1<<19)
|
||||
#define STM32F2XX_RCC_APB1ENR_USART5EN (1<<20)
|
||||
#define STM32F2XX_RCC_APB1ENR_IC1EN (1<<21)
|
||||
#define STM32F2XX_RCC_APB1ENR_IC2EN (1<<22)
|
||||
#define STM32F2XX_RCC_APB1ENR_IC3EN (1<<23)
|
||||
#define STM32F2XX_RCC_APB1ENR_CAN1EN (1<<25)
|
||||
#define STM32F2XX_RCC_APB1ENR_CAN2EN (1<<26)
|
||||
#define STM32F2XX_RCC_APB1ENR_PWREN (1<<28)
|
||||
#define STM32F2XX_RCC_APB1ENR_DACEN (1<<29)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCstm32f2xxRcch */
|
||||
Reference in New Issue
Block a user