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/* vxbArmGenIntCtlr.h - ARM Generic interrupt controller driver */
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/*
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* Copyright (c) 2008-2009, 2012, 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01h,15jul13,c_l Add interrupt priority/sensitivity support. (WIND00420705)
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01g,07aug12,j_b add distributor and CPU interface register offset support
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(CQ:WIND00367952)
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01f,15apr12,clx support PPI interrupt type
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01e,09jan12,ggm Fixed interrupt controller configuration (WIND00283926).
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01d,27oct09,z_l add SMP support
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01c,16apr09,j_b change core reset and start IPI #s
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01b,26nov08,j_b declare armGicBase as an extern
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01a,21oct08,j_b written based on vxbMPCoreIntCtlr.h, rev 01a
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*/
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#ifndef __INCvxbArmGenIntCtlrh
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#define __INCvxbArmGenIntCtlrh
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*
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* the explanation of some abbreviations
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*
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* CPC - Cross Processor Call
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* IPI - Inter Processor Interrupt
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* GIC - General Interrupt Controller
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* SGI - Software Generated Interrupt
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* PPI - Private Peripheral Interrupt
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* SPI - Shared Peripheral Interrupt
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*/
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/* MPCore GIC interrupt levels */
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#define INT_LVL_MPCORE_IPI00 0 /* This is vxWorks CPC IPI */
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#define INT_LVL_MPCORE_CPC INT_LVL_MPCORE_IPI00
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#define INT_LVL_MPCORE_IPI01 1 /* This is vxWorks Debug IPI */
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#define INT_LVL_MPCORE_DEBUG INT_LVL_MPCORE_IPI01
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#define INT_LVL_MPCORE_IPI02 2 /* This is vxWorks Reschedule IPI */
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#define INT_LVL_MPCORE_SCHED INT_LVL_MPCORE_IPI02
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#define INT_LVL_MPCORE_IPI03 3 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI04 4 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI05 5 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI06 6 /* This is vxWorks Core Reset IPI */
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#define INT_LVL_MPCORE_RESET INT_LVL_MPCORE_IPI06
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#define INT_LVL_MPCORE_IPI07 7 /* This is vxWorks Core Start IPI */
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#define INT_LVL_MPCORE_START INT_LVL_MPCORE_IPI07
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#define INT_LVL_MPCORE_IPI08 8 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI09 9 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI10 10 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI11 11 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI12 12 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI13 13 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI14 14 /* IPI -> use SWI register in GIC */
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#define INT_LVL_MPCORE_IPI15 15 /* IPI -> use SWI register in GIC */
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#define SGI_INT_MAX 16
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#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
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#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
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#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
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#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
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#define GIC_INT_ALL_ENABLED 0xFF /* priority 0-0xFF can run */
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#define GIC_INT_ALL_DISABLED 0x00 /* nothing higher than 0 hence disabled */
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#define GIC_INT_SPURIOUS 0x3FF /* no interrupt currently */
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#define GIC_INT_ONEMINUS_HIGH 0x55555555 /* interrupt config to 1-N, High */
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#define GIC_CPU_BINP_DEFAULT 0x07 /* split all priority to subpriority */
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#define GIC_CPU_CONTROL_ENABLE 0x1 /* enable the processor interface */
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#define GIC_CPU_ALL_ENABLED 0xFF /* priority 0-E can run */
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#define GIC_CPU_ALL_DISABLED 0x00 /* nothing higher than 0 */
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#define GIC_SGI_SRC_CPU_ID_MASK 0x1C00
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#define GIC_INT_HIGHEST_PRIORITY 0x0 /* the highest priority for interrupts */
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#define GIC_INT_LOWEST_PRIORITY 0x1F /* the lowest priority for interrupts */
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#define GIC_INT_PRIORITY_SHIFT 0x8
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#define GIC_INT_PRIORITY_MASK 0xFF
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#define GIC_INT_TRIGGER_SHIFT 0x2
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#define GIC_CPU_DIR_DEFAULT 0x01010101 /* all interrupts are directed to CPU0 */
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#define GIC_CONTROL_ENABLE 0x01
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#define ALL_PPI_INT_MASK 0xFFFF0000 /* bit field for all PPI interrupts */
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#define ALL_SGI_INT_MASK 0x0000FFFF /* bit field for all SGI interrupts */
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/* ARM GIC interrupt distributor and CPU interface register access macros */
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#define BITS_PER_WORD 32
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#define CONFIGS_PER_WORD 16
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#define PRIOS_PER_WORD 4
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#define TARGETS_PER_WORD 4
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#define NWORD(bitnum) (bitnum / 32)
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#define BIT(bitnum) (1 << (bitnum % BITS_PER_WORD))
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#ifndef _ASMLANGUAGE
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/* GIC distributor and CPU interface register base offsets */
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#define GIC_DIST (armGicBase + armGicDistOffset)
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#define GIC_CPU (armGicBase + armGicCpuOffset)
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/* interrupt distributor control */
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#define GIC_Control ((volatile UINT32 *)(GIC_DIST + 0x000))
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/* interrupt controller type */
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#define GIC_Type ((volatile UINT32 *)(GIC_DIST + 0x004))
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/* interrupt enable */
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#define GIC_IntEnable(Periph) ((volatile UINT32 *)(GIC_DIST + 0x100 + \
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(0x4 * NWORD(Periph))))
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/* clear interrupt enable */
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#define GIC_IntEnClr(Periph) ((volatile UINT32 *)(GIC_DIST + 0x180 + \
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(0x4 * NWORD(Periph))))
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/* interrupt active status */
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#define GIC_IntActSts(Periph) ((volatile UINT32 *)(GIC_DIST + 0x300 + \
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(0x4 * NWORD(Periph))))
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/* clear pending interrupt */
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#define GIC_IntPendClr(Periph) ((volatile UINT32 *)(GIC_DIST + 0x280 + \
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(0x4 * NWORD(Periph))))
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/* interrupt configuration */
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#define GIC_Config(Periph) ((volatile UINT32 *)(GIC_DIST + 0xC00 + \
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(0x4 * (Periph / CONFIGS_PER_WORD))))
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/* interrupt priority */
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#define GIC_Prio(Periph) ((volatile UINT32 *)(GIC_DIST + 0x400 + \
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(0x4 * (Periph / PRIOS_PER_WORD))))
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/* CPU target */
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#define GIC_CPUTarg(Periph) ((volatile UINT32 *)(GIC_DIST + 0x800 + \
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(0x4 * (Periph / TARGETS_PER_WORD))))
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/* software interrupt generate */
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#define GIC_SWInterrupt ((volatile UINT32 *)(GIC_DIST + 0xF00))
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/* CPU interrupt control */
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#define GIC_CPU_Control ((volatile UINT32 *)(GIC_CPU + 0x00))
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/* CPU priority mask */
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#define GIC_CPU_PriMask ((volatile UINT32 *)(GIC_CPU + 0x04))
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/* CPU binary point */
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#define GIC_CPU_BinPoint ((volatile UINT32 *)(GIC_CPU + 0x08))
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/* CPU interrupt acknowledge */
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#define GIC_CPU_IntAck ((volatile UINT32 *)(GIC_CPU + 0x0C))
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/* CPU end of interrupt */
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#define GIC_CPU_EOInt ((volatile UINT32 *)(GIC_CPU + 0x10))
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/* CPU running priority */
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#define GIC_CPU_RunPri ((volatile UINT32 *)(GIC_CPU + 0x14))
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbArmGenIntCtlrh */
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