original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,540 @@
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/* mcfIntc.h - coldfire programmable interrupt timer device header */
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/*
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* Copyright 2007, 2008 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01b,06feb08,rec change CAST_M5208 macros to more generic type
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01a,14nov07,rec created
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*/
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#ifndef __INCmcfIntch
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#define __INCmcfIntch
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/* Register read/write macros */
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#define MCF_INTC_IPRH_OFF 0x000
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#define MCF_INTC_IPRL_OFF 0x004
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#define MCF_INTC_IMRH_OFF 0x008
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#define MCF_INTC_IMRL_OFF 0x00C
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#define MCF_INTC_INTFRCH_OFF 0x010
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#define MCF_INTC_INTFRCL_OFF 0x014
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#define MCF_INTC_ICONFIG_OFF 0x01A
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#define MCF_INTC_SIMR_OFF 0x01C
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#define MCF_INTC_CIMR_OFF 0x01D
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#define MCF_INTC_CLMASK_OFF 0x01E
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#define MCF_INTC_SLMASK_OFF 0x01F
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#define MCF_INTC_ICR0_OFF 0x040
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#define MCF_INTC_ICR1_OFF 0x041
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#define MCF_INTC_ICR2_OFF 0x042
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#define MCF_INTC_ICR3_OFF 0x043
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#define MCF_INTC_ICR4_OFF 0x044
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#define MCF_INTC_ICR5_OFF 0x045
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#define MCF_INTC_ICR6_OFF 0x046
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#define MCF_INTC_ICR7_OFF 0x047
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#define MCF_INTC_ICR8_OFF 0x048
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#define MCF_INTC_ICR9_OFF 0x049
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#define MCF_INTC_ICR10_OFF 0x04A
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#define MCF_INTC_ICR11_OFF 0x04B
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#define MCF_INTC_ICR12_OFF 0x04C
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#define MCF_INTC_ICR13_OFF 0x04D
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#define MCF_INTC_ICR14_OFF 0x04E
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#define MCF_INTC_ICR15_OFF 0x04F
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#define MCF_INTC_ICR16_OFF 0x050
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#define MCF_INTC_ICR17_OFF 0x051
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#define MCF_INTC_ICR18_OFF 0x052
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#define MCF_INTC_ICR19_OFF 0x053
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#define MCF_INTC_ICR20_OFF 0x054
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#define MCF_INTC_ICR21_OFF 0x055
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#define MCF_INTC_ICR22_OFF 0x056
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#define MCF_INTC_ICR23_OFF 0x057
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#define MCF_INTC_ICR24_OFF 0x058
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#define MCF_INTC_ICR25_OFF 0x059
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#define MCF_INTC_ICR26_OFF 0x05A
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#define MCF_INTC_ICR27_OFF 0x05B
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#define MCF_INTC_ICR28_OFF 0x05C
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#define MCF_INTC_ICR29_OFF 0x05D
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#define MCF_INTC_ICR30_OFF 0x05E
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#define MCF_INTC_ICR31_OFF 0x05F
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#define MCF_INTC_ICR32_OFF 0x060
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#define MCF_INTC_ICR33_OFF 0x061
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#define MCF_INTC_ICR34_OFF 0x062
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#define MCF_INTC_ICR35_OFF 0x063
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#define MCF_INTC_ICR36_OFF 0x064
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#define MCF_INTC_ICR37_OFF 0x065
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#define MCF_INTC_ICR38_OFF 0x066
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#define MCF_INTC_ICR39_OFF 0x067
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#define MCF_INTC_ICR40_OFF 0x068
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#define MCF_INTC_ICR41_OFF 0x069
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#define MCF_INTC_ICR42_OFF 0x06A
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#define MCF_INTC_ICR43_OFF 0x06B
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#define MCF_INTC_ICR44_OFF 0x06C
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#define MCF_INTC_ICR45_OFF 0x06D
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#define MCF_INTC_ICR46_OFF 0x06E
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#define MCF_INTC_ICR47_OFF 0x06F
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#define MCF_INTC_ICR48_OFF 0x070
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#define MCF_INTC_ICR49_OFF 0x071
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#define MCF_INTC_ICR50_OFF 0x072
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#define MCF_INTC_ICR51_OFF 0x073
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#define MCF_INTC_ICR52_OFF 0x074
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#define MCF_INTC_ICR53_OFF 0x075
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#define MCF_INTC_ICR54_OFF 0x076
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#define MCF_INTC_ICR55_OFF 0x077
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#define MCF_INTC_ICR56_OFF 0x078
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#define MCF_INTC_ICR57_OFF 0x079
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#define MCF_INTC_ICR58_OFF 0x07A
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#define MCF_INTC_ICR59_OFF 0x07B
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#define MCF_INTC_ICR60_OFF 0x07C
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#define MCF_INTC_ICR61_OFF 0x07D
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#define MCF_INTC_ICR62_OFF 0x07E
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#define MCF_INTC_ICR63_OFF 0x07F
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#define MCF_INTC_SWIACK_OFF 0x0E0
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#define MCF_INTC_L1IACK_OFF 0x0E4
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#define MCF_INTC_L2IACK_OFF 0x0E8
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#define MCF_INTC_L3IACK_OFF 0x0EC
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#define MCF_INTC_L4IACK_OFF 0x0F0
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#define MCF_INTC_L5IACK_OFF 0x0F4
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#define MCF_INTC_L6IACK_OFF 0x0F8
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#define MCF_INTC_L7IACK_OFF 0x0FC
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#define MCF_INTC_IPRH (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IPRH_OFF))
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#define MCF_INTC_IPRL (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IPRL_OFF))
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#define MCF_INTC_IMRH (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IMRH_OFF))
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#define MCF_INTC_IMRL (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_IMRL_OFF))
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#define MCF_INTC_INTFRCH (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_INTFRCH_OFF))
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#define MCF_INTC_INTFRCL (CAST_MCF_VOL(UINT32)(MCF_INTC_BASE + \
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MCF_INTC_INTFRCL_OFF))
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#define MCF_INTC_ICONFIG (CAST_MCF_VOL(UINT16))(MCF_INTC_BASE + \
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MCF_INTC_ICONFIG_OFF))
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#define MCF_INTC_SIMR (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_SIMR_OFF))
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#define MCF_INTC_CIMR (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_CIMR_OFF))
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#define MCF_INTC_CLMASK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_CLMASK_OFF))
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#define MCF_INTC_SLMASK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_SLMASK_OFF))
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#define MCF_INTC_ICR0 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR0_OFF))
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#define MCF_INTC_ICR1 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR1_OFF))
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#define MCF_INTC_ICR2 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR2_OFF))
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#define MCF_INTC_ICR3 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR3_OFF))
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#define MCF_INTC_ICR4 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR4_OFF))
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#define MCF_INTC_ICR5 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR5_OFF))
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#define MCF_INTC_ICR6 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR6_OFF))
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#define MCF_INTC_ICR7 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR7_OFF))
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#define MCF_INTC_ICR8 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR8_OFF))
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#define MCF_INTC_ICR9 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR9_OFF))
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#define MCF_INTC_ICR10 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR10_OFF))
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#define MCF_INTC_ICR11 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR11_OFF))
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#define MCF_INTC_ICR12 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR12_OFF))
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#define MCF_INTC_ICR13 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR13_OFF))
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#define MCF_INTC_ICR14 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR14_OFF))
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#define MCF_INTC_ICR15 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR15_OFF))
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#define MCF_INTC_ICR16 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR16_OFF))
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#define MCF_INTC_ICR17 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR17_OFF))
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#define MCF_INTC_ICR18 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR18_OFF))
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#define MCF_INTC_ICR19 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR19_OFF))
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#define MCF_INTC_ICR20 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR20_OFF))
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#define MCF_INTC_ICR21 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR21_OFF))
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#define MCF_INTC_ICR22 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR22_OFF))
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#define MCF_INTC_ICR23 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR23_OFF))
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#define MCF_INTC_ICR24 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR24_OFF))
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#define MCF_INTC_ICR25 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR25_OFF))
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#define MCF_INTC_ICR26 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR26_OFF))
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#define MCF_INTC_ICR27 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR27_OFF))
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#define MCF_INTC_ICR28 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR28_OFF))
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#define MCF_INTC_ICR29 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR29_OFF))
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#define MCF_INTC_ICR30 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR30_OFF))
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#define MCF_INTC_ICR31 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR31_OFF))
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#define MCF_INTC_ICR32 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR32_OFF))
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#define MCF_INTC_ICR33 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR33_OFF))
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#define MCF_INTC_ICR34 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR34_OFF))
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#define MCF_INTC_ICR35 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR35_OFF))
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#define MCF_INTC_ICR36 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR36_OFF))
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#define MCF_INTC_ICR37 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR37_OFF))
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#define MCF_INTC_ICR38 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR38_OFF))
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#define MCF_INTC_ICR39 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR39_OFF))
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#define MCF_INTC_ICR40 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR40_OFF))
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#define MCF_INTC_ICR41 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR41_OFF))
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#define MCF_INTC_ICR42 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR42_OFF))
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#define MCF_INTC_ICR43 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR43_OFF))
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#define MCF_INTC_ICR44 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR44_OFF))
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#define MCF_INTC_ICR45 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR45_OFF))
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#define MCF_INTC_ICR46 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR46_OFF))
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#define MCF_INTC_ICR47 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR47_OFF))
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#define MCF_INTC_ICR48 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR48_OFF))
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#define MCF_INTC_ICR49 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR49_OFF))
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#define MCF_INTC_ICR50 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR50_OFF))
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#define MCF_INTC_ICR51 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR51_OFF))
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#define MCF_INTC_ICR52 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR52_OFF))
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#define MCF_INTC_ICR53 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR53_OFF))
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#define MCF_INTC_ICR54 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR54_OFF))
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#define MCF_INTC_ICR55 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR55_OFF))
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#define MCF_INTC_ICR56 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR56_OFF))
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#define MCF_INTC_ICR57 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR57_OFF))
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#define MCF_INTC_ICR58 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR58_OFF))
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#define MCF_INTC_ICR59 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR59_OFF))
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#define MCF_INTC_ICR60 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR60_OFF))
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#define MCF_INTC_ICR61 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR61_OFF))
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#define MCF_INTC_ICR62 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR62_OFF))
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#define MCF_INTC_ICR63 (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR63_OFF))
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#define MCF_INTC_ICR(x) (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_ICR0_OFF+((x)*0x001)))
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#define MCF_INTC_SWIACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_SWIACK_OFF))
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#define MCF_INTC_L1IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L1IACK_OFF))
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#define MCF_INTC_L2IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L2IACK_OFF))
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#define MCF_INTC_L3IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L3IACK_OFF))
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#define MCF_INTC_L4IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L4IACK_OFF))
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#define MCF_INTC_L5IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L5IACK_OFF))
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#define MCF_INTC_L6IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L6IACK_OFF))
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#define MCF_INTC_L7IACK (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L7IACK_OFF))
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#define MCF_INTC_LIACK(x) (CAST_MCF_VOL(UINT8)(MCF_INTC_BASE + \
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MCF_INTC_L1IACK_OFF+((x-1)*0x004)))
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/*
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*
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* Interrupt Controller (INTC_IACK)
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*
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*/
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/* Register read/write macros */
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#define MCF_INTC_IACK_GSWIACK (CAST_MCF_VOL(UINT8)(0xFC0540E0))
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#define MCF_INTC_IACK_GL1IACK (CAST_MCF_VOL(UINT8)(0xFC0540E4))
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#define MCF_INTC_IACK_GL2IACK (CAST_MCF_VOL(UINT8)(0xFC0540E8))
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#define MCF_INTC_IACK_GL3IACK (CAST_MCF_VOL(UINT8)(0xFC0540EC))
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#define MCF_INTC_IACK_GL4IACK (CAST_MCF_VOL(UINT8)(0xFC0540F0))
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#define MCF_INTC_IACK_GL5IACK (CAST_MCF_VOL(UINT8)(0xFC0540F4))
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#define MCF_INTC_IACK_GL6IACK (CAST_MCF_VOL(UINT8)(0xFC0540F8))
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#define MCF_INTC_IACK_GL7IACK (CAST_MCF_VOL(UINT8)(0xFC0540FC))
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#define MCF_INTC_IACK_GLIACK(x) (CAST_MCF_VOL(UINT8)(0xFC0540E4+ \
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((x-1)*0x004)))
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/* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */
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||||
#define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)
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||||
/* Bit definitions and macros for MCF_INTC_IACK_GLIACK */
|
||||
#define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0)
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||||
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||||
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|
||||
/* Bit definitions and macros for MCF_INTC_IPRH */
|
||||
#define MCF_INTC_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRL */
|
||||
#define MCF_INTC_IPRL_INT0 (0x00000001)
|
||||
#define MCF_INTC_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRH */
|
||||
#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRL */
|
||||
#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
|
||||
#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCH */
|
||||
#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCL */
|
||||
#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
|
||||
#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
|
||||
#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
|
||||
#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
|
||||
#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
|
||||
#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
|
||||
#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICONFIG */
|
||||
#define MCF_INTC_ICONFIG_EMASK (0x0020)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
|
||||
#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SIMR */
|
||||
#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_CIMR */
|
||||
#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_CLMASK */
|
||||
#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SLMASK */
|
||||
#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICR */
|
||||
#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SWIACK */
|
||||
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_LIACK */
|
||||
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,134 @@
|
||||
/* stm32f2xxIRQ.h - STM32F20x/STM32F21x interrupt request header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,25jul13,mpc Changed priority of system tick timer
|
||||
01a,02may12,rec Created
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains IRQ number and vector assigments specifc to the
|
||||
STM32F20x/STM32F21x interrupt controler.
|
||||
|
||||
SEE ALSO:
|
||||
\tb RM0033 Reference manual STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
|
||||
advanced ARM-based 32-bit MCUs, DEC 2011
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCstm32f2xxIRQh
|
||||
#define __INCstm32f2xxIRQh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* REF: RM0033 Table-20 */
|
||||
|
||||
/* IRQ vector numbers */
|
||||
|
||||
#define SYSTICK_IRQ -1 /* System tick timer */
|
||||
#define WWDG_IRQ 0 /* Window Watchdog */
|
||||
#define PVD_IRQ 1 /* PVD through EXTI line detection */
|
||||
#define TAMP_STAMP_IRQ 2 /* Tamper & TimeStamp through the EXTI line */
|
||||
#define RTC_WKUP_IRQ 3 /* RTC Wakeup interrupt through the EXTI line */
|
||||
#define FLASH_IRQ 4 /* Flash global */
|
||||
#define RCC_IRQ 5 /* RCC global */
|
||||
#define EXTI0_IRQ 6 /* EXTI Line0 */
|
||||
#define EXTI1_IRQ 7 /* EXTI Line1 */
|
||||
#define EXTI2_IRQ 8 /* EXTI Line2 */
|
||||
#define EXTI3_IRQ 9 /* EXTI Line3 */
|
||||
#define EXTI4_IRQ 10 /* EXTI Line4 */
|
||||
#define DMA1_Stream0_IRQ 11 /* DMA1 Stream0 global */
|
||||
#define DMA1_Stream1_IRQ 12 /* DMA1 Stream1 global */
|
||||
#define DMA1_Stream2_IRQ 13 /* DMA1 Stream2 global */
|
||||
#define DMA1_Stream3_IRQ 14 /* DMA1 Stream3 global */
|
||||
#define DMA1_Stream4_IRQ 15 /* DMA1 Stream4 global */
|
||||
#define DMA1_Stream5_IRQ 16 /* DMA1 Stream5 global */
|
||||
#define DMA1_Stream6_IRQ 17 /* DMA1 Stream6 global */
|
||||
#define ADC_IRQ 18 /* ADC1 ADC2 and ADC3 globalinterrupts */
|
||||
#define CAN1_TX_IRQ 19 /* CAN1 TX interrupts */
|
||||
#define CAN1_RX0_IRQ 20 /* CAN1 RX0 interrupts */
|
||||
#define CAN1_RX1_IRQ 21 /* CAN1 RX1 */
|
||||
#define CAN1_SCE_IRQ 22 /* CAN1 SCE */
|
||||
#define EXTI9_5_IRQ 23 /* EXTI Line[9:5] interrupts */
|
||||
#define TIM1_BRK_TIM9_IRQ 24 /* TIM1 Break, TIM9 global */
|
||||
#define TIM1_UP_TIM10_IRQ 25 /* TIM1 Update, TIM10 global */
|
||||
#define TIM1_TRG_COM_TIM11_IRQ 26 /* TIM1 Trig & Commutation TIM11 global */
|
||||
#define TIM1_CC_IRQ 27 /* TIM1 Capture Compare */
|
||||
#define TIM2_IRQ 28 /* TIM2 global */
|
||||
#define TIM3_IRQ 29 /* TIM3 global */
|
||||
#define TIM4_IRQ 30 /* TIM4 global */
|
||||
#define I2C1_EV_IRQ 31 /* I2C1 event */
|
||||
#define I2C1_ER_IRQ 32 /* I2C1 error */
|
||||
#define I2C2_EV_IRQ 33 /* I2C2 event */
|
||||
#define I2C2_ER_IRQ 34 /* I2C2 error */
|
||||
#define SPI1_IRQ 35 /* SPI1 global */
|
||||
#define SPI2_IRQ 36 /* SPI2 global */
|
||||
#define USART1_IRQ 37 /* USART1 global */
|
||||
#define USART2_IRQ 38 /* USART2 global */
|
||||
#define USART3_IRQ 39 /* USART3 global */
|
||||
#define EXTI15_10_IRQ 40 /* EXTI Line[15:10] interrupts */
|
||||
#define RTC_Alarm_IRQ 41 /* RTC Alarms (A and B) through EXTI line */
|
||||
#define OTG_FS_WKUP_IRQ 42 /* USB On-The-Go FS Wakeup through EXTI line */
|
||||
#define TIM8_BRK_TIM12_IRQ 43 /* TIM8 Break interrupt and TIM12 global */
|
||||
#define TIM8_UP_TIM13_IRQ 44 /* TIM8 Update interrupt and TIM13 global */
|
||||
#define TIM8_TRG_COM_TIM1_IRQ 45 /* TIM8 Trig & Commutation, TIM14 global */
|
||||
#define TIM8_CC_TIM8_IRQ 46 /* Capture Compare */
|
||||
#define DMA1_Stream7_IRQ 47 /* DMA1 Stream7 global */
|
||||
#define FSMC_IRQ 48 /* FSMC global */
|
||||
#define SDIO_IRQ 49 /* SDIO global */
|
||||
#define TIM5_IRQ 50 /* TIM5 global */
|
||||
#define SPI3_IRQ 51 /* SPI3 global */
|
||||
#define UART4_IRQ 52 /* UART4 global */
|
||||
#define UART5_IRQ 53 /* UART5 global */
|
||||
#define TIM6_DAC_IRQ 54 /* TIM6 global DAC1, DAC2 underrun error */
|
||||
#define TIM7_TIM7_IRQ 55 /* global */
|
||||
#define DMA2_Stream0_IRQ 56 /* DMA2 Stream0 global */
|
||||
#define DMA2_Stream1_IRQ 57 /* DMA2 Stream1 global */
|
||||
#define DMA2_Stream2_IRQ 58 /* DMA2 Stream2 global */
|
||||
#define DMA2_Stream3_IRQ 59 /* DMA2 Stream3 global */
|
||||
#define DMA2_Stream4_IRQ 60 /* DMA2 Stream4 global */
|
||||
#define ETH_IRQ 61 /* Ethernet global */
|
||||
#define ETH_WKUP_IRQ 62 /* Ethernet Wakeup through EXTI line */
|
||||
#define CAN2_TX_IRQ 63 /* CAN2 TX interrupts */
|
||||
#define CAN2_RX0_IRQ 64 /* CAN2 RX0 interrupts */
|
||||
#define CAN2_RX1_IRQ 65 /* CAN2 RX1 */
|
||||
#define CAN2_SCE_IRQ 66 /* CAN2 SCE */
|
||||
#define OTG_FS_IRQ 67 /* USB On The Go FS global */
|
||||
#define DMA2_Stream5_IRQ 68 /* DMA2 Stream5 global */
|
||||
#define DMA2_Stream6_IRQ 69 /* DMA2 Stream6 global */
|
||||
#define DMA2_Stream7_IRQ 70 /* DMA2 Stream7 global */
|
||||
#define USART6_IRQ 71 /* USART6 global */
|
||||
#define I2C3_EV_IRQ 72 /* I2C3 event */
|
||||
#define I2C3_ER_IRQ 73 /* I2C3 error */
|
||||
#define OTG_HS_EP1_OUT_IRQ 74 /* USB On The Go HS End Point 1 Out global */
|
||||
#define OTG_HS_EP1_IN_IRQ 75 /* USB On The Go HS End Point 1 In global */
|
||||
#define OTG_HS_WKUP_IRQ 76 /* USB On The Go HS Wakeup through EXTI */
|
||||
#define OTG_HS_USB_IRQ 77 /* On The Go HS global */
|
||||
#define DCMI_IRQ 78 /* DCMI global */
|
||||
#define CRYP_IRQ 79 /* crypto global */
|
||||
#define HASH_RNG_IRQ 80 /* Hash and Rng global */
|
||||
|
||||
/* IRQ default priorities (changable) */
|
||||
|
||||
#define SYSTICK_IRQ_PRI 0xff /* System tick timer */
|
||||
#define TIM2_IRQ_PRI 0x20 /* TIM2 global */
|
||||
#define USART3_IRQ_PRI 0x30 /* USART3 global */
|
||||
#define ETH_IRQ_PRI 0x40 /* Ethernet global */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCstm32f2xxIRQh */
|
||||
@@ -0,0 +1,189 @@
|
||||
/* vxbArmGenIntCtlr.h - ARM Generic interrupt controller driver */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008-2009, 2012, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,15jul13,c_l Add interrupt priority/sensitivity support. (WIND00420705)
|
||||
01g,07aug12,j_b add distributor and CPU interface register offset support
|
||||
(CQ:WIND00367952)
|
||||
01f,15apr12,clx support PPI interrupt type
|
||||
01e,09jan12,ggm Fixed interrupt controller configuration (WIND00283926).
|
||||
01d,27oct09,z_l add SMP support
|
||||
01c,16apr09,j_b change core reset and start IPI #s
|
||||
01b,26nov08,j_b declare armGicBase as an extern
|
||||
01a,21oct08,j_b written based on vxbMPCoreIntCtlr.h, rev 01a
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbArmGenIntCtlrh
|
||||
#define __INCvxbArmGenIntCtlrh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
/*
|
||||
* the explanation of some abbreviations
|
||||
*
|
||||
* CPC - Cross Processor Call
|
||||
* IPI - Inter Processor Interrupt
|
||||
* GIC - General Interrupt Controller
|
||||
* SGI - Software Generated Interrupt
|
||||
* PPI - Private Peripheral Interrupt
|
||||
* SPI - Shared Peripheral Interrupt
|
||||
*/
|
||||
|
||||
/* MPCore GIC interrupt levels */
|
||||
|
||||
#define INT_LVL_MPCORE_IPI00 0 /* This is vxWorks CPC IPI */
|
||||
#define INT_LVL_MPCORE_CPC INT_LVL_MPCORE_IPI00
|
||||
|
||||
#define INT_LVL_MPCORE_IPI01 1 /* This is vxWorks Debug IPI */
|
||||
#define INT_LVL_MPCORE_DEBUG INT_LVL_MPCORE_IPI01
|
||||
|
||||
#define INT_LVL_MPCORE_IPI02 2 /* This is vxWorks Reschedule IPI */
|
||||
#define INT_LVL_MPCORE_SCHED INT_LVL_MPCORE_IPI02
|
||||
|
||||
#define INT_LVL_MPCORE_IPI03 3 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI04 4 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI05 5 /* IPI -> use SWI register in GIC */
|
||||
|
||||
#define INT_LVL_MPCORE_IPI06 6 /* This is vxWorks Core Reset IPI */
|
||||
#define INT_LVL_MPCORE_RESET INT_LVL_MPCORE_IPI06
|
||||
|
||||
#define INT_LVL_MPCORE_IPI07 7 /* This is vxWorks Core Start IPI */
|
||||
#define INT_LVL_MPCORE_START INT_LVL_MPCORE_IPI07
|
||||
|
||||
#define INT_LVL_MPCORE_IPI08 8 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI09 9 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI10 10 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI11 11 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI12 12 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI13 13 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI14 14 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI15 15 /* IPI -> use SWI register in GIC */
|
||||
|
||||
|
||||
#define SGI_INT_MAX 16
|
||||
#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
|
||||
#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
|
||||
#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
|
||||
#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
|
||||
|
||||
#define GIC_INT_ALL_ENABLED 0xFF /* priority 0-0xFF can run */
|
||||
#define GIC_INT_ALL_DISABLED 0x00 /* nothing higher than 0 hence disabled */
|
||||
#define GIC_INT_SPURIOUS 0x3FF /* no interrupt currently */
|
||||
#define GIC_INT_ONEMINUS_HIGH 0x55555555 /* interrupt config to 1-N, High */
|
||||
#define GIC_CPU_BINP_DEFAULT 0x07 /* split all priority to subpriority */
|
||||
#define GIC_CPU_CONTROL_ENABLE 0x1 /* enable the processor interface */
|
||||
#define GIC_CPU_ALL_ENABLED 0xFF /* priority 0-E can run */
|
||||
#define GIC_CPU_ALL_DISABLED 0x00 /* nothing higher than 0 */
|
||||
#define GIC_SGI_SRC_CPU_ID_MASK 0x1C00
|
||||
#define GIC_INT_HIGHEST_PRIORITY 0x0 /* the highest priority for interrupts */
|
||||
#define GIC_INT_LOWEST_PRIORITY 0x1F /* the lowest priority for interrupts */
|
||||
#define GIC_INT_PRIORITY_SHIFT 0x8
|
||||
#define GIC_INT_PRIORITY_MASK 0xFF
|
||||
#define GIC_INT_TRIGGER_SHIFT 0x2
|
||||
|
||||
#define GIC_CPU_DIR_DEFAULT 0x01010101 /* all interrupts are directed to CPU0 */
|
||||
|
||||
#define GIC_CONTROL_ENABLE 0x01
|
||||
|
||||
#define ALL_PPI_INT_MASK 0xFFFF0000 /* bit field for all PPI interrupts */
|
||||
#define ALL_SGI_INT_MASK 0x0000FFFF /* bit field for all SGI interrupts */
|
||||
|
||||
/* ARM GIC interrupt distributor and CPU interface register access macros */
|
||||
|
||||
#define BITS_PER_WORD 32
|
||||
#define CONFIGS_PER_WORD 16
|
||||
#define PRIOS_PER_WORD 4
|
||||
#define TARGETS_PER_WORD 4
|
||||
#define NWORD(bitnum) (bitnum / 32)
|
||||
#define BIT(bitnum) (1 << (bitnum % BITS_PER_WORD))
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* GIC distributor and CPU interface register base offsets */
|
||||
|
||||
#define GIC_DIST (armGicBase + armGicDistOffset)
|
||||
#define GIC_CPU (armGicBase + armGicCpuOffset)
|
||||
|
||||
/* interrupt distributor control */
|
||||
|
||||
#define GIC_Control ((volatile UINT32 *)(GIC_DIST + 0x000))
|
||||
|
||||
/* interrupt controller type */
|
||||
|
||||
#define GIC_Type ((volatile UINT32 *)(GIC_DIST + 0x004))
|
||||
|
||||
/* interrupt enable */
|
||||
|
||||
#define GIC_IntEnable(Periph) ((volatile UINT32 *)(GIC_DIST + 0x100 + \
|
||||
(0x4 * NWORD(Periph))))
|
||||
/* clear interrupt enable */
|
||||
|
||||
#define GIC_IntEnClr(Periph) ((volatile UINT32 *)(GIC_DIST + 0x180 + \
|
||||
(0x4 * NWORD(Periph))))
|
||||
/* interrupt active status */
|
||||
|
||||
#define GIC_IntActSts(Periph) ((volatile UINT32 *)(GIC_DIST + 0x300 + \
|
||||
(0x4 * NWORD(Periph))))
|
||||
|
||||
/* clear pending interrupt */
|
||||
|
||||
#define GIC_IntPendClr(Periph) ((volatile UINT32 *)(GIC_DIST + 0x280 + \
|
||||
(0x4 * NWORD(Periph))))
|
||||
/* interrupt configuration */
|
||||
|
||||
#define GIC_Config(Periph) ((volatile UINT32 *)(GIC_DIST + 0xC00 + \
|
||||
(0x4 * (Periph / CONFIGS_PER_WORD))))
|
||||
/* interrupt priority */
|
||||
|
||||
#define GIC_Prio(Periph) ((volatile UINT32 *)(GIC_DIST + 0x400 + \
|
||||
(0x4 * (Periph / PRIOS_PER_WORD))))
|
||||
/* CPU target */
|
||||
|
||||
#define GIC_CPUTarg(Periph) ((volatile UINT32 *)(GIC_DIST + 0x800 + \
|
||||
(0x4 * (Periph / TARGETS_PER_WORD))))
|
||||
/* software interrupt generate */
|
||||
|
||||
#define GIC_SWInterrupt ((volatile UINT32 *)(GIC_DIST + 0xF00))
|
||||
|
||||
/* CPU interrupt control */
|
||||
|
||||
#define GIC_CPU_Control ((volatile UINT32 *)(GIC_CPU + 0x00))
|
||||
|
||||
/* CPU priority mask */
|
||||
|
||||
#define GIC_CPU_PriMask ((volatile UINT32 *)(GIC_CPU + 0x04))
|
||||
|
||||
/* CPU binary point */
|
||||
|
||||
#define GIC_CPU_BinPoint ((volatile UINT32 *)(GIC_CPU + 0x08))
|
||||
|
||||
/* CPU interrupt acknowledge */
|
||||
|
||||
#define GIC_CPU_IntAck ((volatile UINT32 *)(GIC_CPU + 0x0C))
|
||||
|
||||
/* CPU end of interrupt */
|
||||
|
||||
#define GIC_CPU_EOInt ((volatile UINT32 *)(GIC_CPU + 0x10))
|
||||
|
||||
/* CPU running priority */
|
||||
|
||||
#define GIC_CPU_RunPri ((volatile UINT32 *)(GIC_CPU + 0x14))
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbArmGenIntCtlrh */
|
||||
@@ -0,0 +1,327 @@
|
||||
/* vxbCortexMIntCtlr.h - interrupt controller for ARM Cortex-M CPU Cores */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,19aug13,mpc code clean
|
||||
01c,02jul12,m_h Fix macro offsets: multiply by sizeof(UINT32), not 8
|
||||
01b,22may12,j_b move system registers to architecture header, arm-m.h
|
||||
01a,06apr12,m_h created
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file implements macro definitions used by the ARM Cortex-M NVIC
|
||||
* interrupt controller driver.
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbCortexMIntCtlrh
|
||||
#define __INCvxbCortexMIntCtlrh
|
||||
|
||||
#include "arch/arm/arm-m/arm-m.h" /* system register definitions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/********* Default values *********/
|
||||
|
||||
#define CORTEXM_INTCTLR_MAX_PRIORITY 0xFF
|
||||
|
||||
/*
|
||||
* Note. Although Cortex-M3 and Cortex-M4 support a maximum of 256 pins (which
|
||||
* includes the 16 exception vectors at the beginning of the table), ARMv7M
|
||||
* supports a maximum of 512.
|
||||
*/
|
||||
|
||||
#define CORTEXM_INTCTLR_MAX_PINS 512
|
||||
|
||||
/********* Register Bit Values *********/
|
||||
|
||||
/* ICTR Bit Values */
|
||||
|
||||
/*
|
||||
* CORTEXM_INTCTLR_GET_NUM_VECTORS queries the ICTR register and adjusts the
|
||||
* result to represent the total number of exception- and interrupt-vectors
|
||||
* supported by the hardware implementation. The first 16 of these vectors
|
||||
* are reserved for exceptions, the rest are the external interrupts.
|
||||
*
|
||||
* ICTR.INTLINESNUM returns the maximum number of external interrupts
|
||||
* supported. We add 16 to account for the additional 16 exception vectors.
|
||||
*
|
||||
* If ICTR.INTLINESNUM contains 0xF, this actually indicates that there are
|
||||
* 496 interrupt lines, not 512. So, for this case, the value of
|
||||
* CORTEXM_INTCTLR_GET_NUM_VECTORS is adjusted accordingly.
|
||||
*/
|
||||
|
||||
#define CORTEXM_INTCTLR_GET_NUM_VECTORS \
|
||||
((CORTEXM_INT_READ_4(CORTEXM_ICTR)&0xF) == 0xF) \
|
||||
? 512 \
|
||||
: (((CORTEXM_INT_READ_4(CORTEXM_ICTR)&0xF) + 1) * 32) + 16
|
||||
|
||||
/************ Register Address Mappings *****************/
|
||||
|
||||
/* Interrupt Set-Enable Registers */
|
||||
|
||||
/* write a "1" to the appropriate bit to enable the interrupt */
|
||||
|
||||
#define CORTEXM_NVIC_ISER0 (0xE000E100) /* IRQ 0-31 enable */
|
||||
#define CORTEXM_NVIC_ISER1 (0xE000E104) /* IRQ 32-63 enable */
|
||||
#define CORTEXM_NVIC_ISER2 (0xE000E108) /* IRQ 64-95 enable */
|
||||
#define CORTEXM_NVIC_ISER3 (0xE000E10C) /* IRQ 96-127 enable */
|
||||
#define CORTEXM_NVIC_ISER4 (0xE000E110) /* IRQ 128-159 enable */
|
||||
#define CORTEXM_NVIC_ISER5 (0xE000E114) /* IRQ 160-191 enable */
|
||||
#define CORTEXM_NVIC_ISER6 (0xE000E118) /* IRQ 192-223 enable */
|
||||
#define CORTEXM_NVIC_ISER7 (0xE000E11C) /* IRQ 224-255 enable */
|
||||
#define CORTEXM_NVIC_ISER8 (0xE000E120) /* IRQ 256-287 enable */
|
||||
#define CORTEXM_NVIC_ISER9 (0xE000E124) /* IRQ 288-319 enable */
|
||||
#define CORTEXM_NVIC_ISER10 (0xE000E128) /* IRQ 320-351 enable */
|
||||
#define CORTEXM_NVIC_ISER11 (0xE000E12C) /* IRQ 352-383 enable */
|
||||
#define CORTEXM_NVIC_ISER12 (0xE000E130) /* IRQ 384-415 enable */
|
||||
#define CORTEXM_NVIC_ISER13 (0xE000E134) /* IRQ 416-447 enable */
|
||||
#define CORTEXM_NVIC_ISER14 (0xE000E138) /* IRQ 448-479 enable */
|
||||
#define CORTEXM_NVIC_ISER15 (0xE000E13C) /* IRQ 480-495 enable */
|
||||
|
||||
#define CORTEXM_NVIC_ISER(n) (CORTEXM_NVIC_ISER0 + (sizeof(UINT32) * (n)))
|
||||
|
||||
/* Interrupt Clear-Enable Registers */
|
||||
|
||||
/* write a "1" to the appropriate bit to disable the interrupt */
|
||||
|
||||
#define CORTEXM_NVIC_ICER0 (0xE000E180) /* IRQ 0-31 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER1 (0xE000E184) /* IRQ 32-63 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER2 (0xE000E188) /* IRQ 64-95 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER3 (0xE000E18C) /* IRQ 96-127 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER4 (0xE000E190) /* IRQ 128-159 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER5 (0xE000E194) /* IRQ 160-191 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER6 (0xE000E198) /* IRQ 192-223 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER7 (0xE000E19C) /* IRQ 224-255 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER8 (0xE000E1A0) /* IRQ 256-287 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER9 (0xE000E1A4) /* IRQ 288-319 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER10 (0xE000E1A8) /* IRQ 320-351 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER11 (0xE000E1AC) /* IRQ 352-383 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER12 (0xE000E1B0) /* IRQ 384-415 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER13 (0xE000E1B4) /* IRQ 416-447 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER14 (0xE000E1B8) /* IRQ 448-479 clear-enable */
|
||||
#define CORTEXM_NVIC_ICER15 (0xE000E1BC) /* IRQ 480-495 clear-enable */
|
||||
|
||||
#define CORTEXM_NVIC_ICER(n) (CORTEXM_NVIC_ICER0 + (sizeof(UINT32) * (n)))
|
||||
|
||||
/* Interrupt Set-Pending Registers */
|
||||
|
||||
/* write a "1" to the appropriate bit to force an interrupt to pend */
|
||||
|
||||
#define CORTEXM_NVIC_ISPR0 (0xE000E200) /* IRQ 0-31 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR1 (0xE000E204) /* IRQ 32-63 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR2 (0xE000E208) /* IRQ 64-95 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR3 (0xE000E20C) /* IRQ 96-127 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR4 (0xE000E210) /* IRQ 128-159 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR5 (0xE000E214) /* IRQ 160-191 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR6 (0xE000E218) /* IRQ 192-223 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR7 (0xE000E21C) /* IRQ 224-255 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR8 (0xE000E220) /* IRQ 256-287 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR9 (0xE000E224) /* IRQ 288-319 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR10 (0xE000E228) /* IRQ 320-351 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR11 (0xE000E22C) /* IRQ 352-383 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR12 (0xE000E230) /* IRQ 384-415 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR13 (0xE000E234) /* IRQ 416-447 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR14 (0xE000E238) /* IRQ 448-479 set-pending */
|
||||
#define CORTEXM_NVIC_ISPR15 (0xE000E23C) /* IRQ 480-495 set-pending */
|
||||
|
||||
#define CORTEXM_NVIC_ISPR(n) (CORTEXM_NVIC_ISPR0 + (sizeof(UINT32) * (n)))
|
||||
|
||||
/* Interrupt Clear-Pending Registers */
|
||||
|
||||
/* write a "1" to the appropriate bit to un-pend a pended interrupt */
|
||||
|
||||
#define CORTEXM_NVIC_ICPR0 (0xE000E280) /* IRQ 0-31 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR1 (0xE000E284) /* IRQ 32-63 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR2 (0xE000E288) /* IRQ 64-95 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR3 (0xE000E28C) /* IRQ 96-127 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR4 (0xE000E290) /* IRQ 128-159 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR5 (0xE000E294) /* IRQ 160-191 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR6 (0xE000E298) /* IRQ 192-223 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR7 (0xE000E29C) /* IRQ 224-255 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR8 (0xE000E2A0) /* IRQ 256-287 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR9 (0xE000E2A4) /* IRQ 288-319 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR10 (0xE000E2A8) /* IRQ 320-351 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR11 (0xE000E2AC) /* IRQ 352-383 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR12 (0xE000E2B0) /* IRQ 384-415 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR13 (0xE000E2B4) /* IRQ 416-447 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR14 (0xE000E2B8) /* IRQ 448-479 clear-pending */
|
||||
#define CORTEXM_NVIC_ICPR15 (0xE000E2BC) /* IRQ 480-495 clear-pending */
|
||||
|
||||
#define CORTEXM_NVIC_ICPR(n) (CORTEXM_NVIC_ICPR0 + (sizeof(UINT32) * (n)))
|
||||
|
||||
|
||||
/* Interrupt Active Bit Register */
|
||||
|
||||
/*
|
||||
* Combine with ISPR to read status of an interrupt:
|
||||
* Inactive, Active, Pending, or Active and Pending
|
||||
*/
|
||||
|
||||
#define CORTEXM_NVIC_IABR0 (0xE000E300) /* IRQ 0-31 active */
|
||||
#define CORTEXM_NVIC_IABR1 (0xE000E304) /* IRQ 32-63 active */
|
||||
#define CORTEXM_NVIC_IABR2 (0xE000E308) /* IRQ 64-95 active */
|
||||
#define CORTEXM_NVIC_IABR3 (0xE000E30C) /* IRQ 96-127 active */
|
||||
#define CORTEXM_NVIC_IABR4 (0xE000E310) /* IRQ 128-159 active */
|
||||
#define CORTEXM_NVIC_IABR5 (0xE000E314) /* IRQ 160-191 active */
|
||||
#define CORTEXM_NVIC_IABR6 (0xE000E318) /* IRQ 192-223 active */
|
||||
#define CORTEXM_NVIC_IABR7 (0xE000E31C) /* IRQ 224-255 active */
|
||||
#define CORTEXM_NVIC_IABR8 (0xE000E320) /* IRQ 256-287 active */
|
||||
#define CORTEXM_NVIC_IABR9 (0xE000E324) /* IRQ 288-319 active */
|
||||
#define CORTEXM_NVIC_IABR10 (0xE000E328) /* IRQ 320-351 active */
|
||||
#define CORTEXM_NVIC_IABR11 (0xE000E32C) /* IRQ 352-383 active */
|
||||
#define CORTEXM_NVIC_IABR12 (0xE000E330) /* IRQ 384-415 active */
|
||||
#define CORTEXM_NVIC_IABR13 (0xE000E334) /* IRQ 416-447 active */
|
||||
#define CORTEXM_NVIC_IABR14 (0xE000E338) /* IRQ 448-479 active */
|
||||
#define CORTEXM_NVIC_IABR15 (0xE000E33C) /* IRQ 480-495 active */
|
||||
|
||||
#define CORTEXM_NVIC_IABR(n) (CORTEXM_NVIC_IABR0 + (sizeof(UINT32) * (n)))
|
||||
|
||||
/* Interrupt Priority Register */
|
||||
|
||||
#define CORTEXM_NVIC_IPR0 (0xE000E400) /* IRQ 0-3 priority */
|
||||
#define CORTEXM_NVIC_IPR1 (0xE000E404) /* IRQ 4-7 priority */
|
||||
#define CORTEXM_NVIC_IPR2 (0xE000E408) /* IRQ 8-11 priority */
|
||||
#define CORTEXM_NVIC_IPR3 (0xE000E40C) /* IRQ 12-15 priority */
|
||||
#define CORTEXM_NVIC_IPR4 (0xE000E410) /* IRQ 16-19 priority */
|
||||
#define CORTEXM_NVIC_IPR5 (0xE000E414) /* IRQ 20-23 priority */
|
||||
#define CORTEXM_NVIC_IPR6 (0xE000E418) /* IRQ 24-27 priority */
|
||||
#define CORTEXM_NVIC_IPR7 (0xE000E41C) /* IRQ 28-31 priority */
|
||||
#define CORTEXM_NVIC_IPR8 (0xE000E420) /* IRQ 32-35 priority */
|
||||
#define CORTEXM_NVIC_IPR9 (0xE000E424) /* IRQ 36-39 priority */
|
||||
#define CORTEXM_NVIC_IPR10 (0xE000E428) /* IRQ 40-43 priority */
|
||||
#define CORTEXM_NVIC_IPR11 (0xE000E42C) /* IRQ 44-47 priority */
|
||||
#define CORTEXM_NVIC_IPR12 (0xE000E430) /* IRQ 48-51 priority */
|
||||
#define CORTEXM_NVIC_IPR13 (0xE000E434) /* IRQ 52-55 priority */
|
||||
#define CORTEXM_NVIC_IPR14 (0xE000E438) /* IRQ 56-59 priority */
|
||||
#define CORTEXM_NVIC_IPR15 (0xE000E43C) /* IRQ 60-63 priority */
|
||||
#define CORTEXM_NVIC_IPR16 (0xE000E440) /* IRQ 64-67 priority */
|
||||
#define CORTEXM_NVIC_IPR17 (0xE000E444) /* IRQ 68-71 priority */
|
||||
#define CORTEXM_NVIC_IPR18 (0xE000E448) /* IRQ 72-75 priority */
|
||||
#define CORTEXM_NVIC_IPR19 (0xE000E44C) /* IRQ 76-79 priority */
|
||||
#define CORTEXM_NVIC_IPR20 (0xE000E450) /* IRQ 80-83 priority */
|
||||
#define CORTEXM_NVIC_IPR21 (0xE000E454) /* IRQ 84-87 priority */
|
||||
#define CORTEXM_NVIC_IPR22 (0xE000E458) /* IRQ 88-91 priority */
|
||||
#define CORTEXM_NVIC_IPR23 (0xE000E45C) /* IRQ 92-95 priority */
|
||||
#define CORTEXM_NVIC_IPR24 (0xE000E460) /* IRQ 96-99 priority */
|
||||
#define CORTEXM_NVIC_IPR25 (0xE000E464) /* IRQ 100-103 priority */
|
||||
#define CORTEXM_NVIC_IPR26 (0xE000E468) /* IRQ 104-107 priority */
|
||||
#define CORTEXM_NVIC_IPR27 (0xE000E46C) /* IRQ 108-111 priority */
|
||||
#define CORTEXM_NVIC_IPR28 (0xE000E470) /* IRQ 112-115 priority */
|
||||
#define CORTEXM_NVIC_IPR29 (0xE000E474) /* IRQ 116-119 priority */
|
||||
#define CORTEXM_NVIC_IPR30 (0xE000E478) /* IRQ 120-123 priority */
|
||||
#define CORTEXM_NVIC_IPR31 (0xE000E47C) /* IRQ 124-127 priority */
|
||||
#define CORTEXM_NVIC_IPR32 (0xE000E480) /* IRQ 128-131 priority */
|
||||
#define CORTEXM_NVIC_IPR33 (0xE000E484) /* IRQ 132-135 priority */
|
||||
#define CORTEXM_NVIC_IPR34 (0xE000E488) /* IRQ 136-139 priority */
|
||||
#define CORTEXM_NVIC_IPR35 (0xE000E48C) /* IRQ 140-143 priority */
|
||||
#define CORTEXM_NVIC_IPR36 (0xE000E490) /* IRQ 144-147 priority */
|
||||
#define CORTEXM_NVIC_IPR37 (0xE000E494) /* IRQ 148-151 priority */
|
||||
#define CORTEXM_NVIC_IPR38 (0xE000E498) /* IRQ 152-155 priority */
|
||||
#define CORTEXM_NVIC_IPR39 (0xE000E49C) /* IRQ 156-159 priority */
|
||||
#define CORTEXM_NVIC_IPR40 (0xE000E4A0) /* IRQ 160-163 priority */
|
||||
#define CORTEXM_NVIC_IPR41 (0xE000E4A4) /* IRQ 164-167 priority */
|
||||
#define CORTEXM_NVIC_IPR42 (0xE000E4A8) /* IRQ 168-171 priority */
|
||||
#define CORTEXM_NVIC_IPR43 (0xE000E4AC) /* IRQ 172-175 priority */
|
||||
#define CORTEXM_NVIC_IPR44 (0xE000E4B0) /* IRQ 176-179 priority */
|
||||
#define CORTEXM_NVIC_IPR45 (0xE000E4B4) /* IRQ 180-183 priority */
|
||||
#define CORTEXM_NVIC_IPR46 (0xE000E4B8) /* IRQ 184-187 priority */
|
||||
#define CORTEXM_NVIC_IPR47 (0xE000E4BC) /* IRQ 188-191 priority */
|
||||
#define CORTEXM_NVIC_IPR48 (0xE000E4C0) /* IRQ 192-195 priority */
|
||||
#define CORTEXM_NVIC_IPR49 (0xE000E4C4) /* IRQ 196-199 priority */
|
||||
#define CORTEXM_NVIC_IPR50 (0xE000E4C8) /* IRQ 200-203 priority */
|
||||
#define CORTEXM_NVIC_IPR51 (0xE000E4CC) /* IRQ 204-207 priority */
|
||||
#define CORTEXM_NVIC_IPR52 (0xE000E4D0) /* IRQ 208-211 priority */
|
||||
#define CORTEXM_NVIC_IPR53 (0xE000E4D4) /* IRQ 212-215 priority */
|
||||
#define CORTEXM_NVIC_IPR54 (0xE000E4D8) /* IRQ 216-219 priority */
|
||||
#define CORTEXM_NVIC_IPR55 (0xE000E4DC) /* IRQ 220-223 priority */
|
||||
#define CORTEXM_NVIC_IPR56 (0xE000E4E0) /* IRQ 224-227 priority */
|
||||
#define CORTEXM_NVIC_IPR57 (0xE000E4E4) /* IRQ 228-231 priority */
|
||||
#define CORTEXM_NVIC_IPR58 (0xE000E4E8) /* IRQ 232-235 priority */
|
||||
#define CORTEXM_NVIC_IPR59 (0xE000E4EC) /* IRQ 236-239 priority */
|
||||
#define CORTEXM_NVIC_IPR60 (0xE000E4F0) /* IRQ 240-243 priority */
|
||||
#define CORTEXM_NVIC_IPR61 (0xE000E4F4) /* IRQ 244-247 priority */
|
||||
#define CORTEXM_NVIC_IPR62 (0xE000E4F8) /* IRQ 248-251 priority */
|
||||
#define CORTEXM_NVIC_IPR63 (0xE000E4FC) /* IRQ 252-255 priority */
|
||||
#define CORTEXM_NVIC_IPR64 (0xE000E500) /* IRQ 256-259 priority */
|
||||
#define CORTEXM_NVIC_IPR65 (0xE000E504) /* IRQ 260-263 priority */
|
||||
#define CORTEXM_NVIC_IPR66 (0xE000E508) /* IRQ 264-267 priority */
|
||||
#define CORTEXM_NVIC_IPR67 (0xE000E50C) /* IRQ 268-271 priority */
|
||||
#define CORTEXM_NVIC_IPR68 (0xE000E510) /* IRQ 272-275 priority */
|
||||
#define CORTEXM_NVIC_IPR69 (0xE000E514) /* IRQ 276-279 priority */
|
||||
#define CORTEXM_NVIC_IPR70 (0xE000E518) /* IRQ 280-283 priority */
|
||||
#define CORTEXM_NVIC_IPR71 (0xE000E51C) /* IRQ 284-287 priority */
|
||||
#define CORTEXM_NVIC_IPR72 (0xE000E520) /* IRQ 288-291 priority */
|
||||
#define CORTEXM_NVIC_IPR73 (0xE000E524) /* IRQ 292-295 priority */
|
||||
#define CORTEXM_NVIC_IPR74 (0xE000E528) /* IRQ 296-299 priority */
|
||||
#define CORTEXM_NVIC_IPR75 (0xE000E52C) /* IRQ 300-303 priority */
|
||||
#define CORTEXM_NVIC_IPR76 (0xE000E530) /* IRQ 304-307 priority */
|
||||
#define CORTEXM_NVIC_IPR77 (0xE000E534) /* IRQ 308-311 priority */
|
||||
#define CORTEXM_NVIC_IPR78 (0xE000E538) /* IRQ 312-315 priority */
|
||||
#define CORTEXM_NVIC_IPR79 (0xE000E53C) /* IRQ 316-319 priority */
|
||||
#define CORTEXM_NVIC_IPR80 (0xE000E540) /* IRQ 320-323 priority */
|
||||
#define CORTEXM_NVIC_IPR81 (0xE000E544) /* IRQ 324-327 priority */
|
||||
#define CORTEXM_NVIC_IPR82 (0xE000E548) /* IRQ 328-331 priority */
|
||||
#define CORTEXM_NVIC_IPR83 (0xE000E54C) /* IRQ 332-335 priority */
|
||||
#define CORTEXM_NVIC_IPR84 (0xE000E550) /* IRQ 336-339 priority */
|
||||
#define CORTEXM_NVIC_IPR85 (0xE000E554) /* IRQ 340-343 priority */
|
||||
#define CORTEXM_NVIC_IPR86 (0xE000E558) /* IRQ 344-347 priority */
|
||||
#define CORTEXM_NVIC_IPR87 (0xE000E55C) /* IRQ 348-351 priority */
|
||||
#define CORTEXM_NVIC_IPR88 (0xE000E560) /* IRQ 352-355 priority */
|
||||
#define CORTEXM_NVIC_IPR89 (0xE000E564) /* IRQ 356-359 priority */
|
||||
#define CORTEXM_NVIC_IPR90 (0xE000E568) /* IRQ 360-363 priority */
|
||||
#define CORTEXM_NVIC_IPR91 (0xE000E56C) /* IRQ 364-367 priority */
|
||||
#define CORTEXM_NVIC_IPR92 (0xE000E570) /* IRQ 368-371 priority */
|
||||
#define CORTEXM_NVIC_IPR93 (0xE000E574) /* IRQ 372-375 priority */
|
||||
#define CORTEXM_NVIC_IPR94 (0xE000E578) /* IRQ 376-379 priority */
|
||||
#define CORTEXM_NVIC_IPR95 (0xE000E57C) /* IRQ 380-383 priority */
|
||||
#define CORTEXM_NVIC_IPR96 (0xE000E580) /* IRQ 384-387 priority */
|
||||
#define CORTEXM_NVIC_IPR97 (0xE000E584) /* IRQ 388-391 priority */
|
||||
#define CORTEXM_NVIC_IPR98 (0xE000E588) /* IRQ 392-395 priority */
|
||||
#define CORTEXM_NVIC_IPR99 (0xE000E58C) /* IRQ 396-399 priority */
|
||||
#define CORTEXM_NVIC_IPR100 (0xE000E590) /* IRQ 400-403 priority */
|
||||
#define CORTEXM_NVIC_IPR101 (0xE000E594) /* IRQ 404-407 priority */
|
||||
#define CORTEXM_NVIC_IPR102 (0xE000E598) /* IRQ 408-411 priority */
|
||||
#define CORTEXM_NVIC_IPR103 (0xE000E59C) /* IRQ 412-415 priority */
|
||||
#define CORTEXM_NVIC_IPR104 (0xE000E5A0) /* IRQ 416-419 priority */
|
||||
#define CORTEXM_NVIC_IPR105 (0xE000E5A4) /* IRQ 420-423 priority */
|
||||
#define CORTEXM_NVIC_IPR106 (0xE000E5A8) /* IRQ 424-427 priority */
|
||||
#define CORTEXM_NVIC_IPR107 (0xE000E5AC) /* IRQ 428-431 priority */
|
||||
#define CORTEXM_NVIC_IPR108 (0xE000E5B0) /* IRQ 432-435 priority */
|
||||
#define CORTEXM_NVIC_IPR109 (0xE000E5B4) /* IRQ 436-439 priority */
|
||||
#define CORTEXM_NVIC_IPR110 (0xE000E5B8) /* IRQ 440-443 priority */
|
||||
#define CORTEXM_NVIC_IPR111 (0xE000E5BC) /* IRQ 444-447 priority */
|
||||
#define CORTEXM_NVIC_IPR112 (0xE000E5C0) /* IRQ 448-451 priority */
|
||||
#define CORTEXM_NVIC_IPR113 (0xE000E5C4) /* IRQ 452-455 priority */
|
||||
#define CORTEXM_NVIC_IPR114 (0xE000E5C8) /* IRQ 456-459 priority */
|
||||
#define CORTEXM_NVIC_IPR115 (0xE000E5CC) /* IRQ 460-463 priority */
|
||||
#define CORTEXM_NVIC_IPR116 (0xE000E5D0) /* IRQ 464-467 priority */
|
||||
#define CORTEXM_NVIC_IPR117 (0xE000E5D4) /* IRQ 468-471 priority */
|
||||
#define CORTEXM_NVIC_IPR118 (0xE000E5D8) /* IRQ 472-475 priority */
|
||||
#define CORTEXM_NVIC_IPR119 (0xE000E5DC) /* IRQ 476-479 priority */
|
||||
#define CORTEXM_NVIC_IPR120 (0xE000E5E0) /* IRQ 480-483 priority */
|
||||
#define CORTEXM_NVIC_IPR121 (0xE000E5E4) /* IRQ 484-487 priority */
|
||||
#define CORTEXM_NVIC_IPR122 (0xE000E5E8) /* IRQ 488-491 priority */
|
||||
#define CORTEXM_NVIC_IPR123 (0xE000E5EC) /* IRQ 492-495 priority */
|
||||
|
||||
#define CORTEXM_NVIC_IPR(n) (CORTEXM_NVIC_IPR0 + (sizeof(UINT32) * (n)))
|
||||
#define CORTEXM_NVIC_IPR_BYTE(n) (CORTEXM_NVIC_IPR0 + (n))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbCortexMIntCtlrh */
|
||||
|
||||
@@ -0,0 +1,966 @@
|
||||
/* vxbEpicIntCtlr.h - Embedded Programmable Interrupt Controller driver */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006-2010, 2012-2015 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/* Copyright 1996, 1998 Motorola, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
02dec15,wyt use vxbRead32/vxbWrite32 to access EPIC registers in order
|
||||
to prevent the reordering of memory access. (VXW6-84836)
|
||||
05mar14,d_l add Global Revision and critical Registers
|
||||
01x,04feb13,j_z add share message bank A,B,C support.(WIND00333514)
|
||||
01y,28feb13,h_k added T4_ERRATUM_CPU6198 for e6500.
|
||||
01x,09jan13,zl decouple EPIC ID and CPU ID
|
||||
01w,06mar12,wqi correct 4080 core 4 to 7 can't receive doorbell
|
||||
interrupt. (WIND00288544)
|
||||
01v,11jan12,agf fix compiler warnings
|
||||
01u,29apr10,pad Moved extern C statement after include statements.
|
||||
01t,05jan09,b_m add global timer group B support.
|
||||
01s,09dec08,pmr add external proxy support
|
||||
01r,29oct08,pmr fix OPT_EN_N value
|
||||
01p,02jun08,h_k split vxbEpicIntCtlr.c.
|
||||
01o,30may08,pmr flexible interrupt assignment
|
||||
01n,24apr08,pmr initial e500mc support
|
||||
01m,31mar08,dtr Modify IPI vector to work with Linux.
|
||||
01l,06mar08,h_k updated to use global access registers.
|
||||
01k,16jul07,pmr cleanup
|
||||
01j,27jun07,dtr Additonal register for shared message interrupt.
|
||||
01i,11jun07,pmr IPI priority, add FRR definitions
|
||||
01h,12mar07,kk reinstate PCI and SMSG support
|
||||
01g,12mar07,kk backed out PCI and SMSG support temporarily, breaks SMP
|
||||
01f,26feb07,dtr Support Message Shared Interrupts.
|
||||
01e,09Nov06,tor VxBus port
|
||||
01d,22jun06,mmi replaced int with cpuset_t for processor references
|
||||
01c,05may06,mig Add CPU1 IPI support
|
||||
01b,18apr06,dtr Add IPI support.
|
||||
01a,06mar06,dtr Modified from cds8548/sysEpic.h/01b
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbSysEpich
|
||||
#define __INCvxbSysEpich
|
||||
|
||||
|
||||
#include <vxBusLib.h>
|
||||
#include <vxIpiLib.h>
|
||||
#include <../src/hwif/intCtlr/vxbIntCtlrLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* interrupt handler description */
|
||||
|
||||
typedef struct intHandlerDesc
|
||||
{
|
||||
VOIDFUNCPTR vec; /* interrupt vector */
|
||||
int arg; /* interrupt handler argument */
|
||||
struct intHandlerDesc * next; /* pointer to the next handler */
|
||||
} INT_HANDLER_DESC;
|
||||
|
||||
typedef struct intBankDesc
|
||||
{
|
||||
int startIrq;
|
||||
int numIrqs;
|
||||
ULONG regBaseAdrs;
|
||||
short regInterval;
|
||||
short type;
|
||||
} INT_BANK_DESC;
|
||||
|
||||
#define INT_BANK_DESC_NUM 10
|
||||
#define REG_ADRS_MASK 0x00ffffff
|
||||
#define REG_TYPE_MASK 0xff000000
|
||||
#define REG_TYPE_SHIFT 24
|
||||
|
||||
typedef struct vxbEpicIntCtlrDrvCtrl
|
||||
{
|
||||
VXB_DEVICE_ID pInst;
|
||||
struct intCtlrHwConf isrHandle;
|
||||
struct dynamicIntrTable *dynamicInterruptTable;
|
||||
UINT32 dynamicInterruptTableSize;
|
||||
void * regAccessHandle;
|
||||
UINT32 numCpus;
|
||||
UINT32 exPolar;
|
||||
UINT32 exSense;
|
||||
UINT32 inPolar;
|
||||
BOOL crtEnable;
|
||||
int numInts;
|
||||
ULONG * regTable;
|
||||
INT_BANK_DESC * intBankDesc[INT_BANK_DESC_NUM];
|
||||
int extIrq0;
|
||||
int inIrq0;
|
||||
int gtAIrq0;
|
||||
int gtBIrq0;
|
||||
int smsgIrq0;
|
||||
int msgIrq0;
|
||||
int ipiIrq0;
|
||||
UINT32 version;
|
||||
UINT32 numInInts; /* Number of max internal interrupt supported */
|
||||
} VXB_EPICINTCTLR_DRV_CTRL;
|
||||
|
||||
/* limit values */
|
||||
|
||||
/* bits 31(MSB)...0(LSB) enable only 1 bit at bit x */
|
||||
#define EPIC_BIT(x) ((ULONG)(1 << (x)))
|
||||
|
||||
/* bits 31(MSB)...0(LSB) enable from bit x to bit y where y>x */
|
||||
#define EPIC_BITS_M2N(x, y) (( 1 << ((y)-(x)+1) ) - 1) << (x)
|
||||
|
||||
/* bits 31(MSB)...0(LSB) from bit x towards LSB enable y bits */
|
||||
#define EPIC_BITS(x, y) EPIC_BITS_M2N(x-y+1, x)
|
||||
|
||||
#define EPIC_CCSROFF 0x40000 /* EUMBBAR of EPIC */
|
||||
|
||||
/* default is LEVEL sensitive, ACTIVE_HIGH polarity */
|
||||
|
||||
#ifndef EPIC_EX_DFT_SENSE
|
||||
# define EPIC_EX_DFT_SENSE EPIC_SENSE_LVL
|
||||
#endif /* EPIC_EX_DFT_SENSE */
|
||||
|
||||
#ifndef EPIC_EX_DFT_POLAR
|
||||
# define EPIC_EX_DFT_POLAR EPIC_INT_ACT_HIGH
|
||||
#endif /* EPIC_EX_DFT_POLAR */
|
||||
|
||||
#ifndef EPIC_IN_DFT_POLAR
|
||||
# define EPIC_IN_DFT_POLAR EPIC_INT_ACT_HIGH
|
||||
#endif /* EPIC_IN_DFT_POLAR */
|
||||
|
||||
/* Global Revision Registers */
|
||||
#define EPIC_BRR1 (EPIC_CCSROFF + 0x00)
|
||||
#define EPIC_BRR2 (EPIC_CCSROFF + 0x10)
|
||||
|
||||
/* Global Access Registers */
|
||||
#define EPIC_IPI_DPATCH_REG0 (EPIC_CCSROFF + 0x00040)/* IPI0 dispatch */
|
||||
#define EPIC_IPI_DPATCH_REG1 (EPIC_CCSROFF + 0x00050)/* IPI1 dispatch */
|
||||
#define EPIC_IPI_DPATCH_REG2 (EPIC_CCSROFF + 0x00060)/* IPI2 dispatch */
|
||||
#define EPIC_IPI_DPATCH_REG3 (EPIC_CCSROFF + 0x00070)/* IPI3 dispatch */
|
||||
#define EPIC_CTASK_PRI_REG (EPIC_CCSROFF + 0x00080)/* Cur Task Prio */
|
||||
#define EPIC_WHO_AM_I_REG (EPIC_CCSROFF + 0x00090)/* Who am I */
|
||||
#define EPIC_INT_ACK_REG (EPIC_CCSROFF + 0x000a0)/* Int ack */
|
||||
#define EPIC_EOI_REG (EPIC_CCSROFF + 0x000b0)/* End of Int */
|
||||
|
||||
/* Global and Timer */
|
||||
#define EPIC_FEATURES_REG (EPIC_CCSROFF + 0x01000)/* Feature reporting */
|
||||
#define EPIC_GLOBAL_REG (EPIC_CCSROFF + 0x01020)/* Global config. */
|
||||
#define EPIC_VENDOR_ID_REG (EPIC_CCSROFF + 0x01080)/* Vendor id */
|
||||
#define EPIC_PROC_INIT_REG (EPIC_CCSROFF + 0x01090)/* Processor init. */
|
||||
#define EPIC_IPI_0_VEC_REG (EPIC_CCSROFF + 0x010a0)/* IPI0 vect/prio */
|
||||
#define EPIC_IPI_1_VEC_REG (EPIC_CCSROFF + 0x010b0)/* IPI1 vect/prio */
|
||||
#define EPIC_IPI_2_VEC_REG (EPIC_CCSROFF + 0x010c0)/* IPI2 vect/prio */
|
||||
#define EPIC_IPI_3_VEC_REG (EPIC_CCSROFF + 0x010d0)/* IPI3 vect/prio */
|
||||
#define EPIC_SPUR_VEC_REG (EPIC_CCSROFF + 0x010e0)/* Spurious vector */
|
||||
|
||||
/* Global Timer Group A registers */
|
||||
|
||||
#define EPIC_TM_A_FREQ_REG (EPIC_CCSROFF + 0x010f0)/* Timer A Frequency */
|
||||
|
||||
#define EPIC_TM_A0_VEC_REG (EPIC_CCSROFF + 0x01120)/* Gbl TM A0 Vector Pri */
|
||||
#define EPIC_TM_A0_DES_REG (EPIC_CCSROFF + 0x01130)/* Gbl TM A0 Dest. */
|
||||
#define EPIC_TM_A1_VEC_REG (EPIC_CCSROFF + 0x01160)/* Gbl TM A1 Vector Pri */
|
||||
#define EPIC_TM_A1_DES_REG (EPIC_CCSROFF + 0x01170)/* Gbl TM A1 Dest. */
|
||||
#define EPIC_TM_A2_VEC_REG (EPIC_CCSROFF + 0x011a0)/* Gbl TM A2 Vector Pri */
|
||||
#define EPIC_TM_A2_DES_REG (EPIC_CCSROFF + 0x011b0)/* Gbl TM A2 Dest */
|
||||
#define EPIC_TM_A3_VEC_REG (EPIC_CCSROFF + 0x011e0)/* Gbl TM A3 Vector Pri */
|
||||
#define EPIC_TM_A3_DES_REG (EPIC_CCSROFF + 0x011f0)/* Gbl TM A3 Dest. */
|
||||
|
||||
#define EPIC_IRQ_SUMM_REG0 (EPIC_CCSROFF + 0x01310)/* IRQ_OUT Summary 0 */
|
||||
#define EPIC_IRQ_SUMM_REG1 (EPIC_CCSROFF + 0x01320)/* IRQ_OUT Summary 1 */
|
||||
#define EPIC_CRIT_SUMM_REG0 (EPIC_CCSROFF + 0x01330)/* Crit Int Summary 0 */
|
||||
#define EPIC_CRIT_SUMM_REG1 (EPIC_CCSROFF + 0x01340)/* Crit Int Summary 1 */
|
||||
#define EPIC_PERFMON_0_MSK_REG0 (EPIC_CCSROFF + 0x01350)/* PerfMon 0 Mask 0 */
|
||||
#define EPIC_PERFMON_0_MSK_REG1 (EPIC_CCSROFF + 0x01360)/* PerfMon 0 Mask 1 */
|
||||
#define EPIC_PERFMON_1_MSK_REG0 (EPIC_CCSROFF + 0x01370)/* PerfMon 1 Mask 0 */
|
||||
#define EPIC_PERFMON_1_MSK_REG1 (EPIC_CCSROFF + 0x01380)/* PerfMon 1 Mask 1 */
|
||||
#define EPIC_PERFMON_2_MSK_REG0 (EPIC_CCSROFF + 0x01390)/* PerfMon 2 Mask 0 */
|
||||
#define EPIC_PERFMON_2_MSK_REG1 (EPIC_CCSROFF + 0x013a0)/* PerfMon 2 Mask 1 */
|
||||
#define EPIC_PERFMON_3_MSK_REG0 (EPIC_CCSROFF + 0x013b0)/* PerfMon 3 Mask 0 */
|
||||
#define EPIC_PERFMON_3_MSK_REG1 (EPIC_CCSROFF + 0x013c0)/* PerfMon 3 Mask 1 */
|
||||
#define EPIC_MSG_REG0 (EPIC_CCSROFF + 0x01400)/* Message 0 */
|
||||
#define EPIC_MSG_REG1 (EPIC_CCSROFF + 0x01410)/* Message 1 */
|
||||
#define EPIC_MSG_REG2 (EPIC_CCSROFF + 0x01420)/* Message 2 */
|
||||
#define EPIC_MSG_REG3 (EPIC_CCSROFF + 0x01430)/* Message 3 */
|
||||
#define EPIC_MSG_EN_REG_A (EPIC_CCSROFF + 0x01500)/* Message Enable */
|
||||
#define EPIC_MSG_EN_REG_B (EPIC_CCSROFF + 0x02500)/* Message Enable */
|
||||
#define EPIC_MSG_STATE_REG (EPIC_CCSROFF + 0x01510)/* Message Status */
|
||||
|
||||
/* Global Timer Group B registers */
|
||||
|
||||
#define EPIC_TM_B_FREQ_REG (EPIC_CCSROFF + 0x020f0)/* Timer B Frequency */
|
||||
|
||||
#define EPIC_TM_B0_VEC_REG (EPIC_CCSROFF + 0x02120)/* Gbl TM B0 Vector Pri */
|
||||
#define EPIC_TM_B0_DES_REG (EPIC_CCSROFF + 0x02130)/* Gbl TM B0 Dest. */
|
||||
#define EPIC_TM_B1_VEC_REG (EPIC_CCSROFF + 0x02160)/* Gbl TM B1 Vector Pri */
|
||||
#define EPIC_TM_B1_DES_REG (EPIC_CCSROFF + 0x02170)/* Gbl TM B1 Dest. */
|
||||
#define EPIC_TM_B2_VEC_REG (EPIC_CCSROFF + 0x021a0)/* Gbl TM B2 Vector Pri */
|
||||
#define EPIC_TM_B2_DES_REG (EPIC_CCSROFF + 0x021b0)/* Gbl TM B2 Dest */
|
||||
#define EPIC_TM_B3_VEC_REG (EPIC_CCSROFF + 0x021e0)/* Gbl TM B3 Vector Pri */
|
||||
#define EPIC_TM_B3_DES_REG (EPIC_CCSROFF + 0x021f0)/* Gbl TM B3 Dest. */
|
||||
|
||||
/* Shared message interrupt registers */
|
||||
#define EPIC_MSG_STATE_REG (EPIC_CCSROFF + 0x01510)/* Message Status */
|
||||
#define EPIC_MSIR_INT0_STATE_REG (EPIC_CCSROFF + 0x01600)/* interrupt status*/
|
||||
#define EPIC_MSIR_INTX_OFFSET 0x10
|
||||
|
||||
#define EPIC_MSISR_REG (EPIC_CCSROFF + 0x01720)/* interrupt set*/
|
||||
#define EPIC_MSIIR_REG (EPIC_CCSROFF + 0x01740)/* interrupt set*/
|
||||
|
||||
/* Interrupt Source Config */
|
||||
#define EPIC_EX_INT0_VEC_REG (EPIC_CCSROFF + 0x10000)/* Ext IRQ0 vect/prio*/
|
||||
#define EPIC_EX_INT0_DES_REG (EPIC_CCSROFF + 0x10010)/* Ext IRQ0 Dest */
|
||||
#define EPIC_EX_INT1_VEC_REG (EPIC_CCSROFF + 0x10020)/* Ext IRQ1 vect/prio*/
|
||||
#define EPIC_EX_INT1_DES_REG (EPIC_CCSROFF + 0x10030)/* Ext IRQ1 Dest */
|
||||
#define EPIC_EX_INT2_VEC_REG (EPIC_CCSROFF + 0x10040)/* Ext IRQ2 vect/prio*/
|
||||
#define EPIC_EX_INT2_DES_REG (EPIC_CCSROFF + 0x10050)/* Ext IRQ2 Dest */
|
||||
#define EPIC_EX_INT3_VEC_REG (EPIC_CCSROFF + 0x10060)/* Ext IRQ3 vect/prio*/
|
||||
#define EPIC_EX_INT3_DES_REG (EPIC_CCSROFF + 0x10070)/* Ext IRQ3 Dest */
|
||||
#define EPIC_EX_INT4_VEC_REG (EPIC_CCSROFF + 0x10080)/* Ext IRQ4 vect/prio*/
|
||||
#define EPIC_EX_INT4_DES_REG (EPIC_CCSROFF + 0x10090)/* Ext IRQ4 Dest */
|
||||
#define EPIC_EX_INT5_VEC_REG (EPIC_CCSROFF + 0x100a0)/* Ext IRQ5 vect/prio*/
|
||||
#define EPIC_EX_INT5_DES_REG (EPIC_CCSROFF + 0x100b0)/* Ext IRQ5 Dest */
|
||||
#define EPIC_EX_INT6_VEC_REG (EPIC_CCSROFF + 0x100c0)/* Ext IRQ6 vect/prio*/
|
||||
#define EPIC_EX_INT6_DES_REG (EPIC_CCSROFF + 0x100d0)/* Ext IRQ6 Dest */
|
||||
#define EPIC_EX_INT7_VEC_REG (EPIC_CCSROFF + 0x100e0)/* Ext IRQ7 vect/prio*/
|
||||
#define EPIC_EX_INT7_DES_REG (EPIC_CCSROFF + 0x100f0)/* Ext IRQ7 Dest */
|
||||
#define EPIC_EX_INT8_VEC_REG (EPIC_CCSROFF + 0x10100)/* Ext IRQ8 vect/prio*/
|
||||
#define EPIC_EX_INT8_DES_REG (EPIC_CCSROFF + 0x10110)/* Ext IRQ8 Dest */
|
||||
#define EPIC_EX_INT9_VEC_REG (EPIC_CCSROFF + 0x10120)/* Ext IRQ9 vect/prio*/
|
||||
#define EPIC_EX_INT9_DES_REG (EPIC_CCSROFF + 0x10130)/* Ext IRQ9 Dest */
|
||||
#define EPIC_EX_INT10_VEC_REG (EPIC_CCSROFF + 0x10140)/* Ext IRQ10 vect/pri*/
|
||||
#define EPIC_EX_INT10_DES_REG (EPIC_CCSROFF + 0x10150)/* Ext IRQ10 Dest */
|
||||
#define EPIC_EX_INT11_VEC_REG (EPIC_CCSROFF + 0x10160)/* Ext IRQ11 vect/pri*/
|
||||
#define EPIC_EX_INT11_DES_REG (EPIC_CCSROFF + 0x10170)/* Ext IRQ11 Dest */
|
||||
|
||||
#define EPIC_IN_INT0_VEC_REG (EPIC_CCSROFF + 0x10200)/* Int IRQ0 vect/prio*/
|
||||
#define EPIC_IN_INT0_DES_REG (EPIC_CCSROFF + 0x10210)/* Int IRQ0 Dest */
|
||||
#define EPIC_IN_INT1_VEC_REG (EPIC_CCSROFF + 0x10220)/* Int IRQ1 vect/prio*/
|
||||
#define EPIC_IN_INT1_DES_REG (EPIC_CCSROFF + 0x10230)/* Int IRQ1 Dest */
|
||||
#define EPIC_IN_INT2_VEC_REG (EPIC_CCSROFF + 0x10240)/* Int IRQ2 vect/prio*/
|
||||
#define EPIC_IN_INT2_DES_REG (EPIC_CCSROFF + 0x10250)/* Int IRQ2 Dest */
|
||||
#define EPIC_IN_INT3_VEC_REG (EPIC_CCSROFF + 0x10260)/* Int IRQ3 vect/prio*/
|
||||
#define EPIC_IN_INT3_DES_REG (EPIC_CCSROFF + 0x10270)/* Int IRQ3 Dest */
|
||||
#define EPIC_IN_INT4_VEC_REG (EPIC_CCSROFF + 0x10280)/* Int IRQ4 vect/prio*/
|
||||
#define EPIC_IN_INT4_DES_REG (EPIC_CCSROFF + 0x10290)/* Int IRQ4 Dest */
|
||||
#define EPIC_IN_INT5_VEC_REG (EPIC_CCSROFF + 0x102a0)/* Int IRQ5 vect/prio*/
|
||||
#define EPIC_IN_INT5_DES_REG (EPIC_CCSROFF + 0x102b0)/* Int IRQ5 Dest */
|
||||
#define EPIC_IN_INT6_VEC_REG (EPIC_CCSROFF + 0x102c0)/* Int IRQ6 vect/prio*/
|
||||
#define EPIC_IN_INT6_DES_REG (EPIC_CCSROFF + 0x102d0)/* Int IRQ6 Dest */
|
||||
#define EPIC_IN_INT7_VEC_REG (EPIC_CCSROFF + 0x102e0)/* Int IRQ7 vect/prio*/
|
||||
#define EPIC_IN_INT7_DES_REG (EPIC_CCSROFF + 0x102f0)/* Int IRQ7 Dest */
|
||||
#define EPIC_IN_INT8_VEC_REG (EPIC_CCSROFF + 0x10300)/* Int IRQ8 vect/prio*/
|
||||
#define EPIC_IN_INT8_DES_REG (EPIC_CCSROFF + 0x10310)/* Int IRQ8 Dest */
|
||||
#define EPIC_IN_INT9_VEC_REG (EPIC_CCSROFF + 0x10320)/* Int IRQ9 vect/prio*/
|
||||
#define EPIC_IN_INT9_DES_REG (EPIC_CCSROFF + 0x10330)/* Int IRQ9 Dest */
|
||||
#define EPIC_IN_INT10_VEC_REG (EPIC_CCSROFF + 0x10340)/* Int IRQ10 vect/pri*/
|
||||
#define EPIC_IN_INT10_DES_REG (EPIC_CCSROFF + 0x10350)/* Int IRQ10 Dest */
|
||||
#define EPIC_IN_INT11_VEC_REG (EPIC_CCSROFF + 0x10360)/* Int IRQ11 vect/pri*/
|
||||
#define EPIC_IN_INT11_DES_REG (EPIC_CCSROFF + 0x10370)/* Int IRQ11 Dest */
|
||||
#define EPIC_IN_INT12_VEC_REG (EPIC_CCSROFF + 0x10380)/* Int IRQ12 vect/pri*/
|
||||
#define EPIC_IN_INT12_DES_REG (EPIC_CCSROFF + 0x10390)/* Int IRQ12 Dest */
|
||||
#define EPIC_IN_INT13_VEC_REG (EPIC_CCSROFF + 0x103a0)/* Int IRQ13 vect/pri*/
|
||||
#define EPIC_IN_INT13_DES_REG (EPIC_CCSROFF + 0x103b0)/* Int IRQ13 Dest */
|
||||
#define EPIC_IN_INT14_VEC_REG (EPIC_CCSROFF + 0x103c0)/* Int IRQ14 vect/pri*/
|
||||
#define EPIC_IN_INT14_DES_REG (EPIC_CCSROFF + 0x103d0)/* Int IRQ14 Dest */
|
||||
#define EPIC_IN_INT15_VEC_REG (EPIC_CCSROFF + 0x103e0)/* Int IRQ15 vect/pri*/
|
||||
#define EPIC_IN_INT15_DES_REG (EPIC_CCSROFF + 0x103f0)/* Int IRQ15 Dest */
|
||||
#define EPIC_IN_INT16_VEC_REG (EPIC_CCSROFF + 0x10400)/* Int IRQ16 vect/pri*/
|
||||
#define EPIC_IN_INT16_DES_REG (EPIC_CCSROFF + 0x10410)/* Int IRQ16 Dest */
|
||||
#define EPIC_IN_INT17_VEC_REG (EPIC_CCSROFF + 0x10420)/* Int IRQ17 vect/pri*/
|
||||
#define EPIC_IN_INT17_DES_REG (EPIC_CCSROFF + 0x10430)/* Int IRQ17 Dest */
|
||||
#define EPIC_IN_INT18_VEC_REG (EPIC_CCSROFF + 0x10440)/* Int IRQ18 vect/pri*/
|
||||
#define EPIC_IN_INT18_DES_REG (EPIC_CCSROFF + 0x10450)/* Int IRQ18 Dest */
|
||||
#define EPIC_IN_INT19_VEC_REG (EPIC_CCSROFF + 0x10460)/* Int IRQ19 vect/pri*/
|
||||
#define EPIC_IN_INT19_DES_REG (EPIC_CCSROFF + 0x10470)/* Int IRQ19 Dest */
|
||||
#define EPIC_IN_INT20_VEC_REG (EPIC_CCSROFF + 0x10480)/* Int IRQ20 vect/pri*/
|
||||
#define EPIC_IN_INT20_DES_REG (EPIC_CCSROFF + 0x10490)/* Int IRQ20 Dest */
|
||||
#define EPIC_IN_INT21_VEC_REG (EPIC_CCSROFF + 0x104a0)/* Int IRQ21 vect/pri*/
|
||||
#define EPIC_IN_INT21_DES_REG (EPIC_CCSROFF + 0x104b0)/* Int IRQ21 Dest */
|
||||
#define EPIC_IN_INT22_VEC_REG (EPIC_CCSROFF + 0x104c0)/* Int IRQ22 vect/pri*/
|
||||
#define EPIC_IN_INT22_DES_REG (EPIC_CCSROFF + 0x104d0)/* Int IRQ22 Dest */
|
||||
#define EPIC_IN_INT23_VEC_REG (EPIC_CCSROFF + 0x104e0)/* Int IRQ23 vect/pri*/
|
||||
#define EPIC_IN_INT23_DES_REG (EPIC_CCSROFF + 0x104f0)/* Int IRQ23 Dest */
|
||||
#define EPIC_IN_INT24_VEC_REG (EPIC_CCSROFF + 0x10500)/* Int IRQ24 vect/pri*/
|
||||
#define EPIC_IN_INT24_DES_REG (EPIC_CCSROFF + 0x10510)/* Int IRQ24 Dest */
|
||||
#define EPIC_IN_INT25_VEC_REG (EPIC_CCSROFF + 0x10520)/* Int IRQ25 vect/pri*/
|
||||
#define EPIC_IN_INT25_DES_REG (EPIC_CCSROFF + 0x10530)/* Int IRQ25 Dest */
|
||||
#define EPIC_IN_INT26_VEC_REG (EPIC_CCSROFF + 0x10540)/* Int IRQ26 vect/pri*/
|
||||
#define EPIC_IN_INT26_DES_REG (EPIC_CCSROFF + 0x10550)/* Int IRQ26 Dest */
|
||||
#define EPIC_IN_INT27_VEC_REG (EPIC_CCSROFF + 0x10560)/* Int IRQ27 vect/pri*/
|
||||
#define EPIC_IN_INT27_DES_REG (EPIC_CCSROFF + 0x10570)/* Int IRQ27 Dest */
|
||||
#define EPIC_IN_INT28_VEC_REG (EPIC_CCSROFF + 0x10580)/* Int IRQ28 vect/pri*/
|
||||
#define EPIC_IN_INT28_DES_REG (EPIC_CCSROFF + 0x10590)/* Int IRQ28 Dest */
|
||||
#define EPIC_IN_INT29_VEC_REG (EPIC_CCSROFF + 0x105a0)/* Int IRQ29 vect/pri*/
|
||||
#define EPIC_IN_INT29_DES_REG (EPIC_CCSROFF + 0x105b0)/* Int IRQ29 Dest */
|
||||
#define EPIC_IN_INT30_VEC_REG (EPIC_CCSROFF + 0x105c0)/* Int IRQ30 vect/pri*/
|
||||
#define EPIC_IN_INT30_DES_REG (EPIC_CCSROFF + 0x105d0)/* Int IRQ30 Dest */
|
||||
#define EPIC_IN_INT31_VEC_REG (EPIC_CCSROFF + 0x105e0)/* Int IRQ31 vect/pri*/
|
||||
#define EPIC_IN_INT31_DES_REG (EPIC_CCSROFF + 0x105f0)/* Int IRQ31 Dest */
|
||||
#define EPIC_IN_INT32_VEC_REG (EPIC_CCSROFF + 0x10600)/* Int IRQ32 vect/pri*/
|
||||
#define EPIC_IN_INT32_DES_REG (EPIC_CCSROFF + 0x10610)/* Int IRQ32 Dest */
|
||||
#define EPIC_IN_INT33_VEC_REG (EPIC_CCSROFF + 0x10620)/* Int IRQ33 vect/pri*/
|
||||
#define EPIC_IN_INT33_DES_REG (EPIC_CCSROFF + 0x10630)/* Int IRQ33 Dest */
|
||||
#define EPIC_IN_INT34_VEC_REG (EPIC_CCSROFF + 0x10640)/* Int IRQ34 vect/pri*/
|
||||
#define EPIC_IN_INT34_DES_REG (EPIC_CCSROFF + 0x10650)/* Int IRQ34 Dest */
|
||||
#define EPIC_IN_INT35_VEC_REG (EPIC_CCSROFF + 0x10660)/* Int IRQ35 vect/pri*/
|
||||
#define EPIC_IN_INT35_DES_REG (EPIC_CCSROFF + 0x10670)/* Int IRQ35 Dest */
|
||||
#define EPIC_IN_INT36_VEC_REG (EPIC_CCSROFF + 0x10680)/* Int IRQ36 vect/pri*/
|
||||
#define EPIC_IN_INT36_DES_REG (EPIC_CCSROFF + 0x10690)/* Int IRQ36 Dest */
|
||||
#define EPIC_IN_INT37_VEC_REG (EPIC_CCSROFF + 0x106a0)/* Int IRQ37 vect/pri*/
|
||||
#define EPIC_IN_INT37_DES_REG (EPIC_CCSROFF + 0x106b0)/* Int IRQ37 Dest */
|
||||
#define EPIC_IN_INT38_VEC_REG (EPIC_CCSROFF + 0x106c0)/* Int IRQ38 vect/pri*/
|
||||
#define EPIC_IN_INT38_DES_REG (EPIC_CCSROFF + 0x106d0)/* Int IRQ38 Dest */
|
||||
#define EPIC_IN_INT39_VEC_REG (EPIC_CCSROFF + 0x106e0)/* Int IRQ39 vect/pri*/
|
||||
#define EPIC_IN_INT39_DES_REG (EPIC_CCSROFF + 0x106f0)/* Int IRQ39 Dest */
|
||||
#define EPIC_IN_INT40_VEC_REG (EPIC_CCSROFF + 0x10700)/* Int IRQ40 vect/pri*/
|
||||
#define EPIC_IN_INT40_DES_REG (EPIC_CCSROFF + 0x10710)/* Int IRQ40 Dest */
|
||||
#define EPIC_IN_INT41_VEC_REG (EPIC_CCSROFF + 0x10720)/* Int IRQ41 vect/pri*/
|
||||
#define EPIC_IN_INT41_DES_REG (EPIC_CCSROFF + 0x10730)/* Int IRQ41 Dest */
|
||||
#define EPIC_IN_INT42_VEC_REG (EPIC_CCSROFF + 0x10740)/* Int IRQ42 vect/pri*/
|
||||
#define EPIC_IN_INT42_DES_REG (EPIC_CCSROFF + 0x10750)/* Int IRQ42 Dest */
|
||||
#define EPIC_IN_INT43_VEC_REG (EPIC_CCSROFF + 0x10760)/* Int IRQ43 vect/pri*/
|
||||
#define EPIC_IN_INT43_DES_REG (EPIC_CCSROFF + 0x10770)/* Int IRQ43 Dest */
|
||||
#define EPIC_IN_INT44_VEC_REG (EPIC_CCSROFF + 0x10780)/* Int IRQ44 vect/pri*/
|
||||
#define EPIC_IN_INT44_DES_REG (EPIC_CCSROFF + 0x10790)/* Int IRQ44 Dest */
|
||||
#define EPIC_IN_INT45_VEC_REG (EPIC_CCSROFF + 0x107a0)/* Int IRQ45 vect/pri*/
|
||||
#define EPIC_IN_INT45_DES_REG (EPIC_CCSROFF + 0x107b0)/* Int IRQ45 Dest */
|
||||
#define EPIC_IN_INT46_VEC_REG (EPIC_CCSROFF + 0x107c0)/* Int IRQ46 vect/pri*/
|
||||
#define EPIC_IN_INT46_DES_REG (EPIC_CCSROFF + 0x107d0)/* Int IRQ46 Dest */
|
||||
#define EPIC_IN_INT47_VEC_REG (EPIC_CCSROFF + 0x107e0)/* Int IRQ47 vect/pri*/
|
||||
#define EPIC_IN_INT47_DES_REG (EPIC_CCSROFF + 0x107f0)/* Int IRQ48 Dest */
|
||||
|
||||
#define EPIC_MSG_INT0_VEC_REG (EPIC_CCSROFF + 0x11600)/* MSG INT0 vect/prio*/
|
||||
#define EPIC_MSG_INT0_DES_REG (EPIC_CCSROFF + 0x11610)/* MSG INT0 Dest */
|
||||
#define EPIC_MSG_INT1_VEC_REG (EPIC_CCSROFF + 0x11620)/* MSG INT1 vect/prio*/
|
||||
#define EPIC_MSG_INT1_DES_REG (EPIC_CCSROFF + 0x11630)/* MSG INT1 Dest */
|
||||
#define EPIC_MSG_INT2_VEC_REG (EPIC_CCSROFF + 0x11640)/* MSG INT2 vect/prio*/
|
||||
#define EPIC_MSG_INT2_DES_REG (EPIC_CCSROFF + 0x11650)/* MSG INT2 Dest */
|
||||
#define EPIC_MSG_INT3_VEC_REG (EPIC_CCSROFF + 0x11660)/* MSG INT3 vect/prio*/
|
||||
#define EPIC_MSG_INT3_DES_REG (EPIC_CCSROFF + 0x11670)/* MSG INT3 Dest */
|
||||
|
||||
#define EPIC_SMSG_INT0_VEC_REG (EPIC_CCSROFF + 0x11c00)/* MSG INT0 vect/prio*/
|
||||
#define EPIC_SMSG_INT0_DES_REG (EPIC_CCSROFF + 0x11c10)/* MSG INT0 Dest */
|
||||
#define EPIC_SMSG_INT1_VEC_REG (EPIC_CCSROFF + 0x11c20)/* MSG INT1 vect/prio*/
|
||||
#define EPIC_SMSG_INT1_DES_REG (EPIC_CCSROFF + 0x11c30)/* MSG INT1 Dest */
|
||||
#define EPIC_SMSG_INT2_VEC_REG (EPIC_CCSROFF + 0x11c40)/* MSG INT2 vect/prio*/
|
||||
#define EPIC_SMSG_INT2_DES_REG (EPIC_CCSROFF + 0x11c50)/* MSG INT2 Dest */
|
||||
#define EPIC_SMSG_INT3_VEC_REG (EPIC_CCSROFF + 0x11c60)/* MSG INT3 vect/prio*/
|
||||
#define EPIC_SMSG_INT3_DES_REG (EPIC_CCSROFF + 0x11c70)/* MSG INT3 Dest */
|
||||
|
||||
#define EPIC_SMSG_INT4_VEC_REG (EPIC_CCSROFF + 0x11c80)/* MSG INT4 vect/prio*/
|
||||
#define EPIC_SMSG_INT4_DES_REG (EPIC_CCSROFF + 0x11c90)/* MSG INT4 Dest */
|
||||
#define EPIC_SMSG_INT5_VEC_REG (EPIC_CCSROFF + 0x11ca0)/* MSG INT5 vect/prio*/
|
||||
#define EPIC_SMSG_INT5_DES_REG (EPIC_CCSROFF + 0x11cb0)/* MSG INT5 Dest */
|
||||
#define EPIC_SMSG_INT6_VEC_REG (EPIC_CCSROFF + 0x11cc0)/* MSG INT6 vect/prio*/
|
||||
#define EPIC_SMSG_INT6_DES_REG (EPIC_CCSROFF + 0x11cd0)/* MSG INT6 Dest */
|
||||
#define EPIC_SMSG_INT7_VEC_REG (EPIC_CCSROFF + 0x11ce0)/* MSG INT7 vect/prio*/
|
||||
#define EPIC_SMSG_INT7_DES_REG (EPIC_CCSROFF + 0x11cf0)/* MSG INT7 Dest */
|
||||
|
||||
/* Private Access Registers (CPU0) */
|
||||
#define EPIC_IPI_DPATCH0_REG0 (EPIC_CCSROFF + 0x20040)/* IPI0 dispatch */
|
||||
#define EPIC_IPI_DPATCH0_REG1 (EPIC_CCSROFF + 0x20050)/* IPI1 dispatch */
|
||||
#define EPIC_IPI_DPATCH0_REG2 (EPIC_CCSROFF + 0x20060)/* IPI2 dispatch */
|
||||
#define EPIC_IPI_DPATCH0_REG3 (EPIC_CCSROFF + 0x20070)/* IPI3 dispatch */
|
||||
#define EPIC_CTASK_PRI0_REG (EPIC_CCSROFF + 0x20080)/* Cur Task Prio */
|
||||
#define EPIC_WHO_AM_I0_REG (EPIC_CCSROFF + 0x20090)/* Who am I */
|
||||
#define EPIC_INT_ACK0_REG (EPIC_CCSROFF + 0x200a0)/* Int ack */
|
||||
#define EPIC_EOI0_REG (EPIC_CCSROFF + 0x200b0)/* End of Int */
|
||||
|
||||
/* Private Access Registers (CPU1) */
|
||||
#define EPIC_IPI_DPATCH1_REG0 (EPIC_CCSROFF + 0x21040)/* IPI0 dispatch */
|
||||
#define EPIC_IPI_DPATCH1_REG1 (EPIC_CCSROFF + 0x21050)/* IPI1 dispatch */
|
||||
#define EPIC_IPI_DPATCH1_REG2 (EPIC_CCSROFF + 0x21060)/* IPI2 dispatch */
|
||||
#define EPIC_IPI_DPATCH1_REG3 (EPIC_CCSROFF + 0x21070)/* IPI3 dispatch */
|
||||
#define EPIC_CTASK_PRI1_REG (EPIC_CCSROFF + 0x21080)/* Cur Task Prio */
|
||||
#define EPIC_WHO_AM_I1_REG (EPIC_CCSROFF + 0x21090)/* Who am I */
|
||||
#define EPIC_INT_ACK1_REG (EPIC_CCSROFF + 0x210a0)/* Int ack */
|
||||
#define EPIC_EOI1_REG (EPIC_CCSROFF + 0x210b0)/* End of Int */
|
||||
|
||||
#define EPIC_EX_VEC_REG_INTERVAL 0x20 /* ex vector regs distance */
|
||||
#define EPIC_IN_VEC_REG_INTERVAL 0x20 /* in vector regs distance */
|
||||
#define EPIC_GT_VEC_REG_INTERVAL 0x40 /* tm vector regs distance */
|
||||
#define EPIC_MSG_VEC_REG_INTERVAL 0x20 /* msg vector regs distance */
|
||||
#define EPIC_SMSG_VEC_REG_INTERVAL 0x20 /* shared msg vector regs distance */
|
||||
#define EPIC_IPI_VEC_REG_INTERVAL 0x10 /* ipi vector regs distance */
|
||||
|
||||
#define EPIC_EX_DEST_REG_VECREGOFF 0x10 /* EIDR offset from vec reg */
|
||||
#define EPIC_IN_DEST_REG_VECREGOFF 0x10 /* IIDR offset from vec reg */
|
||||
#define EPIC_MSG_DEST_REG_VECREGOFF 0x10 /* MIDR offset from vec reg */
|
||||
#define EPIC_SMSG_DEST_REG_VECREGOFF 0x10 /* MSIDR offset from vec reg */
|
||||
#define EPIC_IILR_REG_DESTREGOFF 0x08 /* IILR offset from dest reg(IIDR) */
|
||||
|
||||
#define EPIC_EX_VEC_REG(irq) (EPIC_EX_INT0_VEC_REG + \
|
||||
((irq) * EPIC_EX_VEC_REG_INTERVAL))
|
||||
|
||||
#define EPIC_IN_VEC_REG(irq) (EPIC_IN_INT0_VEC_REG + \
|
||||
((irq) * EPIC_IN_VEC_REG_INTERVAL))
|
||||
|
||||
#define EPIC_GT_A_VEC_REG(irq) (EPIC_TM_A0_VEC_REG + \
|
||||
((irq) * EPIC_GT_VEC_REG_INTERVAL))
|
||||
|
||||
#define EPIC_GT_B_VEC_REG(irq) (EPIC_TM_B0_VEC_REG + \
|
||||
((irq) * EPIC_GT_VEC_REG_INTERVAL))
|
||||
|
||||
#define EPIC_MSG_VEC_REG(irq) (EPIC_MSG_INT0_VEC_REG + \
|
||||
((irq) * EPIC_MSG_VEC_REG_INTERVAL))
|
||||
#define EPIC_SMSG_VEC_REG(irq) (EPIC_SMSG_INT0_VEC_REG + \
|
||||
((irq) * EPIC_SMSG_VEC_REG_INTERVAL))
|
||||
|
||||
#define EPIC_IPI_VEC_REG(irq) (EPIC_IPI_0_VEC_REG + \
|
||||
((irq) * EPIC_IPI_VEC_REG_INTERVAL))
|
||||
|
||||
#define EPIC_EX_DEST_REG(irq) (EPIC_EX_VEC_REG(irq) + \
|
||||
EPIC_EX_DEST_REG_VECREGOFF)
|
||||
#define EPIC_IN_DEST_REG(irq) (EPIC_IN_VEC_REG(irq) + \
|
||||
EPIC_IN_DEST_REG_VECREGOFF)
|
||||
#define EPIC_MSG_DEST_REG(irq) (EPIC_MSG_VEC_REG(irq) + \
|
||||
EPIC_MSG_DEST_REG_VECREGOFF)
|
||||
|
||||
#define EPIC_SMSG_DEST_REG(irq) (EPIC_SMSG_VEC_REG(irq) + \
|
||||
EPIC_SMSG_DEST_REG_VECREGOFF)
|
||||
|
||||
#define EPIC_IILR_REG(dest) ((dest) + EPIC_IILR_REG_DESTREGOFF)
|
||||
|
||||
/* GCR register */
|
||||
|
||||
#define EPIC_GCR_RESET EPIC_BIT(31)
|
||||
#define EPIC_GCR_MODE_MIXED EPIC_BIT(29)
|
||||
#define EPIC_GCR_MODE_EPF (EPIC_BIT(29) | EPIC_BIT(30))
|
||||
|
||||
/* IPI Vector/Priority registers */
|
||||
|
||||
#define EPIC_IPIVPR_INTR_MSK EPIC_BIT(31)
|
||||
#define EPIC_IPIVPR_INTR_ACTIVE EPIC_BIT(30)
|
||||
#define EPIC_IPIVPR_PRIORITY_MSK (EPIC_BIT(19) | EPIC_BIT(18) | EPIC_BIT(17) | EPIC_BIT(16))
|
||||
#define EPIC_IPIVPR_PRIORITY(p) (((p) << 16) & EPIC_IPIVPR_PRIORITY_MSK)
|
||||
#define EPIC_IPIVPR_PRIORITY_GET(p) (((p) & EPIC_IPIVPR_PRIORITY_MSK) >> 16)
|
||||
#define EPIC_IPIVPR_VECTOR_MSK (0xffff)
|
||||
#define EPIC_IPIVPR_VECTOR(vec) ((vec) & EPIC_IPIVPR_VECTOR_MSK)
|
||||
|
||||
/* Global Timer Vector/Priority registers */
|
||||
|
||||
#define EPIC_GTVPR_INTR_MSK EPIC_BIT(31)
|
||||
#define EPIC_GTVPR_INTR_ACTIVE EPIC_BIT(30)
|
||||
#define EPIC_GTVPR_PRIORITY_MSK (EPIC_BIT(19) | EPIC_BIT(18) | EPIC_BIT(17) | EPIC_BIT(16))
|
||||
#define EPIC_GTVPR_PRIORITY(p) (((p) << 16) & EPIC_GTVPR_PRIORITY_MSK)
|
||||
#define EPIC_GTVPR_VECTOR_MSK (0xffff)
|
||||
#define EPIC_GTVPR_VECTOR(vec) ((vec) & EPIC_GTVPR_VECTOR_MSK)
|
||||
|
||||
/* Summary registers */
|
||||
|
||||
#define EPIC_IRQSR0_MSG_INT_MSK 0xf000
|
||||
#define EPIC_IRQSR0_MSG_INT(n) (EPIC_BIT(15-(n)) & EPIC_IRQSR0_MSG_INT_MSK)
|
||||
#define EPIC_IRQSR0_EX_INT_MSK 0xfff
|
||||
#define EPIC_IRQSR0_EX_INT(n) (EPIC_BIT(11-(n)) & EPIC_IRQSR0_EX_INT_MSK)
|
||||
#define EPIC_IRQSR1_IN_INT(n) EPIC_BIT(31-(n))
|
||||
#define EPIC_CISR0_MSG_INT_MSK 0xf000
|
||||
#define EPIC_CISR0_MSG_INT(n) (EPIC_BIT(15-(n)) & EPIC_CISR0_MSG_INT_MSK)
|
||||
#define EPIC_CISR0_EX_INT_MSK 0xfff
|
||||
#define EPIC_CISR0_EX_INT(n) (EPIC_BIT(11-(n)) & EPIC_CISR0_EX_INT_MSK)
|
||||
#define EPIC_CISR1_IN_INT(n) EPIC_BIT(31-(n))
|
||||
|
||||
/* Message registers */
|
||||
|
||||
#define EPIC_MER_EN_MSK 0xf
|
||||
#define EPIC_MER_EN(n) (EPIC_BIT(n) & EPIC_MER_EN_MSK)
|
||||
#define EPIC_MSR_ST_MSK 0xf
|
||||
#define EPIC_MSR_ST(n) (EPIC_BIT(n) & EPIC_MER_ST_MSK)
|
||||
|
||||
/* EIVPR registers */
|
||||
|
||||
#define EPIC_EIVPR_INTR_MSK EPIC_BIT(31)
|
||||
#define EPIC_EIVPR_INTR_ACTIVE EPIC_BIT(30)
|
||||
#define EPIC_EIVPR_INTR_POLARITY EPIC_BIT(23)
|
||||
#define EPIC_EIVPR_INTR_SENSE EPIC_BIT(22)
|
||||
#define EPIC_EIVPR_POLARITY(p) ((p) << 23)
|
||||
#define EPIC_EIVPR_SENS(s) ((s) << 22)
|
||||
#define EPIC_EIVPR_PRIORITY_MSK (EPIC_BIT(19) | EPIC_BIT(18) | EPIC_BIT(17) | EPIC_BIT(16))
|
||||
#define EPIC_EIVPR_PRIORITY(p) (((p) << 16) & EPIC_EIVPR_PRIORITY_MSK)
|
||||
#define EPIC_EIVPR_VECTOR_MSK (0xffff)
|
||||
#define EPIC_EIVPR_VECTOR(vec) ((vec) & EPIC_EIVPR_VECTOR_MSK)
|
||||
#define EPIC_INT_ACT_LOW 0
|
||||
#define EPIC_INT_ACT_HIGH 1
|
||||
#define EPIC_INT_EDG_NEG 0
|
||||
#define EPIC_INT_EDG_POS 1
|
||||
#define EPIC_SENSE_LVL 1
|
||||
#define EPIC_SENSE_EDG 0
|
||||
|
||||
/* EIDR registers */
|
||||
|
||||
#define EPIC_EIDR_EX_PIN EPIC_BIT(31)
|
||||
#define EPIC_EIDR_CRIT_INT EPIC_BIT(30)
|
||||
#define EPIC_EIDR_CRIT0_INT EPIC_BIT(30)
|
||||
#define EPIC_EIDR_CRIT1_INT EPIC_BIT(29)
|
||||
#define EPIC_EIDR_P1_INT EPIC_BIT(1)
|
||||
#define EPIC_EIDR_P0_INT EPIC_BIT(0)
|
||||
|
||||
/* Options for *VPR and *IDR registers */
|
||||
|
||||
#define EPIC_OPT_EN_MSK EPIC_EIVPR_INTR_MSK
|
||||
#define EPIC_OPT_EN_Y 0x00000000
|
||||
#define EPIC_OPT_EN_N 0x80000000
|
||||
#define EPIC_OPT_POLAR_MSK EPIC_EIVPR_INTR_POLARITY
|
||||
#define EPIC_OPT_POLAR_ACT_LOW 0x00000000
|
||||
#define EPIC_OPT_POLAR_ACT_HIGH 0x00800000
|
||||
#define EPIC_OPT_POLAR_EDG_NEG 0x00000000
|
||||
#define EPIC_OPT_POLAR_EDG_POS 0x00800000
|
||||
#define EPIC_OPT_SENSE_MSK EPIC_EIVPR_INTR_SENSE
|
||||
#define EPIC_OPT_SENSE_EDG 0x00000000
|
||||
#define EPIC_OPT_SENSE_LVL 0x00400000
|
||||
#define EPIC_OPT_PRI_MSK EPIC_EIVPR_PRIORITY_MSK
|
||||
#define EPIC_OPT_PRI_VALUE(p) EPIC_EIVPR_PRIORITY(p)
|
||||
#define EPIC_OPT_EXPIN_MSK (EPIC_EIDR_EX_PIN >> 16)
|
||||
#define EPIC_OPT_EXPIN_OFF (0x00000000 >> 16)
|
||||
#define EPIC_OPT_EXPIN_ON (0x80000000 >> 16)
|
||||
#define EPIC_OPT_CRIT_MSK (EPIC_EIDR_CRIT_INT >> 16)
|
||||
#define EPIC_OPT_CRIT_OFF (0x00000000 >> 16)
|
||||
#define EPIC_OPT_CRIT_ON (0x40000000 >> 16)
|
||||
|
||||
/* IIVPR registers */
|
||||
|
||||
#define EPIC_IIVPR_INTR_MSK EPIC_BIT(31)
|
||||
#define EPIC_IIVPR_INTR_ACTIVE EPIC_BIT(30)
|
||||
#define EPIC_IIVPR_INTR_POLARITY EPIC_BIT(23)
|
||||
#define EPIC_IIVPR_POLARITY(p) ((p) << 23)
|
||||
#define EPIC_IIVPR_PRIORITY_MSK (EPIC_BIT(19) | EPIC_BIT(18) | EPIC_BIT(17) | EPIC_BIT(16))
|
||||
#define EPIC_IIVPR_PRIORITY(p) (((p) << 16) & EPIC_IIVPR_PRIORITY_MSK)
|
||||
#define EPIC_IIVPR_VECTOR_MSK (0xffff)
|
||||
#define EPIC_IIVPR_VECTOR(vec) ((vec) & EPIC_IIVPR_VECTOR_MSK)
|
||||
|
||||
/* IIDR registers */
|
||||
|
||||
#define EPIC_IIDR_EX_PIN EPIC_BIT(31)
|
||||
#define EPIC_IIDR_CRIT_INT EPIC_BIT(30)
|
||||
#define EPIC_IIDR_CRIT0_INT EPIC_BIT(30)
|
||||
#define EPIC_IIDR_CRIT1_INT EPIC_BIT(29)
|
||||
#define EPIC_IIDR_P1_INT EPIC_BIT(1)
|
||||
#define EPIC_IIDR_P0_INT EPIC_BIT(0)
|
||||
|
||||
/* EPIC Critical interrupt summary registers */
|
||||
|
||||
#define EPIC_441_CISR0 (EPIC_CCSROFF + 0x3B00)
|
||||
#define EPIC_441_CISR1 (EPIC_CCSROFF + 0x3B40)
|
||||
#define EPIC_441_CISR_ADDR(n) (EPIC_441_CISR1 + n*0x10)
|
||||
|
||||
#define EPIC_431_CISR0 (EPIC_CCSROFF + 0x1330)
|
||||
#define EPIC_431_CISR1 (EPIC_CCSROFF + 0x1340)
|
||||
#define EPIC_431_CISR2 (EPIC_CCSROFF + 0x1344)
|
||||
|
||||
#define EPIC_431_CISR_ADDR(n) (EPIC_431_CISR1 + n*0x4)
|
||||
|
||||
#define EPIC_CISR0_EXT_MASK 0xfff
|
||||
#define EPIC_441_CISR0_EXT_SHIFT 20
|
||||
|
||||
/* IRQn level register register defines */
|
||||
|
||||
#define EPIC_CINT 0x01
|
||||
#define EPIC_CPU0_CINT_SHIFT 30
|
||||
|
||||
/* Freescale MPIC version number */
|
||||
|
||||
#define FSL_EPIC_400 0x400000
|
||||
#define FSL_EPIC_431 0x400301
|
||||
#define FSL_EPIC_441 0x400401
|
||||
|
||||
/* MIVPR registers */
|
||||
|
||||
#define EPIC_MIVPR_INTR_MSK EPIC_BIT(31)
|
||||
#define EPIC_MIVPR_INTR_ACTIVE EPIC_BIT(30)
|
||||
#define EPIC_MIVPR_PRIORITY_MSK (EPIC_BIT(19) | EPIC_BIT(18) | EPIC_BIT(17) | EPIC_BIT(16))
|
||||
#define EPIC_MIVPR_PRIORITY(p) (((p) << 16) & EPIC_MIVPR_PRIORITY_MSK)
|
||||
#define EPIC_MIVPR_VECTOR_MSK (0xffff)
|
||||
#define EPIC_MIVPR_VECTOR(vec) ((vec) & EPIC_MIVPR_VECTOR_MSK)
|
||||
|
||||
/* MSIVPR registers */
|
||||
|
||||
#define EPIC_MSIVPR_INTR_MSK EPIC_BIT(31)
|
||||
#define EPIC_MSIVPR_INTR_ACTIVE EPIC_BIT(30)
|
||||
#define EPIC_MSIVPR_PRIORITY_MSK (EPIC_BIT(19) | EPIC_BIT(18) | EPIC_BIT(17) | EPIC_BIT(16))
|
||||
#define EPIC_MSIVPR_PRIORITY(p) (((p) << 16) & EPIC_MSIVPR_PRIORITY_MSK)
|
||||
#define EPIC_MSIVPR_VECTOR_MSK (0xffff)
|
||||
#define EPIC_MSIVPR_VECTOR(vec) ((vec) & EPIC_MSIVPR_VECTOR_MSK)
|
||||
|
||||
/* MIDR registers */
|
||||
|
||||
#define EPIC_MIDR_EX_PIN EPIC_BIT(31)
|
||||
#define EPIC_MIDR_CRIT_INT EPIC_BIT(30)
|
||||
#define EPIC_MIDR_CRIT0_INT EPIC_BIT(30)
|
||||
#define EPIC_MIDR_CRIT1_INT EPIC_BIT(29)
|
||||
#define EPIC_MIDR_P1_INT EPIC_BIT(1)
|
||||
#define EPIC_MIDR_P0_INT EPIC_BIT(0)
|
||||
|
||||
/* MSIDR registers */
|
||||
|
||||
#define EPIC_MSIDR_EX_PIN EPIC_BIT(31)
|
||||
#define EPIC_MSIDR_CRIT_INT EPIC_BIT(30)
|
||||
#define EPIC_MSIDR_CRIT0_INT EPIC_BIT(30)
|
||||
#define EPIC_MSIDR_CRIT1_INT EPIC_BIT(29)
|
||||
#define EPIC_MSIDR_P1_INT EPIC_BIT(1)
|
||||
#define EPIC_MSIDR_P0_INT EPIC_BIT(0)
|
||||
|
||||
/* IPIDR registers */
|
||||
|
||||
#define EPIC_IPIDR_P0 EPIC_BIT(0)
|
||||
#define EPIC_IPIDR_P1 EPIC_BIT(1)
|
||||
|
||||
/* CTPR register */
|
||||
|
||||
#define EPIC_CTPR_TASKPRI_MSK (EPIC_BIT(3) | EPIC_BIT(2) | EPIC_BIT(1) | EPIC_BIT(0))
|
||||
#define EPIC_CTPR_TASKPRI(p) ((p) & EPIC_CTPR_TASKPRI_MSK)
|
||||
|
||||
/* WHOAMI register */
|
||||
|
||||
#define EPIC_WHOAMI_ID_MSK (EPIC_BIT(4) | EPIC_BIT(3) | EPIC_BIT(2) | EPIC_BIT(1) | EPIC_BIT(0))
|
||||
#define EPIC_WHOAMI_ID(n) ((n) & EPIC_WHOAMI_ID_MSK)
|
||||
|
||||
/* FRR (feature reporting register) */
|
||||
#define EPIC_FRR_NCPU_MASK 0x00001f00
|
||||
#define EPIC_FRR_NCPU_SHIFT 8
|
||||
|
||||
#define EPIC_INTER_IN_SERVICE 2
|
||||
|
||||
#define EPIC_IN_INTERRUPT 20 /* internal type */
|
||||
#define EPIC_EX_INTERRUPT 21 /* external type */
|
||||
#define EPIC_INV_INTER_SOURCE 22 /* invalid interrupt source */
|
||||
#define EPIC_GT_A_INTERRUPT 23 /* global timer group A type */
|
||||
#define EPIC_MSG_INTERRUPT 24 /* message type */
|
||||
#define EPIC_IPI_INTERRUPT 25 /* inter-processor type */
|
||||
#define EPIC_VEC_HAS_NO_IDR 26 /* vector has no IDR reg */
|
||||
#define EPIC_VEC_OPTION_NA 27 /* option(s) not avail for this vec */
|
||||
#define EPIC_VEC_OPTION_INV 28 /* option mask is invalid */
|
||||
#define EPIC_SMSG_INTERRUPT 29 /* shared message type */
|
||||
#define EPIC_GT_B_INTERRUPT 30 /* global timer group B type */
|
||||
|
||||
#define EPIC_MAX_EXT_IRQS 12
|
||||
#define EPIC_MAX_IN_IRQS 48
|
||||
#define EPIC_MAX_GT_A_IRQS 4
|
||||
#define EPIC_MAX_GT_B_IRQS 4
|
||||
#define EPIC_MAX_MSG_IRQS 4
|
||||
#define EPIC_MAX_IPI_IRQS 4
|
||||
#define EPIC_MAX_SMSG_IRQS 8
|
||||
|
||||
#define EPIC_MAX_SMSG_SHARED_IRQS 32
|
||||
|
||||
#define EPIC_VEC_EXT_IRQ0 0
|
||||
#define EPIC_VEC_IN_IRQ0 (EPIC_VEC_EXT_IRQ0 + EPIC_MAX_EXT_IRQS)
|
||||
#define EPIC_VEC_GT_A_IRQ0 (EPIC_VEC_IN_IRQ0 + EPIC_MAX_IN_IRQS)
|
||||
#define EPIC_VEC_GT_B_IRQ0 (EPIC_VEC_GT_A_IRQ0 + EPIC_MAX_GT_A_IRQS)
|
||||
#define EPIC_VEC_MSG_IRQ0 (EPIC_VEC_GT_B_IRQ0 + EPIC_MAX_GT_B_IRQS)
|
||||
#define EPIC_VEC_SMSG_IRQ0 (EPIC_VEC_MSG_IRQ0 + EPIC_MAX_MSG_IRQS)
|
||||
#define EPIC_VEC_CTRL_EXT (EPIC_MAX_ALL_IRQS)
|
||||
/* EPIC_VEC_IPI_IRQ0 matches linux mpic which uses the last 4 vectors below
|
||||
* spurious vector
|
||||
*/
|
||||
#define EPIC_VEC_IPI_IRQ0 (255 - EPIC_MAX_IPI_IRQS)
|
||||
#define EPIC_MAX_ALL_IRQS 255
|
||||
|
||||
#define EPIC_PRIORITY_MIN 0 /* minimum level of priority */
|
||||
#define EPIC_PRIORITY_MAX 15 /* maximum level of priority */
|
||||
#define EPIC_PRIORITY_DEFAULT 3
|
||||
#define EPIC_INV_PRIO_ERROR ((ULONG)(-1))
|
||||
|
||||
#define EPIC_L2CACHE_INT_NUM 0
|
||||
#define EPIC_L2CACHE_INT_VEC (EPIC_L2CACHE_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_ECM_INT_NUM 1
|
||||
#define EPIC_ECM_INT_VEC (EPIC_ECM_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DDR_INT_NUM 2
|
||||
#define EPIC_DDR_INT_VEC (EPIC_DDR_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_LBC_INT_NUM 3
|
||||
#define EPIC_LBC_INT_VEC (EPIC_LBC_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DMA0_INT_NUM 4
|
||||
#define EPIC_DMA0_INT_VEC (EPIC_DMA0_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DMA1_INT_NUM 5
|
||||
#define EPIC_DMA1_INT_VEC (EPIC_DMA1_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DMA2_INT_NUM 6
|
||||
#define EPIC_DMA2_INT_VEC (EPIC_DMA2_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DMA3_INT_NUM 7
|
||||
#define EPIC_DMA3_INT_VEC (EPIC_DMA3_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_PCI1_INT_NUM 8
|
||||
#define EPIC_PCI1_INT_VEC (EPIC_PCI1_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
|
||||
#define EPIC_PCI2_INT_NUM 9
|
||||
#define EPIC_PCI2_INT_VEC (EPIC_PCI2_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_PCI_EXPRESS_INT_NUM 10
|
||||
#define EPIC_PCI_EXPRESS_INT_VEC (EPIC_PCI_EXPRESS_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES11_INT_NUM 11
|
||||
#define EPIC_RES11_INT_VEC (EPIC_RES11_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DUART2_INT_NUM 12
|
||||
#define EPIC_DUART2_INT_VEC (EPIC_DUART2_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
|
||||
#define EPIC_TSEC1TX_INT_NUM 13
|
||||
#define EPIC_TSEC1TX_INT_VEC (EPIC_TSEC1TX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC1RX_INT_NUM 14
|
||||
#define EPIC_TSEC1RX_INT_VEC (EPIC_TSEC1RX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC3TX_INT_NUM 15
|
||||
#define EPIC_TSEC3TX_INT_VEC (EPIC_TSEC3TX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC3RX_INT_NUM 16
|
||||
#define EPIC_TSEC3RX_INT_VEC (EPIC_TSEC3RX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC3ERR_INT_NUM 17
|
||||
#define EPIC_TSEC3ERR_INT_VEC (EPIC_TSEC3ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC1ERR_INT_NUM 18
|
||||
#define EPIC_TSEC1ERR_INT_VEC (EPIC_TSEC1ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC2TX_INT_NUM 19
|
||||
#define EPIC_TSEC2TX_INT_VEC (EPIC_TSEC2TX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC2RX_INT_NUM 20
|
||||
#define EPIC_TSEC2RX_INT_VEC (EPIC_TSEC2RX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC4TX_INT_NUM 21
|
||||
#define EPIC_TSEC4TX_INT_VEC (EPIC_TSEC4TX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC4RX_INT_NUM 22
|
||||
#define EPIC_TSEC4RX_INT_VEC (EPIC_TSEC4RX_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC4ERR_INT_NUM 23
|
||||
#define EPIC_TSEC4ERR_INT_VEC (EPIC_TSEC4ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_TSEC2ERR_INT_NUM 24
|
||||
#define EPIC_TSEC2ERR_INT_VEC (EPIC_TSEC2ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES25_INT_NUM 25
|
||||
#define EPIC_RES25_INT_VEC (EPIC_RES25_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_DUART_INT_NUM 26
|
||||
#define EPIC_DUART_INT_VEC (EPIC_DUART_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_I2C_INT_NUM 27
|
||||
#define EPIC_I2C_INT_VEC (EPIC_I2C_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_PERFMON_INT_NUM 28
|
||||
#define EPIC_PERFMON_INT_VEC (EPIC_PERFMON_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SEC_INT_NUM 29
|
||||
#define EPIC_SEC_INT_VEC (EPIC_SEC_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES30_INT_NUM 30
|
||||
#define EPIC_RES30_INT_VEC (EPIC_RES30_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES31_INT_NUM 31
|
||||
#define EPIC_RES31_INT_VEC (EPIC_RES31_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
|
||||
#define EPIC_SR_ERR_INT_NUM 32
|
||||
#define EPIC_SR_ERR_INT_VEC (EPIC_SR_ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SR_OUT_DB1_INT_NUM 33
|
||||
#define EPIC_SR_OUT_DB1_INT_VEC (EPIC_SR_OUT_DB1_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SR_IN_DB1_INT_NUM 34
|
||||
#define EPIC_SR_IN_DB1_INT_VEC (EPIC_SR_IN_DB1_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES35_INT_NUM 35
|
||||
#define EPIC_RES35_INT_VEC (EPIC_RES35_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES36_INT_NUM 36
|
||||
#define EPIC_RES36_INT_VEC (EPIC_RES36_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SR_OUT_MU1_INT_NUM 37
|
||||
#define EPIC_SR_OUT_MU1_INT_VEC (EPIC_SR_OUT_MU1_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SR_IN_MU1_INT_NUM 38
|
||||
#define EPIC_SR_IN_MU1_INT_VEC (EPIC_SR_IN_MU1_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SR_OUT_MU2_INT_NUM 39
|
||||
#define EPIC_SR_OUT_MU2_INT_VEC (EPIC_SR_OUT_MU2_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_SR_IN_MU2_INT_NUM 40
|
||||
#define EPIC_SR_IN_MU2_INT_VEC (EPIC_SR_IN_MU2_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES41_INT_NUM 41
|
||||
#define EPIC_RES41_INT_VEC (EPIC_RES41_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES42_INT_NUM 42
|
||||
#define EPIC_RES42_INT_VEC (EPIC_RES42_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES43_INT_NUM 43
|
||||
#define EPIC_RES43_INT_VEC (EPIC_RES43_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES44_INT_NUM 44
|
||||
#define EPIC_RES44_INT_VEC (EPIC_RES44_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES45_INT_NUM 45
|
||||
#define EPIC_RES45_INT_VEC (EPIC_RES45_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES46_INT_NUM 46
|
||||
#define EPIC_RES46_INT_VEC (EPIC_RES46_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
#define EPIC_RES47_INT_NUM 47
|
||||
#define EPIC_RES47_INT_VEC (EPIC_RES47_INT_NUM + EPIC_VEC_IN_IRQ0)
|
||||
|
||||
#define VXB_EPICINTCTLR_ENABLE_INTS(intMask) \
|
||||
_VXB_EPICINTCTLR_ENABLE_INTS(intMask)
|
||||
#if defined(T4_ERRATUM_CPU6198) && defined(_WRS_CONFIG_SMP)
|
||||
#define VXB_EPICINTCTLR_DISABLE_INTS(intMask) intCpuLock()
|
||||
#else
|
||||
#define VXB_EPICINTCTLR_DISABLE_INTS(intMask) \
|
||||
_VXB_EPICINTCTLR_DISABLE_INTS(intMask)
|
||||
#endif /* T4_ERRATUM_CPU6198 && _WRS_CONFIG_SMP */
|
||||
|
||||
/* Bank A, B, C shared message macros */
|
||||
|
||||
#define EPIC_RES_PER_VECTOR 32 /* Each Vector has 32 resource */
|
||||
#define EPIC_MAX_SMSG_RESOURCE 768 /* BankA, B, C 3 * 8 * 32 */
|
||||
#define EPIC_MAX_SMSG_VEC 24 /* BankA, B, C 3 * 8 */
|
||||
#define EPIC_MAX_1BANK_RESOURCE 256 /* The resoure number in one Bank 8 * 32 */
|
||||
#define EPIC_BASE (EPIC_CCSROFF + (UINT32)pEpicRegBase) /* EPIC controller register base */
|
||||
|
||||
#define EPIC_SMSG_VEC_STAT EPIC_DRV_CTRL(smsgIrq0)
|
||||
#define EPIC_SMSG_VEC_NUM (EPIC_DRV_CTRL(intBankDesc[5]->numIrqs))
|
||||
#define MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
|
||||
|
||||
/* Shared message signaled interrupt index register */
|
||||
|
||||
#define EPIC_MSIIRA 0x1740
|
||||
#define EPIC_MSIIRB 0x1940
|
||||
#define EPIC_MSIIRC 0x1b40
|
||||
|
||||
/* Shared Message Signaled Interrupt Registers */
|
||||
|
||||
#define EPIC_MSIRA0 0x1600
|
||||
#define EPIC_MSIRB0 0x1800
|
||||
#define EPIC_MSIRC0 0x1A00
|
||||
|
||||
#define EPIC_MISRA_X(pin) (EPIC_CCSROFF + EPIC_MSIRA0 + (pin)* 0x10)
|
||||
#define EPIC_MISRB_X(pin) (EPIC_CCSROFF + EPIC_MSIRB0 + (pin)* 0x10)
|
||||
#define EPIC_MISRC_X(pin) (EPIC_CCSROFF + EPIC_MSIRC0 + (pin)* 0x10)
|
||||
|
||||
/* macros to fields in interrupt controller pin array */
|
||||
|
||||
#define EPIC_INT_INDEX_GET(pEnt,inputPin, index) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
index = pPin->intIndex; \
|
||||
}
|
||||
|
||||
#define EPIC_INT_INDEX_SET(pEnt,inputPin, index) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
pPin->intIndex = index; \
|
||||
}
|
||||
#define EPIC_DESTCPU_GET(pEnt,inputPin,destCpu) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
destCpu = pPin->pinCpu; \
|
||||
}
|
||||
|
||||
#define EPIC_DESTCPU_SET(pEnt,inputPin,destCpu) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
pPin->pinCpu = destCpu; \
|
||||
}
|
||||
|
||||
#define EPIC_ISR_GET(pEnt,inputPin,funcPtr) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
funcPtr = pPin->isr; \
|
||||
}
|
||||
|
||||
#define EPIC_ARG_GET(pEnt,inputPin,argument) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
argument = pPin->pArg; \
|
||||
}
|
||||
|
||||
#define EPIC_NAME_SET(pEnt,inputPin,name) \
|
||||
{ \
|
||||
struct vxbIntCtlrPin * pPin = \
|
||||
vxbIntCtlrPinEntryGet(pEnt,inputPin); \
|
||||
pPin->drvName = name; \
|
||||
}
|
||||
|
||||
#if defined (_WRS_HAS_DCC_ASM_SYNTAX)
|
||||
__asm volatile void _VXB_EPICINTCTLR_ENABLE_INTS (int intMask)
|
||||
{
|
||||
% reg intMask
|
||||
! "r7" /* r7 clobbered */
|
||||
mfmsr r7 /* move MSR to r7 */
|
||||
or r7, r7, intMask /* restore EE (and CE) bit */
|
||||
mtmsr r7 /* UNLOCK INTERRUPTS */
|
||||
}
|
||||
|
||||
__asm volatile void _VXB_EPICINTCTLR_DISABLE_INTS (int intMask)
|
||||
{
|
||||
% reg intMask
|
||||
! "r7" /* r7 clobbered */
|
||||
mfmsr r7 /* move MSR to r7 */
|
||||
andc r7, r7, intMask /* mask EE (and CE) bit */
|
||||
mtmsr r7 /* LOCK INTERRUPTS */
|
||||
}
|
||||
#elif defined (_WRS_HAS_GCC_ASM_SYNTAX)
|
||||
static __inline__ void _VXB_EPICINTCTLR_ENABLE_INTS (int intMask)
|
||||
{
|
||||
__asm__ volatile
|
||||
(
|
||||
"mfmsr 7;" /* move MSR to r7 */
|
||||
"or 7, 7, %0;" /* restore EE (and CE) bit */
|
||||
"mtmsr 7" /* UNLOCK INTERRUPTS */
|
||||
: /* no output */
|
||||
: "r" (intMask) /* input: intMask is %0 */
|
||||
: "r7" /* r7 clobbered */
|
||||
);
|
||||
}
|
||||
|
||||
static __inline__ void _VXB_EPICINTCTLR_DISABLE_INTS (int intMask)
|
||||
{
|
||||
__asm__ volatile
|
||||
(
|
||||
"mfmsr 7;" /* move MSR to r7 */
|
||||
"andc 7, 7, %0;" /* mask EE (and CE) bit */
|
||||
"mtmsr 7" /* LOCK INTERRUPTS */
|
||||
: /* no output */
|
||||
: "r" (intMask) /* input: intMask is %0 */
|
||||
: "r7" /* r7 clobbered */
|
||||
);
|
||||
}
|
||||
#else /* _WRS_HAS_DCC_ASM_SYNTAX */
|
||||
#error The compiler does not support this type of in-line assembly
|
||||
#endif /* _WRS_HAS_DCC_ASM_SYNTAX */
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
/* function pointer points to the EPIC ID getter, that can be set by BSP */
|
||||
|
||||
extern UINT (*_func_vxbSysEpicIdGet) (UINT);
|
||||
|
||||
extern void vxbSysEpicIdAssign (UINT cpuCount, BOOL epicIdInterval);
|
||||
extern UINT vxbSysEpicIdGet (UINT physCpuIndex);
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
extern VXB_DEVICE_ID epicVxbId; /* EPIC device ID */
|
||||
extern VOIDFUNCPTR _func_vxbSysEpicIntHandler;
|
||||
extern VXIPI_EMIT_FUNC _func_vxEpicIpiCtrlInitIpiEmit;
|
||||
|
||||
extern void vxbSysEpicIntHandler (void);
|
||||
extern STATUS vxbEpicIpiGen
|
||||
(
|
||||
VXB_DEVICE_ID pCtlr,
|
||||
INT32 ipiId,
|
||||
phys_cpuset_t cpus
|
||||
);
|
||||
|
||||
#ifdef PPC_e6500
|
||||
extern void vxbSysEpicE6500IntHandler (void);
|
||||
extern STATUS vxbEpicE6500IpiGen
|
||||
(
|
||||
VXB_DEVICE_ID pCtlr,
|
||||
INT32 ipiId,
|
||||
phys_cpuset_t cpus
|
||||
);
|
||||
#endif /* PPC_e6500 */
|
||||
|
||||
/* access macros */
|
||||
|
||||
#define EPIC_DRV_CTRL(member) \
|
||||
((struct vxbEpicIntCtlrDrvCtrl *)(epicVxbId->pDrvCtrl))->member
|
||||
|
||||
#define EPIC_REG_READ(offset) \
|
||||
vxbRead32 (EPIC_DRV_CTRL(regAccessHandle), \
|
||||
(UINT32 *)((UINT32)pEpicRegBase + (offset & REG_ADRS_MASK)))
|
||||
|
||||
#define EPIC_REG_WRITE(offset, value) \
|
||||
vxbWrite32 (EPIC_DRV_CTRL(regAccessHandle), \
|
||||
(UINT32 *)((UINT32)pEpicRegBase + (offset & REG_ADRS_MASK)), \
|
||||
value)
|
||||
|
||||
#define EPIC_REG_NO_OFFSET_READ(regAdrs) \
|
||||
vxbRead32 (EPIC_DRV_CTRL(regAccessHandle), (UINT32 *)(regAdrs))
|
||||
|
||||
#define EPIC_REG_NO_OFFSET_WRITE(regAdrs, value) \
|
||||
vxbWrite32 (EPIC_DRV_CTRL(regAccessHandle), (UINT32 *)(regAdrs), value)
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
#define VXB_SYS_EPIC_ID_GET(physCpuIndex) \
|
||||
_func_vxbSysEpicIdGet == NULL ? physCpuIndex : \
|
||||
_func_vxbSysEpicIdGet (physCpuIndex)
|
||||
#else
|
||||
#define VXB_SYS_EPIC_ID_GET(physCpuIndex) physCpuIndex
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbSysEpich */
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
/* vxbI8259IntCtlr.h - Intel 8259a PIC (Programmable Interrupt Controller) */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2007 Wind River Systems, Inc. All rights are reserved.
|
||||
*
|
||||
* The right to copy, distribute, modify, or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,11jun07,ami added
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbI8259IntCtlrh
|
||||
#define __INCvxbI8259IntCtlrh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/* ICW1 */
|
||||
|
||||
#define I8259_PIC_ICW4_NEEDED 0x01
|
||||
#define I8259_PIC_N0_ICW4_NEEDED 0x00
|
||||
#define I8259_PIC_SINGLE_MODE 0x02
|
||||
#define I8259_PIC_CASCADE_MODE 0x00
|
||||
#define I8259_PIC_INTERVAL_4 0x04
|
||||
#define I8259_PIC_INTERVAL_8 0x00
|
||||
#define I8259_PIC_LEVEL_TRIGGER 0x08
|
||||
#define I8259_PIC_EDGE_TRIGGER 0x00
|
||||
#define I8259_PIC_ICW1 0x10
|
||||
|
||||
/* ICW4 */
|
||||
|
||||
#define I8259_I8259_PIC_8086_MODE 0x01
|
||||
#define I8259_I8259_PIC_8080_MODE 0x00
|
||||
#define I8259_PIC_AUTO_EOI 0x02
|
||||
#define I8259_PIC_NORMAL_EOI 0x00
|
||||
#define I8259_PIC_NON_BUFFERED 0x04
|
||||
#define I8259_PIC_BUFFERED_SLAVE 0x08
|
||||
#define I8259_PIC_BUFFERED_MASTER 0x0C
|
||||
#define I8259_PIC_SPECIAL_NESTED 0x10
|
||||
#define I8259_PIC_NOT_SPECIAL_NESTED 0x00
|
||||
|
||||
/* Operational Command Word 1 */
|
||||
|
||||
#define I8259_PIC_MASK_ALL_INTR 0xFF
|
||||
|
||||
/* Operational Command Word 2 */
|
||||
|
||||
#define I8259_PIC_NONSPECIFIC_EOI 0x20
|
||||
#define I8259_PIC_SPECIFIC_EOI 0x60
|
||||
#define I8259_PIC_ROT_NONSPEC_EOI 0xA0
|
||||
#define I8259_PIC_ROT_AUT_EOI_SET 0x80
|
||||
#define I8259_PIC_ROT_AUT_EOI_CLR 0x00
|
||||
#define I8259_PIC_ROT_SPEC_AUT_EOI 0xE0
|
||||
#define I8259_PIC_SET_PRIORTY_CMD 0xC0
|
||||
#define I8259_PIC_OCW2_NOP 0x40
|
||||
|
||||
/* Operational Command Word 3 */
|
||||
|
||||
#define I8259_PIC_RESET_SPECIAL_MASK 0x40
|
||||
#define I8259_PIC_SET_SPECIAL_MASK 0x60
|
||||
#define I8259_PIC_OCW3 0x08
|
||||
#define I8259_PIC_POLL_CMD 0x04
|
||||
#define I8259_PIC_NO_POLL_CMD 0x00
|
||||
#define I8259_PIC_READ_IR_REG 0x02
|
||||
#define I8259_PIC_READ_IS_REG 0x03
|
||||
#define I8259_PIC_DISABLE_SMM 0x08
|
||||
#define I8259_PIC_ENABLE_SMM 0x68
|
||||
|
||||
#define I8259_PORTB_OFFSET 0x1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbI8259IntCtlrh */
|
||||
|
||||
@@ -0,0 +1,250 @@
|
||||
/* vxbMPCoreIntCtlr.h - MPCore interrupt ctrl driver */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007, 2009-2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify, or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,29jul10,pad Moved extern C statement after include statements.
|
||||
01b,16apr09,j_b change core reset and start IPI #s
|
||||
01a,23aug07,jb Created from top of vxbEbGenIntrCtl.c rev 01c
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbMPCoreIntCtlrh
|
||||
#define __INCvxbMPCoreIntCtlrh
|
||||
|
||||
#include <vxBusLib.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* MPCore GIC Interrupt levels */
|
||||
#define INT_LVL_MPCORE_IPI00 0 /* This is vxWorks CPC IPI */
|
||||
#define INT_LVL_MPCORE_CPC INT_LVL_MPCORE_IPI00
|
||||
|
||||
#define INT_LVL_MPCORE_IPI01 1 /* This is vxWorks Debug IPI */
|
||||
#define INT_LVL_MPCORE_DEBUG INT_LVL_MPCORE_IPI01
|
||||
|
||||
#define INT_LVL_MPCORE_IPI02 2 /* This is vxWorks Reschedule IPI */
|
||||
#define INT_LVL_MPCORE_SCHED INT_LVL_MPCORE_IPI02
|
||||
|
||||
#define INT_LVL_MPCORE_IPI03 3 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI04 4 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI05 5 /* IPI -> use SWI register in GIC */
|
||||
|
||||
#define INT_LVL_MPCORE_IPI06 6 /* This is vxWorks Core Reset IPI */
|
||||
#define INT_LVL_MPCORE_RESET INT_LVL_MPCORE_IPI06
|
||||
|
||||
#define INT_LVL_MPCORE_IPI07 7 /* This is vxWorks Core Start IPI */
|
||||
#define INT_LVL_MPCORE_START INT_LVL_MPCORE_IPI07
|
||||
|
||||
#define INT_LVL_MPCORE_IPI08 8 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI09 9 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI10 10 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI11 11 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI12 12 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI13 13 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI14 14 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_IPI15 15 /* IPI -> use SWI register in GIC */
|
||||
#define INT_LVL_MPCORE_SPARE00 16 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE01 17 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE02 18 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE03 19 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE04 20 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE05 21 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE06 22 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE07 23 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE08 24 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE09 25 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE10 26 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE11 27 /* not used */
|
||||
#define INT_LVL_MPCORE_SPARE12 28 /* not used */
|
||||
#define INT_LVL_MPCORE_PVT_TMR 29 /* Private Timer */
|
||||
#define INT_LVL_MPCORE_PVT_WDG 30 /* Private WatchDog */
|
||||
#define INT_LVL_MPCORE_PVT_IRQ 31 /* nIRQ */
|
||||
#define INT_LVL_MPCORE_TST_INT00 32 /* AACIINTR */
|
||||
#define INT_LVL_MPCORE_TST_INT01 33 /* TIMERINT01 */
|
||||
#define INT_LVL_MPCORE_TST_INT02 34 /* TIMERINT23 */
|
||||
#define INT_LVL_MPCORE_TST_INT03 35 /* USBnINT */
|
||||
#define INT_LVL_MPCORE_TST_INT04 36 /* UARTINT0 */
|
||||
#define INT_LVL_MPCORE_TST_INT05 37 /* UARTINT1 */
|
||||
#define INT_LVL_MPCORE_TST_INT06 38 /* RTCINT */
|
||||
#define INT_LVL_MPCORE_TST_INT07 39 /* KMIINT0 */
|
||||
#define INT_LVL_MPCORE_TST_INT08 40 /* KMIINT1*/
|
||||
#define INT_LVL_MPCORE_TST_INT09 41 /* ETHINTR */
|
||||
#define INT_LVL_MPCORE_TST_INT10 42 /* GIC1 on EB */
|
||||
#define INT_LVL_MPCORE_TST_INT11 43 /* GIC2 on EB */
|
||||
#define INT_LVL_MPCORE_TST_INT12 44 /* GIC3 on EB */
|
||||
#define INT_LVL_MPCORE_TST_INT13 45 /* GIC4 on EB */
|
||||
#define INT_LVL_MPCORE_TST_INT14 46 /* MCIINTR0 */
|
||||
#define INT_LVL_MPCORE_TST_INT15 47 /* MCIINTR1*/
|
||||
#define INT_LVL_MPCORE_NOT_USED 48 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ00 49 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ01 50 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ02 51 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ03 52 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ04 53 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ05 54 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ06 55 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ07 56 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ08 57 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ09 58 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ10 59 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_PMUIRQ11 60 /* PMU interrupts */
|
||||
#define INT_LVL_MPCORE_L220_EVENT 61
|
||||
#define INT_LVL_MPCORE_L220_SLV_ERR 62
|
||||
#define INT_LVL_MPCORE_L220_DEC_ERR 63
|
||||
|
||||
#define INT_LVL_MPCORE_GIC1 INT_LVL_MPCORE_TST_INT10
|
||||
|
||||
#define MPCORE_GIC_INT_LEVELS_MAX 64
|
||||
|
||||
#define MPCORE_GIC_BINP_DEFAULT 0x03
|
||||
#define MPCORE_GIC_CONTROL_ENABLE 0x1
|
||||
#define MPCORE_GIC_INT_ALL_ENABLED 0xF0 /* priority 0-E can run */
|
||||
#define MPCORE_GIC_INT_ALL_DISABLED 0x00 /* nothing higher than 0*/
|
||||
#define MPCORE_GIC_INT_SPURIOUS 0x3FF /* No interrupt currently */
|
||||
#define MPCORE_GIC_ONEMINUS_HIGH 0xAAAAAAAA /* Intrpt config to 1-N, High */
|
||||
#define MPCORE_GIC_SWINTRMASK 0X0000FFFF /* Mask for enabling S/W intr */
|
||||
|
||||
/* Generic Controller Defines */
|
||||
#ifndef CONFIGS_PER_WORD
|
||||
#define CONFIGS_PER_WORD 16
|
||||
#endif
|
||||
#ifndef PRIOS_PER_WORD
|
||||
#define PRIOS_PER_WORD 4
|
||||
#endif
|
||||
#ifndef TARGETS_PER_WORD
|
||||
#define TARGETS_PER_WORD 4
|
||||
#endif
|
||||
#ifndef NWORD
|
||||
#define NWORD(bitnum) (bitnum / 32)
|
||||
#endif
|
||||
#ifndef BIT
|
||||
#define BIT(bitnum) (1 << (bitnum % BITS_PER_WORD))
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* MPCore Distributor and Controller defines */
|
||||
|
||||
/* TO DO - Add code to grab and use base from arm11MPCorePeriphBaseAddr */
|
||||
|
||||
#define MPCORE_SYS_BASE 0x1F000000
|
||||
|
||||
#define MPCORE_GIC_DIST (MPCORE_SYS_BASE + 0x1000)
|
||||
|
||||
/* MPCORE_GIC_Config used in code */
|
||||
|
||||
#define MPCORE_GIC_Config(Periph) ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + 0xC00 + \
|
||||
(0x4 * (Periph / CONFIGS_PER_WORD))))
|
||||
|
||||
/* MPCORE_GIC_Prio used in code */
|
||||
|
||||
#define MPCORE_GIC_Prio(Periph) ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + 0x400 + \
|
||||
(0x4 * (Periph / PRIOS_PER_WORD))))
|
||||
|
||||
/* These three used in code */
|
||||
|
||||
#define MPCORE_GIC_Control ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + 0x000))
|
||||
|
||||
/* MPCORE_GIC_CPUTarg used in code */
|
||||
|
||||
#define MPCORE_GIC_CPUTarg(Periph) ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + \
|
||||
0x800 + \
|
||||
(0x4 * (Periph/TARGETS_PER_WORD))))
|
||||
|
||||
/* MPCORE_GIC_IntEnable used in code */
|
||||
|
||||
#define MPCORE_GIC_IntEnable(Periph) ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + \
|
||||
0x100 + (0x4 * NWORD(Periph))))
|
||||
|
||||
/* MPCORE_GIC_IntEnClr used in code */
|
||||
|
||||
#define MPCORE_GIC_IntEnClr(Periph) ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + 0x180 + \
|
||||
(0x4 * NWORD(Periph))))
|
||||
|
||||
/* MPCORE_GIC_IntPendClr used in code */
|
||||
|
||||
#define MPCORE_GIC_IntPendClr(Periph) ((volatile unsigned int *)\
|
||||
(MPCORE_GIC_DIST + 0x280 + \
|
||||
(0x4 * NWORD(Periph))))
|
||||
|
||||
/* MPCORE_GIC Software Interrupt Register */
|
||||
|
||||
#define MPCORE_GIC_SWInterrupt ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x1F00))
|
||||
|
||||
/* Per Cpu Private space */
|
||||
#define MPCORE_CPU_Control ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x100))
|
||||
|
||||
/* MPCORE_CPU_PrioMask used in code */
|
||||
|
||||
#define MPCORE_CPU_PrioMask ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x104))
|
||||
|
||||
#define MPCORE_CPU_BinPoint ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x108))
|
||||
|
||||
/* MPCORE_CPU_IntAck used in code */
|
||||
|
||||
#define MPCORE_CPU_IntAck ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x10C))
|
||||
|
||||
/* MPCORE_CPU_EOInt used in code */
|
||||
|
||||
#define MPCORE_CPU_EOInt ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x110))
|
||||
|
||||
/* Aliased address space */
|
||||
|
||||
/* Per Cpu Aliased space */
|
||||
#define MPCORE_CPU_A_Control(CPU) ((volatile unsigned int *)\
|
||||
((MPCORE_SYS_BASE + 0x200) + ((CPU) * 100)))
|
||||
|
||||
/* MPCORE_CPU_PrioMask used in code */
|
||||
|
||||
#define MPCORE_A_CPU_PrioMask(CPU) ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x204) + ((CPU) * 100))
|
||||
|
||||
#define MPCORE_A_CPU_BinPoint(CPU) ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x208) + ((CPU) * 100))
|
||||
|
||||
/* MPCORE_A_CPU_IntAck used in code */
|
||||
|
||||
#define MPCORE_A_CPU_IntAck(CPU) ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x20C) + ((CPU) * 100))
|
||||
|
||||
/* MPCORE_A_CPU_EOInt used in code */
|
||||
|
||||
#define MPCORE_A_CPU_EOInt(CPU) ((volatile unsigned int *)\
|
||||
(MPCORE_SYS_BASE + 0x210) + ((CPU) * 100))
|
||||
|
||||
IMPORT STATUS vxbSysMPCoreIpiConnect (VOIDFUNCPTR * vector, \
|
||||
VOIDFUNCPTR routine, INT32 parameter);
|
||||
IMPORT STATUS vxbSysMPCoreIpiEnable (INT32 vector);
|
||||
IMPORT STATUS vxbSysMPCoreIpiDisable (INT32 vector);
|
||||
IMPORT STATUS sysEbMPCoreIpiGen(INT32 level, cpuset_t processor);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbMPCoreIntCtlrh */
|
||||
|
||||
@@ -0,0 +1,385 @@
|
||||
/* vxbMpApic.h - VxBus driver header files for the
|
||||
* Intel MP APIC/xAPIC (Advanced PIC)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2010,2014 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01p,18aug14,jb VXW6-83164 - MPAPIC_DATA_MAX_LEN of 4096 is too small for
|
||||
large SMP systems
|
||||
01o,13aug10,j_l Adjust BIOS_ROM_START and BIOS_ROM_SIZE.
|
||||
Fix for WIND00227546 - does not boot on Hanlan Creek.
|
||||
01n,24jun10,j_l Add local APIC global variables.
|
||||
01m,30apr10,jb Merge from 64bit view
|
||||
01l,21apr10,h_k made MP_APIC_DATA compatible between 32-bit and 64-bit.
|
||||
01k,12apr10,h_k LP64 adaptation.
|
||||
01j,14jan10,sem Corrected IOAPIC_LENGTH constant
|
||||
01i,10aug09,rec WIND00176001 - multiple IO Apic support mods...
|
||||
add MPAPIC_DATA_MAX_LEN
|
||||
01h,21nov08,scm multiple IO Apic support mods...
|
||||
01g,03oct08,rec WIND00137112 - restore MPAPIC_DATA_START definition
|
||||
01f,29sep08,rec remove MPAPIC_DATA_START
|
||||
01e,24jun08,scm clean up for acpi support...
|
||||
01c,24apr08,scm WIND00103470 - SMP/SYMMETRIC_IO_MODE warm re-boot support.
|
||||
01b,27feb08,h_k changed LOAPIC_IPI_INFO.
|
||||
01a,21Mar07,scm created.
|
||||
*/
|
||||
|
||||
/*
|
||||
* DESCRIPTION
|
||||
* This is the VxBus driver for the Local APIC Interrupt Driver
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbMpApic
|
||||
#define __INCvxbMpApic
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Extended BIOS Data Area */
|
||||
#define EBDA_START 0x9d000
|
||||
#define EBDA_SIZE 0x03000
|
||||
#define EBDA_END (EBDA_START + (EBDA_SIZE - 1))
|
||||
|
||||
/* memory location where MP data stored for warm reboot */
|
||||
#ifndef MPAPIC_DATA_START
|
||||
#define MPAPIC_DATA_START 0x00102000
|
||||
#endif
|
||||
|
||||
#ifndef MPAPIC_DATA_MAX_LEN
|
||||
#define MPAPIC_DATA_MAX_LEN 8192 /* max buf size vxMP table */
|
||||
#endif
|
||||
|
||||
/* identify startup structure used for initialization: NONE/MP/ACPI/USR */
|
||||
#define NO_MP_STRUCT 0x0
|
||||
#define MP_MP_STRUCT 0x1
|
||||
#define ACPI_MP_STRUCT 0x2
|
||||
#define USR_MP_STRUCT 0x3
|
||||
|
||||
/* BIOS ROM space */
|
||||
#define BIOS_ROM_START 0xef000
|
||||
#define BIOS_ROM_SIZE 0x11000
|
||||
#define BIOS_ROM_END (BIOS_ROM_START + (BIOS_ROM_SIZE - 1))
|
||||
|
||||
/* Local APIC base addr */
|
||||
#define LOAPIC_BASE 0xfee00000
|
||||
#define LOAPIC_LENGTH 0x00001000
|
||||
|
||||
/* EOI Register */
|
||||
#define LOAPIC_EOI 0xb0
|
||||
|
||||
/* IO APIC Index base addr */
|
||||
#define IOAPIC_BASE 0xfec00000
|
||||
#define IOAPIC_LENGTH 0x00001000
|
||||
|
||||
/* NOTE: entry into the sysMmuPhysDesc[] done once at initialization,
|
||||
* for now, IOAPIC_LENGTH expected to equal maximum apic space required.
|
||||
*/
|
||||
|
||||
#define IOAPIC_MAX_LENGTH 0x00001000
|
||||
|
||||
/* Maximum Number of IOAPICs in the system */
|
||||
#ifndef MAX_IOAPICS
|
||||
#define MAX_IOAPICS 0x10
|
||||
#endif
|
||||
|
||||
/* EOI Register */
|
||||
#define IOAPIC_EOI 0x40
|
||||
|
||||
/* MP Apic Table Phys-To-Virt translation */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
#define MPAPIC_PHYS_TO_VIRT(x) (void *) ((ULONG)pMpApicData + \
|
||||
(pMpApicData->x - pMpApicData->mpApicDataLoc))
|
||||
#else
|
||||
#define MPAPIC_PHYS_TO_VIRT(x) (void *) (pMpApicData->x)
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
/* MultiProcessor Specification version 1.4 */
|
||||
|
||||
typedef struct /* MP Floating Pointer Structure */
|
||||
{
|
||||
char signature [4]; /* "_MP_" */
|
||||
UINT32 configTableAddr; /* address of the MP configuration table */
|
||||
UINT8 length; /* length of the floating pointer structure */
|
||||
UINT8 specRev; /* version number of the MP specification */
|
||||
UINT8 cksum; /* checksum of the pointer structure */
|
||||
UINT8 featureByte[5]; /* MP feature bytes 1 - 5 */
|
||||
} MP_FPS;
|
||||
|
||||
typedef struct /* MP Configuration Table Header */
|
||||
{
|
||||
char mpSignature[4]; /* "PCMP" */
|
||||
UINT16 tableLength; /* length of the base configuration table */
|
||||
UINT8 specRevision; /* version number of the MP specification */
|
||||
UINT8 cksum; /* checksum of the base configuration table */
|
||||
char oemId[8]; /* string that identifies the manufacturer */
|
||||
char prodId[12]; /* string that identifies the product */
|
||||
UINT32 oemTablePtr; /* address to an OEM configuration table */
|
||||
UINT16 oemTableSize; /* size of the OEM configuration table */
|
||||
UINT16 entryCount; /* number of entries in the variable table */
|
||||
UINT32 localApicBaseAddr; /* address of the Local APIC */
|
||||
UINT16 extendedTableLength; /* length of the extended entries */
|
||||
UINT8 extendedTableCksum; /* checksum of the extended table entries */
|
||||
UINT8 reserved;
|
||||
} MP_HEADER;
|
||||
|
||||
typedef struct /* MP Config Table Entry for CPU's */
|
||||
{
|
||||
UINT8 entryType; /* 0 identifies a processor entry */
|
||||
UINT8 localApicId; /* Local APIC ID number */
|
||||
UINT8 localApicVersion; /* Local APIC's version number */
|
||||
UINT8 cpuFlags; /* EN: usable, BP: boot-processor */
|
||||
UINT32 cpuSig; /* stepping, model, family of the CPU */
|
||||
UINT32 featureFlags; /* feature definition flag */
|
||||
UINT32 reserved[2];
|
||||
} MP_CPU;
|
||||
|
||||
typedef struct /* MP Config Table Entry for IO APIC's */
|
||||
{
|
||||
UINT8 entryType; /* 2 identifies an IO APIC entry */
|
||||
UINT8 ioApicId; /* ID of this IO APIC */
|
||||
UINT8 ioApicVersion; /* version of this IO APIC */
|
||||
UINT8 ioApicFlags; /* usable or not */
|
||||
UINT32 ioApicBaseAddress; /* address of this IO APIC */
|
||||
} MP_IOAPIC;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 entryType;
|
||||
UINT8 busId;
|
||||
UINT8 busType[6];
|
||||
} MP_BUS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 entryType;
|
||||
UINT8 interruptType;
|
||||
UINT16 interruptFlags;
|
||||
UINT8 sourceBusId;
|
||||
UINT8 sourceBusIrq;
|
||||
UINT8 destApicId;
|
||||
UINT8 destApicIntIn;
|
||||
} MP_INTERRUPT;
|
||||
|
||||
typedef MP_INTERRUPT MP_IOINTERRUPT;
|
||||
typedef MP_INTERRUPT MP_LOINTERRUPT;
|
||||
|
||||
typedef struct apic_info
|
||||
{
|
||||
UINT8 id;
|
||||
UINT32 *addr;
|
||||
} APIC_INFO;
|
||||
|
||||
typedef union loapic_ipi_info
|
||||
{
|
||||
UINT32 all;
|
||||
|
||||
struct {
|
||||
UINT32 vectorNo:8;
|
||||
UINT32 deliMode:3;
|
||||
UINT32 destMode:1;
|
||||
UINT32 reserve2:2;
|
||||
UINT32 level:1;
|
||||
UINT32 trigger:1;
|
||||
UINT32 reserve1:2;
|
||||
UINT32 shortHand:2;
|
||||
UINT32 reserve0:4;
|
||||
UINT32 apicId:8;
|
||||
} icr;
|
||||
} LOAPIC_IPI_INFO;
|
||||
|
||||
/* mpApicData structure - structure holding mpApic details retrieved from
|
||||
* BIOS/ACPI/or USER defined methods.
|
||||
*
|
||||
*
|
||||
* The dynamic tables/structures are found contiguosly in memory following
|
||||
* the mpApicData structure. So, if the mpApicData structure is stored
|
||||
* at LOCAL_MEM_LOCAL_ADR + 0x2000, we look something like:
|
||||
*
|
||||
*
|
||||
* | |
|
||||
* | |
|
||||
* ------------------------ <--- LOCAL_MEM_LOCAL_ADR + 0x2000
|
||||
* | |
|
||||
* | mpApicData Struct. |
|
||||
* | |
|
||||
* | | <--- sizeof(MP_APIC_DATA)
|
||||
* +-----| ptr to Local Apic |
|
||||
* | | Index Tbl |
|
||||
* | | |
|
||||
* |+----| ptr to Bus Routing |
|
||||
* || | Tbl |
|
||||
* || | |
|
||||
* ||+---| ptr to Interrupt |
|
||||
* ||| | Routing Tbl |
|
||||
* ||| | |
|
||||
* |||+--| ptr to Logical Tbl |
|
||||
* |||| | |
|
||||
* ||||+-| ptr to Address Tbl |
|
||||
* ||||| | |
|
||||
* ||||| | |
|
||||
* ||||| ------------------------
|
||||
* ||||+>| |
|
||||
* |||| | mpApicAddrTable | <--- (mpApicNioApic * sizeof(UINT32))
|
||||
* |||| | |
|
||||
* |||| ------------------------
|
||||
* |||+->| |
|
||||
* ||| | mpApicLogicalTable | <--- (mpApicNioApic * sizeof(UINT8))
|
||||
* ||| | |
|
||||
* ||| ------------------------
|
||||
* ||+-->| |
|
||||
* ||| ------------------------
|
||||
* ||+-->| |
|
||||
* || | mpApicInterruptTable | <--- ((mpApicNioint + mpApicNloint) *
|
||||
* || | | sizeof(MP_INTERRUPT))
|
||||
* || | |
|
||||
* || ------------------------
|
||||
* |+--->| |
|
||||
* | | mpApicBusTable | <--- (mpApicNbus * sizeof(MP_BUS))
|
||||
* | | |
|
||||
* | ------------------------
|
||||
* +---->| |
|
||||
* | mploApicIndexTable | <--- (mpApicCpuCount * sizeof(UINT8))
|
||||
* | |
|
||||
* ------------------------
|
||||
* | |
|
||||
*
|
||||
*/
|
||||
|
||||
typedef struct mpApicData
|
||||
{
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
UINT32 reserved; /* (not used in LP64) */
|
||||
#else
|
||||
void *pInst; /* instance pointer */
|
||||
#endif
|
||||
|
||||
UINT32 mpApicDataLoc; /* mem location of MP_APIC_DATA */
|
||||
UINT32 mpApicMpSize; /* size of MP_APIC_DATA */
|
||||
|
||||
UINT32 mpApicBootOpt; /* NONE/MP/ACPI/USR boot structure used */
|
||||
|
||||
MP_FPS mpApicFps; /* MP Floating Pointer Structure */
|
||||
|
||||
MP_HEADER mpApicHeader; /* MP Configuration Table Header */
|
||||
|
||||
UINT32 mpApicloBase; /* def Local APIC addr */
|
||||
|
||||
UINT32 mpApicNioApic; /* number of IO APICs (MP Table) */
|
||||
|
||||
/* logical io apic id to address mapping */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
UINT32 reserved1; /* (not used in LP64) */
|
||||
#else
|
||||
UINT32 *mpApicAddrTable;
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
UINT32 mpApicAtLoc; /* mem location of mpApicAddrTable */
|
||||
UINT32 mpApicAtSize; /* size of mpApicAddrTable */
|
||||
|
||||
/* recorded id mapping */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
UINT32 reserved2; /* (not used in LP64) */
|
||||
#else
|
||||
UINT8 *mpApicLogicalTable;
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
UINT32 mpApicLtLoc; /* mem location of mpApicLogicalTable */
|
||||
UINT32 mpApicLtSize; /* size of mpApicLogicalTable */
|
||||
|
||||
/* interrupt routing table */
|
||||
|
||||
UINT32 mpApicNioint; /* number of io interrupts (MP Table) */
|
||||
UINT32 mpApicNloint; /* number of local interrupts (MP Table) */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
UINT32 reserved3; /* (not used in LP64) */
|
||||
#else
|
||||
MP_INTERRUPT *mpApicInterruptTable;
|
||||
#endif
|
||||
|
||||
UINT32 mpApicItLoc; /* mem location of mpApicInterruptTable */
|
||||
UINT32 mpApicItSize; /* size of mpApicInterruptTable */
|
||||
|
||||
/* bus routing table */
|
||||
|
||||
UINT32 mpApicNbus; /* number of buses (MP Table) */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
UINT32 reserved4; /* (not used in LP64) */
|
||||
#else
|
||||
MP_BUS *mpApicBusTable;
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
UINT32 mpApicBtLoc; /* mem location of mpApicBusTable */
|
||||
UINT32 mpApicBtSize; /* size of mpApicBusTable */
|
||||
|
||||
/* NOTE: mploApicIndexTable, mpApicLaLoc, mpApicLaSize, mpCpuIndexTable,
|
||||
* and mpApicCpuCount are used under SMP and AMP, they are considered
|
||||
* RESERVED for future use under standard UP builds.
|
||||
*/
|
||||
|
||||
/* loApic Id translation */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
UINT32 reserved5; /* (not used in LP64) */
|
||||
#else
|
||||
UINT8 *mploApicIndexTable;
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
UINT32 mpApicLaLoc; /* mem location of mploApicIndexTable */
|
||||
UINT32 mpApicLaSize; /* size of mploApicIndexTable */
|
||||
|
||||
/* cpu Id translation */
|
||||
|
||||
UINT8 mpCpuIndexTable[256];
|
||||
|
||||
UINT32 mpApicCpuCount; /* CPU counter */
|
||||
UINT8 mpApicCpuBSP; /* Boot Strap Processor localApicId */
|
||||
}MP_APIC_DATA;
|
||||
|
||||
/* MP Configuration Table Entries */
|
||||
|
||||
#define MP_ENTRY_CPU 0 /* Entry Type: CPU */
|
||||
#define MP_ENTRY_BUS 1 /* Entry Type: BUS */
|
||||
#define MP_ENTRY_IOAPIC 2 /* Entry Type: IO APIC */
|
||||
#define MP_ENTRY_IOINTERRUPT 3 /* Entry Type: IO INT */
|
||||
#define MP_ENTRY_LOINTERRUPT 4 /* Entry Type: LO INT */
|
||||
|
||||
/* Extended MP Configuration Table Entries */
|
||||
|
||||
#define EXT_MP_ENTRY_SASM 128 /* Entry Type: System Address Space Map */
|
||||
#define EXT_MP_ENTRY_BHD 129 /* Entry Type: Bus Hierarchy Descriptor */
|
||||
#define EXT_MP_ENTRY_CBASM 130 /* Entry Type: Comp Addr Space Modifier */
|
||||
|
||||
/* MP Configuration Table CPU Flags */
|
||||
|
||||
#define MP_CPU_FLAGS_BP 0x02
|
||||
|
||||
/* Local APIC global variables */
|
||||
|
||||
IMPORT UINT32 glbLoApicOldSvr; /* original SVR */
|
||||
IMPORT UINT32 glbLoApicOldLint0; /* original LINT0 */
|
||||
IMPORT UINT32 glbLoApicOldLint1; /* original LINT1 */
|
||||
IMPORT char * glbLoApicBaseAdrs; /* Lo Apic Register Base address */
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
IMPORT char * glbLoApicIdAdrs; /* Lo Apic ID register address */
|
||||
#endif /* _WRS_CONFIG_LP64 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbMpAPic */
|
||||
@@ -0,0 +1,161 @@
|
||||
/* vxbMpicIntCtlr.h - Multicore Programmable Interrupt Controller driver */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,09may12,syt Added TRIG_ENTRY_NUM and IPI vector defines. (WIND00341799)
|
||||
01h,22sep11,syt Added macro MPIC_QUIRK_IACK.(WIND00295774)
|
||||
01g,29jun11,syt Added MPIC register resource flag defines.
|
||||
01f,23mar11,x_s Added macro MPIC_EOI_P0_REG.
|
||||
01e,06mar11,x_s Added SMP support.
|
||||
01d,12jan11,x_z Fixed documentation issue.
|
||||
01c,15oct10,x_z Fixed macro MPIC_IPI0_VEC and MPIC_MAX_EXT_VEC.
|
||||
01b,27jun10,x_z Fixed some macros and code clean.
|
||||
01a,30mar10,x_s Modified from vxbEpicIntCtlr.h/01s
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbMpicIntCtlrh
|
||||
#define __INCvxbMpicIntCtlrh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Registers Offsets */
|
||||
|
||||
#define MPIC_VP0_REG 0x10000 /* Vector/Priority */
|
||||
#define MPIC_DST0_REG 0x10010 /* Destination */
|
||||
#define MPIC_IPI_DPATCH_REG0 0x00040 /* IPI0 dispatch */
|
||||
#define MPIC_IPI_DPATCH_REG1 0x00050 /* IPI1 dispatch */
|
||||
#define MPIC_IPI_DPATCH_REG2 0x00060 /* IPI2 dispatch */
|
||||
#define MPIC_IPI_DPATCH_REG3 0x00070 /* IPI3 dispatch */
|
||||
|
||||
#define MPIC_CTASK_PRI_REG 0x20080 /* Cur Task Prio for CPU0 */
|
||||
#define MPIC_WHO_AM_I_REG 0x00090 /* Who am I */
|
||||
#define MPIC_INT_ACK_REG 0x000A0 /* Non Critical Interrupt Acknowledge */
|
||||
#define MPIC_EOI_REG 0x000B0 /* Non Critical End of Interrupt */
|
||||
#define MPIC_EOI_P0_REG 0x200B0 /* Non Critical End of Interrupt for CPU0 */
|
||||
#define MPIC_CRT_INT_ACK_REG 0x000C0 /* Critical Interrupt Acknowledge */
|
||||
#define MPIC_CRT_EOI_REG 0x000D0 /* Critical End of Interrupt */
|
||||
#define MPIC_MC_INT_ACK_REG 0x000E0 /* MachineCheck Interrupt Acknowledge */
|
||||
#define MPIC_MC_EOI_REG 0x000F0 /* MachineCheck End of Interrupt */
|
||||
|
||||
#define MPIC_FEATURES_REG0 0x01000 /* Feature reporting */
|
||||
#define MPIC_GLOBAL_REG0 0x01020 /* Global config */
|
||||
#define MPIC_VENDOR_TYPE_REG 0x01040 /* Vendor Interrupt Type Config */
|
||||
#define MPIC_VENDOR_VIRD_REG 0x01050 /* Vendor raw interrupt debug config */
|
||||
#define MPIC_VENDOR_REVID_REG 0x01070 /* Vendor soft core revision ID */
|
||||
#define MPIC_VENDOR_ID_REG 0x01080 /* Vendor id */
|
||||
#define MPIC_PROC_INIT_REG 0x01090 /* Processor init. */
|
||||
|
||||
#define MPIC_IPI_VEC_REG0 0x010A0 /* IPI0 vect/prio */
|
||||
#define MPIC_IPI_VEC_REG1 0x010B0 /* IPI1 vect/prio */
|
||||
#define MPIC_IPI_VEC_REG2 0x010C0 /* IPI2 vect/prio */
|
||||
#define MPIC_IPI_VEC_REG3 0x010D0 /* IPI3 vect/prio */
|
||||
#define MPIC_SPUR_VEC_REG 0x010E0 /* Spurious vector */
|
||||
|
||||
#define MPIC_TVP0_REG 0x01120 /* Timer0 Vector/Priority */
|
||||
#define MPIC_TDST0_REG 0x01130 /* Timer0 Destination */
|
||||
|
||||
#define MPIC_NAME "mpic"
|
||||
|
||||
/* Vector/Priority Registers */
|
||||
|
||||
#define MPIC_VECPRI_MASK 0x80000000
|
||||
#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
|
||||
#define MPIC_VECPRI_PRIORITY_MASK 0xf
|
||||
#define MPIC_VECPRI_PRIORITY_SHIFT 16
|
||||
#define MPIC_VECPRI_VECTOR_MASK 0x000000ff
|
||||
#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
|
||||
#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
|
||||
#define MPIC_VECPRI_POLARITY_MASK 0x00800000
|
||||
#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
|
||||
#define MPIC_VECPRI_SENSE_EDGE 0x00000000
|
||||
#define MPIC_VECPRI_SENSE_MASK 0x00400000
|
||||
|
||||
/* FRR (feature reporting register) */
|
||||
|
||||
#define MPIC_FRR_NIRQ_MASK 0x007f0000
|
||||
#define MPIC_FRR_NIRQ_SHIFT 16
|
||||
#define MPIC_FRR_NCPU_MASK 0x00001f00
|
||||
#define MPIC_FRR_NCPU_SHIFT 8
|
||||
|
||||
/* Global configuration register */
|
||||
|
||||
#define MPIC_GLOBAL_GCONF_RESET 0x80000000
|
||||
#define MPIC_GLOBAL_GCONF_8259_PTHROU_DIS 0x20000000
|
||||
#define MPIC_GLOBAL_GCONF_NO_BIAS 0x10000000
|
||||
#define MPIC_GLOBAL_GCONF_BASE_MASK 0x000fffff
|
||||
#define MPIC_GLOBAL_GCONF_MCK 0x08000000
|
||||
|
||||
/* Vendor Interrupt Type Configuration Register */
|
||||
|
||||
#define MPIC_VENDOR_TYPE_MCB_MASK 0x1F /* Lower MachineCheck Border */
|
||||
#define MPIC_VENDOR_TYPE_MCB_SHIFT 8
|
||||
#define MPIC_VENDOR_TYPE_CRB_MASK 0x1F /* Lower Critical Interrupt */
|
||||
/* Border */
|
||||
|
||||
/* Vector Destination Register */
|
||||
|
||||
#define MPIC_CPUID_DST_MASK 0x0000000F
|
||||
#define MPIC_CPUID_DST(cpuid) (1 << (cpuid))
|
||||
|
||||
/* General vector configuration */
|
||||
|
||||
#define MPIC_MAX_EXT_VEC 128
|
||||
#define MPIC_SPUR_VEC 255
|
||||
#define MPIC_MAX_IPI_IRQS 4
|
||||
#define MPIC_IPI0_VEC (MPIC_SPUR_VEC - 4)
|
||||
#define MPIC_IPI1_VEC (MPIC_IPI0_VEC + 1)
|
||||
#define MPIC_IPI2_VEC (MPIC_IPI0_VEC + 2)
|
||||
#define MPIC_IPI3_VEC (MPIC_IPI0_VEC + 3)
|
||||
|
||||
#define MPIC_MAX_TIMER_IRQS 4
|
||||
#define MPIC_TIMER0_VEC (MPIC_IPI0_VEC - 4)
|
||||
|
||||
#define MPIC_PRI_DEF 10
|
||||
#define MPIC_PRIORITY_MIN 0 /* lowest priority */
|
||||
#define MPIC_PRIORITY_MAX 15 /* highest priority */
|
||||
|
||||
/* Register Access Macro */
|
||||
|
||||
#define MPIC_PIN_TO_VEC_ADDR(pin) (MPIC_VP0_REG + ((pin) * 0x20))
|
||||
#define MPIC_PIN_TO_DST_ADDR(pin) (MPIC_DST0_REG + ((pin) * 0x20))
|
||||
|
||||
#define MPIC_IPIID_TO_DPATCH_ADDR(id) (MPIC_IPI_DPATCH_REG0 + ((id) * 0x10))
|
||||
#define MPIC_IPIID_TO_IVP_ADDR(id) (MPIC_IPI_VEC_REG0 + ((id) * 0x10))
|
||||
|
||||
#define MPIC_TIMERID_TO_DPATCH_ADDR(id) (MPIC_TDST0_REG + ((id) * 0x40))
|
||||
#define MPIC_TIMERID_TO_IVP_ADDR(id) (MPIC_TVP0_REG + ((id) * 0x40))
|
||||
#define MPIC_CPUID_TO_CTASK_PRI_ADDR(id) (MPIC_CTASK_PRI_REG + ((id) * 0x1000))
|
||||
#define MPIC_CPUID_TO_EOI_ADDR(id) (MPIC_EOI_P0_REG + ((id) * 0x1000))
|
||||
|
||||
/* MPIC driver resource flags bit defines */
|
||||
|
||||
#define MPIC_REG_DCR 0x00000000
|
||||
#define MPIC_REG_MEM 0x00000001
|
||||
#define MPIC_REG_MEM_BE 0x00000002
|
||||
#define MPIC_REG_MEM_LE 0x00000004
|
||||
#define MPIC_QUIRK_WHOAMI 0x00000008
|
||||
#define MPIC_QUIRK_NO_REG 0x00000010
|
||||
#define MPIC_QUIRK_IACK 0x00000020
|
||||
|
||||
#define MPIC_REG_ACS_MASK 0x00000003
|
||||
|
||||
/* The number of IRQ trigger table's entry */
|
||||
|
||||
#define TRIG_ENTRY_NUM 256
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbMpicIntCtlrh */
|
||||
@@ -0,0 +1,105 @@
|
||||
/* vxbOmap35xxIntCtlr.h - interrupt controller for TI OMAP CPU */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008-2009, 2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,07jul11,clx add definitions to support 128 interrupts.
|
||||
01b,02mar09,m_h cleanup
|
||||
01a,01jul08,m_h created
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbOmap35xxIntCtlrh
|
||||
#define __INCvxbOmap35xxIntCtlrh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/********* Bitmaps defining default setup values *********/
|
||||
|
||||
/* Priority Threshold. Default = disabled */
|
||||
#define OMAP_DEFAULT_PRIORITY_THRESHOLD 0xff
|
||||
|
||||
/* power saving through INTCPS_IDLE latency */
|
||||
#define OMAP_DEFAULT_LATENCY 0x00000000
|
||||
|
||||
/* Soft reset with autoidle */
|
||||
#define OMAP_DEFAULT_SYSCONFIG 0x00000003
|
||||
|
||||
/* Protection disabled */
|
||||
#define OMAP_DEFAULT_PROTECTION 0x00000000
|
||||
|
||||
/* Enable IRQ, not FIQ */
|
||||
#define OMAP_INTCPS_CONTROL_NEWIRQAGR 0x00000001
|
||||
|
||||
|
||||
/************ Register Offsets *****************/
|
||||
|
||||
#define OMAP_INTCPS_SYSCONFIG (0x0010)
|
||||
#define OMAP_INTCPS_SYSSTATUS (0x0014)
|
||||
#define OMAP_INTCPS_SIR_IRQ (0x0040)
|
||||
#define OMAP_INTCPS_SIR_FIQ (0x0044)
|
||||
#define OMAP_INTCPS_CONTROL (0x0048)
|
||||
#define OMAP_INTCPS_PROTECTION (0x004C)
|
||||
#define OMAP_INTCPS_IDLE (0x0050)
|
||||
#define OMAP_INTCPS_IRQ_PRIORITY (0x0060)
|
||||
#define OMAP_INTCPS_FIQ_PRIORITY (0x0064)
|
||||
#define OMAP_INTCPS_THRESHOLD (0x0068)
|
||||
#define OMAP_INTCPS_ITR0 (0x0080 + (0x20 * 0))
|
||||
#define OMAP_INTCPS_ITR1 (0x0080 + (0x20 * 1))
|
||||
#define OMAP_INTCPS_ITR2 (0x0080 + (0x20 * 2))
|
||||
#define OMAP_INTCPS_ITR3 (0x0080 + (0x20 * 3))
|
||||
#define OMAP_INTCPS_MIR0 (0x0084 + (0x20 * 0))
|
||||
#define OMAP_INTCPS_MIR1 (0x0084 + (0x20 * 1))
|
||||
#define OMAP_INTCPS_MIR2 (0x0084 + (0x20 * 2))
|
||||
#define OMAP_INTCPS_MIR3 (0x0084 + (0x20 * 3))
|
||||
#define OMAP_INTCPS_MIR_CLEAR0 (0x0088 + (0x20 * 0))
|
||||
#define OMAP_INTCPS_MIR_CLEAR1 (0x0088 + (0x20 * 1))
|
||||
#define OMAP_INTCPS_MIR_CLEAR2 (0x0088 + (0x20 * 2))
|
||||
#define OMAP_INTCPS_MIR_CLEAR3 (0x0088 + (0x20 * 3))
|
||||
#define OMAP_INTCPS_MIR_SET0 (0x008C + (0x20 * 0))
|
||||
#define OMAP_INTCPS_MIR_SET1 (0x008C + (0x20 * 1))
|
||||
#define OMAP_INTCPS_MIR_SET2 (0x008C + (0x20 * 2))
|
||||
#define OMAP_INTCPS_MIR_SET3 (0x008C + (0x20 * 3))
|
||||
#define OMAP_INTCPS_ISR_SET0 (0x0090 + (0x20 * 0))
|
||||
#define OMAP_INTCPS_ISR_SET1 (0x0090 + (0x20 * 1))
|
||||
#define OMAP_INTCPS_ISR_SET2 (0x0090 + (0x20 * 2))
|
||||
#define OMAP_INTCPS_ISR_SET3 (0x0090 + (0x20 * 3))
|
||||
#define OMAP_INTCPS_ISR_CLEAR0 (0x0094 + (0x20 * 0))
|
||||
#define OMAP_INTCPS_ISR_CLEAR1 (0x0094 + (0x20 * 1))
|
||||
#define OMAP_INTCPS_ISR_CLEAR2 (0x0094 + (0x20 * 2))
|
||||
#define OMAP_INTCPS_ISR_CLEAR3 (0x0094 + (0x20 * 3))
|
||||
#define OMAP_INTCPS_PENDING_IRQ0 (0x0098 + (0x20 * 0))
|
||||
#define OMAP_INTCPS_PENDING_IRQ1 (0x0098 + (0x20 * 1))
|
||||
#define OMAP_INTCPS_PENDING_IRQ2 (0x0098 + (0x20 * 2))
|
||||
#define OMAP_INTCPS_PENDING_IRQ3 (0x0098 + (0x20 * 3))
|
||||
#define OMAP_INTCPS_PENDING_FIQ0 (0x009C + (0x20 * 0))
|
||||
#define OMAP_INTCPS_PENDING_FIQ1 (0x009C + (0x20 * 1))
|
||||
#define OMAP_INTCPS_PENDING_FIQ2 (0x009C + (0x20 * 2))
|
||||
#define OMAP_INTCPS_ILR(m) (0x0100 + (0x4 * (m)))
|
||||
|
||||
#define OMAP_INTCPS_ITR(n) (0x0080 + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_MIR(n) (0x0084 + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_MIR_CLEAR(n) (0x0088 + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_MIR_SET(n) (0x008C + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_ISR_SET(n) (0x0090 + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_ISR_SET(n) (0x0090 + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_PENDING_IRQ(n) (0x0098 + (0x20 * (n)))
|
||||
#define OMAP_INTCPS_PENDING_FIQ(n) (0x009C + (0x20 * (n)))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbOmap35xxIntCtlrh */
|
||||
|
||||
@@ -0,0 +1,73 @@
|
||||
/* vxbPpc4xxUicIntCtlr.h - PPC4xx Universal Interrupt Controller driver */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,31mar08,b_m written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
|
||||
This header file supplies several UIC interrupt attributes macros that are
|
||||
expected to be used in hwconf.c by a specific BSP that uses this driver.
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbPpc4xxUicIntCtlrh
|
||||
#define __INCvxbPpc4xxUicIntCtlrh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* UIC Registers Offsets */
|
||||
|
||||
#define UIC_SR 0x00 /* Status Register */
|
||||
#define UIC_SSR 0x01 /* Set Status Register */
|
||||
#define UIC_ER 0x02 /* Enable Register */
|
||||
#define UIC_CR 0x03 /* Critical Register */
|
||||
#define UIC_PR 0x04 /* Polarity Register */
|
||||
#define UIC_TR 0x05 /* Trigger Register */
|
||||
#define UIC_MSR 0x06 /* Masked Status Register */
|
||||
#define UIC_VR 0x07 /* Vector Register */
|
||||
#define UIC_VCR 0x08 /* Vector Configuration Register */
|
||||
|
||||
#define UIC_NAME "uic"
|
||||
|
||||
/* Vector Configuration Register */
|
||||
|
||||
#define UIC_PRI_HIGHEST_SR0 0x00000001
|
||||
#define UIC_PRI_HIGHEST_SR31 0x00000000
|
||||
|
||||
/* UIC Interrupt Attributes */
|
||||
|
||||
#define UIC_INT_NORMAL 0x00
|
||||
#define UIC_INT_CRITICAL 0x01
|
||||
|
||||
#define UIC_INT_LEVEL_LOW 0x00
|
||||
#define UIC_INT_LEVEL_HIGH 0x02
|
||||
|
||||
#define UIC_INT_EDGE_FALLING 0x00
|
||||
#define UIC_INT_EDGE_RISING 0x04
|
||||
|
||||
#define UIC_INT_LEVEL 0x00
|
||||
#define UIC_INT_EDGE 0x08
|
||||
|
||||
#define UIC_INT_MAX_NUM 32
|
||||
|
||||
#define UIC_PIN_TO_BIT(pin) (0x00000001 << (31 - (pin)))
|
||||
#define UIC_PIN_TO_MASK(pin) (0xffffffff << (32 - (pin)))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INCvxbPpc4xxUicIntCtlrh */
|
||||
@@ -0,0 +1,201 @@
|
||||
/* vxbPxa3xxGpioIntCtlr.h - Gpio interrupt controller for PXA3XX */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,03mar09,d_l created.
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbPxa3xxGpioIntCtlrh
|
||||
#define __INCvxbPxa3xxGpioIntCtlrh
|
||||
|
||||
#include <vxWorks.h>
|
||||
#include <vxBusLib.h>
|
||||
#include <hwif/vxbus/vxBus.h>
|
||||
|
||||
/* defines */
|
||||
|
||||
#define GPIO_EDGE_NONE 0
|
||||
#define GPIO_EDGE_RISE 1
|
||||
#define GPIO_EDGE_FALL 2
|
||||
#define GPIO_EDGE_BOTH 3
|
||||
|
||||
#define GPIO_DIR_IN 0
|
||||
#define GPIO_DIR_OUT 1
|
||||
|
||||
#define GPIO_LEVEL_LOW 0
|
||||
#define GPIO_LEVEL_HIGH 1
|
||||
|
||||
#define GPIO_NORMAL 0
|
||||
#define GPIO_INTERRUPT 1
|
||||
|
||||
/* default definitions */
|
||||
|
||||
#ifndef GPIO_BIT
|
||||
# define GPIO_BIT(_bitNumber) (1 << (_bitNumber))
|
||||
#endif /* GPIO_BIT */
|
||||
|
||||
#ifndef PXA3XX_GPIO_BASE
|
||||
# define PXA3XX_GPIO_BASE (PXA3XX_PERIPHERAL_BASE + 0x00E00000)
|
||||
#endif /* PXA3XX_GPIO_BASE */
|
||||
|
||||
#define PXA3XX_GPIO_REG_COUNT 3
|
||||
#define BULVERDE_GPIO_REG_COUNT 4
|
||||
#define PXA3XX_GPIO_PIN_MAX 80
|
||||
#define BULVERDE_GPIO_PIN_MAX 120
|
||||
#define PXA3XX_GPIO_PIN_MIN 0
|
||||
#define BULVERDE_GPIO_PIN_MIN PXA3XX_GPIO_PIN_MIN
|
||||
#define PXA3XX_GPIO_INT_NUM 78 /* number of gpio interrupts */
|
||||
#define GPIO_INT_LEVEL_MIN 0
|
||||
#define GPIO_INT_LEVEL_MAX (BULVERDE_GPIO_PIN_MAX - 2)
|
||||
#define PXA3XX_GPIO_INT_2TO80 78 /* number of 2nd lvl gpio interrupts */
|
||||
#define PXA3XX_GPIO_INT_80 PXA3XX_GPIO_PIN_MAX
|
||||
#define BULVERDE_GPIO_INT_120 BULVERDE_GPIO_PIN_MAX
|
||||
#define PXA3XX_GPIO_INT_2 2
|
||||
#define PXA3XX_GPIO_INT_1 1
|
||||
#define BULVERDE_GPIO_INT_1 1
|
||||
#define PXA3XX_GPIO_INT_2TO80MASK 0x0ffff800
|
||||
|
||||
/* GPIO pin level register */
|
||||
|
||||
#define PXA3XX_GPIO_GPLR_HI 1 /* pin level high */
|
||||
#define PXA3XX_GPIO_GPLR_LO 0 /* pin level low */
|
||||
|
||||
/* GPIO pin Direction register */
|
||||
|
||||
#define PXA3XX_GPIO_GPDR_OUT 1 /* pin direction as output */
|
||||
#define PXA3XX_GPIO_GPDR_IN 0 /* pin direction as input */
|
||||
|
||||
/* GPIO pin output set register */
|
||||
|
||||
#define PXA3XX_GPIO_GPSR_SET 1 /* set pin level to high */
|
||||
|
||||
/* GPIO pin output clear register */
|
||||
|
||||
#define PXA3XX_GPIO_GPCR_SET 1 /* clear pin level to zero */
|
||||
|
||||
/* GPIO pin rising edge register */
|
||||
|
||||
#define PXA3XX_GPIO_GRER_RISING 1 /* set gpio to rising edge */
|
||||
|
||||
/* GPIO pin falling edge register */
|
||||
|
||||
#define PXA3XX_GPIO_GFER_FALLING 1 /* set gpio to falling edge */
|
||||
|
||||
#define PXA3XX_GPIO_INT_RISING 0x01 /* software GPIO_BIT flag */
|
||||
#define PXA3XX_GPIO_INT_FALLING 0x02 /* software GPIO_BIT flag */
|
||||
|
||||
/* GPIO pin edge detect register */
|
||||
|
||||
#define PXA3XX_GPIO_GEDR_DETECT 1 /* edge detect has occured */
|
||||
#define PXA3XX_GPIO_GEDR_RESET 0x0fffffff
|
||||
|
||||
/* registers definition */
|
||||
|
||||
/* General Purpose I/O Registers */
|
||||
|
||||
#define PXA3XX_GPIO_GPLR 0x40E00000 /* GPIO Pin Level (31-0) */
|
||||
#define PXA3XX_GPIO_GPLR_x 0x40E00000 /* GPIO Pin Level (31-0) */
|
||||
#define PXA3XX_GPIO_GPLR_y 0x40E00004 /* GPIO Pin Level (63-32) */
|
||||
#define PXA3XX_GPIO_GPLR_z 0x40E00008 /* GPIO Pin Level (84-64) */
|
||||
#define PXA3XX_GPIO_GPDR 0x40E0000C /* GPIO Pin Direction (31-0) */
|
||||
#define PXA3XX_GPIO_GPDR_x 0x40E0000C /* GPIO Pin Direction (31-0) */
|
||||
#define PXA3XX_GPIO_GPDR_y 0x40E00010 /* GPIO Pin Direction (63-32) */
|
||||
#define PXA3XX_GPIO_GPDR_z 0x40E00014 /* GPIO Pin Direction (84-64) */
|
||||
#define PXA3XX_GPIO_GPSR 0x40E00018 /* GPIO Output Set (31-0) */
|
||||
#define PXA3XX_GPIO_GPSR_x 0x40E00018 /* GPIO Output Set (31-0) */
|
||||
#define PXA3XX_GPIO_GPSR_y 0x40E0001C /* GPIO Output Set (63-32) */
|
||||
#define PXA3XX_GPIO_GPSR_z 0x40E00020 /* GPIO Output Set (84-64) */
|
||||
#define PXA3XX_GPIO_GPCR 0x40E00024 /* GPIO Output Clear (31-0) */
|
||||
#define PXA3XX_GPIO_GPCR_x 0x40E00024 /* GPIO Output Clear (31-0) */
|
||||
#define PXA3XX_GPIO_GPCR_y 0x40E00028 /* GPIO Output Clear (63-32) */
|
||||
#define PXA3XX_GPIO_GPCR_z 0x40E0002C /* GPIO Output Clear (84-64) */
|
||||
#define PXA3XX_GPIO_GRER 0x40E00030 /* GPIO Rising Edge Detect Enable (31-0) */
|
||||
#define PXA3XX_GPIO_GRER_x 0x40E00030 /* GPIO Rising Edge Detect Enable (31-0) */
|
||||
#define PXA3XX_GPIO_GRER_y 0x40E00034 /* GPIO Rising Edge Detect Enable (63-32) */
|
||||
#define PXA3XX_GPIO_GRER_z 0x40E00038 /* GPIO Rising Edge Detect Enable (84-64) */
|
||||
#define PXA3XX_GPIO_GFER 0x40E0003C /* GPIO Falling Edge Detect Enable (31-0) */
|
||||
#define PXA3XX_GPIO_GFER_x 0x40E0003C /* GPIO Falling Edge Detect Enable (31-0) */
|
||||
#define PXA3XX_GPIO_GFER_y 0x40E00040 /* GPIO Falling Edge Detect Enable (63-32) */
|
||||
#define PXA3XX_GPIO_GFER_z 0x40E00044 /* GPIO Falling Edge Detect Enable (84-64) */
|
||||
#define PXA3XX_GPIO_GEDR 0x40E00048 /* GPIO Edge Detect Status (31-0) */
|
||||
#define PXA3XX_GPIO_GEDR_x 0x40E00048 /* GPIO Edge Detect Status (31-0) */
|
||||
#define PXA3XX_GPIO_GEDR_y 0x40E0004C /* GPIO Edge Detect Status (63-32) */
|
||||
#define PXA3XX_GPIO_GEDR_z 0x40E00050 /* GPIO Edge Detect Status (84-64) */
|
||||
#define PXA3XX_GPIO_GAFR0_x 0x40E00054 /* GPIO Alternate Function Select (31-0) */
|
||||
#define PXA3XX_GPIO_GAFR1_x 0x40E00058 /* GPIO Alternate Function Select (31-0) */
|
||||
#define PXA3XX_GPIO_GAFR0_y 0x40E0005C /* GPIO Alternate Function Select (63-32) */
|
||||
#define PXA3XX_GPIO_GAFR1_y 0x40E00060 /* GPIO Alternate Function Select (63-32) */
|
||||
#define PXA3XX_GPIO_GAFR0_z 0x40E00064 /* GPIO Alternate Function Select (84-64) */
|
||||
#define PXA3XX_GPIO_GAFR1_z 0x40E00068 /* GPIO Alternate Function Select (84-64) */
|
||||
|
||||
/* Index */
|
||||
|
||||
#define PXA3XX_GPIO_GPLR_x_IDX 0x00000000 /* GPIO Pin Level (31-0) */
|
||||
#define PXA3XX_GPIO_GPLR_y_IDX 0x00000004 /* GPIO Pin Level (63-32) */
|
||||
#define PXA3XX_GPIO_GPLR_z_IDX 0x00000008 /* GPIO Pin Level (95-64) */
|
||||
#define PXA3XX_GPIO_GPDR_x_IDX 0x0000000C /* GPIO Pin Direction (31-0) */
|
||||
#define PXA3XX_GPIO_GPDR_y_IDX 0x00000010 /* GPIO Pin Direction (63-32) */
|
||||
#define PXA3XX_GPIO_GPDR_z_IDX 0x00000014 /* GPIO Pin Direction (95-64) */
|
||||
#define PXA3XX_GPIO_GPDR_3_IDX 0x0000010C /* GPIO Pin Direction (127-96) */
|
||||
#define PXA3XX_GPIO_GPSR_x_IDX 0x00000018 /* GPIO Output Set (31-0) */
|
||||
#define PXA3XX_GPIO_GPSR_y_IDX 0x0000001C /* GPIO Output Set (63-32) */
|
||||
#define PXA3XX_GPIO_GPSR_z_IDX 0x00000020 /* GPIO Output Set (95-64) */
|
||||
#define PXA3XX_GPIO_GPSR_3_IDX 0x00000118 /* GPIO Output Set (127-96) */
|
||||
#define PXA3XX_GPIO_GPCR_x_IDX 0x00000024 /* GPIO Output Clear (31-0) */
|
||||
#define PXA3XX_GPIO_GPCR_y_IDX 0x00000028 /* GPIO Output Clear (63-32) */
|
||||
#define PXA3XX_GPIO_GPCR_z_IDX 0x0000002C /* GPIO Output Clear (95-64) */
|
||||
#define PXA3XX_GPIO_GPCR_3_IDX 0x00000124 /* GPIO Output Clear (127-96) */
|
||||
#define PXA3XX_GPIO_GRER_x_IDX 0x00000030 /* GPIO Rising Edge Detect Enable (31-0) */
|
||||
#define PXA3XX_GPIO_GRER_y_IDX 0x00000034 /* GPIO Rising Edge Detect Enable (63-32) */
|
||||
#define PXA3XX_GPIO_GRER_z_IDX 0x00000038 /* GPIO Rising Edge Detect Enable (95-64) */
|
||||
#define PXA3XX_GPIO_GRER_3_IDX 0x00000130 /* GPIO Rising Edge Detect Enable (127-96) */
|
||||
#define PXA3XX_GPIO_GFER_x_IDX 0x0000003C /* GPIO Falling Edge Detect Enable (31-0) */
|
||||
#define PXA3XX_GPIO_GFER_y_IDX 0x00000040 /* GPIO Falling Edge Detect Enable (63-32) */
|
||||
#define PXA3XX_GPIO_GFER_z_IDX 0x00000044 /* GPIO Falling Edge Detect Enable (95-64) */
|
||||
#define PXA3XX_GPIO_GFER_3_IDX 0x0000013C /* GPIO Falling Edge Detect Enable (127-96) */
|
||||
#define PXA3XX_GPIO_GEDR_x_IDX 0x00000048 /* GPIO Edge Detect Status (31-0) */
|
||||
#define PXA3XX_GPIO_GEDR_y_IDX 0x0000004C /* GPIO Edge Detect Status (63-32) */
|
||||
#define PXA3XX_GPIO_GEDR_z_IDX 0x00000050 /* GPIO Edge Detect Status (95-64) */
|
||||
#define PXA3XX_GPIO_GEDR_3_IDX 0x00000138 /* GPIO Edge Detect Status (127-96) */
|
||||
#define PXA3XX_GPIO_GAFR0_x_IDX 0x00000054 /* GPIO Alternate Function Select (31-0) */
|
||||
#define PXA3XX_GPIO_GAFR1_x_IDX 0x00000058 /* GPIO Alternate Function Select (31-0) */
|
||||
#define PXA3XX_GPIO_GAFR0_y_IDX 0x0000005C /* GPIO Alternate Function Select (63-32) */
|
||||
#define PXA3XX_GPIO_GAFR1_y_IDX 0x00000060 /* GPIO Alternate Function Select (63-32) */
|
||||
#define PXA3XX_GPIO_GAFR0_z_IDX 0x00000064 /* GPIO Alternate Function Select (95-64) */
|
||||
#define PXA3XX_GPIO_GAFR1_z_IDX 0x00000068 /* GPIO Alternate Function Select (95-64) */
|
||||
#define PXA3XX_GPIO_GAFR0_3_IDX 0x0000006C /* GPIO Alternate Function Select (127-96) */
|
||||
#define PXA3XX_GPIO_GAFR1_3_IDX 0x00000070 /* GPIO Alternate Function Select (127-96) */
|
||||
|
||||
typedef struct pxa3xxGpioIntCtlrInput
|
||||
{
|
||||
int pin;
|
||||
char * pName;
|
||||
char edge;
|
||||
char dir;
|
||||
char defaultLevel;
|
||||
char usage;
|
||||
} PXA3XX_GPIO_INTCTLR_INPUT;
|
||||
|
||||
/*
|
||||
* PXA3XX GPIO Register Setup Structure
|
||||
*
|
||||
* Filled in by the bsp in sysLib.c and parsed by
|
||||
* pxa3xxGpioHwInit. It must be NULL terminated.
|
||||
*/
|
||||
|
||||
typedef struct pxa3xxGpioRegInit
|
||||
{
|
||||
UINT32 regAddr;
|
||||
UINT32 regVal;
|
||||
} PXA3XX_GPIO_REG_INIT;
|
||||
|
||||
#endif /* __INCvxbPxa3xxGpioIntCtlrh */
|
||||
@@ -0,0 +1,96 @@
|
||||
/* vxbQeIntCtlr.h - Quicc Engine interrupt controller header file */
|
||||
|
||||
/* Copyright (c) 2007 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,03jun07,dtr adapted from qeIntrCtl.h.
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbQeIntCtlrh
|
||||
#define __INCvxbQeIntCtlrh
|
||||
|
||||
#include "vxWorks.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST(x)
|
||||
#else /* _ASMLANGUAGE */
|
||||
#define CAST(x) (x)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef QE_IVEC_TO_INUM
|
||||
# undef QE_IVEC_TO_INUM
|
||||
#endif /* IVEC_TO_INUM */
|
||||
|
||||
#ifdef QE_INUM_TO_IVEC
|
||||
# undef QE_INUM_TO_IVEC
|
||||
#endif /* INUM_TO_IVEC */
|
||||
|
||||
#define QE_IVEC_TO_INUM(intVec) (qeIvecToInum(intVec))
|
||||
#define QE_INUM_TO_IVEC(intNum) (qeInumToIvec(intNum))
|
||||
|
||||
#define QE_INUM_MAX 64
|
||||
#define QE_IVEC_MAX 64
|
||||
#ifndef _ASMLANGUAGE
|
||||
#define CAST(x) (x)
|
||||
#ifndef VUINT32
|
||||
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
|
||||
#endif
|
||||
#else
|
||||
#define CAST(x)
|
||||
#endif
|
||||
|
||||
#define QE_CICR(base) ((VUINT32 *) ((base) + 0x80)) /* interrupt configuration Register */
|
||||
#define QE_CIVEC(base) ((VUINT32 *) ((base) + 0x84))
|
||||
#define QE_CRIPNR(base) ((VUINT32 *) ((base) + 0x88))
|
||||
#define QE_CIPNR(base) ((VUINT32 *) ((base) + 0x8C))
|
||||
#define QE_CIPXCC(base) ((VUINT32 *) ((base) + 0x90))
|
||||
#define QE_CIPYCC(base) ((VUINT32 *) ((base) + 0x94))
|
||||
#define QE_CIPWCC(base) ((VUINT32 *) ((base) + 0x98))
|
||||
#define QE_CIPZCC(base) ((VUINT32 *) ((base) + 0x9C))
|
||||
#define QE_CIMR(base) ((VUINT32 *) ((base) + 0xA0))
|
||||
#define QE_CRIMR(base) ((VUINT32 *) ((base) + 0xA4))
|
||||
#define QE_CICNR(base) ((VUINT32 *) ((base) + 0xA8))
|
||||
#define QE_CIPRTA(base) ((VUINT32 *) ((base) + 0xB0))
|
||||
#define QE_CIPRTB(base) ((VUINT32 *) ((base) + 0xB4))
|
||||
#define QE_CRIC(base) ((VUINT32 *) ((base) + 0xBC))
|
||||
#define QE_CHIVEC(base) ((VUINT32 *) ((base) + 0xE0))
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
typedef struct qe_intr_handler
|
||||
{
|
||||
VOIDFUNCPTR vec; /* interrupt vector */
|
||||
int arg; /* interrupt handler argument */
|
||||
void *pNext;
|
||||
} QE_INTR_HANDLER;
|
||||
|
||||
/* SIU Interrupt Mask structure; a value for the high and low parts */
|
||||
typedef struct qe_siu_int_mask
|
||||
{
|
||||
UINT32 crimr;
|
||||
UINT32 cimr;
|
||||
} QE_SIU_INT_MASK;
|
||||
|
||||
/* function declarations */
|
||||
|
||||
IMPORT STATUS vxbQeIntrInit ();
|
||||
extern STATUS vxbQeIntDisable (int );
|
||||
IMPORT STATUS vxbQeIntEnable (int );
|
||||
extern int qeIvecToInum(VOIDFUNCPTR *);
|
||||
extern VOIDFUNCPTR * qeInumToIvec(int);
|
||||
extern void vxbQeIntCtlrRegister(void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbQeIntCtlrh */
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
/* vxbQuiccIntCtlr.h - PowerQuicc interrupt controller header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005, 2008, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,29jul10,pad Moved extern C statement after include statements.
|
||||
01b,21feb08,x_s Support 8377 version of interrupt controller.
|
||||
01a,10jan05,dtr created from quiccIntrCtl.h/01b.
|
||||
*/
|
||||
|
||||
#ifndef __INCvxbQuiccIntCtlrh
|
||||
#define __INCvxbQuiccIntCtlrh
|
||||
|
||||
#include <vxWorks.h>
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST(x)
|
||||
#else /* _ASMLANGUAGE */
|
||||
#include <vxBusLib.h>
|
||||
#define CAST(x) (x)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef IVEC_TO_INUM
|
||||
# undef IVEC_TO_INUM
|
||||
#endif /* IVEC_TO_INUM */
|
||||
|
||||
#ifdef INUM_TO_IVEC
|
||||
# undef INUM_TO_IVEC
|
||||
#endif /* INUM_TO_IVEC */
|
||||
|
||||
#define IVEC_TO_INUM(intVec) (quiccIvecToInum(intVec))
|
||||
#define INUM_TO_IVEC(intNum) (quiccInumToIvec(intNum))
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#define CAST(x) (x)
|
||||
#ifndef VUINT32
|
||||
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
|
||||
#endif
|
||||
#else
|
||||
#define CAST(x)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#define QUICC_IVEC_MAX 128
|
||||
/* Interrupt Controller Registers */
|
||||
|
||||
#define QUICC_SICR(base) ((VUINT32 *) ((base) + 0x000))
|
||||
#define QUICC_SIVEC(base) ((VUINT32 *) ((base) + 0x004))
|
||||
#define QUICC_SIPNR_H(base) ((VUINT32 *) ((base) + 0x008))
|
||||
#define QUICC_SIPNR_L(base) ((VUINT32 *) ((base) + 0x00C))
|
||||
|
||||
#define QUICC_SIPRR_A(base) ((VUINT32 *) ((base) + 0x010))
|
||||
|
||||
#define QUICC_SIPRR_D(base) ((VUINT32 *) ((base) + 0x01C))
|
||||
|
||||
#define QUICC_SIMR_H(base) ((VUINT32 *) ((base) + 0x020))
|
||||
#define QUICC_SIMR_L(base) ((VUINT32 *) ((base) + 0x024))
|
||||
|
||||
#define QUICC_SICNR(base) ((VUINT32 *) ((base) + 0x028))
|
||||
#define QUICC_SEPNR(base) ((VUINT32 *) ((base) + 0x02C))
|
||||
#define QUICC_SMPRR_A(base) ((VUINT32 *) ((base) + 0x030))
|
||||
#define QUICC_SMPRR_B(base) ((VUINT32 *) ((base) + 0x034))
|
||||
|
||||
#define QUICC_SEMSR(base) ((VUINT32 *) ((base) + 0x038))
|
||||
#define QUICC_SECNR(base) ((VUINT32 *) ((base) + 0x03C))
|
||||
|
||||
#define QUICC_SERSR(base) ((VUINT32 *) ((base) + 0x040))
|
||||
#define QUICC_SERMR(base) ((VUINT32 *) ((base) + 0x044))
|
||||
#define QUICC_SERCR(base) ((VUINT32 *) ((base) + 0x048))
|
||||
#define QUICC_SEPCR(base) ((VUINT32 *) ((base) + 0x04C))
|
||||
|
||||
|
||||
|
||||
#define QUICC_SIFCR_H(base) ((VUINT32 *) ((base) + 0x050))
|
||||
#define QUICC_SIFCR_L(base) ((VUINT32 *) ((base) + 0x054))
|
||||
#define QUICC_SEFCR(base) ((VUINT32 *) ((base) + 0x058))
|
||||
#define QUICC_SERFR(base) ((VUINT32 *) ((base) + 0x05C))
|
||||
#define QUICC_SCVCR(base) ((VUINT32 *) ((base) + 0x060))
|
||||
#define QUICC_SMVCR(base) ((VUINT32 *) ((base) + 0x064))
|
||||
|
||||
#define QUICC_MSIR0(base) ((VUINT32 *) ((base) + 0x0C0))
|
||||
#define QUICC_MSIR1(base) ((VUINT32 *) ((base) + 0x0C4))
|
||||
#define QUICC_MSIR2(base) ((VUINT32 *) ((base) + 0x0C8))
|
||||
#define QUICC_MSIR3(base) ((VUINT32 *) ((base) + 0x0CC))
|
||||
#define QUICC_MSIR4(base) ((VUINT32 *) ((base) + 0x0D0))
|
||||
#define QUICC_MSIR5(base) ((VUINT32 *) ((base) + 0x0D4))
|
||||
#define QUICC_MSIR6(base) ((VUINT32 *) ((base) + 0x0D8))
|
||||
#define QUICC_MSIR7(base) ((VUINT32 *) ((base) + 0x0DC))
|
||||
|
||||
#define QUICC_MSIMR(base) ((VUINT32 *) ((base) + 0x0F0))
|
||||
#define QUICC_MSISR(base) ((VUINT32 *) ((base) + 0x0F4))
|
||||
#define QUICC_MSIIR(base) ((VUINT32 *) ((base) + 0x0F8))
|
||||
|
||||
/* interrupt handler */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
typedef struct intr_handler
|
||||
{
|
||||
VOIDFUNCPTR vec; /* interrupt vector */
|
||||
int arg; /* interrupt handler argument */
|
||||
void *pNext;
|
||||
} INTR_HANDLER;
|
||||
|
||||
typedef struct siu_int_mask
|
||||
{
|
||||
UINT32 simr_h;
|
||||
UINT32 simr_l;
|
||||
UINT32 semr;
|
||||
} SIU_INT_MASK;
|
||||
|
||||
/* function declarations */
|
||||
|
||||
IMPORT STATUS vxbSysQuiccIntrInit (VXB_DEVICE_ID pInst);
|
||||
extern STATUS vxbSysQuiccIntDisable (int );
|
||||
IMPORT STATUS vxbSysQuiccIntEnable (int );
|
||||
extern int quiccIvecToInum(VOIDFUNCPTR *);
|
||||
extern VOIDFUNCPTR * quiccInumToIvec(int);
|
||||
extern void vxbQuiccIntCtlrRegister(void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxbQuiccIntCtlrh */
|
||||
Reference in New Issue
Block a user