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/* dot11Bsp.h - Contains definitions used to communicate with the BSP */
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/* Copyright 2004 Wind River Systems, Inc. */
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/*
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Modification History
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--------------------
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02g,27feb08,hfc added entries for vxbus driver
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02f,01mar07,spw Moved device / vendor id definitions to this file
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02e,09sep05,rb Added countryCode as boot parameter
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02d,25jan05,rb Made security components optionally buildable
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02c,07jan05,rb Added members to dot11BspFuncs for 802.1X Integration
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02b,01nov04,rb Added settings for security policy
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02a,25aug04,rb Wind River Wireless Ethernet Driver 2.0 FCS
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*/
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/*
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DESCRIPTION
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This file contains the definitions necessary for the DOT11 Frameowrk to load
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the Atheros cards from the BSP, as defined in sysAr521xEnd.c
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*/
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#ifndef __INCdot11Bsph
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#define __INCdot11Bsph
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef VXBUS
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#include <hwif/vxbus/vxBus.h>
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#include <../src/hwif/h/vxbus/vxbAccess.h>
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#include <hwif/vxbus/vxbPciLib.h>
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#include <hwif/util/vxbDmaBufLib.h>
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#include <hwif/util/vxbParamSys.h>
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#endif /*VXBUS*/
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/* This structure is used to hold basic default WLAN configuration parameters
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that are used by the device driver on start up. They can be defined by
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the user through the project facility or by making modifications to this
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file and using the command line build option */
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typedef struct dot11_default_config_s
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{
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char* ssid; /* Default SSID */
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UINT32 mode; /* Default Station mode */
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UINT32 radio; /* Default radio */
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UINT32 channel; /* Default channel */
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UINT32 country;
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UINT32 secPol; /* Security Policy : a bitmap of allowed sec. policies */
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UINT32 authPol; /* Authentication Policy: specifies 802.1X or PSK */
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UINT32 ciphPol; /* Cipher Policy: Specifies list of allowed ciphers */
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UINT8 preSharedKey[64]; /* If authPol == PSK, then this contains the PSK*/
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char * rsnPassphrase;
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} DOT11_DEFAULT_CONFIG;
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#ifndef VXBUS
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typedef struct dot11_bsp_func
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{
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/* Connect interrupt handler to vector */
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void (*sysIntConnect)(int, int, int, STATUS*);
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/* Disconnect interrupt handler from vector */
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void (*sysIntDisconnect)(int, int, int, STATUS*);
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/* System level interrupt enable */
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void (*sysIntEnable)(INT32, STATUS*);
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/* System level interrupt disable */
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void (*sysIntDisable)(INT32, STATUS*);
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/* Micro second delay */
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void (*sysUsDelay)(int);
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/* Cache invalidate function */
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STATUS (*sysCacheInvalidate)(void*, UINT32);
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/* Cache flush function */
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STATUS (*sysCacheFlush)(void*, UINT32);
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/* Converts bus address to CPU address */
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UINT32 (*sysPhysToVirt) (UINT32);
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/* Converts CPU address to bus address */
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UINT32 (*sysVirtToPhys) (UINT32);
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/* Write buffer flush function */
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STATUS (*sysWbufFlush)();
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/* Memory poll deallocation function */
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void (*sysDmaMemFree)(UINT32);
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/* SME types declared here so that the configlettes / cmd line can
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include or exclude them at will */
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STATUS (*essInit)(DOT11_FW*);
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STATUS (*ibssInit)(DOT11_FW*);
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STATUS (*apInit)(DOT11_FW*);
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STATUS (*rsnInit)(DOT11_FW*);
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} DOT11_BSP_FUNC;
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typedef struct dot11_bsp_info
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{
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UINT32 magicNum; /* version */
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UINT32 memBaseAddr; /* Mem base */
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UINT32 ivec; /* IRQ vector */
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UINT32 ilevel; /* IRQ level */
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UINT16 pciVendorId; /* PCI Vendor Id */
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UINT16 pciSubVendorId; /* PCI Subvendor Id*/
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UINT16 pciDeviceId; /* PCI Dev ID */
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UINT16 pciSubDeviceId; /* PCI Sub dev Id */
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UINT32 dmaBuffAddr; /* DMA buffer addr */
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UINT32 dmaBufSize; /* dma Buffer Size */
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UINT32 cacheLineSz; /* cache line size */
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UINT32 cfgFlag; /* configuration flag */
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UINT8 pciChipSetRev; /* chipset version */
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DOT11_BSP_FUNC* binding; /* access function provided by BSP */
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DOT11_DEFAULT_CONFIG* config; /* Default configuration */
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} DOT11_BSP_INFO;
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#endif /* VXBUS */
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#define DOT11_BSP_INFO_VER_0 0x1001
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/*
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* Supported device and vendor IDs of AR521X devices. Newer chipset
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* versions or OEM versions will likely need new PCI_DEVICE_ID and/or
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* PCI_VENDOR_ID entries.
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*/
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/* AR5211 */
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#define AR5211_VENDOR_ID (0x168C)
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#define AR5211_DEFAULT (0x1112) /* No eeprom HW default */
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#define AR5311_DEVID (0x0011) /* Final ar5311 devid */
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#define AR5211_DEVID (0x0012) /* Final ar5211 devid */
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#define AR5211_LEGACY (0xFF12) /* Original emulation board */
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#define AR5211_FPGA11B (0xF11B) /* 11b emulation board */
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#define AR5211_SREV_1_0 (0x40)
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#define AR5211_SREV_1_1 (0x42)
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#define AR5211_SREV_REG (0x4020)
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/* AR5212 */
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#define AR5212_VENDOR_ID (0x168C)
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#define AR5212_DEFAULT (0x1113) /* No eeprom HW default */
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#define AR5212_DEVID (0x0013) /* ar5212 devid */
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#define AR5312_DEVID (0x0030) /* Final ar5312 devid */
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#define AR5212_SREV_1_0 (0x50)
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#define AR5212_SREV_1_1 (0x51)
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#define AR5212_SREV_1_3 (0x53)
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#define AR5212_SREV_1_4 (0x56)
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#define AR5212_SREV_REG (0x4020)
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/* AR5212 compatible devid's also attach to 5212 */
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#define AR5212_DEVID_0014 (0x0014) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_0015 (0x0015) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_0016 (0x0016) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_0017 (0x0017) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_0018 (0x0018) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_0019 (0x0019) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_001A (0x001A) /* ar5212 forward compatibility id */
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#define AR5212_DEVID_001B (0x001B) /* ar5212 forward compatibility id */
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/* AR5213 */
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#define AR5213_SREV_1_0 (0x55)
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#define AR5213_SREV_REG (0x4020)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCdot11Bsph */
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