original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,48 @@
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/* busLocal.h - sysBusToLocal/sysLocalToBus header */
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/* Copyright 1984-1992 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01b,22sep92,rrr added support for c++
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01a,16jun92,ccc created.
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*/
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/*
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DESCRIPTION
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This file contains header information for the sysBusToLocal() and
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sysLocalToBus() routines.
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*/
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#ifndef __INCbusLocalh
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#define __INCbusLocalh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* function declarations */
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#ifndef _ASMLANGUAGE
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT STATUS sysLocalToBusAdrs (int adrsSpace, char *localAdrs,
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char **pBusAdrs);
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IMPORT STATUS sysBusToLocalAdrs (int adrsSpace, char *busAdrs,
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char **pLocalAdrs);
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#else /* __STDC__ */
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IMPORT STATUS sysLocalToBusAdrs ();
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IMPORT STATUS sysBusToLocalAdrs ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCbusLocalh */
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@@ -0,0 +1,529 @@
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/* dga001Vme.h - Densan DGA-001 VMEbus Interface Controller */
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/* Copyright 1994-1997 Wind River Systems, Inc. */
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#include "copyright_wrs.h"
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/*
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modification history
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--------------------
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01l,12jul97,hk renamed as dga001Vme.h from drv/multi/dga001.h.
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01k,15jan96,hk added support for DVE-SH7043.
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01j,10nov95,hk changed CSR to DGA_CSR.
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01i,09nov95,hk fixed CSR1_1_RRS, but not used. did some code reviewing.
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01h,04jul95,hk modified some macro names.
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01g,07jun95,hk changed CSR20/CSR21 bit defs. copyright to '95.
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01f,15dec94,sa wrote CSR13_0, CSR15_0, CSR16_0, CSR17, IFR0, IFR1, IFR3.
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01e,14nov94,hk wrote CSR18_1.
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01d,09nov94,sa write CSR12, CSR14 and CSR23.
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01c,19oct94,sa write CSR19 to CSR21
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01b,08sep94,sa write to CSR7
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01a,07sep94,sa derived from 01e of vmechip.h.
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*/
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#ifdef DOC
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#define INCdga001Vmeh
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#endif /* DOC */
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#ifndef __INCdga001Vmeh
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#define __INCdga001Vmeh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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This file contains constants for the Densan DGA-001 VMEbus Interface.
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The macro DGA001_BASE_ADRS must be defined when using local bus addresses
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defined in this header. The macro IFR_BUS_BASE_ADRS must be defined when
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using VMEbus addresses defined in this header.
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The following standards have been adopted in the creation of this file.
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Registers in the CSR have the prefix "DGA_CSR". And "DGA_CSR0_0" means most
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low address of CSR0 register.
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Registers in the IFR have the prefix "DGA_IFR" when addressed locally and
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the prefix "IFR_BUS" when addressed from the VMEbus. The bit definitions
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are shared.
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The registers are listed in ascending (numerical) order; the definitions
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for each register start with a header, e.g.:
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Register Register Register Register
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Mnemonic Number Address Name
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| | | |
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v v v v
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/@***********************************************************************
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* CSR0_0 0x00 0x00 local bus control and status*
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***********************************************************************@/
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The format of the definitions is as follows. The define name always
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starts with the register mnemonic it is associated with. The [7-0]
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number at the end of the comment indicates the bit position to which the
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the define applies. In the definition of PURSTF, for example, the 7
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indicates bit 7:
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|
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v
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#define CSR1_0_PURSTF 0x80 /@ power-up status bit 7 @/
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If the define applies to more than one bit, then the applicable bit
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range is specified by two digits. In the following example,
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CSR0_LBT applies to the two bit field, bits 5-4:
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|
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v
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#define CSR0_0_LBT 0x10 /@ local bus time-out (mask) 54 @/
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If no bit field is given, then the define applies to the whole register.
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*/
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#define DGA001_LONG_ADRS(offset) \
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((volatile UINT32 *)(DGA001_BASE_ADRS + offset))
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#if defined(TARGET_DVE7604) || defined(TARGET_DVE7043)
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#define DGA001_BYTE_ADRS(offset) \
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((volatile UINT8 *)(DGA001_BASE_ADRS + DGA001_BYTE_ACCESS_OFFSET + offset))
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#else
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#define DGA001_BYTE_ADRS(offset) \
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((volatile UINT8 *)(DGA001_BASE_ADRS + offset))
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#endif /* TARGET_DVE7604 */
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/*
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* Control and Status Register (CSR) definitions.
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*
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* only the local CPU can access the LCSR.
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*/
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#define DGA_CSR0 DGA001_LONG_ADRS(0x00)
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#define DGA_CSR0_0 DGA001_BYTE_ADRS(0x00)
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#define DGA_CSR0_1 DGA001_BYTE_ADRS(0x01)
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#define DGA_CSR0_2 DGA001_BYTE_ADRS(0x02)
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#define DGA_CSR0_3 DGA001_BYTE_ADRS(0x03)
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#define DGA_CSR1 DGA001_LONG_ADRS(0x04)
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#define DGA_CSR1_0 DGA001_BYTE_ADRS(0x04)
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#define DGA_CSR1_1 DGA001_BYTE_ADRS(0x05)
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#define DGA_CSR1_2 DGA001_BYTE_ADRS(0x06)
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#define DGA_CSR1_3 DGA001_BYTE_ADRS(0x07)
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#define DGA_CSR2 DGA001_LONG_ADRS(0x08)
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#define DGA_CSR2_0 DGA001_BYTE_ADRS(0x08)
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#define DGA_CSR2_1 DGA001_BYTE_ADRS(0x09)
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#define DGA_CSR2_2 DGA001_BYTE_ADRS(0x0a)
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#define DGA_CSR2_3 DGA001_BYTE_ADRS(0x0b)
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#define DGA_CSR3 DGA001_LONG_ADRS(0x0c)
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#define DGA_CSR3_0 DGA001_BYTE_ADRS(0x0c)
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#define DGA_CSR3_1 DGA001_BYTE_ADRS(0x0d)
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#define DGA_CSR3_2 DGA001_BYTE_ADRS(0x0e)
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#define DGA_CSR3_3 DGA001_BYTE_ADRS(0x0f)
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#define DGA_CSR4 DGA001_LONG_ADRS(0x10)
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#define DGA_CSR4_0 DGA001_BYTE_ADRS(0x10)
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#define DGA_CSR4_1 DGA001_BYTE_ADRS(0x11)
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#define DGA_CSR4_2 DGA001_BYTE_ADRS(0x12)
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#define DGA_CSR4_3 DGA001_BYTE_ADRS(0x13)
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#define DGA_CSR5 DGA001_LONG_ADRS(0x14)
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#define DGA_CSR5_0 DGA001_BYTE_ADRS(0x14)
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#define DGA_CSR5_1 DGA001_BYTE_ADRS(0x15)
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#define DGA_CSR5_2 DGA001_BYTE_ADRS(0x16)
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#define DGA_CSR5_3 DGA001_BYTE_ADRS(0x17)
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#define DGA_CSR6 DGA001_LONG_ADRS(0x18)
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#define DGA_CSR6_0 DGA001_BYTE_ADRS(0x18)
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#define DGA_CSR6_1 DGA001_BYTE_ADRS(0x19)
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#define DGA_CSR6_2 DGA001_BYTE_ADRS(0x1a)
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#define DGA_CSR6_3 DGA001_BYTE_ADRS(0x1b)
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#define DGA_CSR7 DGA001_LONG_ADRS(0x1c)
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#define DGA_CSR7_0 DGA001_BYTE_ADRS(0x1c)
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#define DGA_CSR7_1 DGA001_BYTE_ADRS(0x1d)
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#define DGA_CSR7_2 DGA001_BYTE_ADRS(0x1e)
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#define DGA_CSR7_3 DGA001_BYTE_ADRS(0x1f)
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#define DGA_CSR8 DGA001_LONG_ADRS(0x21)
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#define DGA_CSR9 DGA001_LONG_ADRS(0x24)
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#define DGA_CSR10 DGA001_LONG_ADRS(0x28)
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#define DGA_CSR10_0 DGA001_BYTE_ADRS(0x28)
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#define DGA_CSR10_1 DGA001_BYTE_ADRS(0x29)
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#define DGA_CSR10_2 DGA001_BYTE_ADRS(0x2a)
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#define DGA_CSR10_3 DGA001_BYTE_ADRS(0x2b)
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#define DGA_CSR11 DGA001_LONG_ADRS(0x2c)
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#define DGA_CSR11_0 DGA001_BYTE_ADRS(0x2c)
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#define DGA_CSR11_1 DGA001_BYTE_ADRS(0x2d)
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#define DGA_CSR11_2 DGA001_BYTE_ADRS(0x2e)
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#define DGA_CSR11_3 DGA001_BYTE_ADRS(0x2f)
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#define DGA_CSR12 DGA001_LONG_ADRS(0x30)
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#define DGA_CSR13 DGA001_LONG_ADRS(0x34)
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#define DGA_CSR14 DGA001_LONG_ADRS(0x38)
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#define DGA_CSR15 DGA001_LONG_ADRS(0x3c)
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#define DGA_CSR16 DGA001_LONG_ADRS(0x40)
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#define DGA_CSR17 DGA001_LONG_ADRS(0x44)
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#define DGA_CSR18 DGA001_LONG_ADRS(0x48)
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#define DGA_CSR18_1 DGA001_BYTE_ADRS(0x49)
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#define DGA_CSR18_2 DGA001_BYTE_ADRS(0x4a)
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#define DGA_CSR18_3 DGA001_BYTE_ADRS(0x4b)
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#define DGA_CSR19 DGA001_LONG_ADRS(0x4c)
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#define DGA_CSR19_0 DGA001_BYTE_ADRS(0x4c)
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#define DGA_CSR19_1 DGA001_BYTE_ADRS(0x4d)
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#define DGA_CSR19_2 DGA001_BYTE_ADRS(0x4e)
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#define DGA_CSR19_3 DGA001_BYTE_ADRS(0x4f)
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#define DGA_CSR20 DGA001_LONG_ADRS(0x50)
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#define DGA_CSR21 DGA001_LONG_ADRS(0x54)
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#define DGA_CSR22 DGA001_LONG_ADRS(0x58)
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#define DGA_CSR23 DGA001_LONG_ADRS(0x5c)
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#define DGA_CSR24 DGA001_LONG_ADRS(0x60)
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#define DGA_CSR25 DGA001_LONG_ADRS(0x64)
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#define DGA_CSR26 DGA001_LONG_ADRS(0x68)
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#define DGA_CSR27 DGA001_LONG_ADRS(0x6c)
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/*
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* Interface Register (IFR) definitions.
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*
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* All registers of the IFR are accessible to both the local processor
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* and to other VMEbus masters.
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*/
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#define DGA_IFR0 DGA001_LONG_ADRS(0x70)
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#define DGA_IFR1 DGA001_LONG_ADRS(0x74)
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#define DGA_IFR2 DGA001_LONG_ADRS(0x78)
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#define DGA_IFR3 DGA001_LONG_ADRS(0x7c)
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/*************************************************************************
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* CSR0_0 0x00 0x00 local bus control *
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*************************************************************************/
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#define CSR0_0_LBT_DIS 0x30 /* local bus time-out disable 5-4 */
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#define CSR0_0_LBT_256 0x20 /* local bus time-out 256 clks 5-4 */
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#define CSR0_0_LBT_128 0x10 /* local bus time-out 128 clks 5-4 */
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#define CSR0_0_LBT_64 0x00 /* local bus time-out 64 clks 5-4 */
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#define CSR0_0_TAOUTE 0x08 /* local bus TAOUT enable 3 */
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/*************************************************************************
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* CSR0_1 0x00 0x01 bus error control and status *
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*************************************************************************/
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#define CSR0_1_BERDYO 0x80 /* activate RDYO# upon bus error 7 */
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#define CSR0_1_LBTOUT 0x04 /* local bus time-out (status) 2 */
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#define CSR0_1_RQTOUT 0x02 /* request time-out (status) 1 */
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#define CSR0_1_VMEBERR 0x01 /* VMEbus bus error (status) 0 */
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/*************************************************************************
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* CSR0_2 0x00 0x02 general purpose output enable *
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*************************************************************************/
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#define CSR0_2_GPOE7 0x80 /* general purpose output 7 enable 7 */
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#define CSR0_2_GPOE6 0x40 /* general purpose output 6 enable 6 */
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#define CSR0_2_GPOE5 0x20 /* general purpose output 5 enable 5 */
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#define CSR0_2_GPOE4 0x10 /* general purpose output 4 enable 4 */
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#define CSR0_2_GPOE3 0x08 /* general purpose output 3 enable 3 */
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#define CSR0_2_GPOE2 0x04 /* general purpose output 2 enable 2 */
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#define CSR0_2_GPOE1 0x02 /* general purpose output 1 enable 1 */
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#define CSR0_2_GPOE0 0x01 /* general purpose output 0 enable 0 */
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/*************************************************************************
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* CSR0_3 0x00 0x03 general purpose I/O *
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*************************************************************************/
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#define CSR0_3_GPIO7 0x80 /* general purpose I/O 7 7 */
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#define CSR0_3_GPIO6 0x40 /* general purpose I/O 6 6 */
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#define CSR0_3_GPIO5 0x20 /* general purpose I/O 5 5 */
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#define CSR0_3_GPIO4 0x10 /* general purpose I/O 4 4 */
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#define CSR0_3_GPIO3 0x08 /* general purpose I/O 3 3 */
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#define CSR0_3_GPIO2 0x04 /* general purpose I/O 2 2 */
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#define CSR0_3_GPIO1 0x02 /* general purpose I/O 1 1 */
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#define CSR0_3_GPIO0 0x01 /* general purpose I/O 0 0 */
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/*************************************************************************
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* CSR1_0 0x01 0x04 reset control and status *
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*************************************************************************/
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||||
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#define CSR1_0_PURSTF 0x80 /* power-up reset (status) 7 */
|
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#define CSR1_0_RSWEN 0x40 /* reset switch enable 6 */
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#define CSR1_0_RSWSYS 0x20 /* VMEbus SYSRESET enable 5 */
|
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|
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/*************************************************************************
|
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* CSR1_1 0x01 0x05 system controller configuration *
|
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*************************************************************************/
|
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|
||||
#define CSR1_1_SYSCON 0x80 /* system controller (status) 7 */
|
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|
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#define CSR1_1_RRS 0x10 /* round robin arbitration 4 */
|
||||
#define CSR1_1_PRI 0x00 /* prioritized arbitration 4 */
|
||||
|
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#define CSR1_1_ARBT_DIS 0x0c /* arbitration time-out disable 3-2 */
|
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#define CSR1_1_ARBT_63 0x08 /* arbitration time-out 63 usec 3-2 */
|
||||
#define CSR1_1_ARBT_31 0x04 /* arbitration time-out 31 usec 3-2 */
|
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#define CSR1_1_ARBT_15 0x00 /* arbitration time-out 15 usec 3-2 */
|
||||
|
||||
#define CSR1_1_SBT_DIS 0x03 /* VME bus time-out disable 1-0 */
|
||||
#define CSR1_1_SBT_511 0x02 /* VME bus time-out 511 usec 1-0 */
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#define CSR1_1_SBT_255 0x01 /* VME bus time-out 255 usec 1-0 */
|
||||
#define CSR1_1_SBT_127 0x00 /* VME bus time-out 127 usec 1-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR1_2 0x01 0x06 VMEbus requester control *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR1_2_DWB 0x80 /* VMEbus request 7 */
|
||||
#define CSR1_2_OWN 0x40 /* VMEbus request (status) 6 */
|
||||
|
||||
#define CSR1_2_RQT_DIS 0x30 /* request time-out disable 5-4 */
|
||||
#define CSR1_2_RQT_1023 0x20 /* request time-out 1023 usec 5-4 */
|
||||
#define CSR1_2_RQT_511 0x10 /* request time-out 511 usec 5-4 */
|
||||
#define CSR1_2_RQT_255 0x00 /* request time-out 255 usec 5-4 */
|
||||
|
||||
#define CSR1_2_RNV 0x0c /* release never 3-2 */
|
||||
#define CSR1_2_RBC 0x08 /* release when bus clear 3-2 */
|
||||
#define CSR1_2_RWD 0x04 /* release when done 3-2 */
|
||||
#define CSR1_2_ROR 0x00 /* release on request 3-2 */
|
||||
|
||||
#define CSR1_2_BR3 0x03 /* VMEbus request level 3 1-0 */
|
||||
#define CSR1_2_BR2 0x02 /* VMEbus request level 2 1-0 */
|
||||
#define CSR1_2_BR1 0x01 /* VMEbus request level 1 1-0 */
|
||||
#define CSR1_2_BR0 0x00 /* VMEbus request level 0 1-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR1_3 0x01 0x07 VMEbus master control *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR1_3_RMC 0x80 /* read-modify-write cycle 7 */
|
||||
|
||||
#define CSR1_3_AAMEN 0x40 /* addess modifier code enable 6 */
|
||||
#define CSR1_3_AAMDIS 0x00 /* addess modifier code disable 6 */
|
||||
#define CSR1_3_AAM 0x3f /* addess modifier code (mask) 5-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR2_0 0x02 0x08 unused *
|
||||
* to *
|
||||
* CSR3_1 0x03 0x0d unused *
|
||||
*************************************************************************/
|
||||
|
||||
/*************************************************************************
|
||||
* CSR3_2 0x03 0x0e interface register address *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR3_2_IFRA_H 0xff /* interface register addess (mask) 7-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR3_3 0x03 0x0f interface register address *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR3_3_IFRA_L 0xf0 /* interface register addess (mask) 7-4 */
|
||||
|
||||
#define CSR3_3_IFRSUP 0x02 /* respond to supervisor 1 */
|
||||
#define CSR3_3_IFRUSR 0x01 /* respond to user 0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR4_01 0x04 0x10 slave address 0 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR4_01_SL0A 0xffff /* slave addess 0 (mask) 15-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR4_23 0x04 0x12 address mask 0 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR4_23_AM0A 0xffff /* address mask 0 (mask) 15-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR5_01 0x05 0x14 mapping address 0 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR5_01_MP0A 0xffff /* mapping address 0 (mask) 15-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR5_23 0x05 0x16 slave control 0 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR5_23_A32EN0 0x0020 /* respond to extended 5 */
|
||||
#define CSR5_23_A24EN0 0x0010 /* respond to standard 4 */
|
||||
#define CSR5_23_SUPER0 0x0008 /* respond to supervisor 3 */
|
||||
#define CSR5_23_USER0 0x0004 /* respond to user 2 */
|
||||
#define CSR5_23_PRGRM0 0x0002 /* respond to program 1 */
|
||||
#define CSR5_23_DATA0 0x0001 /* respond to data 0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR6_01 0x06 0x18 save address 1 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR6_01_SL0A 0xffff /* slave addess 1 (mask) 15-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR6_23 0x06 0x1a address mask 1 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR6_23_AM0A 0xffff /* address mask 1 (mask) 15-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR7_01 0x07 0x1c mapping addess 1 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR7_01_MP0A 0xffff /* mapping address 1 (mask) 15-0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR7_23 0x07 0x1e slave control 1 *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR7_23_A32EN0 0x0020 /* respond to extended 5 */
|
||||
#define CSR7_23_A24EN0 0x0010 /* respond to standard 4 */
|
||||
#define CSR7_23_SUPER0 0x0008 /* respond to supervisor 3 */
|
||||
#define CSR7_23_USER0 0x0004 /* respond to user 2 */
|
||||
#define CSR7_23_PRGRM0 0x0002 /* respond to program 1 */
|
||||
#define CSR7_23_DATA0 0x0001 /* respond to data 0 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR12 0x0c 0x30 tick timer 0 control *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR12_TT0CEN 0x80000000 /* tick timer 0 enable */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR13 0x0d 0x34 tick timer 0 counter *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR13_TT0OCL 0x80000000 /* overflow counter clear */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR14 0x0e 0x38 tick timer 1 control *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR14_TT1CEN 0x80000000 /* tick timer 1 enable */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR15 0x0f 0x3c tick timer 1 counter *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR15_TT1OCL 0x80000000 /* overflow counter clear */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR16 0x10 0x40 watchdog timer control *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR16_WDTCEN 0x80000000 /* watchdog timer enable */
|
||||
#define CSR16_WDTSFE 0x40000000 /* watchdog timer SYSFAIL enable*/
|
||||
|
||||
/*************************************************************************
|
||||
* CSR17 0x11 0x44 watchdog timer counter *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR17_WDTCLR 0x80000000 /* watchdog timer counter clear */
|
||||
#define CSR17_WDTOUT 0x01000000 /* watchdog timeout (status) */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR18_1 0x12 0x49 interrupt sense mode control *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR18_1_ACFLVL 0x80 /* ACFAIL int level(1)/edge(0) sense 7 */
|
||||
#define CSR18_1_ABTLVL 0x40 /* ABORT int level(1)/edge(0) sense 6 */
|
||||
#define CSR18_1_SFLVL 0x20 /* SYSFAIL int level(1)/edge(0) sense 5 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR20 0x14 0x50 interrupt status *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR20_ACFIRQ 0x80000000 /* ACFAIL interrupt 31 */
|
||||
#define CSR20_ABTIRQ 0x40000000 /* ABORT interrupt 30 */
|
||||
#define CSR20_SFIRQ 0x20000000 /* SYSFAIL interrupt 29 */
|
||||
#define CSR20_BERIRQ 0x10000000 /* BERR interrupt 28 */
|
||||
#define CSR20_IAKIRQ 0x08000000 /* IAK interrupt 27 */
|
||||
#define CSR20_SRQIRQ 0x04000000 /* SRQ interrupt 26 */
|
||||
#define CSR20_SAKIRQ 0x02000000 /* SAKF interrupt 25 */
|
||||
|
||||
#define CSR20_GP7IRQ 0x00800000 /* GP7 interrupt 23 */
|
||||
#define CSR20_DMAIRQ 0x00400000 /* DMA interrupt 22 */
|
||||
#define CSR20_TT1IRQ 0x00200000 /* TT1 interrupt 21 */
|
||||
#define CSR20_TT0IRQ 0x00100000 /* TT0 interrupt 20 */
|
||||
#define CSR20_GP3IRQ 0x00080000 /* GP3 interrupt 19 */
|
||||
#define CSR20_GP2IRQ 0x00040000 /* GP2 interrupt 18 */
|
||||
#define CSR20_GP1IRQ 0x00020000 /* GP1 interrupt 17 */
|
||||
#define CSR20_GP0IRQ 0x00010000 /* GP0 interrupt 16 */
|
||||
|
||||
#define CSR20_SWIRQ7 0x00008000 /* SWIRQ7 interrupt 15 */
|
||||
#define CSR20_SWIRQ6 0x00004000 /* SWIRQ6 interrupt 14 */
|
||||
#define CSR20_SWIRQ5 0x00002000 /* SWIRQ5 interrupt 13 */
|
||||
#define CSR20_SWIRQ4 0x00001000 /* SWIRQ4 interrupt 12 */
|
||||
#define CSR20_SWIRQ3 0x00000800 /* SWIRQ3 interrupt 11 */
|
||||
#define CSR20_SWIRQ2 0x00000400 /* SWIRQ2 interrupt 10 */
|
||||
#define CSR20_SWIRQ1 0x00000200 /* SWIRQ1 interrupt 9 */
|
||||
#define CSR20_SWIRQ0 0x00000100 /* SWIRQ0 interrupt 8 */
|
||||
|
||||
#define CSR20_VMIRQ7 0x00000080 /* VMIRQ7 interrupt 7 */
|
||||
#define CSR20_VMIRQ6 0x00000040 /* VMIRQ7 interrupt 6 */
|
||||
#define CSR20_VMIRQ5 0x00000020 /* VMIRQ7 interrupt 5 */
|
||||
#define CSR20_VMIRQ4 0x00000010 /* VMIRQ4 interrupt 4 */
|
||||
#define CSR20_VMIRQ3 0x00000008 /* VMIRQ3 interrupt 3 */
|
||||
#define CSR20_VMIRQ2 0x00000004 /* VMIRQ2 interrupt 2 */
|
||||
#define CSR20_VMIRQ1 0x00000002 /* VMIRQ1 interrupt 1 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR21 0x14 0x50 interrupt enable *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR21_ACFIEN 0x80000000 /* ACFAIL interrupt 31 */
|
||||
#define CSR21_ABTIEN 0x40000000 /* ABORT interrupt 30 */
|
||||
#define CSR21_SFIEN 0x20000000 /* SYSFAIL interrupt 29 */
|
||||
#define CSR21_BERIEN 0x10000000 /* BERR interrupt 28 */
|
||||
#define CSR21_IAKIEN 0x08000000 /* IAK interrupt 27 */
|
||||
#define CSR21_SRQIEN 0x04000000 /* SRQ interrupt 26 */
|
||||
#define CSR21_SAKIEN 0x02000000 /* SAKF interrupt 25 */
|
||||
|
||||
#define CSR21_GP7IEN 0x00800000 /* GP7 interrupt 23 */
|
||||
#define CSR21_DMAIEN 0x00400000 /* DMA interrupt 22 */
|
||||
#define CSR21_TT1IEN 0x00200000 /* TT1 interrupt 21 */
|
||||
#define CSR21_TT0IEN 0x00100000 /* TT0 interrupt 20 */
|
||||
#define CSR21_GP3IEN 0x00080000 /* GP3 interrupt 19 */
|
||||
#define CSR21_GP2IEN 0x00040000 /* GP2 interrupt 18 */
|
||||
#define CSR21_GP1IEN 0x00020000 /* GP1 interrupt 17 */
|
||||
#define CSR21_GP0IEN 0x00010000 /* GP0 interrupt 16 */
|
||||
|
||||
#define CSR21_SWIEN7 0x00008000 /* SWIRQ7 interrupt 15 */
|
||||
#define CSR21_SWIEN6 0x00004000 /* SWIRQ6 interrupt 14 */
|
||||
#define CSR21_SWIEN5 0x00002000 /* SWIRQ5 interrupt 13 */
|
||||
#define CSR21_SWIEN4 0x00001000 /* SWIRQ4 interrupt 12 */
|
||||
#define CSR21_SWIEN3 0x00000800 /* SWIRQ3 interrupt 11 */
|
||||
#define CSR21_SWIEN2 0x00000400 /* SWIRQ2 interrupt 10 */
|
||||
#define CSR21_SWIEN1 0x00000200 /* SWIRQ1 interrupt 9 */
|
||||
#define CSR21_SWIEN0 0x00000100 /* SWIRQ0 interrupt 8 */
|
||||
|
||||
#define CSR21_VMIEN7 0x00000080 /* VMIRQ7 interrupt 7 */
|
||||
#define CSR21_VMIEN6 0x00000040 /* VMIRQ7 interrupt 6 */
|
||||
#define CSR21_VMIEN5 0x00000020 /* VMIRQ7 interrupt 5 */
|
||||
#define CSR21_VMIEN4 0x00000010 /* VMIRQ4 interrupt 4 */
|
||||
#define CSR21_VMIEN3 0x00000008 /* VMIRQ3 interrupt 3 */
|
||||
#define CSR21_VMIEN2 0x00000004 /* VMIRQ2 interrupt 2 */
|
||||
#define CSR21_VMIEN1 0x00000002 /* VMIRQ1 interrupt 1 */
|
||||
|
||||
/*************************************************************************
|
||||
* CSR23 0x16 0x5c interrupt clear *
|
||||
*************************************************************************/
|
||||
|
||||
#define CSR23_ACFICL 0x80000000 /* ACFAIL clear 31 */
|
||||
#define CSR23_ABTICL 0x40000000 /* ABORT clear 30 */
|
||||
#define CSR23_SFICL 0x20000000 /* SYSFAIL clear 29 */
|
||||
#define CSR23_IAKICL 0x08000000 /* IAK clear 27 */
|
||||
#define CSR23_SRQICL 0x04000000 /* SRQ clear 26 */
|
||||
#define CSR23_SAKICL 0x02000000 /* SAK clear 25 */
|
||||
#define CSR23_DMAICL 0x00400000 /* DMA clear 22 */
|
||||
#define CSR23_TT1ICL 0x00200000 /* TT1 clear 21 */
|
||||
#define CSR23_TT0ICL 0x00100000 /* TT0 clear 20 */
|
||||
|
||||
/*************************************************************************
|
||||
* IFR0 0x1c 0x70 interface register 0 *
|
||||
*************************************************************************/
|
||||
|
||||
#define IFR0_SRQF 0x80000000 /* SRQ clear 31 */
|
||||
|
||||
/*************************************************************************
|
||||
* IFR1 0x1d 0x74 interface register 1 *
|
||||
*************************************************************************/
|
||||
|
||||
#define IFR1_SAKF 0x80000000 /* SAK clear 31 */
|
||||
|
||||
/*************************************************************************
|
||||
* IFR3 0x1f 0x7c interface register 3 *
|
||||
*************************************************************************/
|
||||
|
||||
#define IFR3_SWREN 0x80000000 /* software reset enable bit 31 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* INCdga001Vmeh */
|
||||
@@ -0,0 +1,659 @@
|
||||
/* ivac.h - Ironics/VTC's VME Address Controller (VAC) constants */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,22sep92,rrr added support for c++
|
||||
01e,07jul92,jwt cleaned up ANSI compiler warnings.
|
||||
01d,26may92,rrr the tree shuffle
|
||||
01c,04oct91,rrr passed through the ansification filter
|
||||
-fixed #else and #endif
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01b,31jan91,rjt initial release to windriver after many minor fixes.
|
||||
01a,25jul90,rjt writen by modifying IV-SPRC sparcmon version.
|
||||
*/
|
||||
|
||||
#ifndef __INCivach
|
||||
#define __INCivach
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
Assembly language files should turn off type declarations by not
|
||||
including those portions of this include file, this is done by
|
||||
placing a "#define _ASMLANGUAGE" statement before this file is
|
||||
included in any other files.
|
||||
|
||||
Also, in order to incorparate stronger typing of all constants, and to
|
||||
allow the same constants to be typed in C files,yet usable in
|
||||
assembly files. An unorthadox method of TYPING is used by CONDITIONALLY
|
||||
#define'ing the constant TYPES. If no _ASMLANGUAGE #define is present,
|
||||
then the type is defined to a blank space, otherwise it is defined
|
||||
to be a C type. This looks weird but works nicely.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
Naming of register names and constants was done ( or was attempted ) so that
|
||||
the front end of the names would indicate a related group while the tail
|
||||
end of the names would further define the purpose of the name. Some groups
|
||||
often contained sub-groups. Also some names don't follow this convention for
|
||||
the sake of readability and other reasons.
|
||||
|
||||
An H_ prefix indicates that the constant is typed as a pointer to
|
||||
unsigned short register.
|
||||
An B_ prefix indicates that the constant is typed as a pointer to
|
||||
unsigned char register.
|
||||
|
||||
Because of unpredictability of structure sizing and placement for
|
||||
different compilers, we use contants to access each register.
|
||||
|
||||
Most constants are defined for consistancy in name AND intended usage.
|
||||
BIT MANIPUATION is set up so that each bit field has 3 or more defines
|
||||
associated with it.
|
||||
|
||||
1. BIT VALUE MASK
|
||||
2. ASSERTED VALUE(S)
|
||||
3. DEASERTED VALUE
|
||||
|
||||
Where ASSERTED VALUE = 0 and dasserted value = 0xff for ACTIVE LOW SIGNALS
|
||||
or vice versa,
|
||||
where ASSERTED VALUE = 0xff and dasserted value = 0 for ACTIVE HIGH SIGNALS.
|
||||
|
||||
The active high bits may also be something other than 0xff for
|
||||
multi-bit fields. EG: for at 2 bit active high field there may be
|
||||
4 asserted values associated with it: 0x00 0x01 0x02 0x03.
|
||||
|
||||
the bit field should be altered as follows:
|
||||
new_reg_value = (old_reg_val & ~MASK) | (MASK & VALUE )
|
||||
|
||||
REGISTER BIT STATUS for a bit field has 2 or more defines associated with it.
|
||||
|
||||
1. BIT MASK
|
||||
2. POSSIBLE BIT VALUE
|
||||
3. .
|
||||
4 .
|
||||
|
||||
returned_bit_field_status = MASK & reg_value
|
||||
|
||||
Most constants are declared immediatly after the register they are used in.
|
||||
Some constants are shared between more than 1 register and are only defined
|
||||
once after the first register.
|
||||
*/
|
||||
|
||||
|
||||
/* IMPORTANT NOTICE: NOT ALL CONSTANTS HAVE BEEN TESTED */
|
||||
|
||||
|
||||
/* The following #defines allow or disallow C types */
|
||||
#ifndef _ASMLANGUAGE
|
||||
/* C code typing */
|
||||
#ifndef P_VA_TYPE
|
||||
#define P_VA_TYPE (unsigned short *)
|
||||
#endif
|
||||
#ifndef VA_TYPE
|
||||
#define VA_TYPE (unsigned short)
|
||||
#endif
|
||||
#else
|
||||
/* No typing allowing in assembly */
|
||||
#define VA_TYPE
|
||||
#define P_VA_TYPE
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#define VAC_ADR 0xfffd0000
|
||||
#define VAC_TYPE unsigned short
|
||||
|
||||
/*
|
||||
IMPORTANT
|
||||
Some boards may require a special routine to access the VAC registers.
|
||||
Example: a board whose cache must be bypassed to ensure register integrity.
|
||||
If they do, there should be vaXetReg() macros #define'd to call that
|
||||
special routine. Otherwise the following vaXetReg() macros will be used.
|
||||
For portability reasons, it might be a good idea to only use vaXetReg()
|
||||
to alter any VAC registers in C code. If this macro is insufficient
|
||||
then "#undef vaRegSet" and write a C routine (or another macro) to replace it.
|
||||
*/
|
||||
|
||||
#ifndef vaRegSet
|
||||
#define vaRegSet(hReg,val) (*(hReg) = (VAC_TYPE) (val))
|
||||
#endif /* vaRegSet */
|
||||
#ifndef vaRegGet
|
||||
#define vaRegGet(bReg) *(bReg)
|
||||
#endif /* vaRegGet */
|
||||
|
||||
/* Slave Select mask and base registers */
|
||||
#define H_VAC_SLS1_MASK P_VA_TYPE (VAC_ADR + 0x0000)
|
||||
#define H_VAC_SLS1_BASE P_VA_TYPE (VAC_ADR + 0x0100)
|
||||
#define H_VAC_SLS0_MASK P_VA_TYPE (VAC_ADR + 0x0200)
|
||||
#define H_VAC_SLS0_BASE P_VA_TYPE (VAC_ADR + 0x0300)
|
||||
|
||||
|
||||
/* group & module Addr. decodes for IPC Reg. */
|
||||
#define H_VAC_ICFSEL P_VA_TYPE(VAC_ADR + 0x0400)
|
||||
#define GROUP_BASE_MASK 0xff00
|
||||
#define MODULE_BASE_MASK 0x00ff
|
||||
#define GROUP_SHIFT 0x0000
|
||||
#define MODULE_SHIFT 0x0008
|
||||
|
||||
/* DRAM Upper Limit Mask Register */
|
||||
#define H_VAC_DRAM_MASK P_VA_TYPE (VAC_ADR + 0x0500)
|
||||
|
||||
/* Boundry 2 Address Reg. */
|
||||
#define H_VAC_B2_BASE P_VA_TYPE (VAC_ADR + 0x0600)
|
||||
|
||||
/* Boundry 3 Address Reg. */
|
||||
#define H_VAC_B3_BASE P_VA_TYPE (VAC_ADR + 0x0700 )
|
||||
|
||||
/* A24 Base Address Reg. */
|
||||
#define H_VAC_A24_BASE P_VA_TYPE (VAC_ADR + 0x0800 )
|
||||
|
||||
/* Region 1,2,3 Attribute Reg. */
|
||||
#define H_VAC_R1_ATTRIB P_VA_TYPE (VAC_ADR + 0x0900)
|
||||
#define H_VAC_R2_ATTRIB P_VA_TYPE (VAC_ADR + 0x0a00)
|
||||
#define H_VAC_R3_ATTRIB P_VA_TYPE (VAC_ADR + 0x0b00 )
|
||||
|
||||
#define ATR_DATA_SZ_MASK VA_TYPE 0x8000
|
||||
#define ATR_D16 VA_TYPE 0x8000
|
||||
#define ATR_D32 VA_TYPE 0x0
|
||||
|
||||
#define ATR_ADR_SZ_MASK VA_TYPE 0x6000
|
||||
#define ATR_A16 VA_TYPE 0x2000
|
||||
#define ATR_A24 VA_TYPE 0x0000
|
||||
#define ATR_A32 VA_TYPE 0x4000
|
||||
|
||||
#define ATR_CACHE_MASK VA_TYPE 0x1000
|
||||
#define ATR_CACHE_INHIBIT VA_TYPE 0x1000
|
||||
#define ATR_CACHE_ENABLE VA_TYPE 0x0000
|
||||
|
||||
#define ATR_SEGMENT_MAP_MASK VA_TYPE 0x0c00
|
||||
#define ATR_NULL VA_TYPE 0x0
|
||||
#define ATR_SHR VA_TYPE 0x0400
|
||||
#define ATR_VSB VA_TYPE 0x0800
|
||||
#define ATR_VME VA_TYPE 0x0c00
|
||||
|
||||
|
||||
/* Dsack Timing Control Reg. */
|
||||
#define H_VAC_IO4_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0c00)
|
||||
#define H_VAC_IO5_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0d00)
|
||||
#define H_VAC_SHR_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0e00)
|
||||
#define H_VAC_EPROM_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0f00)
|
||||
#define H_VAC_IO0_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1000)
|
||||
#define H_VAC_IO1_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1100)
|
||||
#define H_VAC_IO2_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1200)
|
||||
#define H_VAC_IO3_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1300)
|
||||
|
||||
#define DSACK_DELAY_MASK 0xE000
|
||||
#define DSACK_DELAY_0 0x0000
|
||||
#define DSACK_DELAY_1 0x2000
|
||||
#define DSACK_DELAY_2 0x4000
|
||||
#define DSACK_DELAY_3 0x6000
|
||||
#define DSACK_DELAY_4 0x8000
|
||||
#define DSACK_DELAY_5 0xA000
|
||||
#define DSACK_DELAY_6 0xC000
|
||||
#define DSACK_DELAY_7 0xE000
|
||||
|
||||
#define DSACK1_ENABLE 0x1000
|
||||
#define DSASK0_ENABLE 0x0800
|
||||
|
||||
#define DSACK_RECOVERY_MASK 0x0700
|
||||
#define RECOVERY_DELAY_0 0x0000
|
||||
#define RECOVERY_DELAY_1 0x0100
|
||||
#define RECOVERY_DELAY_2 0x0200
|
||||
#define RECOVERY_DELAY_3 0x0300
|
||||
#define RECOVERY_DELAY_4 0x0400
|
||||
#define RECOVERY_DELAY_5 0x0500
|
||||
#define RECOVERY_DELAY_6 0x0600
|
||||
#define RECOVERY_DELAY_7 0x0700
|
||||
|
||||
#define IORD_DELAY_MASK 0x00c0
|
||||
#define IORD_DELAY_0 0x0000
|
||||
#define IORD_DELAY_1 0x0040
|
||||
#define IORD_DELAY_2 0x0080
|
||||
#define IORD_DELAY_3 0x00c0
|
||||
|
||||
#define IOWR_DELAY_MASK 0x0030
|
||||
#define IOWR_DELAY_0 0x0000
|
||||
#define IOWR_DELAY_1 0x0010
|
||||
#define IOWR_DELAY_2 0x0020
|
||||
#define IOWR_DELAY_3 0x0030
|
||||
|
||||
#define IOSELI_DELAY_MASK 0x000c
|
||||
#define IOSELI_DELAY_0 0x0000
|
||||
#define IOSELI_DELAY_1 0x0004
|
||||
#define IOSELI_DELAY_2 0x0008
|
||||
#define IOSELI_DELAY_3 0x000c
|
||||
|
||||
#define IORD_CYCLE_END_CTL 0x0002
|
||||
#define IOWR_CYCLE_END_CTL 0x0001
|
||||
|
||||
/* Decode Control Register */
|
||||
#define H_VAC_DECODE_CTL P_VA_TYPE (VAC_ADR + 0x1400)
|
||||
|
||||
#define SLACKDR VA_TYPE 0x8000
|
||||
#define QDRAM VA_TYPE 0x4000
|
||||
|
||||
/* slave 1 device selection */
|
||||
#define SL1_MASK VA_TYPE 0x3000
|
||||
#define SL1DS1 VA_TYPE 0x2000
|
||||
#define SL1DS0 VA_TYPE 0x1000
|
||||
#define SL1_EPROM VA_TYPE 0x0000
|
||||
#define SL1_VSB VA_TYPE 0x1000
|
||||
#define SL1_SHRCS VA_TYPE 0x2000
|
||||
#define SL1_DRAM VA_TYPE 0x3000
|
||||
|
||||
#define SL1A32 VA_TYPE 0x0800
|
||||
#define SL1A16 VA_TYPE 0x0400
|
||||
#define QSL0 VA_TYPE 0x0200
|
||||
#define QSL1 VA_TYPE 0x0100
|
||||
#define QICF VA_TYPE 0x0080
|
||||
#define QBNDRY VA_TYPE 0x0040
|
||||
#define ACKDR VA_TYPE 0x0020
|
||||
#define REDSL1 VA_TYPE 0x0010
|
||||
#define REDSL0 VA_TYPE 0x0008
|
||||
#define DRDLY1 VA_TYPE 0x0004
|
||||
#define DRDLY0 VA_TYPE 0x0002
|
||||
#define QBFPU VA_TYPE 0x0001
|
||||
|
||||
/* VAC interrupt status register and its bit mask constants */
|
||||
#define H_VAC_IRQ_STAT P_VA_TYPE (VAC_ADR +0x1500 )
|
||||
|
||||
|
||||
#define VAC_IRQ_PIO9 VA_TYPE 0x8000
|
||||
#define VAC_IRQ_PIO8 VA_TYPE 0x4000
|
||||
#define VAC_IRQ_PIO7 VA_TYPE 0x2000
|
||||
#define VAC_IRQ_PIO4 VA_TYPE 0x1000
|
||||
#define VAC_IRQ_MBX VA_TYPE 0x0800
|
||||
#define VAC_IRQ_TMR VA_TYPE 0x0400
|
||||
#define VAC_IRQ_SIOA VA_TYPE 0x0200
|
||||
#define VAC_IRQ_SIOB VA_TYPE 0x0100
|
||||
|
||||
|
||||
/* VAC IRQ signal map and control register */
|
||||
#define H_VAC_IRQ_CTL P_VA_TYPE (VAC_ADR +0x1600 )
|
||||
|
||||
/*
|
||||
The values are designed to be used as follows. The interrupt
|
||||
source on the VAC and the actual PIO signals to the VIC are
|
||||
combined to produce a VAC interrupt control value, or bit map,
|
||||
that can be used with a mask value to toggle the control bits.
|
||||
|
||||
Example:
|
||||
control bit map IRQ pin dest VAC IRQ source
|
||||
#define IRQ_VAC_TMR_CTL_MAP (IRQ_DEST_PIO10 << IRQ_VAC_SRC_TMR)
|
||||
|
||||
To remove a VAC interrupt you must disable and enable the VAC interrupt
|
||||
via the VAC Interrupt Control Register.
|
||||
|
||||
Clear the IRQ map to disable the IRQ:
|
||||
|
||||
sysVacFieldSet (H_VAC_IRQ_CTL, IRQ_VAC_TMR_CTL_MASK,
|
||||
(IRQ_VAC_TMR_CTL_MAP & VAC_IRQ_DISABLE));
|
||||
|
||||
Map it back in to enable the IRQ:
|
||||
|
||||
sysVacFieldSet (H_VAC_IRQ_CTL, IRQ_VAC_TMR_CTL_MASK,
|
||||
(IRQ_VAC_TMR_CTL_MAP & VAC_IRQ_ENABLE));
|
||||
*/
|
||||
|
||||
#define IRQ_PIO9_CTL_MASK VA_TYPE 0xc000
|
||||
#define IRQ_PIO8_CTL_MASK VA_TYPE 0x3000
|
||||
#define IRQ_PIO7_CTL_MASK VA_TYPE 0x0c00
|
||||
#define IRQ_PIO4_CTL_MASK VA_TYPE 0x0300
|
||||
#define IRQ_MBX_CTL_MASK VA_TYPE 0x00c0
|
||||
#define IRQ_SIOA_CTL_MASK VA_TYPE 0x0030
|
||||
#define IRQ_SIOB_CTL_MASK VA_TYPE 0x000c
|
||||
#define IRQ_VAC_TMR_CTL_MASK VA_TYPE 0x0003
|
||||
|
||||
#define VAC_IRQ_DISABLE 0
|
||||
#define VAC_IRQ_ENABLE 0xffff
|
||||
|
||||
|
||||
/* shift values to map the pio signal destination */
|
||||
#define IRQ_SRC_PIO9 VA_TYPE 0xE
|
||||
#define IRQ_SRC_PIO8 VA_TYPE 0xC
|
||||
#define IRQ_SRC_PIO7 VA_TYPE 0xA
|
||||
#define IRQ_SRC_PIO4 VA_TYPE 0x8
|
||||
#define IRQ_SRC_MBX VA_TYPE 0x6
|
||||
#define IRQ_SRC_SIOA VA_TYPE 0x4
|
||||
#define IRQ_SRC_SIOB VA_TYPE 0x2
|
||||
#define IRQ_SRC_VAC_TMR VA_TYPE 0x0
|
||||
|
||||
/* pio signal destination */
|
||||
#define IRQ_DEST_NULL 0
|
||||
#define IRQ_DEST_PIO7 1
|
||||
#define IRQ_DEST_PIO10 2
|
||||
#define IRQ_DEST_PIO11 3
|
||||
|
||||
|
||||
|
||||
/* device present flags */
|
||||
#define H_VAC_DEVICE_LOC P_VA_TYPE (VAC_ADR +0x1700 )
|
||||
|
||||
#define IOSEL5_PRESENT VA_TYPE 0x0020
|
||||
#define IOSEL4_PRESENT VA_TYPE 0x0010
|
||||
#define IOSEL3_PRESENT VA_TYPE 0x0008
|
||||
#define IOSEL2_PRESENT VA_TYPE 0x0004
|
||||
#define IOSEL1_PRESENT VA_TYPE 0x0002
|
||||
#define IOSEL0_PRESENT VA_TYPE 0x0001
|
||||
|
||||
/* this reg used to init pio data out values */
|
||||
#define H_VAC_PIO_DATA P_VA_TYPE (VAC_ADR +0x1800 )
|
||||
|
||||
/* read only - contains login levels of pio pins */
|
||||
#define H_VAC_PIO_PIN P_VA_TYPE (VAC_ADR +0x1900 )
|
||||
|
||||
/* set up the direction of pio */
|
||||
#define H_VAC_PIO_DIR P_VA_TYPE (VAC_ADR + 0x1a00)
|
||||
|
||||
/* assign functions to the pio */
|
||||
#define H_VAC_PIO_FUNC P_VA_TYPE (VAC_ADR + 0x1b00)
|
||||
|
||||
/* pio bit mask defines */
|
||||
#define PIO0 VA_TYPE 0x0001
|
||||
#define PIO1 VA_TYPE 0x0002
|
||||
#define PIO2 VA_TYPE 0x0004
|
||||
#define PIO3 VA_TYPE 0x0008
|
||||
#define PIO4 VA_TYPE 0x0010
|
||||
#define PIO5 VA_TYPE 0x0020
|
||||
#define PIO6 VA_TYPE 0x0040
|
||||
#define PIO7 VA_TYPE 0x0080
|
||||
#define PIO8 VA_TYPE 0x0100
|
||||
#define PIO9 VA_TYPE 0x0200
|
||||
#define PIO10 VA_TYPE 0x0400
|
||||
#define PIO11 VA_TYPE 0x0800
|
||||
#define PIO12 VA_TYPE 0x1000
|
||||
#define PIO13 VA_TYPE 0x2000
|
||||
#define PIO9_DEBOUNCE_ENABLE VA_TYPE 0x4000
|
||||
#define CPU_SPACE_EMULATE VA_TYPE 0x8000
|
||||
|
||||
#define TXDA_TO_PIO0 VA_TYPE 0x0001
|
||||
#define RXTA_TO_PIO1 VA_TYPE 0x0002
|
||||
#define TXDB_TO_PIO2 VA_TYPE 0x0004
|
||||
#define TXDB_TO_PIO3 VA_TYPE 0x0008
|
||||
#define IORD_TO_PIO4 VA_TYPE 0x0010
|
||||
#define IOWR_TO_PIO5 VA_TYPE 0x0020
|
||||
#define IOSEL3_TO_PIO6 VA_TYPE 0x0040
|
||||
#define PIO7IRQ_TO_PIO7 VA_TYPE 0x0080
|
||||
#define IOSEL4_TO_PIO8 VA_TYPE 0x0100
|
||||
#define IOSEL5_TO_PIO9 VA_TYPE 0x0200
|
||||
#define PIO10IRQ_TO_PIO10 VA_TYPE 0x0400
|
||||
#define PIO11IRQ_TO_PIO10 VA_TYPE 0x0800
|
||||
#define SHRCS_TO_PIO12 VA_TYPE 0x1000
|
||||
#define IOSEL2_TO_PIO13 VA_TYPE 0x2000
|
||||
#define PIO9_DEBOUNCE_DISABLE VA_TYPE 0x4000
|
||||
#define CPU_SPACE_EMULATE_VIA_IOSEL5 VA_TYPE 0x8000
|
||||
|
||||
/* SIO STUFF */
|
||||
|
||||
/*
|
||||
Get table for BAUD_PRESCALE_INIT VALS:
|
||||
|
||||
NOTE
|
||||
The SIO baud rate divisor is dependent on CPU_CLOCK
|
||||
and is derived from the following formula
|
||||
|
||||
/ CPU clock rate \
|
||||
divisor = truncate | ---------------------------- + 0.5 |
|
||||
\ 16 * (MAX baud rate desired) /
|
||||
|
||||
where divisor > 8.
|
||||
|
||||
This value is loaded into the top byte of the VAC CPU
|
||||
clock divisor.
|
||||
|
||||
The baud rate selection table will allow selection of
|
||||
8 different baud rates. Each lower than the MAX baud rate
|
||||
by a power of 2. If 9600 baud is the MAX baud rate, then
|
||||
the following powers are available:
|
||||
|
||||
baud select value baud rate
|
||||
7 76800 don't use
|
||||
6 19200
|
||||
5 9600
|
||||
4 4800
|
||||
3 2400
|
||||
2 1200
|
||||
1 600
|
||||
0 300
|
||||
*/
|
||||
|
||||
/* max rate cpu clk divisor */
|
||||
/* check these values for roundup */
|
||||
#define BAUD_9600_CLK_20MHz 0x2000
|
||||
#define BAUD_9600_CLK_25MHz 0x2800
|
||||
#define BAUD_9600_CLK_32MHz 0x3400
|
||||
#define BAUD_9600_CLK_33MHz 0x3500
|
||||
|
||||
#define BAUD_19200_CLK_20MHz 0x0fff /*subtract one from above formula*/
|
||||
#define BAUD_19200_CLK_25MHz 0x1400
|
||||
#define BAUD_19200_CLK_32MHz 0x1a00
|
||||
#define BAUD_19200_CLK_33MHz 0x1a00
|
||||
#define BAUD_19200_CLK_40MHz 0x2000
|
||||
|
||||
/*Baud Rate Prescaler used on CPU Clk. */
|
||||
#define H_VAC_BAUD_PRESCALE P_VA_TYPE (VAC_ADR + 0x1c00)
|
||||
|
||||
/* control register */
|
||||
#define H_VAC_SIOA_MODE P_VA_TYPE (VAC_ADR + 0x1d00)
|
||||
|
||||
/* control bits for both sioa and siob */
|
||||
#define SIO_CTL_ENABLE VA_TYPE 0xfcff
|
||||
#define SIO_CTL_DISABLE VA_TYPE 0x0300
|
||||
|
||||
/* the following are masks */
|
||||
#define PARITY_ENABLE VA_TYPE 0x8000
|
||||
#define EVEN_PARITY VA_TYPE 0x4000
|
||||
#define EIGHT_BITS VA_TYPE 0x2000
|
||||
|
||||
#define BAUD_RATE_MASK VA_TYPE 0x1c00
|
||||
|
||||
#define RESET_RECV VA_TYPE 0x0200
|
||||
#define RESET_XMIT VA_TYPE 0x0100
|
||||
#define XMITER VA_TYPE 0x0080
|
||||
#define RECVER VA_TYPE 0x0040
|
||||
#define SEND_BREAK VA_TYPE 0x0020
|
||||
#define TXDA_TO_RXDA VA_TYPE 0x0010
|
||||
|
||||
/* NOTE: vac sio data bytes are taken from high 8 bits !! */
|
||||
|
||||
/* xmit data */
|
||||
#define H_VAC_SIOA_XMIT P_VA_TYPE (VAC_ADR + 0x1e00)
|
||||
|
||||
/* control register */
|
||||
#define H_VAC_SIOB_MODE P_VA_TYPE (VAC_ADR + 0x1f00)
|
||||
|
||||
/* rec data */
|
||||
#define H_VAC_SIOA_RECV P_VA_TYPE (VAC_ADR + 0x2000)
|
||||
#define H_VAC_SIOB_RECV P_VA_TYPE (VAC_ADR + 0x2100)
|
||||
|
||||
/* xmit data */
|
||||
#define H_VAC_SIOB_XMIT P_VA_TYPE (VAC_ADR + 0x2200)
|
||||
|
||||
/* sio interrupt mask regs */
|
||||
#define H_VAC_SIOA_IRQ_MASK P_VA_TYPE (VAC_ADR + 0x2300)
|
||||
#define H_VAC_SIOB_IRQ_MASK P_VA_TYPE (VAC_ADR + 0x2400)
|
||||
|
||||
#define SINGLE_CHAR_RECV_MASK VA_TYPE 0x8000
|
||||
#define FIFO_FULL_MASK VA_TYPE 0x4000
|
||||
#define BREAK_CHANGE_MASK VA_TYPE 0x2000
|
||||
#define ERROR_MASK VA_TYPE 0x1000
|
||||
#define XMIT_READY_MASK VA_TYPE 0x0800
|
||||
#define XMIT_EMPTY_MASK VA_TYPE 0x0400
|
||||
|
||||
#define SIO_MASK_ENABLE VA_TYPE 0xffff
|
||||
#define SIO_MASK_DISABLE VA_TYPE 0x0000
|
||||
|
||||
|
||||
/* sio status regs */
|
||||
#define H_VAC_SIOA_STAT P_VA_TYPE (VAC_ADR + 0x2500)
|
||||
#define H_VAC_SIOB_STAT P_VA_TYPE (VAC_ADR + 0x2600)
|
||||
|
||||
#define CHAR_READY VA_TYPE 0x8000
|
||||
#define FIFO_FULL VA_TYPE 0x4000
|
||||
#define BREAK_CHANGE VA_TYPE 0x2000
|
||||
#define PARITY_ERROR VA_TYPE 0x1000
|
||||
#define FRAMING_ERROR VA_TYPE 0x0800
|
||||
#define OVERRUN_ERROR VA_TYPE 0x0400
|
||||
#define XMIT_READY VA_TYPE 0x0200
|
||||
#define XMIT_EMPTY VA_TYPE 0x0100
|
||||
|
||||
/* VAC TIMER STUFF */
|
||||
|
||||
#define H_VAC_TMR_DATA P_VA_TYPE (VAC_ADR + 0x2700)
|
||||
#define H_VAC_TMR_CTL P_VA_TYPE (VAC_ADR + 0x2800)
|
||||
|
||||
#define PRESCALER_IN_MASK VA_TYPE 0x3f00
|
||||
#define PRESCALER_IN_SHIFT 8
|
||||
|
||||
/* use this to read the instantaneous count value of prescaler */
|
||||
#define PRESCALER_OUT_MASK VA_TYPE 0x003f
|
||||
|
||||
#define VAC_20MHZ_CPU_1MHZ_PRESCALER (19 << PRESCALER_IN_SHIFT)
|
||||
#define VAC_25MHZ_CPU_1MHZ_PRESCALER (24 << PRESCALER_IN_SHIFT)
|
||||
#define VAC_33MHZ_CPU_1MHZ_PRESCALER (32 << PRESCALER_IN_SHIFT)
|
||||
#define VAC_40MHZ_CPU_1MHZ_PRESCALER (39 << PRESCALER_IN_SHIFT)
|
||||
|
||||
/* Load command disables timer and then loads the interal timer registers */
|
||||
/* with the values in the prescaler control bits and the timer data register */
|
||||
#define RUN_LOAD_MASK VA_TYPE 0x4000
|
||||
#define RUN_CMD VA_TYPE 0x4000
|
||||
#define STOP_N_LOAD_CMD VA_TYPE 0x0000
|
||||
|
||||
/* You can set the timer to only produce a single irq after the time */
|
||||
/* has elapsed or reset the counter for continuous irqs */
|
||||
#define SINGLE_CONT_MASK VA_TYPE 0x8000
|
||||
#define SINGLE_IRQ_CMD VA_TYPE 0x8000
|
||||
#define CONT_IRQ_CMD VA_TYPE 0x0000
|
||||
|
||||
/*************************************************************************
|
||||
* The vac timer rate is calculated as follows:
|
||||
*
|
||||
*
|
||||
* / CPU_CLOCK \
|
||||
* | ------------------- |
|
||||
* \ prescaler value + 1 /
|
||||
*timer rate = ------------------------------
|
||||
* (65536 - time data reg. value)
|
||||
*
|
||||
*
|
||||
* where prescaler is set to an arbitrary value.
|
||||
*
|
||||
*
|
||||
*this gives us a time data register value of
|
||||
*
|
||||
*
|
||||
* / CPU_CLOCK \
|
||||
* | ------------------- |
|
||||
* \ prescaler value + 1 /
|
||||
*timer data val = 65536 - ----------------------------
|
||||
* reqested timer rate
|
||||
*
|
||||
*
|
||||
*
|
||||
*
|
||||
*PROGRAMING EXAMPLE:
|
||||
*
|
||||
*
|
||||
*to get a 100Hz time rate with a 25MHz cpu clock
|
||||
*
|
||||
* - arbitrarily set prescaler value to 24 which will produce a
|
||||
* 1MHz time period for each count in the time data register
|
||||
*
|
||||
*
|
||||
* / 25000000 \
|
||||
* | --------- |
|
||||
* \ 24 + 1 /
|
||||
* time data val = 65536 - ------------- = 55536 = 0xd8f0
|
||||
* 100
|
||||
*
|
||||
*
|
||||
* - set prescaler
|
||||
* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~PRSCALER_IN_MASK) |
|
||||
* VAC_25MHZ_CPU_1MHZ_PRESCALER ;
|
||||
* - set timer data register
|
||||
* *H_VAC_TMR_DATA = 0x8df0 ;
|
||||
*
|
||||
* - disable timer and load above values into internal registers
|
||||
* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~RUN_LOAD_MASK) | STOP_N_LOAD_CMD ;
|
||||
*
|
||||
* - set control for continuous operation
|
||||
* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~SINGLE_CONT_MASK) | CONT_CMD ;
|
||||
*
|
||||
* - start timer
|
||||
* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~RUN_LOAD_MASK) | RUN_CMD ;
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
/* Vac ID Reg. Read to Startup */
|
||||
#define H_VAC_ID_GO P_VA_TYPE (VAC_ADR + 0x2900)
|
||||
|
||||
|
||||
|
||||
/* now for some generic io Macros */
|
||||
/* These macros are designed so that they can be dropped into a generic */
|
||||
/* serial handler, They are intended to be the basic building blocks used */
|
||||
/* to port any serial handler to use the VAC. */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
|
||||
#define SIOA 0
|
||||
#define SIOB 1
|
||||
|
||||
/*the following macros expect SIOA or SIOB for u arg-there's no error checking*/
|
||||
|
||||
#define XMITER_EMPTY(u) ( XMIT_EMPTY & vaRegGet( H_VAC_SIOA_STAT + \
|
||||
((u)* ( H_VAC_SIOB_STAT - H_VAC_SIOA_STAT ) ) ) )
|
||||
#define XMITER_READY(u) ( XMIT_READY & vaRegGet( H_VAC_SIOA_STAT + \
|
||||
((u)* ( H_VAC_SIOB_STAT - H_VAC_SIOA_STAT ) ) ) )
|
||||
#define RECVER_READY(u) ( CHAR_READY & vaRegGet( H_VAC_SIOA_STAT + \
|
||||
((u)* ( H_VAC_SIOB_STAT - H_VAC_SIOA_STAT ) ) ) )
|
||||
|
||||
#define XMIT_CHAR(u,ch) vaRegSet( H_VAC_SIOA_XMIT + \
|
||||
((u)* ( H_VAC_SIOB_XMIT - H_VAC_SIOA_XMIT ) ) , \
|
||||
(unsigned short)( ((unsigned short)(ch))<<8 ) )
|
||||
|
||||
#define RECV_CHAR(u,pc) *(pc) = (unsigned char)(0x00ff & \
|
||||
vaRegGet( H_VAC_SIOA_RECV + \
|
||||
((u)* ( H_VAC_SIOB_RECV - H_VAC_SIOA_RECV ) ) ) )
|
||||
|
||||
#define POLLING
|
||||
|
||||
/* The following P_GETC and P_PUTC macros are designed for POLLING only!!! */
|
||||
/* NOTE: The delay loops may need to be altered depending on the board rev. */
|
||||
#ifdef POLLING
|
||||
|
||||
/* P_PUTC(u,ch) - output char "ch" to "u" where "u" is SIOA or SIOB */
|
||||
/* add delay, NOTE: no fifo stuff allowed */
|
||||
|
||||
#define P_PUTC(u,ch) \
|
||||
while ( ! XMITER_READY( (u) ) ) ; \
|
||||
XMIT_CHAR( (u),(ch) ); \
|
||||
while ( XMITER_READY( (u) ) )
|
||||
|
||||
|
||||
/* P_GETC(u,pc) - input char into char pointer "pc" from */
|
||||
/* "u" where "u" is SIOA or SIOB */
|
||||
|
||||
#define P_GETC(u,pc) \
|
||||
{ \
|
||||
int x; \
|
||||
while ( ! RECVER_READY( (u) ) ) \
|
||||
for(x=0;x<100;x++) ; \
|
||||
RECV_CHAR( (u), (pc) ) ; \
|
||||
}
|
||||
|
||||
#endif /* POLLING */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCivach */
|
||||
@@ -0,0 +1,226 @@
|
||||
/* vbic.h - SBE VBIC Chip Set header */
|
||||
|
||||
/* Copyright 1984-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,22sep92,rrr added support for c++
|
||||
01d,26may92,rrr the tree shuffle
|
||||
01c,04oct91,rrr passed through the ansification filter
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01b,05oct90,shl added copyright notice.
|
||||
made #endif ANSI style.
|
||||
01a,10sep89,rld original SBE release.
|
||||
*/
|
||||
|
||||
/*
|
||||
This header file defines the register layout of the SBE VMEbus
|
||||
Interface Controller chip (VBIC) and supplies alpha-numeric
|
||||
equivalences for register bit definitions.
|
||||
*/
|
||||
|
||||
#ifndef __INCvbich
|
||||
#define __INCvbich
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define VBIC_ADRS(reg) (VBIC + (reg*VBIC_REG_OFFSET))
|
||||
#else
|
||||
#define VBIC_ADRS(reg) ((char *) VBIC + (reg*VBIC_REG_OFFSET))
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define VBIC_VECTNMI VBIC_ADRS(0x00) /* NMI vector */
|
||||
#define VBIC_VECTLIR1 VBIC_ADRS(0x01) /* Local vectors */
|
||||
#define VBIC_VECTLIR2 VBIC_ADRS(0x02)
|
||||
#define VBIC_VECTLIR3 VBIC_ADRS(0x03)
|
||||
#define VBIC_VECTLIR4 VBIC_ADRS(0x04)
|
||||
#define VBIC_VECTLIR5 VBIC_ADRS(0x05)
|
||||
#define VBIC_VECTLIR6 VBIC_ADRS(0x06)
|
||||
#define VBIC_VECTLIR7 VBIC_ADRS(0x07)
|
||||
#define VBIC_VECTLIR8 VBIC_ADRS(0x08)
|
||||
#define VBIC_VECTLIR9 VBIC_ADRS(0x09)
|
||||
#define VBIC_VECTLI10 VBIC_ADRS(0x0a)
|
||||
#define VBIC_VECTVIG VBIC_ADRS(0x0b) /* VMEbus Interrupt Generator */
|
||||
#define VBIC_VECTMSM VBIC_ADRS(0x0c) /* Millisecond Marker */
|
||||
#define VBIC_VECTVME VBIC_ADRS(0x0d) /* VMEbus interrupter for VIR1-7 */
|
||||
|
||||
#define VBIC_IRMASKA VBIC_ADRS(0x0e) /* Interrupt enable register A */
|
||||
#define M_LIR1 0x02 /* Enable level 1 interrupt */
|
||||
#define M_LIR2 0x04 /* Enable level 2 interrupt */
|
||||
#define M_LIR3 0x08 /* Enable level 3 interrupt */
|
||||
#define M_LIR4 0x10 /* Enable level 4 interrupt */
|
||||
#define M_LIR5 0x20 /* Enable level 5 interrupt */
|
||||
#define M_LIR6 0x40 /* Enable level 6 interrupt */
|
||||
#define M_LIR7 0x80 /* Enable level 7 interrupt */
|
||||
|
||||
#define VBIC_IRMASKB VBIC_ADRS(0x0f) /* Interrupt enable register B */
|
||||
#define M_LIR8 0x01 /* Enable level 8 interrupt */
|
||||
#define M_LIR9 0x02 /* Enable level 9 interrupt */
|
||||
#define M_LIR10 0x04 /* Enable level 10 interrupt */
|
||||
#define M_MSM 0x40 /* Enable MSM interrupt */
|
||||
#define M_VIG 0x80 /* Enable VIG interrupt */
|
||||
|
||||
#define VBIC_IRMASKC VBIC_ADRS(0x10) /* Interrupt enable register C */
|
||||
#define M_VIR1 0x02 /* Enable VME level 1 interrupt */
|
||||
#define M_VIR2 0x04 /* Enable VME level 2 interrupt */
|
||||
#define M_VIR3 0x08 /* Enable VME level 3 interrupt */
|
||||
#define M_VIR4 0x10 /* Enable VME level 4 interrupt */
|
||||
#define M_VIR5 0x20 /* Enable VME level 5 interrupt */
|
||||
#define M_VIR6 0x40 /* Enable VME level 6 interrupt */
|
||||
#define M_VIR7 0x80 /* Enable VME level 7 interrupt */
|
||||
|
||||
#define VBIC_IRSCANA VBIC_ADRS(0x11) /* Interrupt Request status A */
|
||||
#define S_LIR1 0x02 /* Asserting level 1 intr */
|
||||
#define S_LIR2 0x04 /* Asserting level 2 intr */
|
||||
#define S_LIR3 0x08 /* Asserting level 3 intr */
|
||||
#define S_LIR4 0x10 /* Asserting level 4 intr */
|
||||
#define S_LIR5 0x20 /* Asserting level 5 intr */
|
||||
#define S_LIR6 0x40 /* Asserting level 6 intr */
|
||||
#define S_LIR7 0x80 /* Asserting level 7 intr */
|
||||
|
||||
#define VBIC_IRSCANB VBIC_ADRS(0x12) /* Interrupt Request status B */
|
||||
#define S_LIR8 0x01 /* Asserting level 8 intr */
|
||||
#define S_LIR9 0x02 /* Asserting level 9 intr */
|
||||
#define S_LIR10 0x04 /* Asserting level 10 intr */
|
||||
#define S_MSM 0x40 /* Asserting MSM intr */
|
||||
#define S_VIG 0x80 /* Asserting VIG intr */
|
||||
|
||||
#define VBIC_IRSCANC VBIC_ADRS(0x13) /* VIR1-7 Int Request status C */
|
||||
#define S_VIR1 0x02 /* Asserting VME level 1 intr */
|
||||
#define S_VIR2 0x04 /* Asserting VME level 2 intr */
|
||||
#define S_VIR3 0x08 /* Asserting VME level 3 intr */
|
||||
#define S_VIR4 0x10 /* Asserting VME level 4 intr */
|
||||
#define S_VIR5 0x20 /* Asserting VME level 5 intr */
|
||||
#define S_VIR6 0x40 /* Asserting VME level 6 intr */
|
||||
#define S_VIR7 0x80 /* Asserting VME level 7 intr */
|
||||
|
||||
#define VBIC_VBICCTL VBIC_ADRS(0x14) /* VBIC Control */
|
||||
#define VBC_NONMIV 0 /* NMI uses VECTNMI as vector */
|
||||
#define VBC_NMIV 0x80 /* NMI is auto-vectored */
|
||||
|
||||
#define VBIC_ICLIR1 VBIC_ADRS(0x15) /* Interruptor Config */
|
||||
#define VBIC_ICLIR2 VBIC_ADRS(0x16)
|
||||
#define VBIC_ICLIR3 VBIC_ADRS(0x17)
|
||||
#define VBIC_ICLIR4 VBIC_ADRS(0x18)
|
||||
#define VBIC_ICLIR5 VBIC_ADRS(0x19)
|
||||
#define VBIC_ICLIR6 VBIC_ADRS(0x1a)
|
||||
#define VBIC_ICLIR7 VBIC_ADRS(0x1b)
|
||||
#define VBIC_ICLIR8 VBIC_ADRS(0x1c)
|
||||
#define VBIC_ICLIR9 VBIC_ADRS(0x1d)
|
||||
#define VBIC_ICLIR10 VBIC_ADRS(0x1e)
|
||||
#define ICL_AUTOV 0x80 /* Auto-vectored interrupt */
|
||||
#define ICL_EXTV 0x40 /* External vectored interrupt */
|
||||
#define ICL_EDGE 0x20 /* Edge sensitive interrupter */
|
||||
#define ICL_LEVEL 0x00 /* Level sensitive interrupter */
|
||||
#define ICL_HIGH 0x10 /* Active high / rising edge */
|
||||
#define ICL_LOW 0x00 /* Active low / falling edge */
|
||||
|
||||
#define VBIC_ICVIR1 VBIC_ADRS(0x1f) /* VME Interruptor Config */
|
||||
#define VBIC_ICVIR2 VBIC_ADRS(0x20)
|
||||
#define VBIC_ICVIR3 VBIC_ADRS(0x21)
|
||||
#define VBIC_ICVIR4 VBIC_ADRS(0x22)
|
||||
#define VBIC_ICVIR5 VBIC_ADRS(0x23)
|
||||
#define VBIC_ICVIR6 VBIC_ADRS(0x24)
|
||||
#define VBIC_ICVIR7 VBIC_ADRS(0x25)
|
||||
|
||||
#define VBIC_ICVIG VBIC_ADRS(0x26) /* VIG Interrupter Config */
|
||||
#define VBIC_ICMSM VBIC_ADRS(0x27) /* MSM Interruptor Config */
|
||||
#define VBIC_MSMCTL VBIC_ADRS(0x28) /* Millisecond Marker Control */
|
||||
#define MSM_IRQEN 0x80 /* MSM interrupter is enabled */
|
||||
#define MSM_HALTED 0x40 /* MSM is halted */
|
||||
#define MSM_MSEC1 0x20 /* MSM is in 1ms mode */
|
||||
#define MSM_TEST 0x10 /* MSM is in test mode */
|
||||
#define MSM_NORMAL 2 /* cmd: set to normal (~test) */
|
||||
#define MSM_SEC1 3 /* cmd: 1ms interrupt mode */
|
||||
#define MSM_SEC10 4 /* cmd: 10ms interrupt mode */
|
||||
#define MSM_STOP 5 /* cmd: stops MSM counter */
|
||||
#define MSM_GO 6 /* cmd: starts MSM counter */
|
||||
#define MSM_INIT 7 /* cmd: sets MSM counter to 0 */
|
||||
|
||||
#define VBIC_VIRSID1 VBIC_ADRS(0x29) /* StsID latched from VME level 1 */
|
||||
#define VBIC_VIRSID2 VBIC_ADRS(0x2a)
|
||||
#define VBIC_VIRSID3 VBIC_ADRS(0x2b)
|
||||
#define VBIC_VIRSID4 VBIC_ADRS(0x2c)
|
||||
#define VBIC_VIRSID5 VBIC_ADRS(0x2d)
|
||||
#define VBIC_VIRSID6 VBIC_ADRS(0x2e)
|
||||
#define VBIC_VIRSID7 VBIC_ADRS(0x2f)
|
||||
|
||||
#define VBIC_RSTCTL VBIC_ADRS(0x30) /* Software Reset Control */
|
||||
#define VBIC_RESET 0x6a /* cmd: resets VBIC */
|
||||
#define VBIC_SLOTSTAT VBIC_ADRS(0x37) /* Slot-1 status */
|
||||
#define SLOT1 0x80 /* slot 1 jumper installed */
|
||||
#define VBIC_VOUTCTL VBIC_ADRS(0x40) /* VME Interrupt Output Control */
|
||||
#define VIG_GEN_1 0x01 /* Generate bus intr level 1 */
|
||||
#define VIG_GEN_2 0x02 /* Generate bus intr level 2 */
|
||||
#define VIG_GEN_3 0x03 /* Generate bus intr level 3 */
|
||||
#define VIG_GEN_4 0x04 /* Generate bus intr level 4 */
|
||||
#define VIG_GEN_5 0x05 /* Generate bus intr level 5 */
|
||||
#define VIG_GEN_6 0x06 /* Generate bus intr level 6 */
|
||||
#define VIG_GEN_7 0x07 /* Generate bus intr level 7 */
|
||||
#define VIG_PEND_1 0x02 /* Pending bus intr level 1 */
|
||||
#define VIG_PEND_2 0x04 /* Pending bus intr level 2 */
|
||||
#define VIG_PEND_3 0x08 /* Pending bus intr level 3 */
|
||||
#define VIG_PEND_4 0x10 /* Pending bus intr level 4 */
|
||||
#define VIG_PEND_5 0x20 /* Pending bus intr level 5 */
|
||||
#define VIG_PEND_6 0x40 /* Pending bus intr level 6 */
|
||||
#define VIG_PEND_7 0x80 /* Pending bus intr level 7 */
|
||||
|
||||
#define VBIC_VOUTSID1 VBIC_ADRS(0x41) /* StsID to send for VME level 1 */
|
||||
#define VBIC_VOUTSID2 VBIC_ADRS(0x42) /* StsID to send for VME level 2 */
|
||||
#define VBIC_VOUTSID3 VBIC_ADRS(0x43) /* StsID to send for VME level 3 */
|
||||
#define VBIC_VOUTSID4 VBIC_ADRS(0x44) /* StsID to send for VME level 4 */
|
||||
#define VBIC_VOUTSID5 VBIC_ADRS(0x45) /* StsID to send for VME level 5 */
|
||||
#define VBIC_VOUTSID6 VBIC_ADRS(0x46) /* StsID to send for VME level 6 */
|
||||
#define VBIC_VOUTSID7 VBIC_ADRS(0x47) /* StsID to send for VME level 7 */
|
||||
|
||||
#define VBIC_VIGCTL VBIC_ADRS(0x48) /* VMEbus Intr Generator Control */
|
||||
#define VIG_ENABLE_1 0x02 /* Enable VME int ACK interrupt */
|
||||
#define VIG_ENABLE_2 0x04
|
||||
#define VIG_ENABLE_3 0x08
|
||||
#define VIG_ENABLE_4 0x10
|
||||
#define VIG_ENABLE_5 0x20
|
||||
#define VIG_ENABLE_6 0x40
|
||||
#define VIG_ENABLE_7 0x80
|
||||
|
||||
#define VBIC_VIASR VBIC_ADRS(0x49) /* VMEbus Intr Ack Status */
|
||||
#define SR_IACK_1 0x02 /* Level 1 IACK completed */
|
||||
#define SR_IACK_2 0x04 /* Level 2 IACK completed */
|
||||
#define SR_IACK_3 0x08 /* Level 3 IACK completed */
|
||||
#define SR_IACK_4 0x10 /* Level 4 IACK completed */
|
||||
#define SR_IACK_5 0x20 /* Level 5 IACK completed */
|
||||
#define SR_IACK_6 0x40 /* Level 6 IACK completed */
|
||||
#define SR_IACK_7 0x80 /* Level 7 IACK completed */
|
||||
|
||||
#define VBIC_SRCLR VBIC_ADRS(0x4a) /* VIASR Bit CLear */
|
||||
#define SRCLR_1 0x01 /* Clear bit 1 of VIASR */
|
||||
#define SRCLR_2 0x02 /* Clear bit 2 of VIASR */
|
||||
#define SRCLR_3 0x03 /* Clear bit 3 of VIASR */
|
||||
#define SRCLR_4 0x04 /* Clear bit 4 of VIASR */
|
||||
#define SRCLR_5 0x05 /* Clear bit 5 of VIASR */
|
||||
#define SRCLR_6 0x06 /* Clear bit 6 of VIASR */
|
||||
#define SRCLR_7 0x07 /* Clear bit 7 of VIASR */
|
||||
|
||||
#define VBIC_SYSCTL VBIC_ADRS(0x4b) /* System Control Register */
|
||||
#define BUS_TIME_16 0x00 /* 16us timeout period */
|
||||
#define BUS_TIME_32 0x40 /* 32us timeout period */
|
||||
#define BUS_TIME_64 0x80 /* 64us timeout period */
|
||||
#define BUS_TIME_128 0xc0 /* 128us timeout period */
|
||||
#define BUS_ARB_RRS 0x00 /* Round robin */
|
||||
#define BUS_ARB_PRRS 0x20 /* Priority round robin */
|
||||
#define BUS_ARB_PRI 0x30 /* Absolute priority */
|
||||
#define BUS_LVL_0 0x00 /* Use bus request level 0 */
|
||||
#define BUS_LVL_1 0x04 /* Use bus request level 1 */
|
||||
#define BUS_LVL_2 0x08 /* Use bus request level 2 */
|
||||
#define BUS_LVL_3 0x0c /* Use bus request level 3 */
|
||||
#define BUS_REL_ROR 0x00 /* Release bus on request */
|
||||
#define BUS_REL_RWD 0x02 /* Release bus when done */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvbich */
|
||||
@@ -0,0 +1,701 @@
|
||||
/* vic068.h - VMEbus Interface Controller */
|
||||
|
||||
/* Copyright 1984-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,22sep92,rrr added support for c++
|
||||
01j,26may92,rrr the tree shuffle
|
||||
01i,04oct91,rrr passed through the ansification filter
|
||||
-fixed #else and #endif
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01h,06may91,nfs moved ifdef's to ensure clean mangening
|
||||
01g,30apr91,nfs added ifdef for documentation
|
||||
01f,25apr91,nfs corrected VME_ICGS and VME_ICMS defines (rs33 document error)
|
||||
corrected VME_SET_ADRS and VME_CLR_ADRS (VIC document error)
|
||||
ICR5 defines removed, revisions are referred to by their hex
|
||||
code (f1,f2,f3,f4,f5 and f8 are currently valid)
|
||||
01e,25mar91,del re-definition of VIC_ADRS and VME_ICF_ADRS permitted
|
||||
01d,25mar91,nfs re-written
|
||||
jcf
|
||||
01c,25nov90,gae WRS cleanup.
|
||||
01b,22mar90,eve general cleanup
|
||||
01a,12mar89,fwa written.
|
||||
*/
|
||||
|
||||
#ifdef DOC
|
||||
#define INCvic068h
|
||||
#endif /* DOC */
|
||||
|
||||
#ifndef __INCvic068h
|
||||
#define __INCvic068h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
This file contains constants for the VTC VMEbus Interface controller.
|
||||
The macro VIC_BASE_ADRS must be defined when including this header.
|
||||
|
||||
The following standards have been adopted in the creation of this file.
|
||||
|
||||
Register definitions which provide access to the VIC chip locally
|
||||
(on-board) have the prefix "VIC". Register definitions which provide
|
||||
access to the VIC chip via the VMEbus (off-board) have the prefix
|
||||
"VME".
|
||||
|
||||
The registers are listed in ascending (numerical) order; the definitions
|
||||
for each register are started with a header eg.
|
||||
|
||||
Register Register Register Register
|
||||
Mnemonic Number Address Name
|
||||
| | | |
|
||||
v v v v
|
||||
*****************************************************************
|
||||
* VIICR 0x01 0x03 VME Interrupter Irq Control Reg *
|
||||
*****************************************************************
|
||||
|
||||
in some cases where a number of registers have the same definitions the
|
||||
header looks like this eg.
|
||||
|
||||
****************************************************************
|
||||
* VICR1 0x02 0x07 VME Interrupt Control Reg #1 *
|
||||
* to *
|
||||
* VICR7 0x08 0x1f VME Interrupt Control Reg #7 *
|
||||
****************************************************************
|
||||
|
||||
The format of the definitions is as follows; the define name always
|
||||
starts with the register mnemonic it is associated with. The [7-0]
|
||||
number at the end of the comment indicates the bit position the define
|
||||
applies to; the definition ICGICR_IRQ_EN_ICGS3, in the following
|
||||
example, the 7 applies to bit 7
|
||||
| |
|
||||
v v
|
||||
define ICGICR_IRQ_EN_ICGS3 0x00 * enable ICGS3 local int 7 *
|
||||
|
||||
If the define applies to more than one bit, then the applicable bit
|
||||
range is specified by two digits; in the following example ICGICR_IRQ_EN_ICGS,
|
||||
applies to the four bit field, bits 7-4.
|
||||
|
|
||||
v
|
||||
define ICGICR_IRQ_EN_ICGS 0x00 * enable all ICGS local int's 74 *
|
||||
|
||||
If no bit field is given, then the define applies to the whole register.
|
||||
*/
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST
|
||||
#else
|
||||
/* #define CAST (UCHAR *) */
|
||||
#define CAST (char *)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/* on-board access, register definitions */
|
||||
|
||||
#define VIC_REG_INTERVAL 4
|
||||
|
||||
#ifndef VIC_ADRS /* to permit alternative board addressing */
|
||||
#define VIC_ADRS(reg) (CAST (VIC_BASE_ADRS + (reg * VIC_REG_INTERVAL) + 3))
|
||||
#endif /* VIC_ADRS */
|
||||
|
||||
#define VIC_VIICR VIC_ADRS(0x00) /* VME Interrupter Irq Control Reg */
|
||||
#define VIC_VICR1 VIC_ADRS(0x01) /* VME Interrupt Control Reg #1 */
|
||||
#define VIC_VICR2 VIC_ADRS(0x02) /* VME Interrupt Control Reg #2 */
|
||||
#define VIC_VICR3 VIC_ADRS(0x03) /* VME Interrupt Control Reg #3 */
|
||||
#define VIC_VICR4 VIC_ADRS(0x04) /* VME Interrupt Control Reg #4 */
|
||||
#define VIC_VICR5 VIC_ADRS(0x05) /* VME Interrupt Control Reg #5 */
|
||||
#define VIC_VICR6 VIC_ADRS(0x06) /* VME Interrupt Control Reg #6 */
|
||||
#define VIC_VICR7 VIC_ADRS(0x07) /* VME Interrupt Control Reg #7 */
|
||||
#define VIC_DSICR VIC_ADRS(0x08) /* DMA Status Int Control Reg */
|
||||
#define VIC_LICR1 VIC_ADRS(0x09) /* Local Interrupt Control Reg #1 */
|
||||
#define VIC_LICR2 VIC_ADRS(0x0a) /* Local Interrupt Control Reg #2 */
|
||||
#define VIC_LICR3 VIC_ADRS(0x0b) /* Local Interrupt Control Reg #3 */
|
||||
#define VIC_LICR4 VIC_ADRS(0x0c) /* Local Interrupt Control Reg #4 */
|
||||
#define VIC_LICR5 VIC_ADRS(0x0d) /* Local Interrupt Control Reg #5 */
|
||||
#define VIC_LICR6 VIC_ADRS(0x0e) /* Local Interrupt Control Reg #6 */
|
||||
#define VIC_LICR7 VIC_ADRS(0x0f) /* Local Interrupt Control Reg #7 */
|
||||
#define VIC_ICGICR VIC_ADRS(0x10) /* ICGS Interrupt Control Reg */
|
||||
#define VIC_ICMICR VIC_ADRS(0x11) /* ICMS Interrupt Control Reg */
|
||||
#define VIC_EGICR VIC_ADRS(0x12) /* Error Group Int Control Reg */
|
||||
#define VIC_ICGIVBR VIC_ADRS(0x13) /* ICGS Interrupt Vector Base Reg */
|
||||
#define VIC_ICMIVBR VIC_ADRS(0x14) /* ICMS Interrupt Vector Base Reg */
|
||||
#define VIC_LIVBR VIC_ADRS(0x15) /* Local Int Vector Base Reg */
|
||||
#define VIC_EGIVBR VIC_ADRS(0x16) /* Error Group Int Vec Base Reg */
|
||||
#define VIC_ICSR VIC_ADRS(0x17) /* Interprocessor Comm Switch Reg */
|
||||
#define VIC_ICR0 VIC_ADRS(0x18) /* Interprocessor Comm. Reg #0 */
|
||||
#define VIC_ICR1 VIC_ADRS(0x19) /* Interprocessor Comm. Reg #1 */
|
||||
#define VIC_ICR2 VIC_ADRS(0x1a) /* Interprocessor Comm. Reg #2 */
|
||||
#define VIC_ICR3 VIC_ADRS(0x1b) /* Interprocessor Comm. Reg #3 */
|
||||
#define VIC_ICR4 VIC_ADRS(0x1c) /* Interprocessor Comm. Reg #4 */
|
||||
#define VIC_ICR5 VIC_ADRS(0x1d) /* Interprocessor Comm. Reg #5 */
|
||||
#define VIC_ICR6 VIC_ADRS(0x1e) /* Interprocessor Comm. Reg #6 */
|
||||
#define VIC_ICR7 VIC_ADRS(0x1f) /* Interprocessor Comm. Reg #7 */
|
||||
#define VIC_VIRSR VIC_ADRS(0x20) /* VME Interrupt Request/Stat. Reg */
|
||||
#define VIC_VIVR1 VIC_ADRS(0x21) /* VME Interrupt Vector Reg #1 */
|
||||
#define VIC_VIVR2 VIC_ADRS(0x22) /* VME Interrupt Vector Reg #2 */
|
||||
#define VIC_VIVR3 VIC_ADRS(0x23) /* VME Interrupt Vector Reg #3 */
|
||||
#define VIC_VIVR4 VIC_ADRS(0x24) /* VME Interrupt Vector Reg #4 */
|
||||
#define VIC_VIVR5 VIC_ADRS(0x25) /* VME Interrupt Vector Reg #5 */
|
||||
#define VIC_VIVR6 VIC_ADRS(0x26) /* VME Interrupt Vector Reg #6 */
|
||||
#define VIC_VIVR7 VIC_ADRS(0x27) /* VME Interrupt Vector Reg #7 */
|
||||
#define VIC_TTR VIC_ADRS(0x28) /* Transfer Time-out Reg */
|
||||
#define VIC_LBTR VIC_ADRS(0x29) /* Local Bus Timing Reg */
|
||||
#define VIC_BTDR VIC_ADRS(0x2a) /* Block Transfer Definition Reg */
|
||||
#define VIC_ICR VIC_ADRS(0x2b) /* Interface Configuration Reg */
|
||||
#define VIC_ARCR VIC_ADRS(0x2c) /* Arbiter/Requester Config. Reg */
|
||||
#define VIC_AMSR VIC_ADRS(0x2d) /* AM Source Reg */
|
||||
#define VIC_BESR VIC_ADRS(0x2e) /* Bus Error Status Reg */
|
||||
#define VIC_DSR VIC_ADRS(0x2f) /* DMA Status Reg */
|
||||
#define VIC_SS0CR0 VIC_ADRS(0x30) /* Slave Select 0/Control Reg #0 */
|
||||
#define VIC_SS0CR1 VIC_ADRS(0x31) /* Slave Select 0/Control Reg #1 */
|
||||
#define VIC_SS1CR0 VIC_ADRS(0x32) /* Slave Select 1/Control Reg #0 */
|
||||
#define VIC_SS1CR1 VIC_ADRS(0x33) /* Slave Select 1/Control Reg #1 */
|
||||
#define VIC_RCR VIC_ADRS(0x34) /* Release Control Reg */
|
||||
#define VIC_BTCR VIC_ADRS(0x35) /* Block Transfer Control Reg */
|
||||
#define VIC_BTLR0 VIC_ADRS(0x36) /* Block Transfer Length Reg #0 */
|
||||
#define VIC_BTLR1 VIC_ADRS(0x37) /* Block Transfer Length Reg #1 */
|
||||
#define VIC_SRR VIC_ADRS(0x38) /* System Reset Reg */
|
||||
|
||||
/* off-board access, register definitions */
|
||||
|
||||
#define VME_ICF_REG_INTERVAL 2
|
||||
|
||||
#ifndef VME_ICF_ADRS /* to permit alternative off-board addressing */
|
||||
#define VME_ICF_ADRS(adrs, icf, type, reg) \
|
||||
(CAST (adrs + icf + (reg * VME_ICF_REG_INTERVAL) + type ))
|
||||
#endif /* VME_ICF_ADRS */
|
||||
|
||||
/* Interprocessor Communication Facility - icf */
|
||||
|
||||
#define VME_ICR 0x00 /* IC Registers ICR0-7 */
|
||||
#define VME_ICGS 0x10 /* IC Global Switches ICGS0-3 */
|
||||
#define VME_ICMS 0x20 /* IC Module Switches ICMS0-3 */
|
||||
|
||||
/* Type of register access - type */
|
||||
|
||||
#define VME_ODD_ADRS 0x01 /* ICR always accessed at odd byte addresses */
|
||||
|
||||
#define VME_SET_ADRS 0x01 /* ICGS and ICMS set switch access */
|
||||
#define VME_CLR_ADRS 0x00 /* ICGS and ICMS clear switch access */
|
||||
|
||||
#define VME_ICR0(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,0)
|
||||
#define VME_ICR1(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,1)
|
||||
#define VME_ICR2(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,2)
|
||||
#define VME_ICR3(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,3)
|
||||
#define VME_ICR4(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,4)
|
||||
#define VME_ICR5(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,5)
|
||||
#define VME_ICR6(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,6)
|
||||
#define VME_ICR7(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICR,VME_ODD_ADRS,7)
|
||||
|
||||
#define VME_ICGS0_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,0)
|
||||
#define VME_ICGS0_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,0)
|
||||
#define VME_ICGS1_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,1)
|
||||
#define VME_ICGS1_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,1)
|
||||
#define VME_ICGS2_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,2)
|
||||
#define VME_ICGS2_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,2)
|
||||
#define VME_ICGS3_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_SET_ADRS,3)
|
||||
#define VME_ICGS3_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICGS,VME_CLR_ADRS,3)
|
||||
|
||||
#define VME_ICMS0_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,0)
|
||||
#define VME_ICMS0_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,0)
|
||||
#define VME_ICMS1_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,1)
|
||||
#define VME_ICMS1_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,1)
|
||||
#define VME_ICMS2_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,2)
|
||||
#define VME_ICMS2_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,2)
|
||||
#define VME_ICMS3_SET(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_SET_ADRS,3)
|
||||
#define VME_ICMS3_CLR(baseAdrs) VME_ICF_ADRS(baseAdrs,VME_ICMS,VME_CLR_ADRS,3)
|
||||
|
||||
/****************************************************************
|
||||
* VIICR 0x00 0x03 VME Interrupter Irq Control Reg *
|
||||
*****************************************************************/
|
||||
|
||||
#define VIICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask 7 */
|
||||
#define VIICR_IRQ_DISABLE 0x80 /* disable interrupter IRQ 7 */
|
||||
|
||||
/***************************************************************
|
||||
* VICR1 0x01 0x07 VME Interrupt Control Reg #1 *
|
||||
* to *
|
||||
* VICR7 0x07 0x1f VME Interrupt Control Reg #7 *
|
||||
****************************************************************/
|
||||
|
||||
#define VICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask 7 */
|
||||
#define VICR_IRQ_DISABLE 0x80 /* disable interrupt IRQ 7 */
|
||||
|
||||
/***************************************************************
|
||||
* DSICR 0x08 0x23 DMA Status Int Control Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define DSICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask 7 */
|
||||
#define DSICR_IRQ_DISABLE 0x80 /* disable DMA termination IRQ 7 */
|
||||
|
||||
/***************************************************************
|
||||
* LICR1 0x09 0x27 Local Interrupt Control Reg #1 *
|
||||
* to *
|
||||
* LICR7 0x0f 0x3f Local Interrupt Control Reg #7 *
|
||||
****************************************************************/
|
||||
|
||||
#define LICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask */
|
||||
#define LICR_IRQ_STATE 0x08 /* LIRQ(i) state 3 */
|
||||
#define LICR_IRQ_VEC_DEV 0x00 /* device supplies vector 4 */
|
||||
#define LICR_IRQ_VEC_VIC 0x10 /* VIC supplies vector 4 */
|
||||
#define LICR_IRQ_LEVEL 0x00 /* level sensitive 5 */
|
||||
#define LICR_IRQ_EDGE 0x20 /* edge sensitive 5 */
|
||||
#define LICR_IRQ_ACTIVEL 0x00 /* active low 6 */
|
||||
#define LICR_IRQ_ACTIVEH 0x40 /* active high 6 */
|
||||
#define LICR_IRQ_ENABLE 0x00 /* enable IRQ 7 */
|
||||
#define LICR_IRQ_DISABLE 0x80 /* disable IRQ 7 */
|
||||
|
||||
/***************************************************************
|
||||
* ICGICR 0x10 0x43 ICGS Interrupt Control Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define ICGICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask */
|
||||
#define ICGICR_IRQ_ICGS0_ENA 0x00 /* enable ICGS0 local interrpt 4 */
|
||||
#define ICGICR_IRQ_ICGS0_DIS 0x10 /* disable ICGS0 local interrpt 4 */
|
||||
#define ICGICR_IRQ_ICGS1_ENA 0x00 /* enable ICGS1 local interrpt 5 */
|
||||
#define ICGICR_IRQ_ICGS1_DIS 0x20 /* disable ICGS1 local interrpt 5 */
|
||||
#define ICGICR_IRQ_ICGS2_ENA 0x00 /* enable ICGS2 local interrpt 6 */
|
||||
#define ICGICR_IRQ_ICGS2_DIS 0x40 /* disable ICGS2 local interrpt 6 */
|
||||
#define ICGICR_IRQ_ICGS3_ENA 0x00 /* enable ICGS3 local interrpt 7 */
|
||||
#define ICGICR_IRQ_ICGS3_DIS 0x80 /* disable ICGS3 local interrpt 7 */
|
||||
|
||||
/***************************************************************
|
||||
* ICMICR 0x11 0x47 ICMS Interrupt Control Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define ICMICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask */
|
||||
#define ICMICR_IRQ_ICMS0_DIS 0x10 /* disable ICMS0 local interrpt 4 */
|
||||
#define ICMICR_IRQ_ICMS1_DIS 0x20 /* disable ICMS1 local interrpt 5 */
|
||||
#define ICMICR_IRQ_ICMS2_DIS 0x40 /* disable ICMS2 local interrpt 6 */
|
||||
#define ICMICR_IRQ_ICMS3_DIS 0x80 /* disable ICMS3 local interrpt 7 */
|
||||
|
||||
/***************************************************************
|
||||
* EGICR 0x12 0x4b Error Group Int Control Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define EGICR_IRQ_LVL_MASK 0x07 /* local interrupt level mask */
|
||||
#define EGICR_IRQ_SYSFAIL_ENA 0x00 /* enable SYSFAIL* local int 4 */
|
||||
#define EGICR_IRQ_SYSFAIL_DIS 0x10 /* disable SYSFAIL* local int 4 */
|
||||
#define EGICR_IRQ_ABTTO_ENA 0x00 /* enable arbitration time out 5 */
|
||||
#define EGICR_IRQ_ABTTO_DIS 0x20 /* disable arbitration time out 5 */
|
||||
#define EGICR_IRQ_WPFAIL_ENA 0x00 /* enable write post fail 6 */
|
||||
#define EGICR_IRQ_WPFAIL_DIS 0x40 /* disable write post fail 6 */
|
||||
#define EGICR_IRQ_ACFAIL_ENA 0x00 /* enable ACFAIL* local int 7 */
|
||||
#define EGICR_IRQ_ACFAIL_DIS 0x80 /* disable ACFAIL* local int 7 */
|
||||
|
||||
/***************************************************************
|
||||
* ICGIVBR 0x13 0x4f ICGS Interrupt Vector Base Reg *
|
||||
****************************************************************/
|
||||
|
||||
/* Identity of interrupting ICGS (read only) */
|
||||
|
||||
#define ICGIVBR_ICGS0 0x00 /* ICGS0 10 */
|
||||
#define ICGIVBR_ICGS1 0x01 /* ICGS1 10 */
|
||||
#define ICGIVBR_ICGS2 0x02 /* ICGS2 10 */
|
||||
#define ICGIVBR_ICGS3 0x03 /* ICGS3 10 */
|
||||
#define ICGIVBR_VEC_MASK 0xfc /* ICGS vector base mask */
|
||||
|
||||
/***************************************************************
|
||||
* ICMIVBR 0x14 0x53 ICMS Interrupt Vector Base Reg *
|
||||
****************************************************************/
|
||||
|
||||
/* Identity of interrupting ICMS (read only) */
|
||||
|
||||
#define ICMIVBR_ICMS0 0x00 /* ICMS0 10 */
|
||||
#define ICMIVBR_ICMS1 0x01 /* ICMS1 10 */
|
||||
#define ICMIVBR_ICMS2 0x02 /* ICMS2 10 */
|
||||
#define ICMIVBR_ICMS3 0x03 /* ICMS3 10 */
|
||||
#define ICMIVBR_VEC_MASK 0xfc /* ICMI vector base mask */
|
||||
|
||||
/***************************************************************
|
||||
* LIVBR 0x15 0x57 Local Int Vector Base Reg *
|
||||
****************************************************************/
|
||||
|
||||
/* Identity of local interrupt (read only) */
|
||||
|
||||
#define LIVBR_LIRQ1 0x01 /* LIRQ1 20 */
|
||||
#define LIVBR_LIRQ2 0x02 /* LIRQ2 20 */
|
||||
#define LIVBR_LIRQ3 0x03 /* LIRQ3 20 */
|
||||
#define LIVBR_LIRQ4 0x04 /* LIRQ4 20 */
|
||||
#define LIVBR_LIRQ5 0x05 /* LIRQ5 20 */
|
||||
#define LIVBR_LIRQ6 0x06 /* LIRQ6 20 */
|
||||
#define LIVBR_LIRQ7 0x07 /* LIRQ7 20 */
|
||||
#define LIVBR_VEC_MASK 0xf8 /* LIRQ vector base mask */
|
||||
|
||||
/***************************************************************
|
||||
* EGIVBR 0x16 0x5b Error Group Int Vec Base Reg *
|
||||
****************************************************************/
|
||||
|
||||
/* Error Conditions (read only) */
|
||||
|
||||
#define EGIVBR_ACFAIL 0x00 /* ACFAIL* error condition 20 */
|
||||
#define EGIVBR_WPFAIL 0x01 /* write post fail error cond 20 */
|
||||
#define EGIVBR_ABTTO 0x02 /* arbitration time out err con 20 */
|
||||
#define EGIVBR_SYSFAIL 0x03 /* SYSFAIL* error condition 20 */
|
||||
#define EGIVBR_VIIA 0x04 /* VMEbus Interrupter Interrupt 20 */
|
||||
/* Acknowledge error condition 20 */
|
||||
#define EGIVBR_DMAI 0x05 /* DMA Interrupt 20 */
|
||||
#define EGIVBR_VEC_MASK 0xf8 /* EGIRQ vector base mask */
|
||||
|
||||
/***************************************************************
|
||||
* ICSR 0x17 0x5f Interprocessor Comm Switch Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define ICSR_ICMS0 0x01 /* set ICMS0 0 */
|
||||
#define ICSR_ICMS1 0x02 /* set ICMS1 1 */
|
||||
#define ICSR_ICMS2 0x04 /* set ICMS2 2 */
|
||||
#define ICSR_ICMS3 0x08 /* set ICMS3 3 */
|
||||
|
||||
/* ICGS (read only) */
|
||||
|
||||
#define ICSR_ICGS0 0x10 /* set ICGS0 4 */
|
||||
#define ICSR_ICGS1 0x20 /* set ICGS1 5 */
|
||||
#define ICSR_ICGS2 0x40 /* set ICGS2 6 */
|
||||
#define ICSR_ICGS3 0x80 /* set ICGS3 7 */
|
||||
|
||||
/***************************************************************
|
||||
* ICR0 0x18 0x63 Interprocessor Comm. Reg #0 *
|
||||
* to *
|
||||
* ICR4 0x1c 0x73 Interprocessor Comm. Reg #4 *
|
||||
****************************************************************/
|
||||
|
||||
/* none */
|
||||
|
||||
/***************************************************************
|
||||
* ICR5 0x1d 0x77 Interprocessor Comm. Reg #5 *
|
||||
* (VIC ID Register) *
|
||||
****************************************************************/
|
||||
|
||||
/* none - revisions are referred to by the hex code */
|
||||
|
||||
/***************************************************************
|
||||
* ICR6 0x1e 0x7b Interprocessor Comm. Reg #6 *
|
||||
****************************************************************/
|
||||
|
||||
/* XXX should the following fields be 6 or 7 bits wide ? */
|
||||
|
||||
#define ICR6_HALT 0x3d /* VIC detected VME HALT 50 */
|
||||
#define ICR6_IRESET 0x3e /* VIC performing reset function 50 */
|
||||
#define ICR6_SYSRESET 0x3f /* VMEbus SYSRESET 50 */
|
||||
#define ICR6_HALT_IRESET 0x40 /* VMEbus HALT or IRESET asserted 6 */
|
||||
#define ICR6_SYSFAIL 0x40 /* assert SYSFAIL 6 */
|
||||
#define ICR6_ACFAIL 0x80 /* ACFAIL state 7 */
|
||||
|
||||
/***************************************************************
|
||||
* ICR7 0x1f 0x7f Interprocessor Comm. Reg #7 *
|
||||
****************************************************************/
|
||||
|
||||
#define ICR7_ICR0 0x01 /* ICR0 semaphore 0 */
|
||||
#define ICR7_ICR1 0x02 /* ICR1 semaphore 1 */
|
||||
#define ICR7_ICR2 0x04 /* ICR2 semaphore 2 */
|
||||
#define ICR7_ICR3 0x08 /* ICR3 semaphore 3 */
|
||||
#define ICR7_ICR4 0x10 /* ICR4 semaphore 4 */
|
||||
#define ICR7_MASTER 0x20 /* the VIC is VMEbus master 5 */
|
||||
#define ICR7_RESET 0x40 /* assert RESET* and HALT* 6 */
|
||||
#define ICR7_SYSFAIL_INH 0x80 /* inhibit SYSFAIL* assertion 7 */
|
||||
|
||||
/*****************************************************************
|
||||
* VIRSR 0x20 0x83 VME Interrupt Request/Status Reg *
|
||||
******************************************************************/
|
||||
|
||||
#define VIRSR_IRQ_ENA 0x01 /* VMEbus interrupt enable 0 */
|
||||
#define VIRSR_IRQ1 0x02 /* assert on VMEbus, VME IRQ 1 1 */
|
||||
#define VIRSR_IRQ2 0x04 /* assert on VMEbus, VME IRQ 2 2 */
|
||||
#define VIRSR_IRQ3 0x08 /* assert on VMEbus, VME IRQ 3 3 */
|
||||
#define VIRSR_IRQ4 0x10 /* assert on VMEbus, VME IRQ 4 4 */
|
||||
#define VIRSR_IRQ5 0x20 /* assert on VMEbus, VME IRQ 5 5 */
|
||||
#define VIRSR_IRQ6 0x40 /* assert on VMEbus, VME IRQ 6 6 */
|
||||
#define VIRSR_IRQ7 0x80 /* assert on VMEbus, VME IRQ 7 7 */
|
||||
|
||||
/***************************************************************
|
||||
* VIVR1 0x21 0x87 VME Interrupt Vector Reg #1 *
|
||||
* to *
|
||||
* VIVR7 0x27 0xaf VME Interrupt Vector Reg #7 *
|
||||
****************************************************************/
|
||||
|
||||
/* none */
|
||||
|
||||
/***************************************************************
|
||||
* TTR 0x28 0xa3 Transfer Time-out Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define TTR_VTO_ACQ_EXC 0x00 /* exclude aquisition time 0 */
|
||||
#define TTR_VTO_ACQ_INC 0x01 /* include aquisition time 0 */
|
||||
#define TTR_ARBTO 0x02 /* arbitration timeout occured 1 */
|
||||
#define TTR_LTO_4 0x00 /* local 4 us time out 42 */
|
||||
#define TTR_LTO_16 0x04 /* local 16 us time out 42 */
|
||||
#define TTR_LTO_32 0x08 /* local 32 us time out 42 */
|
||||
#define TTR_LTO_64 0x0c /* local 64 us time out 42 */
|
||||
#define TTR_LTO_128 0x10 /* local 128 us time out 42 */
|
||||
#define TTR_LTO_256 0x14 /* local 256 us time out 42 */
|
||||
#define TTR_LTO_512 0x18 /* local 512 us time out 42 */
|
||||
#define TTR_LTO_INF 0x1c /* local infinite time out 42 */
|
||||
#define TTR_VTO_4 0x00 /* VMEbus 4 us time out 75 */
|
||||
#define TTR_VTO_16 0x20 /* VMEbus 16 us time out 75 */
|
||||
#define TTR_VTO_32 0x40 /* VMEbus 32 us time out 75 */
|
||||
#define TTR_VTO_64 0x60 /* VMEbus 64 us time out 75 */
|
||||
#define TTR_VTO_128 0x80 /* VMEbus 128 us time out 75 */
|
||||
#define TTR_VTO_256 0xa0 /* VMEbus 256 us time out 75 */
|
||||
#define TTR_VTO_512 0xc0 /* VMEbus 512 us time out 75 */
|
||||
#define TTR_VTO_INF 0xe0 /* VMEbus infinite time out 75 */
|
||||
|
||||
/***************************************************************
|
||||
* LBTR 0x29 0xa7 Local Bus Timing Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define LBTR_PASL_2 0x00 /* PAS low 2 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_3 0x01 /* PAS low 3 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_4 0x02 /* PAS low 4 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_5 0x03 /* PAS low 5 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_6 0x04 /* PAS low 6 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_7 0x05 /* PAS low 7 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_8 0x06 /* PAS low 8 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_9 0x07 /* PAS low 9 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_10 0x08 /* PAS low 10 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_11 0x09 /* PAS low 11 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_12 0x0a /* PAS low 12 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_13 0x0b /* PAS low 13 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_14 0x0c /* PAS low 14 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_15 0x0d /* PAS low 15 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_16 0x0e /* PAS low 16 * 64 MHz clocks 30 */
|
||||
#define LBTR_PASL_17 0x0f /* PAS low 17 * 64 MHz clocks 30 */
|
||||
|
||||
#define LBTR_DS_1 0x00 /* DS 1 * 64 MHz clocks 4 */
|
||||
#define LBTR_DS_2 0x10 /* DS 2 * 64 MHz clocks 4 */
|
||||
|
||||
#define LBTR_PASH_1 0x00 /* PAS high 1 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_2 0x20 /* PAS high 2 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_3 0x40 /* PAS high 3 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_4 0x60 /* PAS high 4 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_5 0x80 /* PAS high 5 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_6 0xa0 /* PAS high 6 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_7 0xc0 /* PAS high 7 * 64 MHz clocks 75 */
|
||||
#define LBTR_PASH_8 0xe0 /* PAS high 8 * 64 MHz clocks 75 */
|
||||
|
||||
/***************************************************************
|
||||
* BTDR 0x2a 0xab Block Transfer Definition Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define BTDR_DPADEN 0x01 /* enable dual path DPADEN 0 */
|
||||
#define BTDR_AMSR 0x02 /* use AMSR for BT add modifier 1 */
|
||||
#define BTDR_LBTDMA_ENA 0x04 /* enable local BT 256 byte DMA 2 */
|
||||
#define BTDR_VBTDMA_ENA 0x08 /* enable VME BT 256 byte DMA 3 */
|
||||
|
||||
/***************************************************************
|
||||
* ICR 0x2b 0xaf Interface Configuration Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define ICR_SCON 0x01 /* system controller pin 0 */
|
||||
#define ICR_TURBO 0x02 /* speed up transfers 1 */
|
||||
#define ICR_MORE_SETTLE_TIME 0x04 /* add 1 64 MHz intvl to async pins2 */
|
||||
#define ICR_DLK_RMC_NO_RETRY 0x08 /* enable deadlock signalling 3 */
|
||||
#define ICR_DLK_RETRY 0x10 /* signal deadlock with HALT* 4 */
|
||||
#define ICR_REQ_RMC 0x20 /* request bus if RMC* is asserted 5 */
|
||||
#define ICR_AS_STRETCH 0x40 /* strech AS* 6 */
|
||||
#define ICR_AS_SIZE 0x80 /* use size information for AS* 7 */
|
||||
|
||||
/***************************************************************
|
||||
* ARCR 0x2c 0xb3 Arbiter/Requester Config. Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define ARCR_NOT_FAIR 0x00 /* disable fairness 30 */
|
||||
#define ARCR_NO_TOUT 0x0f /* disable timeout 30 */
|
||||
#define ARCR_DRAM_REFRESH 0x10 /* enable DRAM refresh 4 */
|
||||
|
||||
#define ARCR_VBRL_BR0 0x00 /* VME bus request level BR0 65 */
|
||||
#define ARCR_VBRL_BR1 0x20 /* VME bus request level BR1 65 */
|
||||
#define ARCR_VBRL_BR2 0x40 /* VME bus request level BR2 65 */
|
||||
#define ARCR_VBRL_BR3 0x60 /* VME bus request level BR3 65 */
|
||||
|
||||
#define ARCR_RND_ROBIN 0x00 /* select round robin arbitration 7 */
|
||||
#define ARCR_PRIORITY 0x80 /* select priority arbitration 7 */
|
||||
|
||||
/***************************************************************
|
||||
* AMSR 0x2d 0xb7 AM Source Reg *
|
||||
****************************************************************/
|
||||
|
||||
/* Extended (A32) address modifier codes */
|
||||
|
||||
#define AMSR_EXT_USR_DATA 0x09 /* user data 50 */
|
||||
#define AMSR_EXT_USR_PROG 0x0a /* user program access 50 */
|
||||
#define AMSR_EXT_USR_BLOCK 0x0b /* user block transfer access 50 */
|
||||
#define AMSR_EXT_SPR_DATA 0x0d /* supervisory data access 50 */
|
||||
#define AMSR_EXT_SPR_PROG 0x0e /* supervisory program access 50 */
|
||||
#define AMSR_EXT_SPR_BLOCK 0x0f /* super block transfer access 50 */
|
||||
|
||||
/* AMSR_Short (A16) address modifier codes */
|
||||
|
||||
#define AMSR_SHT_USR_ACCESS 0x29 /* user access 50 */
|
||||
#define AMSR_SHT_SPR_ACCESS 0x2d /* supervisory access 50 */
|
||||
|
||||
/* AMSR_Standard (A24) address modifier codes */
|
||||
|
||||
#define AMSR_STD_USR_DATA 0x39 /* user data 50 */
|
||||
#define AMSR_STD_USR_PROG 0x3a /* user program access 50 */
|
||||
#define AMSR_STD_USR_BLOCK 0x3b /* user block transfer access 50 */
|
||||
#define AMSR_STD_SPR_DATA 0x3d /* supervisory data access 50 */
|
||||
#define AMSR_STD_SPR_PROG 0x3e /* supervisory program access 50 */
|
||||
#define AMSR_STD_SPR_BLOCK 0x3f /* super block transfer access 50 */
|
||||
|
||||
/* AMSR_during slave access/cycles */
|
||||
|
||||
#define AMSR_SLV_CMP_ALL 0x00 /* all 6 add modifier bits comp 6 */
|
||||
#define AMSR_SLV_CMP_3MSB 0x40 /* only 3 most significant add 6 */
|
||||
/* modifier bits compared */
|
||||
|
||||
/* Master access/cycles */
|
||||
|
||||
#define AMSR_MSTR_CMP_ALL 0x00 /* all 6 add modifier bits used 7 */
|
||||
#define AMSR_MSTR_CMP_3MSB 0x80 /* only 3 most significant add 7 */
|
||||
/* modifier bits used */
|
||||
|
||||
/***************************************************************
|
||||
* BESR 0x2e 0xbb Bus Error Status Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define BESR_LBTOA 0x01 /* local bus time out during 0 */
|
||||
/* attempted acquisition */
|
||||
#define BESR_SA_SLSEL1 0x02 /* self-access by SLSEL1 1 */
|
||||
#define BESR_SA_SLSEL0 0x04 /* self-access by SLSEL0 2 */
|
||||
#define BESR_LBTO 0x08 /* local bus time out 3 */
|
||||
#define BESR_VBTO 0x10 /* VMEbus time out (bus master) 4 */
|
||||
#define BESR_VBERR 0x20 /* VMEbus bus error BERR* 5 */
|
||||
#define BESR_LBERR 0x40 /* local bus error LBERR* 6 */
|
||||
#define BESR_MASTER 0x80 /* the VIC is VMEbus master 7 */
|
||||
|
||||
/***************************************************************
|
||||
* DSR 0x2f 0xbf DMA Status Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define DSR_INTER_DMA 0x01 /* interleaved DMA in progress 0 */
|
||||
#define DSR_LBERR_DMA 0x02 /* local bus error LBERR* during DMA 1 */
|
||||
#define DSR_VBERR_DMA 0x04 /* VMEbus bus error BERR* during DMA 2 */
|
||||
#define DSR_LBERR 0x08 /* local bus error LBERR* asserted 3 */
|
||||
#define DSR_VBERR 0x10 /* VMEbus bus error BERR* asserted 4 */
|
||||
#define DSR_BTDMA 0x60 /* VME/local 256 byte address error 65 */
|
||||
#define DSR_MASTER_WP 0x80 /* master write post info is stored 7 */
|
||||
|
||||
/****************************************************************/
|
||||
/* SS0CR0 0x30 0xc3 Slave Select 0/Control Reg #0 */
|
||||
/* and */
|
||||
/* SS1CR0 0x32 0xcb Slave Select 1/Control Reg #0 */
|
||||
/****************************************************************/
|
||||
|
||||
/* SS0CR0 and SS1CR0 */
|
||||
|
||||
#define SSCR0_BLT_NONE 0x00 /* no block transfer allowed 10 */
|
||||
#define SSCR0_BLT_LOCAL 0x01 /* emulate blck trans on local bus 10 */
|
||||
#define SSCR0_BLT_ACC 0x02 /* accelerated block transfer 10 */
|
||||
|
||||
#define SSCR0_ASIZ_A32 0x00 /* A32 address size 32 */
|
||||
#define SSCR0_ASIZ_A24 0x04 /* A24 address size 32 */
|
||||
#define SSCR0_ASIZ_A16 0x08 /* A16 address size 32 */
|
||||
#define SSCR0_ASIZ_AMREG 0x0c /* use Addr Modifier source reg 32 */
|
||||
|
||||
#define SSCR0_SLSEL_D32 0x10 /* D32 SLSEL[01]* data size 4 */
|
||||
#define SSCR0_SLSEL_D16 0x00 /* D32 SLSEL[01]* data size 4 */
|
||||
|
||||
#define SSCR0_SLSEL_SPR 0x20 /* supervisory SLSEL[01]* access only 5 */
|
||||
#define SSCR0_SLSEL_ALL 0x00 /* all modes SLSEL[01]* access 5 */
|
||||
|
||||
/* SS1CR0 */
|
||||
|
||||
#define SSCR0_MASTER_WP 0x40 /* enable master write posting 6 */
|
||||
#define SSCR0_MASTER_NWP 0x00 /* no master write posting 6 */
|
||||
|
||||
#define SSCR0_SLAVE_WP 0x80 /* enable slave write posting 7 */
|
||||
#define SSCR0_SLAVE_NWP 0x00 /* no slave write posting 7 */
|
||||
|
||||
/* SS0CR0 */
|
||||
|
||||
#define SSCR0_TIMER_MASK 0x3f /* timer field mask */
|
||||
#define SSCR0_TIMER_DIS 0x00 /* timer disabled 76 */
|
||||
#define SSCR0_TIMER_50 0x40 /* 50 Hz timer (output on LIRQ2*) 76 */
|
||||
#define SSCR0_TIMER_1000 0x80 /* 1000 Hz timer (outpt on LIRQ2*) 76 */
|
||||
#define SSCR0_TIMER_100 0xc0 /* 100 Hz timer (output on LIRQ2*) 76 */
|
||||
|
||||
/***************************************************************
|
||||
* SS0CR1 0x31 0xc7 Slave Select 0/Control Reg #1 *
|
||||
* and *
|
||||
* SS1CR1 0x33 0xcf Slave Select 1/Control Reg #1 *
|
||||
****************************************************************/
|
||||
|
||||
#define SSCR1_DTACK_0 0x00 /* 0 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_2 0x01 /* 2 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_25 0x02 /* 2.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_3 0x03 /* 3 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_35 0x04 /* 3.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_4 0x05 /* 4 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_45 0x06 /* 4.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_5 0x07 /* 5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_55 0x08 /* 5.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_6 0x09 /* 6 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_65 0x0a /* 6.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_7 0x0b /* 7 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_75 0x0c /* 7.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_8 0x0d /* 8 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_85 0x0e /* 8.5 x 64 Mhz DTACK* delay 30 */
|
||||
#define SSCR1_DTACK_9 0x0f /* 9 x 64 Mhz DTACK* delay 30 */
|
||||
|
||||
#define SSCR1_DSACK_0 0x00 /* 0 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_2 0x10 /* 2 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_25 0x20 /* 2.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_3 0x30 /* 3 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_35 0x40 /* 3.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_4 0x50 /* 4 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_45 0x60 /* 4.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_5 0x70 /* 5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_55 0x80 /* 5.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_6 0x90 /* 6 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_65 0xa0 /* 6.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_7 0xb0 /* 7 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_75 0xc0 /* 7.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_8 0xd0 /* 8 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_85 0xe0 /* 8.5 x 64 Mhz DTACK* delay 74 */
|
||||
#define SSCR1_DSACK_9 0xf0 /* 9 x 64 Mhz DTACK* delay 74 */
|
||||
|
||||
/***************************************************************
|
||||
* RCR 0x34 0xd3 Release Control Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define RCR_ROR 0x00 /* release on request 76 */
|
||||
#define RCR_RWD 0x40 /* release when done 76 */
|
||||
#define RCR_ROC 0x80 /* release on BCLR* 76 */
|
||||
#define RCR_BCAP 0xc0 /* bus capture and hold 76 */
|
||||
|
||||
/***************************************************************
|
||||
* BTCR 0x35 0xd7 Block Transfer Control Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define BTCR_LCIP_MASK 0x0f /* local cycle interl've period mk 30 */
|
||||
|
||||
#define BTCR_DMA_WRITE 0x10 /* write DMA enable 4 */
|
||||
|
||||
/* Note: bits 7, 6 and 5 are mutually exclusive */
|
||||
|
||||
#define BTCR_MBT 0x20 /* enable MOVEM type block trsfer 5 */
|
||||
#define BTCR_VDMA_GO 0x40 /* initiate VME DMA block trsfer 6 */
|
||||
#define BTCR_LDMA_GO 0x80 /* initiate local DMA block trsfer 7 */
|
||||
|
||||
/***************************************************************
|
||||
* BTLR0 0x36 0xdb Block Transfer Length Reg #0 *
|
||||
* and *
|
||||
* BTLR1 0x37 0xdf Block Transfer Length Reg #1 *
|
||||
****************************************************************/
|
||||
|
||||
/* none */
|
||||
|
||||
/***************************************************************
|
||||
* SRR 0x38 0xe3 System Reset Reg *
|
||||
****************************************************************/
|
||||
|
||||
#define SRR_SYSRESET 0xf0 /* assert SYSRESET on the VMEbus and */
|
||||
/* reset all reset-able VIC registers */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvic068h */
|
||||
@@ -0,0 +1,112 @@
|
||||
/* vme2Pci.h - vme2pci chip configuration header */
|
||||
|
||||
/* Copyright 1984-1996 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,13nov96,mas added VME2PCI_IO_OFFSET (SPR 7475).
|
||||
01c,28feb95,caf removed MSW() macro (now in vxWorks.h).
|
||||
01b,20jan95,vin clean up & enhancements.
|
||||
01a,09jan95,kvk created.
|
||||
*/
|
||||
|
||||
/*
|
||||
This file contains type declarations for the vme2pci chip Header
|
||||
and the macros for the PCI BUS. This header has been designed
|
||||
with respect to Genesis 1.5 Engineering Specification Version 1.0A.
|
||||
Configuration registers have to be accessed as long words.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef INCvme2Pcih
|
||||
#define INCvme2Pcih
|
||||
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CASTB
|
||||
#else
|
||||
#define CASTB (char *)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#define VME2PCI_REG_INTERVAL 4
|
||||
|
||||
/* to permit alternative board addressing */
|
||||
#ifndef VME2PCI_IACK_ADRS
|
||||
#define VME2PCI_IACK_ADRS(reg) (CASTB (VME2PCI_BASE_ADRS + \
|
||||
(0xF007) + \
|
||||
(reg * VME2PCI_REG_INTERVAL)))
|
||||
#endif /* VME2PCI_ADRS */
|
||||
|
||||
/*
|
||||
* Defines for the VME2PCI interrupt acknowledge registers
|
||||
*/
|
||||
|
||||
#define VME2PCI_IACK_LEVEL1 VME2PCI_IACK_ADRS(0x00)
|
||||
#define VME2PCI_IACK_LEVEL2 VME2PCI_IACK_ADRS(0x01)
|
||||
#define VME2PCI_IACK_LEVEL3 VME2PCI_IACK_ADRS(0x02)
|
||||
#define VME2PCI_IACK_LEVEL4 VME2PCI_IACK_ADRS(0x03)
|
||||
#define VME2PCI_IACK_LEVEL5 VME2PCI_IACK_ADRS(0x04)
|
||||
#define VME2PCI_IACK_LEVEL6 VME2PCI_IACK_ADRS(0x05)
|
||||
#define VME2PCI_IACK_LEVEL7 VME2PCI_IACK_ADRS(0x06)
|
||||
|
||||
|
||||
/* configuration space header */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
#if (_BYTE_ORDER == _BIG_ENDIAN)
|
||||
UINT16 pciSlvEndAddr1; /* slave end addr1 0x40 */
|
||||
UINT16 pciSlvStrtAddr1; /* slave start addr1 0x42 */
|
||||
UINT16 pciSlvEnable1; /* pci slave enable 1 0x44 */
|
||||
UINT16 pciSlvAddrOffset1; /* addr offset 1 0x46 */
|
||||
UINT16 pciSlvEndAddr2; /* slave end addr2 0x48 */
|
||||
UINT16 pciSlvStrtAddr2; /* slave start addr2 0x4A */
|
||||
UINT16 pciSlvEnable2; /* pci slave enable 2 0x4C */
|
||||
UINT16 pciSlvAddrOffset2; /* addr offset 2 0x4E */
|
||||
#else
|
||||
UINT16 pciSlvStrtAddr1; /* slave start addr1 0x40 */
|
||||
UINT16 pciSlvEndAddr1; /* slave end addr1 0x42 */
|
||||
UINT16 pciSlvAddrOffset1; /* addr offset 1 0x44 */
|
||||
UINT16 pciSlvEnable1; /* pci slave enable 1 0x46 */
|
||||
UINT16 pciSlvStrtAddr2; /* slave start addr2 0x48 */
|
||||
UINT16 pciSlvEndAddr2; /* slave end addr2 0x4A */
|
||||
UINT16 pciSlvAddrOffset2; /* addr offset 2 0x4C */
|
||||
UINT16 pciSlvEnable2; /* pci slave enable 2 0x4E */
|
||||
#endif /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
UINT32 pciIntEnable; /* pending intrpt enabl 0x50 */
|
||||
|
||||
} VME2PCI_CNFG_HDR;
|
||||
|
||||
|
||||
#define VME2PCI_CNFG_OFFSET 0x40 /* offset vme2Pci specific part */
|
||||
#define VME2PCI_IO_OFFSET 0xF840 /* offset vme2Pci specific IO space */
|
||||
|
||||
/* vme2pci device specific masks */
|
||||
|
||||
#define VME2PCI_SLV_ADDR_MASK 0xffff0000 /* pci slave addr mask */
|
||||
#define VME2PCI_SLV_EN_MASK 0x00010000 /* slave enable mask */
|
||||
#define VME2PCI_INT_MASK 0x00000008 /* vme2PCI interrupt mask */
|
||||
#define VME2PCI_INT_LVL_MASK 0x00000007 /* vme2PCI intr level mask */
|
||||
|
||||
#define VME2PCI_INT_LVL_GET(x) (x & VME2PCI_INT_LVL_MASK)
|
||||
|
||||
#define VME2PCI_SLAVE_ENABLE 0x0001 /* slave enable flag */
|
||||
#define VME2PCI_INT_ENABLE 0x00000008 /* Vme2PCI interrupt enable */
|
||||
|
||||
/* pci function declerations */
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
extern int sysVme2PciInit (VME2PCI_CNFG_HDR * pVme2PciCnfgHdr,
|
||||
ULONG vme2PciCnfgBase);
|
||||
|
||||
#else
|
||||
|
||||
extern int sysVme2PciInit ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* INCvme2Pcih */
|
||||
|
||||
|
||||
@@ -0,0 +1,333 @@
|
||||
/* vmechip.h - Motorola MVME6000 VMEbus Interface Controller */
|
||||
|
||||
/* Copyright 1991-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,29sep98,fle doc : made it refgen parsable
|
||||
01e,22sep92,rrr added support for c++
|
||||
01d,03jun92,ccc added a few more constants.
|
||||
01c,26may92,rrr the tree shuffle
|
||||
01b,02jan92,caf fixed GLOBAL_0 bits. changed copyright notice.
|
||||
01a,19dec91,caf written.
|
||||
*/
|
||||
|
||||
#ifdef DOC
|
||||
#define INCvmechiph
|
||||
#endif /* DOC */
|
||||
|
||||
#ifndef __INCvmechiph
|
||||
#define __INCvmechiph
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
This file contains constants for the Motorola MVME6000 VMEbus Interface.
|
||||
The macro VMECHIP_BASE_ADRS must be defined when using local bus addresses
|
||||
defined in this header. The macro GCSR_BUS_BASE_ADRS must be defined when
|
||||
using VMEbus addresses defined in this header.
|
||||
|
||||
The following standards have been adopted in the creation of this file.
|
||||
|
||||
Registers in the LCSR have the prefix "LCSR".
|
||||
|
||||
Registers in the GCSR have the prefix "GCSR" when addressed locally and the
|
||||
prefix "GCSR_BUS" when addressed from the VMEbus. The bit definitions are
|
||||
shared.
|
||||
|
||||
The registers are listed in ascending (numerical) order; the definitions
|
||||
for each register start with a header, e.g.:
|
||||
|
||||
Register Register Register Register
|
||||
Mnemonic Number Address Name
|
||||
| | | |
|
||||
v v v v
|
||||
*************************************************************************
|
||||
* SYS_CONF 0x00 0x01 system controller config *
|
||||
*************************************************************************
|
||||
|
||||
In cases where a number of registers have the same definitions, the
|
||||
header looks like this:
|
||||
|
||||
*************************************************************************
|
||||
* GP_CSR_0 0x13 0x27 general purpose CSR 0 *
|
||||
* to *
|
||||
* GP_CSR_4 0x17 0x2f general purpose CSR 4 *
|
||||
*************************************************************************
|
||||
|
||||
The format of the definitions is as follows. The define name always
|
||||
starts with the register mnemonic it is associated with. The [7-0]
|
||||
number at the end of the comment indicates the bit position to which the
|
||||
the define applies. In the definition of RQST_CONF_DWB, for example,
|
||||
the 7 indicates bit 7:
|
||||
|
|
||||
v
|
||||
define RQST_CONF_DWB 0x80 * device wants bus 7 *
|
||||
|
||||
If the define applies to more than one bit, then the applicable bit
|
||||
range is specified by two digits. In the following example,
|
||||
TMO_CONF_VBTO_2048 applies to the two bit field, bits 5-4:
|
||||
|
|
||||
v
|
||||
define TMO_CONF_VBTO_2048 0x10 * VMEbus time-out 2048 * T 54 *
|
||||
|
||||
If no bit field is given, then the define applies to the whole register.
|
||||
*/
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST
|
||||
#else
|
||||
#define CAST (char *)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define VMECHIP_REG_INTERVAL 2
|
||||
|
||||
#ifndef VMECHIP_ADRS /* to permit alternative board addressing */
|
||||
#define VMECHIP_ADRS(reg) \
|
||||
(CAST (VMECHIP_BASE_ADRS + 1 + (reg * VMECHIP_REG_INTERVAL)))
|
||||
#endif /* VMECHIP_ADRS */
|
||||
|
||||
/*
|
||||
* Local Control and Status Register (LCSR) definitions.
|
||||
*
|
||||
* Only the local CPU can access the LCSR.
|
||||
*/
|
||||
|
||||
#define LCSR_SYS_CONF VMECHIP_ADRS(0x00) /* system controller config */
|
||||
#define LCSR_RQST_CONF VMECHIP_ADRS(0x01) /* requester configuration */
|
||||
#define LCSR_MASTER_CONF VMECHIP_ADRS(0x02) /* master configuration */
|
||||
#define LCSR_SLAVE_CONF VMECHIP_ADRS(0x03) /* slave configuration */
|
||||
#define LCSR_TMO_CONF VMECHIP_ADRS(0x04) /* timer configuration */
|
||||
#define LCSR_SLAVE_AM VMECHIP_ADRS(0x05) /* slave address modifier */
|
||||
#define LCSR_MASTER_AM VMECHIP_ADRS(0x06) /* master address modifier */
|
||||
#define LCSR_INT_MASK VMECHIP_ADRS(0x07) /* interrupt handler mask */
|
||||
#define LCSR_UTIL_INT_MASK VMECHIP_ADRS(0x08) /* utility interrupt mask */
|
||||
#define LCSR_UTIL_VEC_BASE VMECHIP_ADRS(0x09) /* utility interrupt vector */
|
||||
#define LCSR_INT_REQ VMECHIP_ADRS(0x0a) /* interrupt request */
|
||||
#define LCSR_INT_STATUS_ID VMECHIP_ADRS(0x0b) /* status/ID */
|
||||
#define LCSR_BERR_STATUS VMECHIP_ADRS(0x0c) /* bus error status */
|
||||
#define LCSR_GCSR_BASE_ADRS VMECHIP_ADRS(0x0d) /* GCSR base address */
|
||||
|
||||
|
||||
/*
|
||||
* Global Control and Status Register (GCSR) definitions.
|
||||
*
|
||||
* All registers of the GCSR are accessible to both the local processor
|
||||
* and to other VMEbus masters.
|
||||
*/
|
||||
|
||||
/* local addresses for the GCSR */
|
||||
|
||||
#define GCSR_GLOBAL_0 VMECHIP_ADRS(0x10) /* global 0 */
|
||||
#define GCSR_GLOBAL_1 VMECHIP_ADRS(0x11) /* global 1 */
|
||||
#define GCSR_BOARD_ID VMECHIP_ADRS(0x12) /* board ID */
|
||||
#define GCSR_GP_CSR_0 VMECHIP_ADRS(0x13) /* general purpose CSR 0 */
|
||||
#define GCSR_GP_CSR_1 VMECHIP_ADRS(0x14) /* general purpose CSR 1 */
|
||||
#define GCSR_GP_CSR_2 VMECHIP_ADRS(0x15) /* general purpose CSR 2 */
|
||||
#define GCSR_GP_CSR_3 VMECHIP_ADRS(0x16) /* general purpose CSR 3 */
|
||||
#define GCSR_GP_CSR_4 VMECHIP_ADRS(0x17) /* general purpose CSR 4 */
|
||||
|
||||
/* VMEbus addresses for the GCSR */
|
||||
|
||||
#define GCSR_BUS_REG_INTERVAL 2
|
||||
|
||||
#ifndef GCSR_BUS_ADRS /* to permit alternative off-board addressing */
|
||||
#define GCSR_BUS_ADRS(reg) \
|
||||
(CAST (GCSR_BUS_BASE_ADRS + 1 + (reg * GCSR_BUS_REG_INTERVAL)))
|
||||
#endif /* GCSR_BUS_ADRS */
|
||||
|
||||
#define GCSR_BUS_GLOBAL_0 GCSR_BUS_ADRS(0x00) /* global 0 on VMEbus */
|
||||
#define GCSR_BUS_GLOBAL_1 GCSR_BUS_ADRS(0x01) /* global 1 on VMEbus */
|
||||
#define GCSR_BUS_BOARD_ID GCSR_BUS_ADRS(0x02) /* board ID on VMEbus */
|
||||
#define GCSR_BUS_GP_CSR_0 GCSR_BUS_ADRS(0x03) /* general purp. 0 on VMEbus */
|
||||
#define GCSR_BUS_GP_CSR_1 GCSR_BUS_ADRS(0x04) /* general purp. 1 on VMEbus */
|
||||
#define GCSR_BUS_GP_CSR_2 GCSR_BUS_ADRS(0x05) /* general purp. 2 on VMEbus */
|
||||
#define GCSR_BUS_GP_CSR_3 GCSR_BUS_ADRS(0x06) /* general purp. 3 on VMEbus */
|
||||
#define GCSR_BUS_GP_CSR_4 GCSR_BUS_ADRS(0x07) /* general purp. 4 on VMEbus */
|
||||
|
||||
|
||||
/* SYS_CONF 0x00 0x01 system controller config */
|
||||
|
||||
#define SYS_CONF_SCON 0x01 /* system controller on (status) 0 */
|
||||
#define SYS_CONF_SRESET 0x02 /* system reset 1 */
|
||||
#define SYS_CONF_BRDFAIL 0x04 /* board fail 2 */
|
||||
#define SYS_CONF_ROBIN 0x08 /* round robin select 3 */
|
||||
#define SYS_CONF_PRIORITY 0x00 /* priority mode select 3 */
|
||||
|
||||
/* RQST_CONF 0x01 0x03 requester configuration */
|
||||
|
||||
#define RQST_CONF_RQLEV 0x03 /* VMEbus request level (mask) 10 */
|
||||
#define RQST_CONF_RQLEV_0 0x00 /* VMEbus request level 0 10 */
|
||||
#define RQST_CONF_RQLEV_1 0x01 /* VMEbus request level 1 10 */
|
||||
#define RQST_CONF_RQLEV_2 0x02 /* VMEbus request level 2 10 */
|
||||
#define RQST_CONF_RQLEV_3 0x03 /* VMEbus request level 3 10 */
|
||||
|
||||
#define RQST_CONF_RNEVER 0x08 /* release never 3 */
|
||||
#define RQST_CONF_RWD 0x10 /* release when done 4 */
|
||||
#define RQST_CONF_ROR 0x00 /* release on request 4 */
|
||||
#define RQST_CONF_RONR 0x20 /* request on no request 5 */
|
||||
#define RQST_CONF_DHB 0x40 /* device has bus (status) 6 */
|
||||
#define RQST_CONF_DWB 0x80 /* device wants bus 7 */
|
||||
|
||||
/* MASTER_CONF 0x02 0x05 master configuration */
|
||||
|
||||
#define MASTER_CONF_MASD16 0x01 /* master D16 0 */
|
||||
#define MASTER_CONF_MASD32 0x00 /* master D32, D16, D8 0 */
|
||||
#define MASTER_CONF_MASA32 0x00 /* master A32 1 */
|
||||
#define MASTER_CONF_MASA24 0x02 /* master A24 1 */
|
||||
#define MASTER_CONF_MASA16 0x04 /* master A16 2 */
|
||||
#define MASTER_CONF_MASUAT 0x08 /* master unaligned transfers 3 */
|
||||
#define MASTER_CONF_CFILL 0x10 /* cache fill 4 */
|
||||
#define MASTER_CONF_MASWP 0x20 /* master write-posting (CAUTION) 5 */
|
||||
#define MASTER_CONF_020 0x40 /* local CPU is a 68020 6 */
|
||||
#define MASTER_CONF_DDTACK 0x80 /* extra delay for 33MHz 020/030 7 */
|
||||
|
||||
/* SLAVE_CONF 0x03 0x07 slave configuration */
|
||||
|
||||
#define SLAVE_CONF_SLVD16 0x01 /* slave D16 0 */
|
||||
#define SLAVE_CONF_SLVWP 0x20 /* slave write-posting (CAUTION) 5 */
|
||||
#define SLAVE_CONF_SLVEN 0x80 /* slave enable 7 */
|
||||
#define SLAVE_CONF_SLVDIS 0x00 /* slave disable 7 */
|
||||
|
||||
/* TMO_CONF 0x04 0x09 timer configuration */
|
||||
|
||||
#define TMO_CONF_LBTO 0x03 /* local bus time-out (mask) 10 */
|
||||
#define TMO_CONF_LBTO_1024 0x00 /* local bus time-out 1024 * T 10 */
|
||||
#define TMO_CONF_LBTO_2048 0x01 /* local bus time-out 2048 * T 10 */
|
||||
#define TMO_CONF_LBTO_4096 0x02 /* local bus time-out 4096 * T 10 */
|
||||
#define TMO_CONF_LBTO_DIS 0x03 /* local bus time-out disabled 10 */
|
||||
|
||||
#define TMO_CONF_ACTO 0x0c /* access time-out (mask) 32 */
|
||||
#define TMO_CONF_ACTO_1024 0x00 /* access time-out 1024 * T 32 */
|
||||
#define TMO_CONF_ACTO_16384 0x04 /* access time-out 16384 * T 32 */
|
||||
#define TMO_CONF_ACTO_524 0x08 /* access time-out 524290 * T 32 */
|
||||
#define TMO_CONF_ACTO_DIS 0x0c /* access time-out disabled 32 */
|
||||
|
||||
#define TMO_CONF_VBTO 0x30 /* VMEbus time-out (mask) 54 */
|
||||
#define TMO_CONF_VBTO_1024 0x00 /* VMEbus time-out 1024 * T 54 */
|
||||
#define TMO_CONF_VBTO_2048 0x10 /* VMEbus time-out 2048 * T 54 */
|
||||
#define TMO_CONF_VBTO_4096 0x20 /* VMEbus time-out 4096 * T 54 */
|
||||
#define TMO_CONF_VBTO_DIS 0x30 /* VMEbus time-out disabled 54 */
|
||||
|
||||
#define TMO_CONF_ARBTO 0x40 /* arbitration timer 6 */
|
||||
|
||||
/* SLAVE_AM 0x05 0x0b slave address modifier */
|
||||
|
||||
#define SLAVE_AM_DATA 0x01 /* respond to data 0 */
|
||||
#define SLAVE_AM_PROGRAM 0x02 /* respond to program 1 */
|
||||
#define SLAVE_AM_BLOCK 0x04 /* respond to block (never set) 2 */
|
||||
|
||||
#define SLAVE_AM_SHORT 0x08 /* respond to short 3 */
|
||||
#define SLAVE_AM_STND 0x10 /* respond to standard 4 */
|
||||
#define SLAVE_AM_EXTED 0x20 /* respond to extended 5 */
|
||||
|
||||
#define SLAVE_AM_USER 0x40 /* respond to user 6 */
|
||||
#define SLAVE_AM_SUPER 0x80 /* respond to supervisor 7 */
|
||||
|
||||
/* MASTER_AM 0x06 0x0d master address modifier */
|
||||
|
||||
#define MASTER_AM_AM 0x3f /* address modifier code (mask) 50 */
|
||||
|
||||
#define MASTER_AM_AMSEL 0x80 /* address modifier select 7 */
|
||||
#define MASTER_AM_DYNAMIC 0x00 /* AM code dynamically determined 7 */
|
||||
|
||||
/* INT_MASK 0x07 0x0f interrupt handler mask */
|
||||
|
||||
#define INT_MASK_IEN1 0x02 /* VMEbus IRQ1 interrupt enable 1 */
|
||||
#define INT_MASK_IEN2 0x04 /* VMEbus IRQ2 interrupt enable 2 */
|
||||
#define INT_MASK_IEN3 0x08 /* VMEbus IRQ3 interrupt enable 3 */
|
||||
#define INT_MASK_IEN4 0x10 /* VMEbus IRQ4 interrupt enable 4 */
|
||||
#define INT_MASK_IEN5 0x20 /* VMEbus IRQ5 interrupt enable 5 */
|
||||
#define INT_MASK_IEN6 0x40 /* VMEbus IRQ6 interrupt enable 6 */
|
||||
#define INT_MASK_IEN7 0x80 /* VMEbus IRQ7 interrupt enable 7 */
|
||||
#define INT_MASK_DISABLE 0x00 /* Disable VMEbus interrupts */
|
||||
|
||||
/* UTIL_INT_MASK 0x08 0x11 utility interrupt mask */
|
||||
|
||||
#define UTIL_INT_MASK_SIGLEN 0x02 /* signal low interrupt enable 1 */
|
||||
#define UTIL_INT_MASK_LM0EN 0x04 /* loc. monitor 0 intrpt. enable 2 */
|
||||
#define UTIL_INT_MASK_IACKEN 0x08 /* IACK interrupt enable 3 */
|
||||
#define UTIL_INT_MASK_LM1EN 0x10 /* loc. monitor 1 intrpt. enable 4 */
|
||||
#define UTIL_INT_MASK_SIGHEN 0x20 /* signal high interrupt enable 5 */
|
||||
#define UTIL_INT_MASK_SFIEN 0x40 /* SYSFAIL interrupt enable 6 */
|
||||
#define UTIL_INT_MASK_WPERREN 0x80 /* write posting bus error enable 7 */
|
||||
#define UTIL_INT_MASK_DISABLE 0x00 /* Disable utility interrupts */
|
||||
|
||||
/* UTIL_VEC_BASE 0x09 0x13 utility interrupt vector */
|
||||
|
||||
#define UTIL_VEC_BASE_UID 0x07 /* utility interrupt ID (mask) 20 */
|
||||
#define UTIL_VEC_BASE_SIGLP 0x01 /* signal low 20 */
|
||||
#define UTIL_VEC_BASE_LM0 0x02 /* location monitor 0 20 */
|
||||
#define UTIL_VEC_BASE_IACK 0x03 /* IACK 20 */
|
||||
#define UTIL_VEC_BASE_LM1 0x04 /* location monitor 1 20 */
|
||||
#define UTIL_VEC_BASE_SIGHP 0x05 /* signal high 20 */
|
||||
#define UTIL_VEC_BASE_SYSFAIL 0x06 /* SYSFAIL 20 */
|
||||
#define UTIL_VEC_BASE_WPBERR 0x07 /* write post bus error 20 */
|
||||
|
||||
#define UTIL_VEC_BASE_UVB 0xf8 /* utility vector base (mask) 73 */
|
||||
|
||||
/* INT_REQ 0x0a 0x15 interrupt request */
|
||||
|
||||
#define INT_REQ_UID 0x07 /* interrupt request (mask) 20 */
|
||||
#define INT_REQ_NONE 0x00 /* none 20 */
|
||||
#define INT_REQ_IRQ1 0x01 /* IRQ1 20 */
|
||||
#define INT_REQ_IRQ2 0x02 /* IRQ2 20 */
|
||||
#define INT_REQ_IRQ3 0x03 /* IRQ3 20 */
|
||||
#define INT_REQ_IRQ4 0x04 /* IRQ4 20 */
|
||||
#define INT_REQ_IRQ5 0x05 /* IRQ5 20 */
|
||||
#define INT_REQ_IRQ6 0x06 /* IRQ6 20 */
|
||||
#define INT_REQ_IRQ7 0x07 /* IRQ7 20 */
|
||||
|
||||
/* INT_STATUS_ID 0x0b 0x17 status/ID */
|
||||
|
||||
/* none */
|
||||
|
||||
/* BERR_STATUS 0x0c 0x19 bus error status */
|
||||
|
||||
#define BERR_STATUS_LBTO 0x01 /* local bus time-out 0 */
|
||||
#define BERR_STATUS_ACTO 0x02 /* access time-out 1 */
|
||||
#define BERR_STATUS_VBERR 0x04 /* VMEbus bus error 2 */
|
||||
#define BERR_STATUS_RMCERR 0x08 /* RMC lock error 3 */
|
||||
|
||||
/* GCSR_BASE_ADRS 0x0d 0x1b GCSR base address */
|
||||
|
||||
#define GCSR_BASE_ADRS 0x0f /* GCSR base address (mask) 30 */
|
||||
#define GCSR_BASE_ADRS_NONE 0x0f /* GCSR not mapped on VMEbus 30 */
|
||||
|
||||
/* GLOBAL_0 0x10 0x21 global 0 */
|
||||
|
||||
#define GLOBAL_0_CHIP_ID 0x0f /* chip ID (mask) 30 */
|
||||
|
||||
#define GLOBAL_0_LM0 0x10 /* location monitor 0 4 */
|
||||
#define GLOBAL_0_LM1 0x20 /* location monitor 1 5 */
|
||||
#define GLOBAL_0_LM2 0x40 /* location monitor 2 6 */
|
||||
#define GLOBAL_0_LM3 0x80 /* location monitor 3 7 */
|
||||
|
||||
/* GLOBAL_1 0x11 0x23 global 1 */
|
||||
|
||||
#define GLOBAL_1_SIGLP 0x01 /* signal low priority 0 */
|
||||
#define GLOBAL_1_SIGHP 0x02 /* signal high priority 1 */
|
||||
#define GLOBAL_1_BRDFAIL 0x10 /* board fail 4 */
|
||||
#define GLOBAL_1_ISF 0x20 /* inhibit SYSFAIL 5 */
|
||||
#define GLOBAL_1_SCON 0x40 /* system controller on (status) 6 */
|
||||
#define GLOBAL_1_R_AND_H 0x80 /* reset and hold 7 */
|
||||
|
||||
/* BOARD_ID 0x12 0x25 board ID */
|
||||
|
||||
/* none */
|
||||
|
||||
/*
|
||||
* GP_CSR_0 0x13 0x27 general purpose CSR 0
|
||||
* to
|
||||
* GP_CSR_4 0x17 0x2f general purpose CSR 4
|
||||
*/
|
||||
|
||||
/* none */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvmechiph */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
/* vsam.h - SBE VSAM Chip Set header */
|
||||
|
||||
/* Copyright 1984-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,22sep92,rrr added support for c++
|
||||
01d,26may92,rrr the tree shuffle
|
||||
01c,04oct91,rrr passed through the ansification filter
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01b,05oct90,shl added copyright notice.
|
||||
made #endif ANSI style.
|
||||
01a,10sep89,rld original SBE release.
|
||||
*/
|
||||
|
||||
/*
|
||||
This header file defines the register layout of the SBE VMEbus
|
||||
Slave Address Manager chip (VSAM) and supplies alpha-numeric
|
||||
equivalences for register bit definitions.
|
||||
*/
|
||||
|
||||
#ifndef __INCvsamh
|
||||
#define __INCvsamh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define VSAM_ADRS(reg) (VSAM + (reg * VSAM_REG_OFFSET))
|
||||
#else
|
||||
#define VSAM_ADRS(reg) ((char *) VSAM + (reg * VSAM_REG_OFFSET))
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/* Location Monitor */
|
||||
|
||||
#define VSAM_LM_VAC_0 VSAM_ADRS(0x00) /* VME Address Register 0 */
|
||||
#define VSAM_LM_VAC_1 VSAM_ADRS(0x01) /* VME Address Register 1 */
|
||||
#define VSAM_LM_VAC_2 VSAM_ADRS(0x02) /* VME Address Register 2 */
|
||||
#define VSAM_LM_VAC_3 VSAM_ADRS(0x03) /* VME Address Register 3 */
|
||||
#define VSAM_LM_BLKS_UPR VSAM_ADRS(0x04) /* VME Block Size */
|
||||
#define VSAM_LM_BLKS_LWR VSAM_ADRS(0x05) /* VME Block Size */
|
||||
#define LM_BLK_2 0x0000 /* 2 byte size */
|
||||
#define LM_BLK_4 0x0002 /* 4 byte size */
|
||||
#define LM_BLK_8 0x0006 /* 8 byte size */
|
||||
#define LM_BLK_16 0x000e /* 16 byte size */
|
||||
#define LM_BLK_32 0x001e /* 32 byte size */
|
||||
#define LM_BLK_64 0x003e /* 64 byte size */
|
||||
#define LM_BLK_128 0x007e /* 128 byte size */
|
||||
#define LM_BLK_256 0x00fe /* 256 byte size */
|
||||
#define LM_BLK_512 0x01fe /* 512 byte size */
|
||||
#define LM_BLK_1K 0x03fe /* 1K byte size */
|
||||
#define LM_BLK_2K 0x07fe /* 2K byte size */
|
||||
#define LM_BLK_4K 0x0ffe /* 4K byte size */
|
||||
#define LM_BLK_8K 0x1ffe /* 8K byte size */
|
||||
#define LM_BLK_16K 0x3ffe /* 16K byte size */
|
||||
#define LM_BLK_32K 0x7ffe /* 32K byte size */
|
||||
#define LM_BLK_64K 0xfffe /* 64K byte size */
|
||||
|
||||
#define VSAM_LM_AMU0 VSAM_ADRS(0x06) /* User Defined VME AM code #1 */
|
||||
#define VSAM_LM_AMU1 VSAM_ADRS(0x07) /* User Defined VME AM code #2 */
|
||||
#define VSAM_LM_CTR VSAM_ADRS(0x08) /* Counter */
|
||||
#define VSAM_LM_MC VSAM_ADRS(0x0a) /* Match count */
|
||||
#define VSAM_LM_CMD VSAM_ADRS(0x0c) /* Location Monitor Command */
|
||||
#define LM_CMD_FLAG 0x08 /* Command Flag */
|
||||
#define LM_CMD_DISABLE 0x0b /* cmd: disable Loc Monitor */
|
||||
#define LM_CMD_ENABLE 0x0c /* cmd: enable Loc Monitor */
|
||||
#define LM_CMD_READ_CNTR 0x0e /* cmd: read Monitor counter */
|
||||
#define LM_CMD_WRITE_CNTR 0x0f /* cmd: write Monitor counter */
|
||||
#define VSAM_LM_CTL VSAM_ADRS(0x0d) /* Location Monitor Control */
|
||||
#define LM_AMU0_ENABLE 0x04 /* Enable AMU0 usage */
|
||||
#define LM_AMU1_ENABLE 0x08 /* Enable AMU1 usage */
|
||||
#define LM_MODE_NONE 0x00 /* No address monitoring */
|
||||
#define LM_MODE_A16 0x01 /* Select A16 monitoring */
|
||||
#define LM_MODE_A24 0x02 /* Select A24 monitoring */
|
||||
#define LM_MODE_A32 0x03 /* Select A32 monitoring */
|
||||
#define VSAM_LM_VSL_UPR VSAM_ADRS(0x0e) /* VME Status Latch */
|
||||
#define LM_VSL_UAT 0x80 /* Decoded UAT transfer */
|
||||
#define LM_VSL_WORD 0x40 /* Decoded Word transfer */
|
||||
#define LM_VSL_BYTE 0x20 /* Decoded Byte transfer */
|
||||
#define LM_VSL_WRITE 0x10 /* Latched VWRITE* signal */
|
||||
#define LM_VSL_LDS1 0x08 /* Latched VDS1* signal */
|
||||
#define LM_VSL_LDS0 0x04 /* Latched VDS0* signal */
|
||||
#define LM_VSL_LA01 0x02 /* Latched VA1 signal */
|
||||
#define LM_VSL_LLWORD 0x01 /* Latched VLWORD* signal */
|
||||
#define VSAM_LM_VSL_LWR VSAM_ADRS(0x0f) /* VME Status Latch */
|
||||
#define LM_VSL_LIACK 0x80 /* Latched VIACK* signal */
|
||||
#define LM_VSL_AMASK 0x3f /* Mask for AM codes */
|
||||
#define VSAM_LM_AMR VSAM_ADRS(0x10) /* Regular VME AM codes */
|
||||
#define LM_AM_SUPER 0x38 /* Respond to supervisor */
|
||||
#define LM_AM_NONPRIV 0x07 /* Respond to non-privilege */
|
||||
#define LM_AM_SUP_ASCENDING 0x20 /* AMF */
|
||||
#define LM_AM_SUP_PGM 0x10 /* AME */
|
||||
#define LM_AM_SUP_DATA 0x08 /* AMD */
|
||||
#define LM_AM_USR_ASCENDING 0x04 /* AMB */
|
||||
#define LM_AM_USR_PGM 0x02 /* AMA */
|
||||
#define LM_AM_USR_DATA 0x01 /* AM9 */
|
||||
#define VSAM_LM_VEC VSAM_ADRS(0x11) /* Interrupt Vector */
|
||||
|
||||
/* Shared Memory */
|
||||
|
||||
#define VSAM_SM_BAV_UPR VSAM_ADRS(0x12) /* Base Addr on VMEbus */
|
||||
#define VSAM_SM_BAV_LWR VSAM_ADRS(0x13) /* Base Addr on VMEbus */
|
||||
#define VSAM_SM_BLKS VSAM_ADRS(0x14) /* Block Size */
|
||||
#define SM_BLK_64K 0x00 /* 64K byte size */
|
||||
#define SM_BLK_128K 0x01 /* 128K byte size */
|
||||
#define SM_BLK_256K 0x03 /* 256K byte size */
|
||||
#define SM_BLK_512K 0x07 /* 512K byte size */
|
||||
#define SM_BLK_1MB 0x0f /* 1MB byte size */
|
||||
#define SM_BLK_2MB 0x1f /* 2MB byte size */
|
||||
#define SM_BLK_4MB 0x3f /* 4MB byte size */
|
||||
#define SM_BLK_8MB 0x7f /* 8MB byte size */
|
||||
#define VSAM_SM_BAL VSAM_ADRS(0x15) /* Base Addr on Local Bus */
|
||||
#define VSAM_SM_AM VSAM_ADRS(0x16) /* AM codes */
|
||||
#define SM_AM_A32 0x80 /* 32-bit address response */
|
||||
#define SM_AM_A24 0x00 /* 24-bit address response */
|
||||
#define SM_AM_SUPER 0x38 /* Respond to supervisor */
|
||||
#define SM_AM_NONPRIV 0x07 /* Respond to non-privilege */
|
||||
#define SM_AM_SUP_ASCENDING 0x20 /* AMF */
|
||||
#define SM_AM_SUP_PGM 0x10 /* AME */
|
||||
#define SM_AM_SUP_DATA 0x08 /* AMD */
|
||||
#define SM_AM_USR_ASCENDING 0x04 /* AMB */
|
||||
#define SM_AM_USR_PGM 0x02 /* AMA */
|
||||
#define SM_AM_USR_DATA 0x01 /* AM9 */
|
||||
#define VSAM_IO_BAV_UPR VSAM_ADRS(0x18) /* Short I/O Base Address */
|
||||
#define VSAM_IO_BAV_LWR VSAM_ADRS(0x19) /* Short I/O Base Address */
|
||||
#define VSAM_IO_AM VSAM_ADRS(0x1a) /* Short I/O AM codes */
|
||||
#define EN_29 0x01 /* Short supervisory AM */
|
||||
#define EN_2D 0x02 /* Short non-priv AM */
|
||||
#define EN_MBX 0x04 /* Assertion of mailbox int */
|
||||
|
||||
/* Mailbox and Status Functions */
|
||||
|
||||
#define VSAM_MBX_VEC VSAM_ADRS(0x1b) /* Mailbox Intr Vector */
|
||||
#define VSAM_MBX_ISR VSAM_ADRS(0x1c) /* Interrupt Status Register */
|
||||
#define MBXP 0x80 /* Mailbox intr is pending */
|
||||
#define LMQP 0x40 /* Loc Monitor intr is pending */
|
||||
#define MBXEN 0x08 /* Mailbox intr is enabled */
|
||||
#define LMQEN 0x04 /* Loc Monitor is enabled */
|
||||
#define VSAM_MBX_USER VSAM_ADRS(0x1d) /* User Defined Register */
|
||||
#define MBX_RESET 0xa5 /* VMEbus resets local board */
|
||||
#define VSAM_MAILBOX_UPR VSAM_ADRS(0x1e)/* Mailbox Register */
|
||||
#define VSAM_MAILBOX_LWR VSAM_ADRS(0x1f)/* Mailbox Write Code Register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvsamh */
|
||||
@@ -0,0 +1,151 @@
|
||||
/* vsbchip2.h - VSBchip2 Interface Controller */
|
||||
|
||||
/* Copyright 1994-1996 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,15nov96,dat fixed SPR 4046, offset for VSBCHIP2_PTR was corrected.
|
||||
01a,16feb94,dzb written.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains constants for the VSBchip2 interface controller.
|
||||
*/
|
||||
|
||||
#ifdef DOC
|
||||
#define __INCvsbchip2h
|
||||
#endif /* DOC */
|
||||
|
||||
#ifndef __INCvsbchip2h
|
||||
#define __INCvsbchip2h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST
|
||||
#define CAST_US
|
||||
#define CAST_UL
|
||||
#else
|
||||
#define CAST (char *)
|
||||
#define CAST_US (unsigned short *)
|
||||
#define CAST_UL (unsigned long *)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifndef VSBCHIP2_BASE_ADRS
|
||||
#define VSBCHIP2_BASE_ADRS 0xfff41000
|
||||
#endif /* VSBCHIP2_BASE_ADRS */
|
||||
|
||||
#ifndef VSBCHIP2_REG_INTERVAL
|
||||
#define VSBCHIP2_REG_INTERVAL 1
|
||||
#endif /* VSBCHIP2_REG_INTERVAL */
|
||||
|
||||
#ifndef VSB_ADRS
|
||||
#define VSB_ADRS(reg) (CAST VSBCHIP2_BASE_ADRS + (reg * VSBCHIP2_REG_INTERVAL))
|
||||
#endif /* VSB_ADRS */
|
||||
|
||||
#ifndef VSB_ADRS_US
|
||||
#define VSB_ADRS_US(reg) (CAST_US VSB_ADRS(reg))
|
||||
#endif /* VSB_ADRS_US */
|
||||
|
||||
#ifndef VSB_ADRS_UL
|
||||
#define VSB_ADRS_UL(reg) (CAST_UL VSB_ADRS(reg))
|
||||
#endif /* VSB_ADRS_UL */
|
||||
|
||||
|
||||
/**********************************/
|
||||
/* VSBCHIP2 register locations: */
|
||||
/**********************************/
|
||||
|
||||
#define VSBCHIP2_CCCSR VSB_ADRS_US (0x000) /* Chip Control/Status Reg */
|
||||
#define VSBCHIP2_LIVBR VSB_ADRS_US (0x002) /* Local Int Vector Base Reg */
|
||||
#define VSBCHIP2_LISR VSB_ADRS_US (0x004) /* Local Interrupt Status Reg */
|
||||
#define VSBCHIP2_LIER VSB_ADRS_US (0x006) /* Local Interrupt Enable Reg */
|
||||
#define VSBCHIP2_LILR VSB_ADRS_UL (0x008) /* Local Interrupt Level Reg */
|
||||
#define VSBCHIP2_VRCSR VSB_ADRS_US (0x010) /* VSB Req Control/Status Reg */
|
||||
#define VSBCHIP2_TCR VSB_ADRS_US (0x014) /* Timer Control Register */
|
||||
#define VSBCHIP2_TCPR VSB_ADRS_US (0x016) /* Timer Clock Prescale Reg */
|
||||
#define VSBCHIP2_LS1ARR VSB_ADRS_UL (0x018) /* Local Bus Slave Addr Reg 1 */
|
||||
#define VSBCHIP2_LS1AOR VSB_ADRS_US (0x01c) /* Local Bus Slave Off Reg 1 */
|
||||
#define VSBCHIP2_LS1AR VSB_ADRS_US (0x01e) /* Local Bus Slave Attr Reg 1 */
|
||||
#define VSBCHIP2_LS2ARR VSB_ADRS_UL (0x020) /* Local Bus Slave Addr Reg 2 */
|
||||
#define VSBCHIP2_LS2AOR VSB_ADRS_US (0x024) /* Local Bus Slave Off Reg 2 */
|
||||
#define VSBCHIP2_LS2AR VSB_ADRS_US (0x026) /* Local Bus Slave Attr Reg 2 */
|
||||
#define VSBCHIP2_LS3ARR VSB_ADRS_UL (0x028) /* Local Bus Slave Addr Reg 3 */
|
||||
#define VSBCHIP2_LS3AOR VSB_ADRS_US (0x02c) /* Local Bus Slave Off Reg 3 */
|
||||
#define VSBCHIP2_LS3AR VSB_ADRS_US (0x02e) /* Local Bus Slave Attr Reg 3 */
|
||||
#define VSBCHIP2_LS4ARR VSB_ADRS_UL (0x030) /* Local Bus Slave Addr Reg 4 */
|
||||
#define VSBCHIP2_LS4AOR VSB_ADRS_US (0x034) /* Local Bus Slave Off Reg 4 */
|
||||
#define VSBCHIP2_LS4AR VSB_ADRS_US (0x036) /* Local Bus Slave Attr Reg 4 */
|
||||
#define VSBCHIP2_LEAR VSB_ADRS_UL (0x074) /* Local Error Address Reg */
|
||||
#define VSBCHIP2_PCCR VSB_ADRS_UL (0x078) /* Prescaler Current Cnt Reg */
|
||||
#define VSBCHIP2_PTR VSB_ADRS_UL (0x07C) /* Prescaler Test Register */
|
||||
#define VSBCHIP2_EAR VSB_ADRS_UL (0x100) /* EVSB Attention Register */
|
||||
#define VSBCHIP2_ETASR VSB_ADRS_UL (0x104) /* EVSB Test-And-Set Reg */
|
||||
#define VSBCHIP2_GPR1 VSB_ADRS_UL (0x108) /* General Purpose Reg 1 */
|
||||
#define VSBCHIP2_GPR2 VSB_ADRS_UL (0x10c) /* General Purpose Reg 2 */
|
||||
#define VSBCHIP2_VESR VSB_ADRS_UL (0x110) /* VSB Error Status Register */
|
||||
#define VSBCHIP2_VICR VSB_ADRS (0x114) /* VSB Interrupt Control Reg */
|
||||
#define VSBCHIP2_VIVR VSB_ADRS (0x115) /* VSB Interrupt Vector Reg */
|
||||
#define VSBCHIP2_VIER VSB_ADRS (0x116) /* VSB Interrupt Enable Reg */
|
||||
#define VSBCHIP2_VISR VSB_ADRS (0x117) /* VSB Interrupt Status Reg */
|
||||
#define VSBCHIP2_VS1ARR VSB_ADRS_UL (0x118) /* VSB Slave Addr Range Reg 1 */
|
||||
#define VSBCHIP2_VS1AOR VSB_ADRS_US (0x11c) /* VSB Slave Addr Off Reg 1 */
|
||||
#define VSBCHIP2_VS1AR VSB_ADRS_US (0x11e) /* VSB Slave Attribute Reg 1 */
|
||||
#define VSBCHIP2_VS2ARR VSB_ADRS_UL (0x120) /* VSB Slave Addr Range Reg 2 */
|
||||
#define VSBCHIP2_VS2AOR VSB_ADRS_US (0x124) /* VSB Slave Addr Off Reg 2 */
|
||||
#define VSBCHIP2_VS2AR VSB_ADRS_US (0x126) /* VSB Slave Attribute Reg 2 */
|
||||
|
||||
/**********************************/
|
||||
/* VSBCHIP2 register definitions: */
|
||||
/**********************************/
|
||||
|
||||
/* VSBCHIP2_VRCSR register definitions: */
|
||||
|
||||
#define VRCSR_LVRWD 0x0100 /* release when done */
|
||||
|
||||
/* VSBCHIP2_VTCR register definitions: */
|
||||
|
||||
#define VTCR_VARBTD 0x1000 /* VSB arbitration timer disable */
|
||||
#define VTCR_VATS_32MS 0x0800 /* VSB access timer select (32 msecs) */
|
||||
#define VTCR_VATS_DIS 0x0c00 /* VSB access timer select (32 msecs) */
|
||||
#define VTCR_VTXS_256US 0x0200 /* VSB transfer timer select (256 usecs) */
|
||||
#define VTCR_VTXS_DIS 0x0300 /* VSB transfer timer select disabled */
|
||||
|
||||
|
||||
/* VSBCHIP2_LS1AR register definitions: */
|
||||
|
||||
#define LS1AR_REN 0x8000 /* read enable (when set, read access) */
|
||||
#define LS1AR_WEN 0x4000 /* write enable (when set, write access) */
|
||||
#define LS1AR_WPE 0x0800 /* write post enable */
|
||||
#define LS1AR_BNCEN 0x0080 /* bounce mode enable */
|
||||
|
||||
#define LS1AR_VSP1 0x0020
|
||||
#define LS1AR_VSP0 0x0010
|
||||
|
||||
|
||||
/* VSBCHIP2_VS1AR register definitions: */
|
||||
|
||||
#define VS1AR_REN 0x8000 /* read enable (when set, read access) */
|
||||
#define VS1AR_WEN 0x4000 /* write enable (when set, write access) */
|
||||
#define VS1AR_POR 0x2000 /* participate on read */
|
||||
#define VS1AR_POW 0x1000 /* participate on write */
|
||||
#define VS1AR_WPE 0x0800 /* write post enable */
|
||||
#define VS1AR_SAS 0x0400 /* system address space */
|
||||
#define VS1AR_ALTAS 0x0200 /* alternate address space */
|
||||
#define VS1AR_IOAS 0x0100 /* I/O address space */
|
||||
#define VS1AR_LOCK 0x0040 /* lock local bus on block transfers */
|
||||
|
||||
#define VS1AR_LBTS1 0x0008
|
||||
#define VS1AR_LBTS0 0x0004
|
||||
#define VS1AR_LBSC1 0x0002
|
||||
#define VS1AR_LBSC0 0x0001
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvsbchip2h */
|
||||
Reference in New Issue
Block a user