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neelimap
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/* i8254.h - intel 8254 timer header */
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/*
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modification history
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--------------------
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01h,25sep98,cdp added ARM support.
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01g,24feb97,bjl moved #if CPU_FAMILY==MIPS after #ifdef __cplusplus
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removed first #endif INCi8254h
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added #endif CPU_FAMILY==MIPS
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01f,22sep92,rrr added support for c++
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01e,26may92,rrr the tree shuffle
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01d,28oct91,wmd added #pragmas as defined by Intel.
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01c,04oct91,rrr passed through the ansification filter
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-fixed #else and #endif
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-changed ASMLANGUAGE to _ASMLANGUAGE
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-changed copyright notice
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01b,20apr90,ajm merged in MIPS BSP version for now, must resolve later.
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01a,20aug91,del installed.
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*/
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#ifndef __INCi8254h
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#define __INCi8254h
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if (CPU_FAMILY == MIPS) || (CPU_FAMILY == ARM)
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/*
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* INTERNAL
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* On some BSPs, the output of counter2 drives the input to counters 0
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* and 1. This mandates setup of counter2 before counters 0 and 1 can be
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* programmed. On hkv3500, counter 2's input is being driven at 3.6864Mhz
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* by the STAR card.
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*/
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#define PAD 3
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#ifndef _ASMLANGUAGE
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typedef struct {
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unsigned char counter0;unsigned char pad0[PAD];/* counter 0 */
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unsigned char counter1;unsigned char pad1[PAD];/* counter 1 */
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unsigned char counter2;unsigned char pad2[PAD];/* counter 2 */
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unsigned char cntrl_word;unsigned char pad3[PAD];/* control word */
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}TIMER;
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#endif /* _ASMLANGUAGE */
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/*
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* control word definitions
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*/
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#define CW_BCDMD 0x1 /* operate in BCD mode */
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#define CW_COUNTLCH 0x00 /* counter latch command */
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#define CW_LSBYTE 0x10 /* r/w least signif. byte only */
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#define CW_MSBYTE 0x20 /* r/w most signif. byte only */
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#define CW_BOTHBYTE 0x30 /* r/w 16 bits, lsb then msb */
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#define CW_READBK 0xc0 /* read-back command */
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#define CW_MODE(x) ((x)<<1) /* set mode to x */
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#define CW_SELECT(x) ((x)<<6) /* select counter x */
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/*
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* Mode defs
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*/
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#define MD_TERMCOUNT 0x0 /* interrupt on terminal count */
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#define MD_HWONESHOT 0x1 /* hw retriggerable one shot */
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#define MD_RATEGEN 0x2 /* rate generator */
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#define MD_SQUAREWV 0x3 /* square wave generator */
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#define MD_SWTRIGSB 0x4 /* software triggered strobe */
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#define MD_HWTRIGSB 0x5 /* hardware triggered strobe */
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#else /* CPU_FAMILY==MIPS */
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/******************************************************************/
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/* Copyright (c) 1989, Intel Corporation
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Intel hereby grants you permission to copy, modify, and
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distribute this software and its documentation. Intel grants
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this permission provided that the above copyright notice
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appears in all copies and that both the copyright notice and
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this permission notice appear in supporting documentation. In
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addition, Intel grants this permission provided that you
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prominently mark as not part of the original any modifications
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made to this software or documentation, and that the name of
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Intel Corporation not be used in advertising or publicity
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pertaining to distribution of the software or the documentation
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without specific, written prior permission.
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Intel Corporation does not warrant, guarantee or make any
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representations regarding the use of, or the results of the use
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of, the software and documentation in terms of correctness,
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accuracy, reliability, currentness, or otherwise; and you rely
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on the software, documentation and results solely at your own
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risk. */
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/******************************************************************/
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/*-------------------------------------------------------------*/
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/*
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* i8254.h header for 82c54-2 timer/counter
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*
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*/
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/*-------------------------------------------------------------*/
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#if CPU_FAMILY == I960
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#pragma align 1
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#endif
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typedef volatile struct
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{
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unsigned char counter_0;
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unsigned char counter_1;
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unsigned char counter_2;
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unsigned char control_word;
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} I82C54;
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#if CPU_FAMILY == I960
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#pragma align 0
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#endif
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/* Control Word Format */
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#define SC(sc) ((sc)<<6)
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#define RW(rw) ((rw)<<4)
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#define MODE(m) ((m)<<1)
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#define BCD (1)
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/* Control Words */
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#define SEL_CNT_0 0x00
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#define SEL_CNT_1 0x40
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#define SEL_CNT_2 0x80
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#define READ_BACK 0xc0
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#define READ_BACK_0 0xc2
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#define READ_BACK_1 0xc4
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#define READ_BACK_2 0xc8
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#define RW_LATCH 0x00
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#define RW_LO_BYTE 0x10
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#define RW_HI_BYTE 0x20
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#define RW_HI_LO_BYTES 0x30
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#define WRT_CNT_0_LO (SEL_CNT_0 | RW_LO_BYTE)
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#define WRT_CNT_1_LO (SEL_CNT_1 | RW_LO_BYTE)
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#define WRT_CNT_2_LO (SEL_CNT_2 | RW_LO_BYTE)
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#define WRT_CNT_0_HI (SEL_CNT_0 | RW_HI_BYTE)
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#define WRT_CNT_1_HI (SEL_CNT_1 | RW_HI_BYTE)
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#define WRT_CNT_2_HI (SEL_CNT_2 | RW_HI_BYTE)
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#define WRT_CNT_0_HI_LO (SEL_CNT_0 | RW_HI_LO_BYTES)
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#define WRT_CNT_1_HI_LO (SEL_CNT_1 | RW_HI_LO_BYTES)
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#define WRT_CNT_2_HI_LO (SEL_CNT_2 | RW_HI_LO_BYTES)
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/* Readback Commands */
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#define READBACK (3<<6)
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#define LATCH_COUNT (1<<4)
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#define LATCH_STATUS (1<<5)
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#define CNT_0 (1<<1)
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#define CNT_1 (1<<2)
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#define CNT_2 (1<<3)
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/* Status Bits */
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#define OUTPUT_BIT (1<<7)
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#define NULL_COUNT_BIT (1<<6)
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#define RW1_BIT (1<<5)
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#define RW0_BIT (1<<4)
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#define M2_BIT (1<<3)
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#define M1_BIT (1<<2)
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#define M0_BIT (1<<1)
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#define BCD_BIT (1<<0)
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#endif /* CPU_FAMILY==MIPS */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCi8254h */
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