original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,82 @@
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||||
/* ambaTimer.h - ARM AMBA timer header */
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||||
|
||||
/* Copyright 1996-1997 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,31oct01,rec integrator AP changes
|
||||
01c,24nov97,jpd renamed from amba.h to ambaTimer.h.
|
||||
01b,18aug97,jpd Added timers 3 and 4, added TC_EXTERNAL definition.
|
||||
01a,10jul96,jpd Written, based on i8253.h version 01b.
|
||||
*/
|
||||
|
||||
#ifndef __INCambaTimerh
|
||||
#define __INCambaTimerh
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||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* default definitions */
|
||||
|
||||
|
||||
/* register definitions */
|
||||
|
||||
#ifndef AMBA_BASE_OFFSET
|
||||
#define AMBA_BASE_OFFSET 0X20
|
||||
#endif
|
||||
|
||||
#define AMBA_TIMER_T1LOAD(base) \
|
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(volatile UINT32 *)((base) + 0x00) /* T1 Load (R/W) */
|
||||
#define AMBA_TIMER_T1VALUE(base) \
|
||||
(volatile UINT32 *)((base) + 0x04) /* T1 Value (R/O) */
|
||||
#define AMBA_TIMER_T1CTRL(base) \
|
||||
(volatile UINT32 *)((base) + 0x08) /* T1 Control (R/W) */
|
||||
#define AMBA_TIMER_T1CLEAR(base) \
|
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(volatile UINT32 *)((base) + 0x0C) /* T1 Clear (W/O) */
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||||
|
||||
#define AMBA_TIMER_T2LOAD(base) \
|
||||
(volatile UINT32 *)((base) + AMBA_BASE_OFFSET + 0x00) /* T2 Load (R/W) */
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||||
#define AMBA_TIMER_T2VALUE(base) \
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(volatile UINT32 *)((base) + AMBA_BASE_OFFSET + 0x04) /* T2 Value (R/O) */
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#define AMBA_TIMER_T2CTRL(base) \
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(volatile UINT32 *)((base) + AMBA_BASE_OFFSET + 0x08) /* T2 Control (R/W) */
|
||||
#define AMBA_TIMER_T2CLEAR(base) \
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(volatile UINT32 *)((base) + AMBA_BASE_OFFSET + 0x0C) /* T2 Clear (W/O) */
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|
||||
#define AMBA_TIMER_T3LOAD(base) \
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(volatile UINT32 *)((base) + 2 * AMBA_BASE_OFFSET + 0x00) /* T3 Load (R/W) */
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#define AMBA_TIMER_T3VALUE(base) \
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(volatile UINT32 *)((base) + 2 * AMBA_BASE_OFFSET + 0x04) /* T3 Value (R/O) */
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#define AMBA_TIMER_T3CTRL(base) \
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(volatile UINT32 *)((base) + 2 * AMBA_BASE_OFFSET + 0x08) /* T3 Control (R/W) */
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#define AMBA_TIMER_T3CLEAR(base) \
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(volatile UINT32 *)((base) + 2 * AMBA_BASE_OFFSET + 0x0C) /* T3 Clear (W/O) */
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#define AMBA_TIMER_T4LOAD(base) \
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(volatile UINT32 *)((base) + 3 * AMBA_BASE_OFFSET + 0x00) /* T4 Load (R/W) */
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#define AMBA_TIMER_T4VALUE(base) \
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(volatile UINT32 *)((base) + 3 * AMBA_BASE_OFFSET + 0x04) /* T4 Value (R/O) */
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#define AMBA_TIMER_T4CTRL(base) \
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(volatile UINT32 *)((base) + 3 * AMBA_BASE_OFFSET + 0x08) /* T4 Control (R/W) */
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#define AMBA_TIMER_T4CLEAR(base) \
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(volatile UINT32 *)((base) + 3 * AMBA_BASE_OFFSET + 0x0C) /* T4 Clear (W/O) */
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||||
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||||
/* Timer Control register bit definitions */
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#define TC_DIV1 0
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#define TC_DIV16 (1<<2)
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#define TC_DIV256 (1<<3)
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#define TC_EXTERNAL (3<<2)
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#define TC_PERIODIC (1<<6)
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#define TC_FREERUN 0
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#define TC_ENABLE (1<<7)
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#define TC_DISABLE 0
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||||
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||||
#ifdef __cplusplus
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||||
}
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#endif
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||||
|
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#endif /* __INCambaTimerh */
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||||
@@ -0,0 +1,29 @@
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||||
/* amd8111Timer.h - AMD8111 Timer register definitions. */
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||||
|
||||
/*
|
||||
* Copyright (c) 2005 Wind River Systems, Inc.
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||||
*
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||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
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||||
modification history
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||||
--------------------
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||||
01a,07jul05,gtf New
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||||
*/
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||||
|
||||
#ifndef __INCamd81111Timerh
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||||
#define __INCamd81111Timerh
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||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCamd8111Timerh */
|
||||
@@ -0,0 +1,68 @@
|
||||
/* coldfireTimer.h - ColdFire Timer header */
|
||||
|
||||
/*
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||||
modification history
|
||||
--------------------
|
||||
01b,03apr01,dh support for 5272 added (allows external definition of TER type)
|
||||
01b,19oct01,dee Merge from T2.1.0 release
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||||
01a,13apr98,mem written
|
||||
*/
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||||
|
||||
#ifndef __INCcoldfireTimerh
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||||
#define __INCcoldfireTimerh
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||||
|
||||
/*
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||||
This file contains constants and typedefs for the timer contained in several
|
||||
of the Motorola ColdFire ports.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* To change the size of the TER register, define the DEFINED_cfTer_t macro
|
||||
and supply a typedef for cfTer_t.
|
||||
*/
|
||||
#ifndef DEFINED_cfTer_t
|
||||
#define DEFINED_cfTer_t
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||||
typedef UINT8 cfTer_t;
|
||||
#endif
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||||
|
||||
/* defines */
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||||
|
||||
#define COLDFIRE_TMR_CE_DIS (0 << 6) /* disable int on capture */
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||||
#define COLDFIRE_TMR_CE_RISE (1 << 6) /* capture on rising edge */
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||||
#define COLDFIRE_TMR_CE_FALL (2 << 6) /* capture on falling edge */
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#define COLDFIRE_TMR_CE_ANY (3 << 6) /* capture on any edge */
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||||
#define COLDFIRE_TMR_OM (1 << 5) /* output mode */
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||||
#define COLDFIRE_TMR_ORI (1 << 4) /* output ref int enable */
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||||
#define COLDFIRE_TMR_FRR (1 << 3) /* free run/restart */
|
||||
#define COLDFIRE_TMR_CLK_STOP (0 << 1) /* stop count */
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||||
#define COLDFIRE_TMR_CLK_BUS (1 << 1) /* system bus clock */
|
||||
#define COLDFIRE_TMR_CLK_BUS16 (2 << 1) /* system bus clock / 16 */
|
||||
#define COLDFIRE_TMR_CLK_TIN (3 << 1) /* TIN pin */
|
||||
#define COLDFIRE_TMR_EN (1 << 0) /* enable (reset) timer */
|
||||
|
||||
#define COLDFIRE_TER_REF (1 << 1) /* output reference event */
|
||||
#define COLDFIRE_TER_CAP (1 << 0) /* capture event */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef struct
|
||||
{
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||||
volatile UINT16 *tmr; /* timer mode register */
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volatile cfTer_t *ter; /* timer event register */
|
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volatile UINT16 *tcn; /* timer counter register */
|
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volatile UINT16 *tcr; /* timer capture register */
|
||||
volatile UINT16 *trr; /* timer reference register */
|
||||
volatile void *imr; /* interrupt mask register */
|
||||
|
||||
int imrSize; /* size of IMR in bytes */
|
||||
ULONG imrMask; /* mask bit in IMR register */
|
||||
} COLDFIRE_TIMER;
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||||
|
||||
#ifdef __cplusplus
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||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCcoldfireTimerh */
|
||||
@@ -0,0 +1,85 @@
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||||
/* cycleLib.h - clock cycle level event library header */
|
||||
|
||||
/* Copyright 2005, 2018 Wind River Systems, Inc. */
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||||
#include "copyright_wrs.h"
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||||
|
||||
/*
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||||
modification history
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||||
--------------------
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||||
01b,25sep18,whu move extern C declaration to the front of structure declaration
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||||
(VXW6-86818)
|
||||
01a,06dec05,prb written.
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||||
*/
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||||
|
||||
#ifndef __INCcycleLibh
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||||
#define __INCcycleLibh
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||||
|
||||
#include <sys/cdefs.h>
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||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#define SET_RELOAD(x)
|
||||
#undef SET_RELOAD
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||||
|
||||
typedef unsigned int CYCLE_TICK;
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typedef unsigned long long int CYCLE_CLOCK;
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||||
|
||||
typedef struct cycleLibEvent_t cycleLibEvent_t;
|
||||
typedef cycleLibEvent_t *CEVENT_ID;
|
||||
|
||||
/*
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||||
* The event queue is a double linked delta queue.
|
||||
*
|
||||
* The next pointer points to the next element, or NULL if it is
|
||||
* the last event in the queue.
|
||||
*
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||||
* The prev pointer points t the previous element. It's value is unspecified
|
||||
* for the first element in the queue.
|
||||
*
|
||||
* The tick value is the number of ticks between the previous event
|
||||
* and this event.
|
||||
*
|
||||
* The rate is the frequency, in ticks, of this event. A value of 0
|
||||
* implies this is not a repeating event.
|
||||
*
|
||||
* The base is only used for repeating events. This is the absolute cycle
|
||||
* value for the next event.
|
||||
*/
|
||||
struct cycleLibEvent_t {
|
||||
CEVENT_ID next; /* Next event to fire */
|
||||
CEVENT_ID prev; /* doubly linked list */
|
||||
CYCLE_TICK tick; /* delta until event fires */
|
||||
void (*callback)(void *); /* callback function */
|
||||
void *arg; /* argument to callback */
|
||||
CYCLE_TICK rate; /* rate if repeating event */
|
||||
CYCLE_CLOCK base; /* time base if repeating */
|
||||
};
|
||||
|
||||
|
||||
extern void cycleLibInit __P((void));
|
||||
extern int cycleLibPoolAlloc __P((int, CEVENT_ID));
|
||||
extern void cycleLibEventFree __P((CEVENT_ID));
|
||||
extern void cycleLibEventHandler __P((void));
|
||||
extern CEVENT_ID cycleLibEventAdd __P((CYCLE_TICK, void(*)(void *),
|
||||
void *));
|
||||
extern CEVENT_ID cycleLibEventAddRepeating __P((CYCLE_TICK, CYCLE_TICK,
|
||||
void(*)(void *), void *));
|
||||
extern CEVENT_ID cycleLibEventAddAbsolute __P((CYCLE_CLOCK,
|
||||
void(*)(void *), void *, CEVENT_ID));
|
||||
extern void cycleLibEventDelete __P((CEVENT_ID, void(*)(void *),
|
||||
void *));
|
||||
__END_DECLS
|
||||
|
||||
/*
|
||||
* The values below should be set in a architecture specific location.
|
||||
*/
|
||||
|
||||
#define SET_TIMER(x) vxDecSet(x)
|
||||
#define GET_CYCLE_CLOCK() gettb()
|
||||
|
||||
__BEGIN_DECLS
|
||||
extern CYCLE_CLOCK gettb __P((void));
|
||||
extern void vxDecSet __P((unsigned));
|
||||
__END_DECLS
|
||||
|
||||
#endif /* __INCcycleLibh */
|
||||
@@ -0,0 +1,41 @@
|
||||
/* i8253.h - Intel 8253 PIT (Programmable Interrupt Timer) */
|
||||
|
||||
/* Copyright 1984-1993 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,16jun93,hdn updated to 5.1.
|
||||
01a,20may92,hdn written.
|
||||
*/
|
||||
|
||||
#ifndef __INCi8253h
|
||||
#define __INCi8253h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The macro PIT_REG_ADDR_INTERVAL must be defined
|
||||
* when including this header.
|
||||
*/
|
||||
|
||||
/* default definitions */
|
||||
|
||||
#define CAST
|
||||
|
||||
#define PIT_ADRS(base,reg) (CAST (base+(reg*PIT_REG_ADDR_INTERVAL)))
|
||||
|
||||
/* register definitions */
|
||||
|
||||
#define PIT_CNT0(base) PIT_ADRS(base,0x00) /* Counter 0. */
|
||||
#define PIT_CNT1(base) PIT_ADRS(base,0x01) /* Counter 1. */
|
||||
#define PIT_CNT2(base) PIT_ADRS(base,0x02) /* Counter 2. */
|
||||
#define PIT_CMD(base) PIT_ADRS(base,0x03) /* Control word. */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCi8253h */
|
||||
@@ -0,0 +1,180 @@
|
||||
/* i8254.h - intel 8254 timer header */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,25sep98,cdp added ARM support.
|
||||
01g,24feb97,bjl moved #if CPU_FAMILY==MIPS after #ifdef __cplusplus
|
||||
removed first #endif INCi8254h
|
||||
added #endif CPU_FAMILY==MIPS
|
||||
01f,22sep92,rrr added support for c++
|
||||
01e,26may92,rrr the tree shuffle
|
||||
01d,28oct91,wmd added #pragmas as defined by Intel.
|
||||
01c,04oct91,rrr passed through the ansification filter
|
||||
-fixed #else and #endif
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01b,20apr90,ajm merged in MIPS BSP version for now, must resolve later.
|
||||
01a,20aug91,del installed.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INCi8254h
|
||||
#define __INCi8254h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if (CPU_FAMILY == MIPS) || (CPU_FAMILY == ARM)
|
||||
/*
|
||||
|
||||
* INTERNAL
|
||||
* On some BSPs, the output of counter2 drives the input to counters 0
|
||||
* and 1. This mandates setup of counter2 before counters 0 and 1 can be
|
||||
* programmed. On hkv3500, counter 2's input is being driven at 3.6864Mhz
|
||||
* by the STAR card.
|
||||
|
||||
*/
|
||||
|
||||
#define PAD 3
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
typedef struct {
|
||||
unsigned char counter0;unsigned char pad0[PAD];/* counter 0 */
|
||||
unsigned char counter1;unsigned char pad1[PAD];/* counter 1 */
|
||||
unsigned char counter2;unsigned char pad2[PAD];/* counter 2 */
|
||||
unsigned char cntrl_word;unsigned char pad3[PAD];/* control word */
|
||||
}TIMER;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/*
|
||||
* control word definitions
|
||||
*/
|
||||
|
||||
#define CW_BCDMD 0x1 /* operate in BCD mode */
|
||||
#define CW_COUNTLCH 0x00 /* counter latch command */
|
||||
#define CW_LSBYTE 0x10 /* r/w least signif. byte only */
|
||||
#define CW_MSBYTE 0x20 /* r/w most signif. byte only */
|
||||
#define CW_BOTHBYTE 0x30 /* r/w 16 bits, lsb then msb */
|
||||
#define CW_READBK 0xc0 /* read-back command */
|
||||
#define CW_MODE(x) ((x)<<1) /* set mode to x */
|
||||
#define CW_SELECT(x) ((x)<<6) /* select counter x */
|
||||
|
||||
/*
|
||||
* Mode defs
|
||||
*/
|
||||
|
||||
#define MD_TERMCOUNT 0x0 /* interrupt on terminal count */
|
||||
#define MD_HWONESHOT 0x1 /* hw retriggerable one shot */
|
||||
#define MD_RATEGEN 0x2 /* rate generator */
|
||||
#define MD_SQUAREWV 0x3 /* square wave generator */
|
||||
#define MD_SWTRIGSB 0x4 /* software triggered strobe */
|
||||
#define MD_HWTRIGSB 0x5 /* hardware triggered strobe */
|
||||
|
||||
#else /* CPU_FAMILY==MIPS */
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
/* Copyright (c) 1989, Intel Corporation
|
||||
|
||||
Intel hereby grants you permission to copy, modify, and
|
||||
distribute this software and its documentation. Intel grants
|
||||
this permission provided that the above copyright notice
|
||||
appears in all copies and that both the copyright notice and
|
||||
this permission notice appear in supporting documentation. In
|
||||
addition, Intel grants this permission provided that you
|
||||
prominently mark as not part of the original any modifications
|
||||
made to this software or documentation, and that the name of
|
||||
Intel Corporation not be used in advertising or publicity
|
||||
pertaining to distribution of the software or the documentation
|
||||
without specific, written prior permission.
|
||||
|
||||
Intel Corporation does not warrant, guarantee or make any
|
||||
representations regarding the use of, or the results of the use
|
||||
of, the software and documentation in terms of correctness,
|
||||
accuracy, reliability, currentness, or otherwise; and you rely
|
||||
on the software, documentation and results solely at your own
|
||||
risk. */
|
||||
/******************************************************************/
|
||||
/*-------------------------------------------------------------*/
|
||||
/*
|
||||
* i8254.h header for 82c54-2 timer/counter
|
||||
*
|
||||
*/
|
||||
/*-------------------------------------------------------------*/
|
||||
|
||||
#if CPU_FAMILY == I960
|
||||
#pragma align 1
|
||||
#endif
|
||||
|
||||
typedef volatile struct
|
||||
{
|
||||
unsigned char counter_0;
|
||||
unsigned char counter_1;
|
||||
unsigned char counter_2;
|
||||
unsigned char control_word;
|
||||
} I82C54;
|
||||
|
||||
#if CPU_FAMILY == I960
|
||||
#pragma align 0
|
||||
#endif
|
||||
|
||||
/* Control Word Format */
|
||||
#define SC(sc) ((sc)<<6)
|
||||
#define RW(rw) ((rw)<<4)
|
||||
#define MODE(m) ((m)<<1)
|
||||
#define BCD (1)
|
||||
|
||||
/* Control Words */
|
||||
|
||||
#define SEL_CNT_0 0x00
|
||||
#define SEL_CNT_1 0x40
|
||||
#define SEL_CNT_2 0x80
|
||||
#define READ_BACK 0xc0
|
||||
#define READ_BACK_0 0xc2
|
||||
#define READ_BACK_1 0xc4
|
||||
#define READ_BACK_2 0xc8
|
||||
|
||||
#define RW_LATCH 0x00
|
||||
#define RW_LO_BYTE 0x10
|
||||
#define RW_HI_BYTE 0x20
|
||||
#define RW_HI_LO_BYTES 0x30
|
||||
|
||||
#define WRT_CNT_0_LO (SEL_CNT_0 | RW_LO_BYTE)
|
||||
#define WRT_CNT_1_LO (SEL_CNT_1 | RW_LO_BYTE)
|
||||
#define WRT_CNT_2_LO (SEL_CNT_2 | RW_LO_BYTE)
|
||||
#define WRT_CNT_0_HI (SEL_CNT_0 | RW_HI_BYTE)
|
||||
#define WRT_CNT_1_HI (SEL_CNT_1 | RW_HI_BYTE)
|
||||
#define WRT_CNT_2_HI (SEL_CNT_2 | RW_HI_BYTE)
|
||||
#define WRT_CNT_0_HI_LO (SEL_CNT_0 | RW_HI_LO_BYTES)
|
||||
#define WRT_CNT_1_HI_LO (SEL_CNT_1 | RW_HI_LO_BYTES)
|
||||
#define WRT_CNT_2_HI_LO (SEL_CNT_2 | RW_HI_LO_BYTES)
|
||||
|
||||
/* Readback Commands */
|
||||
#define READBACK (3<<6)
|
||||
#define LATCH_COUNT (1<<4)
|
||||
#define LATCH_STATUS (1<<5)
|
||||
#define CNT_0 (1<<1)
|
||||
#define CNT_1 (1<<2)
|
||||
#define CNT_2 (1<<3)
|
||||
|
||||
/* Status Bits */
|
||||
#define OUTPUT_BIT (1<<7)
|
||||
#define NULL_COUNT_BIT (1<<6)
|
||||
#define RW1_BIT (1<<5)
|
||||
#define RW0_BIT (1<<4)
|
||||
#define M2_BIT (1<<3)
|
||||
#define M1_BIT (1<<2)
|
||||
#define M0_BIT (1<<1)
|
||||
#define BCD_BIT (1<<0)
|
||||
|
||||
#endif /* CPU_FAMILY==MIPS */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCi8254h */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* ixp400Timer.h - ixp400 processor timer library */
|
||||
|
||||
/*
|
||||
Copyright (c) 2002-2004 Wind River Systems, Inc. All rights reserved.
|
||||
Certain portions of these files may be copyright (c) 2002-2004 Intel
|
||||
Corporation.
|
||||
*/
|
||||
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,24aug05,m_h vxWorks 6.1 support
|
||||
01d,20dec04,pai Updated copyright notice.
|
||||
01c,09jul03,m_h multiple callouts from auxClk
|
||||
01b,27feb03,jb3 add C++ protection
|
||||
01a,05jun02,jb initial version...
|
||||
*/
|
||||
|
||||
#ifndef INCixp400Timerh
|
||||
#define INCixp400Timerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SYS_CLK_RATE_MIN (10) /* Minimum rate at which the system clock can run */
|
||||
#define SYS_CLK_RATE_MAX (1000) /* 1000 ticks, Maximum rate at which the system clock can run */
|
||||
|
||||
/* Do not actually have an auxiliary clock */
|
||||
#define AUX_CLK_RATE_MIN (10) /* Minimum rate at which the auxiliary clock can run */
|
||||
#define AUX_CLK_RATE_MAX (1000) /* 1000 ticks, Maximum rate at which the auxiliary clock can run */
|
||||
|
||||
|
||||
/* auxClk functionality used within this BSP */
|
||||
STATUS ixpAuxClkConnect (FUNCPTR routine, int arg);
|
||||
void ixpAuxClkDisconnect (void);
|
||||
void ixpAuxClkDisable (void);
|
||||
void ixpAuxClkEnable (void);
|
||||
int ixpAuxClkRateGet (void);
|
||||
STATUS ixpAuxClkRateSet (int ticksPerSecond);
|
||||
|
||||
|
||||
/* 50MHz emulation mode for ixp465 */
|
||||
BOOL ixpTimer20NsEmulSet(BOOL useEmul);
|
||||
BOOL ixpTimer20NsEmulGet(void);
|
||||
BOOL ixpAuxTimer20NsEmulSet(BOOL useEmul);
|
||||
BOOL ixpAuxTimer20NsEmulGet(void);
|
||||
|
||||
void ixp400WatchDogInt (void);
|
||||
STATUS ixp400WatchDogConnect(FUNCPTR routine, int arg);
|
||||
STATUS ixp400WatchDogEnable(void);
|
||||
STATUS ixp400WatchDogDisable (void);
|
||||
UINT32 ixp400WatchdogPeriod (void);
|
||||
STATUS ixp400WatchDogPeriodSet(UINT32 counts);
|
||||
UINT32 ixp400WatchDogFreq (void);
|
||||
void ixp400WatchDogService(void);
|
||||
|
||||
/* Assembly specific defs */
|
||||
#ifndef _ASMLANGUAGE
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* INCixp400Timer.h */
|
||||
|
||||
@@ -0,0 +1,101 @@
|
||||
/* m5200GPTimer.h - Motorola MPC5200 General Purpose Timer (GPT) driver */
|
||||
|
||||
/* Copyright 2000-2003 Wind River Systems, Inc. */
|
||||
#include "copyright_wrs.h"
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,06dec03,pdr created
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INCm5200GPTimerh
|
||||
#define __INCm5200GPTimerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* routines */
|
||||
|
||||
/* TMU3 routines */
|
||||
IMPORT STATUS sysUserClkConnect ( FUNCPTR routine, int arg );
|
||||
IMPORT void sysUserClkDisable ( void );
|
||||
IMPORT void sysUserClkEnable ( void );
|
||||
IMPORT int sysUserClkRateGet ( void );
|
||||
IMPORT STATUS sysUserClkRateSet ( int ticksPerSecond );
|
||||
IMPORT BOOL sysUserClkIsRunning ( void );
|
||||
|
||||
/* TMU4 routines */
|
||||
IMPORT STATUS sysUserAuxClkConnect ( FUNCPTR routine, int arg );
|
||||
IMPORT void sysUserAuxClkDisable ( void );
|
||||
IMPORT void sysUserAuxClkEnable ( void );
|
||||
IMPORT int sysUserAuxClkRateGet ( void );
|
||||
IMPORT STATUS sysUserAuxClkRateSet ( int ticksPerSecond );
|
||||
IMPORT BOOL sysUserAuxClkIsRunning ( void );
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __INCm5200GPTimerh */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
/* m5200SliceTimer.h - PowerPC Slice Timer (SLT) header */
|
||||
|
||||
/* Copyright 1984-2003 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,15sep03,pdr created.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains header information for PowerPC Slice timer routines.
|
||||
*/
|
||||
|
||||
#ifndef __INCm5200SliceTimerh
|
||||
#define __INCm5200SliceTimerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* function declarations */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
IMPORT STATUS sysAuxClkConnect (FUNCPTR routine, int arg);
|
||||
IMPORT void sysAuxClkDisable (void);
|
||||
IMPORT void sysAuxClkEnable (void);
|
||||
IMPORT int sysAuxClkRateGet (void);
|
||||
IMPORT STATUS sysAuxClkRateSet (int ticksPerSecond);
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
IMPORT STATUS sysAuxClkConnect ();
|
||||
IMPORT void sysAuxClkDisable ();
|
||||
IMPORT void sysAuxClkEnable ();
|
||||
IMPORT int sysAuxClkRateGet ();
|
||||
IMPORT STATUS sysAuxClkRateSet ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCm5200SliceTimerh */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* m8260Clock - Motorola MPC8260 Clock header file */
|
||||
|
||||
/* Copyright 1984-1999 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,12sep99,ms_ created from m8260Cpm.h, 01d.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains constants for the clock block in the Motorola
|
||||
* MPC8260 PowerQUICC II integrated Communications Processor
|
||||
*/
|
||||
|
||||
#ifndef __INCm8260Clockh
|
||||
#define __INCm8260Clockh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef M8260ABBREVIATIONS
|
||||
#define M8260ABBREVIATIONS
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST(x)
|
||||
#else /* _ASMLANGUAGE */
|
||||
typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
|
||||
typedef volatile INT32 VINT32; /* volatile unsigned word */
|
||||
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
|
||||
typedef volatile INT8 VINT8; /* volatile unsigned byte */
|
||||
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
|
||||
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
|
||||
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
|
||||
#define CAST(x) (x)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* M8260ABBREVIATIONS */
|
||||
|
||||
/*
|
||||
* MPC8260 internal register/memory map (section 17 of prelim. spec)
|
||||
* note that these are offsets from the value stored in the IMMR
|
||||
* register. Also note that in the MPC8260, the IMMR is not a special
|
||||
* purpose register, but it is memory mapped.
|
||||
*/
|
||||
|
||||
/* System Clock Control Register */
|
||||
|
||||
#define M8260_SCCR(base) (CAST(VUINT32 *)((base) + 0x10c80))
|
||||
|
||||
/* System Clock Control Register bit definition (SCCR - 0x10c80) */
|
||||
|
||||
#define M8260_SCCR_RES_MSK 0xfffffff8 /* reserved field Mask */
|
||||
#define M8260_SCCR_CPM_LOW 0x00000004 /* CPM and SIU low power */
|
||||
#define M8260_SCCR_DFBRG_4 0x00000000 /* divide by 4 */
|
||||
#define M8260_SCCR_DFBRG_16 0x00000001 /* divide by 16 */
|
||||
#define M8260_SCCR_DFBRG_64 0x00000002 /* divide by 64 */
|
||||
#define M8260_SCCR_DFBRG_128 0x00000003 /* divide by 128 */
|
||||
#define M8260_SCCR_TBS 0x02000000 /* Time Base Source */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCm8260Clockh */
|
||||
@@ -0,0 +1,123 @@
|
||||
/* m8260Timer.h */
|
||||
|
||||
/* Copyright 1984-1999 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,15jul99,ms_ make compliant with our coding standards
|
||||
01b,21may99,ms_ local
|
||||
01a,17apr99,ms_ adapted from ppc860Timer.h ref 01c
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains header information for PowerPC timer routines.
|
||||
*/
|
||||
|
||||
#ifndef __INCm8260Timerh
|
||||
#define __INCm8260Timerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* CPM Timer Register sets */
|
||||
|
||||
/* Timer 1 and Timer 2 Global Configuration Register */
|
||||
|
||||
#define M8260_TGCR1(base) (CAST(VUINT8 *)((base) + 0x10D80))
|
||||
|
||||
/* Timer 3 and Timer 4 Global Configuration Register */
|
||||
|
||||
#define M8260_TGCR2(base) (CAST(VUINT8 *)((base) + 0x10D84))
|
||||
|
||||
/* CPM Timer Mode Registers */
|
||||
|
||||
#define M8260_TMR1(base) (CAST(VUINT16 *)((base) + 0x10D90)) /* Timer 1 */
|
||||
#define M8260_TMR2(base) (CAST(VUINT16 *)((base) + 0x10D92)) /* Timer 2 */
|
||||
#define M8260_TMR3(base) (CAST(VUINT16 *)((base) + 0x10DA0)) /* Timer 3 */
|
||||
#define M8260_TMR4(base) (CAST(VUINT16 *)((base) + 0x10DA2)) /* Timer 4 */
|
||||
|
||||
/* CPM Timer Reference Registers */
|
||||
|
||||
#define M8260_TRR1(base) (CAST(VUINT16 *)((base) + 0x10D94)) /* Timer 1 */
|
||||
#define M8260_TRR2(base) (CAST(VUINT16 *)((base) + 0x10D96)) /* Timer 2 */
|
||||
#define M8260_TRR3(base) (CAST(VUINT16 *)((base) + 0x10DA4)) /* Timer 3 */
|
||||
#define M8260_TRR4(base) (CAST(VUINT16 *)((base) + 0x10DA6)) /* Timer 4 */
|
||||
|
||||
/* CPM Timer Capture Registers */
|
||||
|
||||
#define M8260_TCR1(base) (CAST(VUINT16 *)((base) + 0x10D98)) /* Timer 1 */
|
||||
#define M8260_TCR2(base) (CAST(VUINT16 *)((base) + 0x10D9A)) /* Timer 2 */
|
||||
#define M8260_TCR3(base) (CAST(VUINT16 *)((base) + 0x10DA8)) /* Timer 3 */
|
||||
#define M8260_TCR4(base) (CAST(VUINT16 *)((base) + 0x10DAA)) /* Timer 4 */
|
||||
|
||||
/* CPM Timer Counters */
|
||||
|
||||
#define M8260_TCN1(base) (CAST(VUINT16 *)((base) + 0x10D9C)) /* Timer 1 */
|
||||
#define M8260_TCN2(base) (CAST(VUINT16 *)((base) + 0x10D9E)) /* Timer 2 */
|
||||
#define M8260_TCN3(base) (CAST(VUINT16 *)((base) + 0x10DAC)) /* Timer 3 */
|
||||
#define M8260_TCN4(base) (CAST(VUINT16 *)((base) + 0x10DAE)) /* Timer 4 */
|
||||
|
||||
/* CPM Timer Event Registers */
|
||||
|
||||
#define M8260_TER1(base) (CAST(VUINT16 *)((base) + 0x10DB0)) /* Timer 1 */
|
||||
#define M8260_TER2(base) (CAST(VUINT16 *)((base) + 0x10DB2)) /* Timer 2 */
|
||||
#define M8260_TER3(base) (CAST(VUINT16 *)((base) + 0x10DB4)) /* Timer 3 */
|
||||
#define M8260_TER4(base) (CAST(VUINT16 *)((base) + 0x10DB6)) /* Timer 4 */
|
||||
|
||||
/* CPM Timer Bit Definitions */
|
||||
|
||||
/* Timer Global Configuration Register Bit Definitions */
|
||||
|
||||
#define M8260_TGCR_CAS2 0x80 /* Cascade Timers 1 and 2*/
|
||||
#define M8260_TGCR_STP2 0x20 /* Stop timer 2 */
|
||||
#define M8260_TGCR_RST2 0x10 /* Reset timer 2 */
|
||||
#define M8260_TGCR_GM1 0x08 /* Gate Mode for TGATE1 */
|
||||
#define M8260_TGCR_STP1 0x02 /* Stop timer 1 */
|
||||
#define M8260_TGCR_RST1 0x01 /* Reset timer 1 */
|
||||
|
||||
#define M8260_TGCR_CAS4 0x80 /* Cascade Timers 3 and 4*/
|
||||
#define M8260_TGCR_STP4 0x20 /* Stop timer 4 */
|
||||
#define M8260_TGCR_RST4 0x10 /* Reset timer 4 */
|
||||
#define M8260_TGCR_GM2 0x08 /* Gate Mode for TGATE2 */
|
||||
#define M8260_TGCR_STP3 0x02 /* Stop timer 3 */
|
||||
#define M8260_TGCR_RST3 0x01 /* Reset timer 3 */
|
||||
|
||||
|
||||
/* Timer Mode Register Bit Definitions */
|
||||
|
||||
#define M8260_TMR_PS_MSK 0xff00 /* Mask for Prescaler Value */
|
||||
#define M8260_TMR_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt */
|
||||
#define M8260_TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
|
||||
#define M8260_TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
|
||||
#define M8260_TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
|
||||
#define M8260_TMR_CE_ANY 0x00c0 /* Capture on any TINx edge */
|
||||
#define M8260_TMR_OM 0x0020 /* Output Mode */
|
||||
#define M8260_TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
|
||||
#define M8260_TMR_FRR 0x0008 /* Free Run/Restart */
|
||||
#define M8260_TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
|
||||
#define M8260_TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
|
||||
#define M8260_TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
|
||||
/* Internal General system clk div 16 */
|
||||
#define M8260_TMR_ICLK_IN_GEN_DIV16 0x0004
|
||||
#define M8260_TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
|
||||
#define M8260_TMR_GE 0x0001 /* Gate Enable */
|
||||
|
||||
/* Timer Event Register Bit Definitions */
|
||||
|
||||
#define M8260_TER_REF 0x0002 /* Output Reference Event */
|
||||
#define M8260_TER_CAP 0x0001 /* Capture Event */
|
||||
|
||||
/* Other Timer Defines */
|
||||
|
||||
#define M8260_TRR_SIZE 16 /* number bits in Reference Register */
|
||||
#define M8260_TMR_PS_MIN 0x00 /* minimum prescale value */
|
||||
#define M8260_TMR_PS_MAX 0xff00 /* maximum prescale value */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCm8260Timerh */
|
||||
@@ -0,0 +1,73 @@
|
||||
/* mc146818.h - Motorolla ? 146818 RTC (Real Time Clock) */
|
||||
|
||||
/* Copyright 1984-2001 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,13apr01,hdn added macros for status register A, B, C, D.
|
||||
01b,09nov93,vin moved AUX_CLK_RATE_MIN and AUX_CLK_RATE_MAX macro definitions
|
||||
to config.h
|
||||
01a,17aug93,hdn written.
|
||||
*/
|
||||
|
||||
#ifndef __INCmc146818h
|
||||
#define __INCmc146818h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int rate;
|
||||
char bits;
|
||||
} CLK_RATE;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
/* offset of status register A, B, C, D */
|
||||
|
||||
#define MC146818_STATUS_A 0x0a /* Status Register A */
|
||||
#define MC146818_STATUS_B 0x0b /* Status Register B */
|
||||
#define MC146818_STATUS_C 0x0c /* Status Register C */
|
||||
#define MC146818_STATUS_D 0x0d /* Status Register D */
|
||||
|
||||
/* bit values for status register A - RW except UIP */
|
||||
|
||||
#define MC146818_UIP 0x80 /* Update In Progress */
|
||||
#define MC146818_DV_BITS 0x70 /* Divider Bits */
|
||||
#define MC146818_RS_BITS 0x0f /* Rate Selection Bits */
|
||||
|
||||
/* bit values for status register B - RW */
|
||||
|
||||
#define MC146818_SET 0x80 /* Set to 1 (abort update) */
|
||||
#define MC146818_PIE 0x40 /* Periodic Int Enable */
|
||||
#define MC146818_AIE 0x20 /* Alarm Int Enable */
|
||||
#define MC146818_UIE 0x10 /* Update-ended Int Enable */
|
||||
#define MC146818_SQWE 0x08 /* Square Wave Enable */
|
||||
#define MC146818_DM 0x04 /* Date Mode */
|
||||
#define MC146818_24 0x02 /* 1=24-hour 0=12-hour */
|
||||
#define MC146818_DSE 0x01 /* Daylight Saving Enable */
|
||||
|
||||
/* bit values for status register C - R */
|
||||
|
||||
#define MC146818_IRQF 0x80 /* Int Request Flag */
|
||||
#define MC146818_PF 0x40 /* Periodic Int Flag */
|
||||
#define MC146818_AF 0x20 /* Alarm Int Flag */
|
||||
#define MC146818_UF 0x10 /* Update-ended Int Flag */
|
||||
|
||||
/* bit values for status register D - R */
|
||||
|
||||
#define MC146818_VRT 0x80 /* Valid RAM and Time */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmc146818h */
|
||||
@@ -0,0 +1,53 @@
|
||||
/* ppc403Timerh.h - PPC 403 Timers header */
|
||||
|
||||
/* Copyright 1984-2002, Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,26apr02,dat Adding cplusplus protection, SPR 75017
|
||||
01b,19sep01,pch Fix reversal of PIT and FIT in comments (for SPR 20698)
|
||||
01a,23feb96,tam created.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INCppc403Timerh
|
||||
#define __INCppc403Timerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
#define _PPC403_TSR_ENW 0x80000000 /* enable next watchdog mask */
|
||||
#define _PPC403_TSR_WIS 0x40000000 /* WDT interrupt status mask */
|
||||
#define _PPC403_TSR_WRS 0x30000000 /* watchdog reset status mask */
|
||||
#define _PPC403_TSR_PIS 0x08000000 /* PIT interrupt status mask */
|
||||
#define _PPC403_TSR_FIS 0x04000000 /* FIT interrupt status mask */
|
||||
|
||||
#define _PPC403_TCR_WP 0xC0000000 /* watchdog period mask */
|
||||
#define _PPC403_TCR_WRC 0x30000000 /* wdog reset control mask */
|
||||
#define _PPC403_TCR_WIE 0x08000000 /* WDT interrupt enable mask */
|
||||
#define _PPC403_TCR_PIE 0x04000000 /* PIT interrupt enable mask */
|
||||
#define _PPC403_TCR_FP 0x03000000 /* FIT period mask */
|
||||
#define _PPC403_TCR_FIE 0x00800000 /* FIT interrupt enable mask */
|
||||
#define _PPC403_TCR_ARE 0x00400000 /* auto-reload enable mask */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef struct {
|
||||
UINT32 fitPeriod; /* Fixed Interval Timer periods */
|
||||
UINT32 fpMask; /* corresponding TCR mask */
|
||||
}FIT_PERIOD;
|
||||
|
||||
typedef struct {
|
||||
UINT32 wdtPeriod; /* Watchdog Timer periods */
|
||||
UINT32 fpMask; /* corresponding TCR mask */
|
||||
}WDT_PERIOD;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCppc403Timerh */
|
||||
@@ -0,0 +1,52 @@
|
||||
/* ppcDecTimer.h - PowerPC Timer header */
|
||||
|
||||
/* Copyright 1984-1996 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,27apr95,caf changed "60x" to "Dec", removed PPC60x_TIMER_INT_VECTOR macro.
|
||||
01b,25jan95,vin cleanup.
|
||||
01a,20jan95,kvk created.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains header information for PowerPC timer routines.
|
||||
*/
|
||||
|
||||
#ifndef __INCppcDecTimerh
|
||||
#define __INCppcDecTimerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* function declarations */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
IMPORT STATUS sysClkConnect (FUNCPTR routine, int arg);
|
||||
IMPORT void sysClkDisable (void);
|
||||
IMPORT void sysClkEnable (void);
|
||||
IMPORT int sysClkRateGet (void);
|
||||
IMPORT STATUS sysClkRateSet (int ticksPerSecond);
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
IMPORT STATUS sysClkConnect ();
|
||||
IMPORT void sysClkDisable ();
|
||||
IMPORT void sysClkEnable ();
|
||||
IMPORT int sysClkRateGet ();
|
||||
IMPORT STATUS sysClkRateSet ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCppcDecTimerh */
|
||||
@@ -0,0 +1,342 @@
|
||||
/* ppcZ8536Timer.h - zilog CIO (counter,timer,parallel i/o chip) */
|
||||
|
||||
/* Copyright 1984-2000 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,13apr00,dat added prototypes for driver entry points
|
||||
01b,18jan99,sut remove ZCIO_DD_OUT, and added ZCIO_DD_PORT_x marcos (SPR 23111)
|
||||
01a,07nov95,kvk created from version 01g of z8536.h for PPC.
|
||||
*/
|
||||
|
||||
/* Note: in the following, the value '0x00' has been replaced by 'ZERO'.
|
||||
This has been done to provide a way to avoid the 'clr.b' instruction
|
||||
on the 68000/10 cpu. 'ZERO' should be defined to be a memory location
|
||||
which holds the value '0x00', this will cause compilers to generate
|
||||
memory to memory transfers rather than clear instructions. */
|
||||
|
||||
#ifndef __INCppcZ8536Timerh
|
||||
#define __INCppcZ8536Timerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* internal register addresses */
|
||||
|
||||
#define ZCIO_MIC ((UINT8) ZERO) /* Master Interrupt Control */
|
||||
#define ZCIO_MCC ((UINT8) 0x01) /* Master Configuration Control */
|
||||
#define ZCIO_PAIV ((UINT8) 0x02) /* Port A Interrupt Vector */
|
||||
#define ZCIO_PBIV ((UINT8) 0x03) /* Port B Interrupt Vector */
|
||||
#define ZCIO_CTIV ((UINT8) 0x04) /* Counter/Timer Interrupt Vector */
|
||||
|
||||
#define ZCIO_PCDPP ((UINT8) 0x05) /* Port C Data Path Polarity */
|
||||
#define ZCIO_PCDD ((UINT8) 0x06) /* Port C Data Direction */
|
||||
#define ZCIO_PCSIOC ((UINT8) 0x07) /* Port C Special I/O Control */
|
||||
#define ZCIO_PACS ((UINT8) 0x08) /* Port A Command and Status */
|
||||
#define ZCIO_PBCS ((UINT8) 0x09) /* Port B Command and Status */
|
||||
|
||||
#define ZCIO_CT1CS ((UINT8) 0x0a) /* C/T 1 Command and Status */
|
||||
#define ZCIO_CT2CS ((UINT8) 0x0b) /* C/T 2 Command and Status */
|
||||
#define ZCIO_CT3CS ((UINT8) 0x0c) /* C/T 3 Command and Status */
|
||||
|
||||
#define ZCIO_PAD ((UINT8) 0x0d) /* Port A Data */
|
||||
#define ZCIO_PBD ((UINT8) 0x0e) /* Port B Data */
|
||||
#define ZCIO_PCD ((UINT8) 0x0f) /* Port C Data */
|
||||
|
||||
#define ZCIO_CT1CCMSB ((UINT8) 0x10) /* C/T 1 Current Count (MS Byte) */
|
||||
#define ZCIO_CT1CCLSB ((UINT8) 0x11) /* C/T 1 Current Count (LS Byte) */
|
||||
#define ZCIO_CT2CCMSB ((UINT8) 0x12) /* C/T 2 Current Count (MS Byte) */
|
||||
#define ZCIO_CT2CCLSB ((UINT8) 0x13) /* C/T 2 Current Count (LS Byte) */
|
||||
#define ZCIO_CT3CCMSB ((UINT8) 0x14) /* C/T 3 Current Count (MS Byte) */
|
||||
#define ZCIO_CT3CCLSB ((UINT8) 0x15) /* C/T 3 Current Count (LS Byte) */
|
||||
|
||||
#define ZCIO_CT1TCMSB ((UINT8) 0x16) /* C/T 1 Time Constant (MS Byte) */
|
||||
#define ZCIO_CT1TCLSB ((UINT8) 0x17) /* C/T 1 Time Constant (LS Byte) */
|
||||
#define ZCIO_CT2TCMSB ((UINT8) 0x18) /* C/T 2 Time Constant (MS Byte) */
|
||||
#define ZCIO_CT2TCLSB ((UINT8) 0x19) /* C/T 2 Time Constant (LS Byte) */
|
||||
#define ZCIO_CT3TCMSB ((UINT8) 0x1a) /* C/T 3 Time Constant (MS Byte) */
|
||||
#define ZCIO_CT3TCLSB ((UINT8) 0x1b) /* C/T 3 Time Constant (LS Byte) */
|
||||
|
||||
#define ZCIO_CT1MS ((UINT8) 0x1c) /* C/T 1 Mode Specification */
|
||||
#define ZCIO_CT2MS ((UINT8) 0x1d) /* C/T 2 Mode Specification */
|
||||
#define ZCIO_CT3MS ((UINT8) 0x1e) /* C/T 3 Mode Specification */
|
||||
|
||||
#define ZCIO_CV ((UINT8) 0x1f) /* Current Vector */
|
||||
|
||||
#define ZCIO_PAMS ((UINT8) 0x20) /* Port A Mode Specification */
|
||||
#define ZCIO_PAHS ((UINT8) 0x21) /* Port A Handshake Specification */
|
||||
#define ZCIO_PADPP ((UINT8) 0x22) /* Port A Data Path Polarity */
|
||||
#define ZCIO_PADD ((UINT8) 0x23) /* Port A Data Direction */
|
||||
#define ZCIO_PASIOC ((UINT8) 0x24) /* Port A Special I/O Control */
|
||||
#define ZCIO_PAPP ((UINT8) 0x25) /* Port A Pattern Polarity */
|
||||
#define ZCIO_PAPT ((UINT8) 0x26) /* Port A Pattern Transition */
|
||||
#define ZCIO_PAPM ((UINT8) 0x27) /* Port A Pattern Mask */
|
||||
|
||||
#define ZCIO_PBMS ((UINT8) 0x28) /* Port B Mode Specification */
|
||||
#define ZCIO_PBHS ((UINT8) 0x29) /* Port B Handshake Specification */
|
||||
#define ZCIO_PBDPP ((UINT8) 0x2a) /* Port B Data Path Polarity */
|
||||
#define ZCIO_PBDD ((UINT8) 0x2b) /* Port B Data Direction */
|
||||
#define ZCIO_PBSIOC ((UINT8) 0x2c) /* Port B Special I/O Control */
|
||||
#define ZCIO_PBPP ((UINT8) 0x2d) /* Port B Pattern Polarity */
|
||||
#define ZCIO_PBPT ((UINT8) 0x2e) /* Port B Pattern Transition */
|
||||
#define ZCIO_PBPM ((UINT8) 0x2f) /* Port B Pattern Mask */
|
||||
|
||||
|
||||
/* If a particular CPU board uses Zilog 8036 counter/timer/parallel I/O chip,
|
||||
* Z8036 should be defined in {target}/sysLib.h. */
|
||||
|
||||
#ifdef Z8036
|
||||
|
||||
#define Z8036_MIC(base) ((char *) ((base) + ZCIO_MIC))
|
||||
#define Z8036_MCC(base) ((char *) ((base) + ZCIO_MCC))
|
||||
#define Z8036_PAIV(base) ((char *) ((base) + ZCIO_PAIV))
|
||||
#define Z8036_PBIV(base) ((char *) ((base) + ZCIO_PBIV))
|
||||
#define Z8036_CTIV(base) ((char *) ((base) + ZCIO_CTIV))
|
||||
#define Z8036_PCDPP(base) ((char *) ((base) + ZCIO_PCDPP))
|
||||
#define Z8036_PCDD(base) ((char *) ((base) + ZCIO_PCDD))
|
||||
#define Z8036_PCSIOC(base) ((char *) ((base) + ZCIO_PCSIOC))
|
||||
#define Z8036_PACS(base) ((char *) ((base) + ZCIO_PACS))
|
||||
#define Z8036_PBCS(base) ((char *) ((base) + ZCIO_PBCS))
|
||||
#define Z8036_CT1CS(base) ((char *) ((base) + ZCIO_CT1CS))
|
||||
#define Z8036_CT2CS(base) ((char *) ((base) + ZCIO_CT2CS))
|
||||
#define Z8036_CT3CS(base) ((char *) ((base) + ZCIO_CT3CS))
|
||||
#define Z8036_PAD(base) ((char *) ((base) + ZCIO_PAD))
|
||||
#define Z8036_PBD(base) ((char *) ((base) + ZCIO_PBD))
|
||||
#define Z8036_PCD(base) ((char *) ((base) + ZCIO_PCD))
|
||||
#define Z8036_CT1CCMSB(base) ((char *) ((base) + ZCIO_CT1CCMSB))
|
||||
#define Z8036_CT1CCLSB(base) ((char *) ((base) + ZCIO_CT1CCLSB))
|
||||
#define Z8036_CT2CCMSB(base) ((char *) ((base) + ZCIO_CT2CCMSB))
|
||||
#define Z8036_CT2CCLSB(base) ((char *) ((base) + ZCIO_CT2CCLSB))
|
||||
#define Z8036_CT3CCMSB(base) ((char *) ((base) + ZCIO_CT3CCMSB))
|
||||
#define Z8036_CT3CCLSB(base) ((char *) ((base) + ZCIO_CT3CCLSB))
|
||||
#define Z8036_CT1TCMSB(base) ((char *) ((base) + ZCIO_CT1TCMSB))
|
||||
#define Z8036_CT1TCLSB(base) ((char *) ((base) + ZCIO_CT1TCLSB))
|
||||
#define Z8036_CT2TCMSB(base) ((char *) ((base) + ZCIO_CT2TCMSB))
|
||||
#define Z8036_CT2TCLSB(base) ((char *) ((base) + ZCIO_CT2TCLSB))
|
||||
#define Z8036_CT3TCMSB(base) ((char *) ((base) + ZCIO_CT3TCMSB))
|
||||
#define Z8036_CT3TCLSB(base) ((char *) ((base) + ZCIO_CT3TCLSB))
|
||||
#define Z8036_CT1MS(base) ((char *) ((base) + ZCIO_CT1MS))
|
||||
#define Z8036_CT2MS(base) ((char *) ((base) + ZCIO_CT2MS))
|
||||
#define Z8036_CT3MS(base) ((char *) ((base) + ZCIO_CT3MS))
|
||||
#define Z8036_CV(base) ((char *) ((base) + ZCIO_CV))
|
||||
#define Z8036_PAMS(base) ((char *) ((base) + ZCIO_PAMS))
|
||||
#define Z8036_PAHS(base) ((char *) ((base) + ZCIO_PAHS))
|
||||
#define Z8036_PADPP(base) ((char *) ((base) + ZCIO_PADPP))
|
||||
#define Z8036_PADD(base) ((char *) ((base) + ZCIO_PADD))
|
||||
#define Z8036_PASIOC(base) ((char *) ((base) + ZCIO_PASIOC))
|
||||
#define Z8036_PAPP(base) ((char *) ((base) + ZCIO_PAPP))
|
||||
#define Z8036_PAPT(base) ((char *) ((base) + ZCIO_PAPT))
|
||||
#define Z8036_PAPM(base) ((char *) ((base) + ZCIO_PAPM))
|
||||
#define Z8036_PBMS(base) ((char *) ((base) + ZCIO_PBMS))
|
||||
#define Z8036_PBHS(base) ((char *) ((base) + ZCIO_PBHS))
|
||||
#define Z8036_PBDPP(base) ((char *) ((base) + ZCIO_PBDPP))
|
||||
#define Z8036_PBDD(base) ((char *) ((base) + ZCIO_PBDD))
|
||||
#define Z8036_PBSIOC(base) ((char *) ((base) + ZCIO_PBSIOC))
|
||||
#define Z8036_PBPP(base) ((char *) ((base) + ZCIO_PBPP))
|
||||
#define Z8036_PBPT(base) ((char *) ((base) + ZCIO_PBPT))
|
||||
#define Z8036_PBPM(base) ((char *) ((base) + ZCIO_PBPM))
|
||||
|
||||
#endif /* Z8036 */
|
||||
|
||||
|
||||
/* Counter/Timer Mode Specification register values (C/T 1, 2 and 3) */
|
||||
|
||||
#define ZCIO_CTMS_DCS_PO ((UINT8) ZERO) /* Pulse Output */
|
||||
#define ZCIO_CTMS_DCS_OSO ((UINT8) 0x01) /* One-Shot Output */
|
||||
#define ZCIO_CTMS_DCS_SWO ((UINT8) 0x02) /* Square-Wave Output */
|
||||
#define ZCIO_CTMS_DCS ((UINT8) 0x03) /* output Duty Cycle Selects */
|
||||
#define ZCIO_CTMS_REB ((UINT8) 0x04) /* Retrigger Enable Bit */
|
||||
#define ZCIO_CTMS_EGE ((UINT8) 0x08) /* External Gate Enable */
|
||||
#define ZCIO_CTMS_ETE ((UINT8) 0x10) /* External Trigger Enable */
|
||||
#define ZCIO_CTMS_ECE ((UINT8) 0x20) /* External Count Enable */
|
||||
#define ZCIO_CTMS_EOE ((UINT8) 0x40) /* External Output Enable */
|
||||
#define ZCIO_CTMS_CSC ((UINT8) 0x80) /* Continuous Single Cycle */
|
||||
|
||||
|
||||
/* Master Configuration Control register values */
|
||||
|
||||
#define ZCIO_MCC_PLC_IND ((UINT8) ZERO) /* port A and B INDependent */
|
||||
#define ZCIO_MCC_LC_IND ((UINT8) ZERO) /* counter/timers INDependent */
|
||||
#define ZCIO_MCC_LC_GATE ((UINT8) 0x01) /* ct1 output GATEs ct2 */
|
||||
#define ZCIO_MCC_LC_TRIG ((UINT8) 0x02) /* ct1 output TRIGgers ct2 */
|
||||
#define ZCIO_MCC_LC_CNT ((UINT8) 0x03) /* ct1 output is ct2 CouNT input */
|
||||
#define ZCIO_MCC_LC ((UINT8) 0x03) /* counter/timer Link Controls */
|
||||
#define ZCIO_MCC_PAE ((UINT8) 0x04) /* Port A Enable */
|
||||
#define ZCIO_MCC_PLC ((UINT8) 0x08) /* Port Link Control */
|
||||
#define ZCIO_MCC_PLC_LNK ((UINT8) 0x08) /* port A and B are LiNKed */
|
||||
#define ZCIO_MCC_CT3PCE ((UINT8) 0x10) /* C/T 3 and Port C Enable */
|
||||
#define ZCIO_MCC_CT2E ((UINT8) 0x20) /* Counter/Timer 2 Enable */
|
||||
#define ZCIO_MCC_CT1E ((UINT8) 0x40) /* Counter/Timer 1 Enable */
|
||||
#define ZCIO_MCC_PBE ((UINT8) 0x80) /* Port B Enable */
|
||||
|
||||
|
||||
/* Master Interrupt Control register values */
|
||||
|
||||
#define ZCIO_MIC_RESET ((UINT8) 0x01) /* device RESET */
|
||||
#define ZCIO_MIC_RJ ((UINT8) 0x02) /* Right Just */
|
||||
#define ZCIO_MIC_CTVIS ((UINT8) 0x04) /* C/T Vector Includes Status */
|
||||
#define ZCIO_MIC_PBVIS ((UINT8) 0x08) /* Port B Vector Includes Status */
|
||||
#define ZCIO_MIC_PAVIS ((UINT8) 0x10) /* Port A Vector Includes Status */
|
||||
#define ZCIO_MIC_NV ((UINT8) 0x20) /* No Vector */
|
||||
#define ZCIO_MIC_DLC ((UINT8) 0x40) /* Disable Lower Chain */
|
||||
#define ZCIO_MIC_MIE ((UINT8) 0x80) /* Master Interrupt Enable */
|
||||
|
||||
|
||||
/* Command and Status resigter values (port A and B and C/T 1, 2 and 3) */
|
||||
|
||||
#define ZCIO_CS_NC ((UINT8) ZERO) /* Null Code */
|
||||
#define ZCIO_CS_CIP ((UINT8) 0x01) /* Count In Progress */
|
||||
#define ZCIO_CS_IOE ((UINT8) 0x01) /* Interrupt On Error */
|
||||
#define ZCIO_CS_TCB ((UINT8) 0x02) /* Trigger Command Bit */
|
||||
#define ZCIO_CS_PMF ((UINT8) 0x02) /* Pattern Match Flag */
|
||||
#define ZCIO_CS_IRF ((UINT8) 0x04) /* Input Register Full */
|
||||
#define ZCIO_CS_GCB ((UINT8) 0x04) /* Gate Command Bit */
|
||||
#define ZCIO_CS_RCC ((UINT8) 0x08) /* Read Counter Control */
|
||||
#define ZCIO_CS_ORE ((UINT8) 0x08) /* Output Register Empty */
|
||||
#define ZCIO_CS_ERR ((UINT8) 0x10) /* interrupt ERRor */
|
||||
#define ZCIO_CS_IP ((UINT8) 0x20) /* Interrupt Pending */
|
||||
#define ZCIO_CS_CLIPIUS ((UINT8) 0x20) /* CLear IP and IUS */
|
||||
#define ZCIO_CS_IE ((UINT8) 0x40) /* Interrupt Enable */
|
||||
#define ZCIO_CS_SIUS ((UINT8) 0x40) /* Set Interrupt Under Service */
|
||||
#define ZCIO_CS_CLIUS ((UINT8) 0x60) /* CLear Interrupt Under Service */
|
||||
#define ZCIO_CS_IUS ((UINT8) 0x80) /* Interrupt Under Service */
|
||||
#define ZCIO_CS_SIP ((UINT8) 0x80) /* Set Interrupt Pending */
|
||||
#define ZCIO_CS_CLIP ((UINT8) 0xa0) /* CLear Interrupt Pending */
|
||||
#define ZCIO_CS_SIE ((UINT8) 0xc0) /* Set Interrupt Enable */
|
||||
#define ZCIO_CS_CLIE ((UINT8) 0xe0) /* CLear Interrupt Enable */
|
||||
|
||||
|
||||
/* Data Direction register values (port A, B and C) */
|
||||
#ifndef ZCIO_DD_PORT_A
|
||||
#define ZCIO_DD_PORT_A ((UINT8) ZERO) /* OUTput bit */
|
||||
#endif
|
||||
|
||||
#ifndef ZCIO_DD_PORT_B
|
||||
#define ZCIO_DD_PORT_B ((UINT8) ZERO) /* OUTput bit */
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef ZCIO_DD_PORT_C
|
||||
#define ZCIO_DD_PORT_C ((UINT8) ZERO) /* OUTput bit */
|
||||
#endif
|
||||
|
||||
|
||||
#define ZCIO_DD_IN ((UINT8) 0xff) /* INput bit */
|
||||
|
||||
|
||||
/* Data Path Polarity register values (port A, B and C) */
|
||||
|
||||
#define ZCIO_DPP_NONINV ((UINT8) ZERO) /* NON-INVerting */
|
||||
#define ZCIO_DPP_INVERT ((UINT8) 0xff) /* INVerting */
|
||||
|
||||
|
||||
/* Port Handshake Specification register values (port A and B) */
|
||||
|
||||
#define ZCIO_PHS_RWS_RWD ((UINT8) ZERO) /* Request/Wait Disabled */
|
||||
#define ZCIO_PHS_DTS_2 ((UINT8) ZERO) /* 2 PCLK cycles */
|
||||
#define ZCIO_PHS_HTS_IH ((UINT8) ZERO) /* Interlocked Handshake */
|
||||
#define ZCIO_PHS_DTS_4 ((UINT8) 0x01) /* 4 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_6 ((UINT8) 0x02) /* 6 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_8 ((UINT8) 0x03) /* 8 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_10 ((UINT8) 0x04) /* 10 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_12 ((UINT8) 0x05) /* 12 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_14 ((UINT8) 0x06) /* 14 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS ((UINT8) 0x07) /* Deskew Time Specification */
|
||||
#define ZCIO_PHS_DTS_16 ((UINT8) 0x07) /* 16 PCLK cycles */
|
||||
#define ZCIO_PHS_RWS_OW ((UINT8) 0x08) /* Output Wait */
|
||||
#define ZCIO_PHS_RWS_IW ((UINT8) 0x18) /* Input Wait */
|
||||
#define ZCIO_PHS_RWS_SR ((UINT8) 0x20) /* Special Request */
|
||||
#define ZCIO_PHS_RWS_OR ((UINT8) 0x28) /* Output Request */
|
||||
#define ZCIO_PHS_RWS_IR ((UINT8) 0x38) /* Input Request */
|
||||
#define ZCIO_PHS_RWS ((UINT8) 0x38) /* Request/Wait Specification */
|
||||
#define ZCIO_PHS_HTS_SH ((UINT8) 0x40) /* Strobed Handshake */
|
||||
#define ZCIO_PHS_HTS_PH ((UINT8) 0x80) /* Pulsed Handshake */
|
||||
#define ZCIO_PHS_HTS_3WH ((UINT8) 0xc0) /* 3-Wire Handshake */
|
||||
#define ZCIO_PHS_HTS ((UINT8) 0xc0) /* Handshake Type Specification */
|
||||
|
||||
|
||||
/* Interrupt Vector register values (port A and B and C/Ts) */
|
||||
|
||||
#define ZCIO_IV_ERR ((UINT8) ZERO) /* Error */
|
||||
#define ZCIO_IV_CT3 ((UINT8) ZERO) /* Counter/Timer 3 */
|
||||
#define ZCIO_IV_CT2 ((UINT8) 0x02) /* Counter/Timer 2 */
|
||||
#define ZCIO_IV_PMF ((UINT8) 0x02) /* Pattern Match Flag */
|
||||
#define ZCIO_IV_IRF ((UINT8) 0x04) /* Input Register Full */
|
||||
#define ZCIO_IV_CT1 ((UINT8) 0x04) /* Counter/Timer 1 */
|
||||
#define ZCIO_IV_CTE ((UINT8) 0x06) /* Counter/Timer Error */
|
||||
#define ZCIO_IV_ORE ((UINT8) 0x08) /* Output Register Empty */
|
||||
|
||||
|
||||
/* Port Mode Specification register values (port A and B) */
|
||||
|
||||
#define ZCIO_PMS_PTS_BIT ((UINT8) ZERO) /* BIT port */
|
||||
#define ZCIO_PMS_PMS_DPM ((UINT8) ZERO) /* Disable Pattern Match */
|
||||
#define ZCIO_PMS_LPM ((UINT8) 0x01) /* Latch on Pattern Match */
|
||||
#define ZCIO_PMS_DTE ((UINT8) 0x01) /* Deskew Timer Enable */
|
||||
#define ZCIO_PMS_PMS_AND ((UINT8) 0x02) /* "AND" mode */
|
||||
#define ZCIO_PMS_PMS_OR ((UINT8) 0x04) /* "OR" mode */
|
||||
#define ZCIO_PMS_PMS ((UINT8) 0x06) /* Pattern Mode Specification */
|
||||
#define ZCIO_PMS_PMS_PEV ((UINT8) 0x06) /* "Priority Encoded Vector" mode */
|
||||
#define ZCIO_PMS_IMO ((UINT8) 0x08) /* Interrupt on Match Only */
|
||||
#define ZCIO_PMS_SB ((UINT8) 0x10) /* Single Buffered mode */
|
||||
#define ZCIO_PMS_ITB ((UINT8) 0x20) /* Interrupt on Two Bytes */
|
||||
#define ZCIO_PMS_PTS_IN ((UINT8) 0x40) /* INput port */
|
||||
#define ZCIO_PMS_PTS_OUT ((UINT8) 0x80) /* OUTput port */
|
||||
#define ZCIO_PMS_PTS_BI ((UINT8) 0xc0) /* BIdirectal port */
|
||||
#define ZCIO_PMS_PTS ((UINT8) 0xc0) /* Port Type Select */
|
||||
|
||||
|
||||
/* Pattern Mask resigter values (port A and B) */
|
||||
|
||||
#define ZCIO_PM_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
|
||||
#define ZCIO_PM_ANY ((UINT8) ZERO) /* Any Transition (^ or v) */
|
||||
#define ZCIO_PM_ZERO ((UINT8) 0xff) /* Zero (0) */
|
||||
#define ZCIO_PM_ONE ((UINT8) 0xff) /* One (1) */
|
||||
#define ZCIO_PM_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
|
||||
#define ZCIO_PM_1TO0 ((UINT8) 0xff) /* One to Zero Transition (v) */
|
||||
|
||||
/* Pattern Polarity register values (port A and B) */
|
||||
|
||||
#define ZCIO_PP_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
|
||||
#define ZCIO_PP_ANY ((UINT8) ZERO) /* Any Transition (^ or v) */
|
||||
#define ZCIO_PP_ZERO ((UINT8) ZERO) /* Zero (0) */
|
||||
#define ZCIO_PP_1TO0 ((UINT8) ZERO) /* One to Zero Transition (v) */
|
||||
#define ZCIO_PP_ONE ((UINT8) 0xff) /* One (1) */
|
||||
#define ZCIO_PP_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
|
||||
|
||||
/* Pattern Transition register values (port A and B) */
|
||||
|
||||
#define ZCIO_PT_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
|
||||
#define ZCIO_PT_ZERO ((UINT8) ZERO) /* Zero (0) */
|
||||
#define ZCIO_PT_ONE ((UINT8) ZERO) /* One (1) */
|
||||
#define ZCIO_PT_ANY ((UINT8) 0xff) /* Any Transition (^ or v) */
|
||||
#define ZCIO_PT_1TO0 ((UINT8) 0xff) /* One to Zero Transition (v) */
|
||||
#define ZCIO_PT_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
|
||||
|
||||
/* Special I/O Control register values (port A B and C) */
|
||||
|
||||
#define ZCIO_SIO_NORMAL ((UINT8) ZERO) /* NORMAL input or output */
|
||||
#define ZCIO_SIO_ODRAIN ((UINT8) 0xff) /* output with Open DRAIN */
|
||||
#define ZCIO_SIO_1CATCH ((UINT8) 0xff) /* input with 1's CATCHer */
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
IMPORT UINT sysZ8536Init (void);
|
||||
IMPORT void sysCioReset (volatile UINT8 * pCio);
|
||||
IMPORT void sysClkIntCIO (void);
|
||||
|
||||
#else /* __STDC__ */
|
||||
|
||||
IMPORT UINT sysZ8536Init ();
|
||||
IMPORT void sysCioReset ();
|
||||
IMPORT void sysClkIntCIO ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCppcZ8536Timerh */
|
||||
@@ -0,0 +1,109 @@
|
||||
/* quiccTimer.h */
|
||||
|
||||
/* Copyright 1984-2005 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,2mar05,dtr adapted from m8260Timer.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains header information for PowerPC timer routines.
|
||||
*/
|
||||
|
||||
#ifndef __INCquiccTimerh
|
||||
#define __INCquiccTimerh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Real Time Clock Module Registers */
|
||||
|
||||
#define RTCNR 0x00300
|
||||
#define RTLDR 0x00304
|
||||
#define RTPSR 0x00308
|
||||
#define RTCTR 0x0030c
|
||||
#define RTEVR 0x00310
|
||||
#define RTALR 0x00314
|
||||
|
||||
#define QUICC_RTCNR(base) (CAST(VUINT32 *)((base) | RTCNR))
|
||||
#define QUICC_RTLDR(base) (CAST(VUINT32 *)((base) | RTLDR))
|
||||
#define QUICC_RTPSR(base) (CAST(VUINT32 *)((base) | RTPSR))
|
||||
#define QUICC_RTCTR(base) (CAST(VUINT32 *)((base) | RTCTR))
|
||||
#define QUICC_RTEVR(base) (CAST(VUINT32 *)((base) | RTEVR))
|
||||
#define QUICC_RTALR(base) (CAST(VUINT32 *)((base) | RTALR))
|
||||
|
||||
/* Periodic Interval Timer Registers */
|
||||
|
||||
#define PTCNR 0x00400
|
||||
#define PTLDR 0x00404
|
||||
#define PTPSR 0x00408
|
||||
#define PTCTR 0x0040c
|
||||
#define PTEVR 0x00410
|
||||
|
||||
#define QUICC_PTCNR(base) (CAST(VUINT32 *)((base) | PTCNR))
|
||||
#define QUICC_PTLDR(base) (CAST(VUINT32 *)((base) | PTLDR))
|
||||
#define QUICC_PTPSR(base) (CAST(VUINT32 *)((base) | PTPSR))
|
||||
#define QUICC_PTCTR(base) (CAST(VUINT32 *)((base) | PTCTR))
|
||||
#define QUICC_PTEVR(base) (CAST(VUINT32 *)((base) | PTEVR))
|
||||
|
||||
/* Global Timers Module 1 */
|
||||
|
||||
/*
|
||||
Example usage:
|
||||
|
||||
*QUICC_GTCFR1(immrVal, GTM1_MODULE_BASE) = 0 ;
|
||||
or
|
||||
*QUICC_GTCFR1(immrVal, GTM2_MODLUE_BASE) = 0 ;
|
||||
*/
|
||||
|
||||
#define QUICC_GTCFR1(base,mbase) (CAST(VUINT8 *)((base) | (mbase) | 0x00000))
|
||||
#define QUICC_GTCFR2(base,mbase) (CAST(VUINT8 *)((base) | (mbase) | 0x00004))
|
||||
#define QUICC_GTMDR1(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00010))
|
||||
#define QUICC_GTMDR2(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00012))
|
||||
|
||||
/* 16 bit mode */
|
||||
#define QUICC_GTRFR1(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00014))
|
||||
#define QUICC_GTRFR2(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00016))
|
||||
#define QUICC_GTCPR1(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00018))
|
||||
#define QUICC_GTCPR2(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0001a))
|
||||
#define QUICC_GTCNR1(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0001c))
|
||||
#define QUICC_GTCNR2(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0001e))
|
||||
/* 32 bit cascaded mode */
|
||||
#define QUICC_GTRFR1_2(base,mbase) (CAST(VUINT32 *)((base) | (mbase) | 0x00014))
|
||||
#define QUICC_GTCPR1_2(base,mbase) (CAST(VUINT32 *)((base) | (mbase) | 0x00018))
|
||||
#define QUICC_GTCNR1_2(base,mbase) (CAST(VUINT32 *)((base) | (mbase) | 0x0001c))
|
||||
|
||||
#define QUICC_GTMDR3(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00020))
|
||||
#define QUICC_GTMDR4(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00022))
|
||||
|
||||
/* 16 bit mode */
|
||||
#define QUICC_GTRFR3(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00024))
|
||||
#define QUICC_GTRFR4(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00026))
|
||||
#define QUICC_GTCPR3(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00028))
|
||||
#define QUICC_GTCPR4(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0002a))
|
||||
#define QUICC_GTCNR3(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0002c))
|
||||
#define QUICC_GTCNR4(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0002e))
|
||||
/* 32 bit cascaded mode */
|
||||
#define QUICC_GTRFR3_4(base,mbase) (CAST(VUINT32 *)((base) | (mbase) | 0x00024))
|
||||
#define QUICC_GTCPR3_4(base,mbase) (CAST(VUINT32 *)((base) | (mbase) | 0x00028))
|
||||
#define QUICC_GTCNR3_4(base,mbase) (CAST(VUINT32 *)((base) | (mbase) | 0x0002c))
|
||||
|
||||
|
||||
#define QUICC_GTEVR1(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00030))
|
||||
#define QUICC_GTEVR2(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00032))
|
||||
#define QUICC_GTEVR3(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00034))
|
||||
#define QUICC_GTEVR4(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00036))
|
||||
#define QUICC_GTPSR1(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x00038))
|
||||
#define QUICC_GTPSR2(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0003a))
|
||||
#define QUICC_GTPSR3(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0003c))
|
||||
#define QUICC_GTPSR4(base,mbase) (CAST(VUINT16 *)((base) | (mbase) | 0x0003e))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCquiccTimerh */
|
||||
@@ -0,0 +1,72 @@
|
||||
/* timerDev.h - Generic Timer header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1996, 2003, 2009-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,19aug11,dee WIND00278138 - 64-bit timestamp support
|
||||
01h,07oct10,rec change sysOneShotDisable and sysOneShotEnable prototypes
|
||||
01g,17mar09,h_k updated for LP64 support.
|
||||
01f,06nov03,rec add sysOneShotEnable and sysOneShotDisable prototypes
|
||||
01e,27aug03,rec add power management prototypes
|
||||
01d,06aug96,dat merged in timestamp support
|
||||
01c,22sep92,rrr added support for c++
|
||||
01b,07jul92,ccc change name to timerDev.h
|
||||
01a,22jun92,ccc created.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains header information for generic timer routines.
|
||||
*/
|
||||
|
||||
#ifndef __INCtimerDevh
|
||||
#define __INCtimerDevh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* function declarations */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
IMPORT STATUS sysClkConnect (FUNCPTR routine, _Vx_usr_arg_t arg);
|
||||
IMPORT void sysClkDisable (void);
|
||||
IMPORT void sysClkEnable (void);
|
||||
IMPORT int sysClkRateGet (void);
|
||||
IMPORT STATUS sysClkRateSet (int ticksPerSecond);
|
||||
IMPORT STATUS sysAuxClkConnect (FUNCPTR routine, _Vx_usr_arg_t arg);
|
||||
IMPORT void sysAuxClkDisable (void);
|
||||
IMPORT void sysAuxClkEnable (void);
|
||||
IMPORT int sysAuxClkRateGet (void);
|
||||
IMPORT STATUS sysAuxClkRateSet (int ticksPerSecond);
|
||||
IMPORT STATUS sysTimestampConnect (FUNCPTR routine, _Vx_usr_arg_t arg);
|
||||
IMPORT STATUS sysTimestampEnable (void);
|
||||
IMPORT STATUS sysTimestampDisable (void);
|
||||
IMPORT UINT32 sysTimestampFreq (void);
|
||||
IMPORT UINT32 sysTimestampPeriod (void);
|
||||
IMPORT UINT32 sysTimestamp (void);
|
||||
IMPORT UINT32 sysTimestampLock (void);
|
||||
IMPORT UINT64 sysTimestamp64Freq (void);
|
||||
IMPORT UINT64 sysTimestamp64Period (void);
|
||||
IMPORT STATUS sysTimestamp64 (UINT64 * counterVal);
|
||||
IMPORT STATUS sysTimestamp64Lock (UINT64 * counterVal);
|
||||
IMPORT void sysOneShotEnable (UINT32 nTicks);
|
||||
IMPORT UINT32 sysOneShotDisable (void);
|
||||
IMPORT void sysOneShotInit (void);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCtimerDevh */
|
||||
@@ -0,0 +1,18 @@
|
||||
/* timestampDev.h - timestamp device header */
|
||||
|
||||
/* Copyright 1993-2002 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,26apr02,dat Adding cplusplus protection, SPR 75017
|
||||
01b,06aug96,dat timestamp info was merged into timerDev.h
|
||||
01a,17sep93,dzb created.
|
||||
*/
|
||||
|
||||
/*
|
||||
DESCRIPTION
|
||||
This file contains header information for generic timestamp device routines.
|
||||
*/
|
||||
|
||||
#include "drv/timer/timerDev.h" /* everything is in timerDev.h now */
|
||||
@@ -0,0 +1,322 @@
|
||||
/* z8536.h - zilog CIO (counter,timer,parallel i/o chip) */
|
||||
|
||||
/* Copyright 1984-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01g,22sep92,rrr added support for c++
|
||||
01f,26may92,rrr the tree shuffle
|
||||
01e,04oct91,rrr passed through the ansification filter
|
||||
-changed TINY and UTINY to INT8 and UINT8
|
||||
-changed copyright notice
|
||||
01d,05oct90,shl added copyright notice.
|
||||
made #endif ANSI style.
|
||||
01c,10jan90,shl merged with z8036.h.
|
||||
01b,11sep89,dab changed U8 to UINT8.
|
||||
01a,10aug88,rml written
|
||||
*/
|
||||
|
||||
/* Note: in the following, the value '0x00' has been replaced by 'ZERO'.
|
||||
This has been done to provide a way to avoid the 'clr.b' instruction
|
||||
on the 68000/10 cpu. 'ZERO' should be defined to be a memory location
|
||||
which holds the value '0x00', this will cause compilers to generate
|
||||
memory to memory transfers rather than clear instructions. */
|
||||
|
||||
#ifndef __INCz8536h
|
||||
#define __INCz8536h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* internal register addresses */
|
||||
|
||||
#define ZCIO_MIC ((UINT8) ZERO) /* Master Interrupt Control */
|
||||
#define ZCIO_MCC ((UINT8) 0x01) /* Master Configuration Control */
|
||||
#define ZCIO_PAIV ((UINT8) 0x02) /* Port A Interrupt Vector */
|
||||
#define ZCIO_PBIV ((UINT8) 0x03) /* Port B Interrupt Vector */
|
||||
#define ZCIO_CTIV ((UINT8) 0x04) /* Counter/Timer Interrupt Vector */
|
||||
|
||||
#define ZCIO_PCDPP ((UINT8) 0x05) /* Port C Data Path Polarity */
|
||||
#define ZCIO_PCDD ((UINT8) 0x06) /* Port C Data Direction */
|
||||
#define ZCIO_PCSIOC ((UINT8) 0x07) /* Port C Special I/O Control */
|
||||
#define ZCIO_PACS ((UINT8) 0x08) /* Port A Command and Status */
|
||||
#define ZCIO_PBCS ((UINT8) 0x09) /* Port B Command and Status */
|
||||
|
||||
#define ZCIO_CT1CS ((UINT8) 0x0a) /* C/T 1 Command and Status */
|
||||
#define ZCIO_CT2CS ((UINT8) 0x0b) /* C/T 2 Command and Status */
|
||||
#define ZCIO_CT3CS ((UINT8) 0x0c) /* C/T 3 Command and Status */
|
||||
|
||||
#define ZCIO_PAD ((UINT8) 0x0d) /* Port A Data */
|
||||
#define ZCIO_PBD ((UINT8) 0x0e) /* Port B Data */
|
||||
#define ZCIO_PCD ((UINT8) 0x0f) /* Port C Data */
|
||||
|
||||
#define ZCIO_CT1CCMSB ((UINT8) 0x10) /* C/T 1 Current Count (MS Byte) */
|
||||
#define ZCIO_CT1CCLSB ((UINT8) 0x11) /* C/T 1 Current Count (LS Byte) */
|
||||
#define ZCIO_CT2CCMSB ((UINT8) 0x12) /* C/T 2 Current Count (MS Byte) */
|
||||
#define ZCIO_CT2CCLSB ((UINT8) 0x13) /* C/T 2 Current Count (LS Byte) */
|
||||
#define ZCIO_CT3CCMSB ((UINT8) 0x14) /* C/T 3 Current Count (MS Byte) */
|
||||
#define ZCIO_CT3CCLSB ((UINT8) 0x15) /* C/T 3 Current Count (LS Byte) */
|
||||
|
||||
#define ZCIO_CT1TCMSB ((UINT8) 0x16) /* C/T 1 Time Constant (MS Byte) */
|
||||
#define ZCIO_CT1TCLSB ((UINT8) 0x17) /* C/T 1 Time Constant (LS Byte) */
|
||||
#define ZCIO_CT2TCMSB ((UINT8) 0x18) /* C/T 2 Time Constant (MS Byte) */
|
||||
#define ZCIO_CT2TCLSB ((UINT8) 0x19) /* C/T 2 Time Constant (LS Byte) */
|
||||
#define ZCIO_CT3TCMSB ((UINT8) 0x1a) /* C/T 3 Time Constant (MS Byte) */
|
||||
#define ZCIO_CT3TCLSB ((UINT8) 0x1b) /* C/T 3 Time Constant (LS Byte) */
|
||||
|
||||
#define ZCIO_CT1MS ((UINT8) 0x1c) /* C/T 1 Mode Specification */
|
||||
#define ZCIO_CT2MS ((UINT8) 0x1d) /* C/T 2 Mode Specification */
|
||||
#define ZCIO_CT3MS ((UINT8) 0x1e) /* C/T 3 Mode Specification */
|
||||
|
||||
#define ZCIO_CV ((UINT8) 0x1f) /* Current Vector */
|
||||
|
||||
#define ZCIO_PAMS ((UINT8) 0x20) /* Port A Mode Specification */
|
||||
#define ZCIO_PAHS ((UINT8) 0x21) /* Port A Handshake Specification */
|
||||
#define ZCIO_PADPP ((UINT8) 0x22) /* Port A Data Path Polarity */
|
||||
#define ZCIO_PADD ((UINT8) 0x23) /* Port A Data Direction */
|
||||
#define ZCIO_PASIOC ((UINT8) 0x24) /* Port A Special I/O Control */
|
||||
#define ZCIO_PAPP ((UINT8) 0x25) /* Port A Pattern Polarity */
|
||||
#define ZCIO_PAPT ((UINT8) 0x26) /* Port A Pattern Transition */
|
||||
#define ZCIO_PAPM ((UINT8) 0x27) /* Port A Pattern Mask */
|
||||
|
||||
#define ZCIO_PBMS ((UINT8) 0x28) /* Port B Mode Specification */
|
||||
#define ZCIO_PBHS ((UINT8) 0x29) /* Port B Handshake Specification */
|
||||
#define ZCIO_PBDPP ((UINT8) 0x2a) /* Port B Data Path Polarity */
|
||||
#define ZCIO_PBDD ((UINT8) 0x2b) /* Port B Data Direction */
|
||||
#define ZCIO_PBSIOC ((UINT8) 0x2c) /* Port B Special I/O Control */
|
||||
#define ZCIO_PBPP ((UINT8) 0x2d) /* Port B Pattern Polarity */
|
||||
#define ZCIO_PBPT ((UINT8) 0x2e) /* Port B Pattern Transition */
|
||||
#define ZCIO_PBPM ((UINT8) 0x2f) /* Port B Pattern Mask */
|
||||
|
||||
|
||||
/* If a particular CPU board uses Zilog 8036 counter/timer/parallel I/O chip,
|
||||
* Z8036 should be defined in {target}/sysLib.h. */
|
||||
|
||||
#ifdef Z8036
|
||||
|
||||
#define Z8036_MIC(base) ((char *) ((base) + ZCIO_MIC))
|
||||
#define Z8036_MCC(base) ((char *) ((base) + ZCIO_MCC))
|
||||
#define Z8036_PAIV(base) ((char *) ((base) + ZCIO_PAIV))
|
||||
#define Z8036_PBIV(base) ((char *) ((base) + ZCIO_PBIV))
|
||||
#define Z8036_CTIV(base) ((char *) ((base) + ZCIO_CTIV))
|
||||
#define Z8036_PCDPP(base) ((char *) ((base) + ZCIO_PCDPP))
|
||||
#define Z8036_PCDD(base) ((char *) ((base) + ZCIO_PCDD))
|
||||
#define Z8036_PCSIOC(base) ((char *) ((base) + ZCIO_PCSIOC))
|
||||
#define Z8036_PACS(base) ((char *) ((base) + ZCIO_PACS))
|
||||
#define Z8036_PBCS(base) ((char *) ((base) + ZCIO_PBCS))
|
||||
#define Z8036_CT1CS(base) ((char *) ((base) + ZCIO_CT1CS))
|
||||
#define Z8036_CT2CS(base) ((char *) ((base) + ZCIO_CT2CS))
|
||||
#define Z8036_CT3CS(base) ((char *) ((base) + ZCIO_CT3CS))
|
||||
#define Z8036_PAD(base) ((char *) ((base) + ZCIO_PAD))
|
||||
#define Z8036_PBD(base) ((char *) ((base) + ZCIO_PBD))
|
||||
#define Z8036_PCD(base) ((char *) ((base) + ZCIO_PCD))
|
||||
#define Z8036_CT1CCMSB(base) ((char *) ((base) + ZCIO_CT1CCMSB))
|
||||
#define Z8036_CT1CCLSB(base) ((char *) ((base) + ZCIO_CT1CCLSB))
|
||||
#define Z8036_CT2CCMSB(base) ((char *) ((base) + ZCIO_CT2CCMSB))
|
||||
#define Z8036_CT2CCLSB(base) ((char *) ((base) + ZCIO_CT2CCLSB))
|
||||
#define Z8036_CT3CCMSB(base) ((char *) ((base) + ZCIO_CT3CCMSB))
|
||||
#define Z8036_CT3CCLSB(base) ((char *) ((base) + ZCIO_CT3CCLSB))
|
||||
#define Z8036_CT1TCMSB(base) ((char *) ((base) + ZCIO_CT1TCMSB))
|
||||
#define Z8036_CT1TCLSB(base) ((char *) ((base) + ZCIO_CT1TCLSB))
|
||||
#define Z8036_CT2TCMSB(base) ((char *) ((base) + ZCIO_CT2TCMSB))
|
||||
#define Z8036_CT2TCLSB(base) ((char *) ((base) + ZCIO_CT2TCLSB))
|
||||
#define Z8036_CT3TCMSB(base) ((char *) ((base) + ZCIO_CT3TCMSB))
|
||||
#define Z8036_CT3TCLSB(base) ((char *) ((base) + ZCIO_CT3TCLSB))
|
||||
#define Z8036_CT1MS(base) ((char *) ((base) + ZCIO_CT1MS))
|
||||
#define Z8036_CT2MS(base) ((char *) ((base) + ZCIO_CT2MS))
|
||||
#define Z8036_CT3MS(base) ((char *) ((base) + ZCIO_CT3MS))
|
||||
#define Z8036_CV(base) ((char *) ((base) + ZCIO_CV))
|
||||
#define Z8036_PAMS(base) ((char *) ((base) + ZCIO_PAMS))
|
||||
#define Z8036_PAHS(base) ((char *) ((base) + ZCIO_PAHS))
|
||||
#define Z8036_PADPP(base) ((char *) ((base) + ZCIO_PADPP))
|
||||
#define Z8036_PADD(base) ((char *) ((base) + ZCIO_PADD))
|
||||
#define Z8036_PASIOC(base) ((char *) ((base) + ZCIO_PASIOC))
|
||||
#define Z8036_PAPP(base) ((char *) ((base) + ZCIO_PAPP))
|
||||
#define Z8036_PAPT(base) ((char *) ((base) + ZCIO_PAPT))
|
||||
#define Z8036_PAPM(base) ((char *) ((base) + ZCIO_PAPM))
|
||||
#define Z8036_PBMS(base) ((char *) ((base) + ZCIO_PBMS))
|
||||
#define Z8036_PBHS(base) ((char *) ((base) + ZCIO_PBHS))
|
||||
#define Z8036_PBDPP(base) ((char *) ((base) + ZCIO_PBDPP))
|
||||
#define Z8036_PBDD(base) ((char *) ((base) + ZCIO_PBDD))
|
||||
#define Z8036_PBSIOC(base) ((char *) ((base) + ZCIO_PBSIOC))
|
||||
#define Z8036_PBPP(base) ((char *) ((base) + ZCIO_PBPP))
|
||||
#define Z8036_PBPT(base) ((char *) ((base) + ZCIO_PBPT))
|
||||
#define Z8036_PBPM(base) ((char *) ((base) + ZCIO_PBPM))
|
||||
|
||||
#endif /* Z8036 */
|
||||
|
||||
|
||||
/* Counter/Timer Mode Specification register values (C/T 1, 2 and 3) */
|
||||
|
||||
#define ZCIO_CTMS_DCS_PO ((UINT8) ZERO) /* Pulse Output */
|
||||
#define ZCIO_CTMS_DCS_OSO ((UINT8) 0x01) /* One-Shot Output */
|
||||
#define ZCIO_CTMS_DCS_SWO ((UINT8) 0x02) /* Square-Wave Output */
|
||||
#define ZCIO_CTMS_DCS ((UINT8) 0x03) /* output Duty Cycle Selects */
|
||||
#define ZCIO_CTMS_REB ((UINT8) 0x04) /* Retrigger Enable Bit */
|
||||
#define ZCIO_CTMS_EGE ((UINT8) 0x08) /* External Gate Enable */
|
||||
#define ZCIO_CTMS_ETE ((UINT8) 0x10) /* External Trigger Enable */
|
||||
#define ZCIO_CTMS_ECE ((UINT8) 0x20) /* External Count Enable */
|
||||
#define ZCIO_CTMS_EOE ((UINT8) 0x40) /* External Output Enable */
|
||||
#define ZCIO_CTMS_CSC ((UINT8) 0x80) /* Continuous Single Cycle */
|
||||
|
||||
|
||||
/* Master Configuration Control register values */
|
||||
|
||||
#define ZCIO_MCC_PLC_IND ((UINT8) ZERO) /* port A and B INDependent */
|
||||
#define ZCIO_MCC_LC_IND ((UINT8) ZERO) /* counter/timers INDependent */
|
||||
#define ZCIO_MCC_LC_GATE ((UINT8) 0x01) /* ct1 output GATEs ct2 */
|
||||
#define ZCIO_MCC_LC_TRIG ((UINT8) 0x02) /* ct1 output TRIGgers ct2 */
|
||||
#define ZCIO_MCC_LC_CNT ((UINT8) 0x03) /* ct1 output is ct2 CouNT input */
|
||||
#define ZCIO_MCC_LC ((UINT8) 0x03) /* counter/timer Link Controls */
|
||||
#define ZCIO_MCC_PAE ((UINT8) 0x04) /* Port A Enable */
|
||||
#define ZCIO_MCC_PLC ((UINT8) 0x08) /* Port Link Control */
|
||||
#define ZCIO_MCC_PLC_LNK ((UINT8) 0x08) /* port A and B are LiNKed */
|
||||
#define ZCIO_MCC_CT3PCE ((UINT8) 0x10) /* C/T 3 and Port C Enable */
|
||||
#define ZCIO_MCC_CT2E ((UINT8) 0x20) /* Counter/Timer 2 Enable */
|
||||
#define ZCIO_MCC_CT1E ((UINT8) 0x40) /* Counter/Timer 1 Enable */
|
||||
#define ZCIO_MCC_PBE ((UINT8) 0x80) /* Port B Enable */
|
||||
|
||||
|
||||
/* Master Interrupt Control register values */
|
||||
|
||||
#define ZCIO_MIC_RESET ((UINT8) 0x01) /* device RESET */
|
||||
#define ZCIO_MIC_RJ ((UINT8) 0x02) /* Right Just */
|
||||
#define ZCIO_MIC_CTVIS ((UINT8) 0x04) /* C/T Vector Includes Status */
|
||||
#define ZCIO_MIC_PBVIS ((UINT8) 0x08) /* Port B Vector Includes Status */
|
||||
#define ZCIO_MIC_PAVIS ((UINT8) 0x10) /* Port A Vector Includes Status */
|
||||
#define ZCIO_MIC_NV ((UINT8) 0x20) /* No Vector */
|
||||
#define ZCIO_MIC_DLC ((UINT8) 0x40) /* Disable Lower Chain */
|
||||
#define ZCIO_MIC_MIE ((UINT8) 0x80) /* Master Interrupt Enable */
|
||||
|
||||
|
||||
/* Command and Status resigter values (port A and B and C/T 1, 2 and 3) */
|
||||
|
||||
#define ZCIO_CS_NC ((UINT8) ZERO) /* Null Code */
|
||||
#define ZCIO_CS_CIP ((UINT8) 0x01) /* Count In Progress */
|
||||
#define ZCIO_CS_IOE ((UINT8) 0x01) /* Interrupt On Error */
|
||||
#define ZCIO_CS_TCB ((UINT8) 0x02) /* Trigger Command Bit */
|
||||
#define ZCIO_CS_PMF ((UINT8) 0x02) /* Pattern Match Flag */
|
||||
#define ZCIO_CS_IRF ((UINT8) 0x04) /* Input Register Full */
|
||||
#define ZCIO_CS_GCB ((UINT8) 0x04) /* Gate Command Bit */
|
||||
#define ZCIO_CS_RCC ((UINT8) 0x08) /* Read Counter Control */
|
||||
#define ZCIO_CS_ORE ((UINT8) 0x08) /* Output Register Empty */
|
||||
#define ZCIO_CS_ERR ((UINT8) 0x10) /* interrupt ERRor */
|
||||
#define ZCIO_CS_IP ((UINT8) 0x20) /* Interrupt Pending */
|
||||
#define ZCIO_CS_CLIPIUS ((UINT8) 0x20) /* CLear IP and IUS */
|
||||
#define ZCIO_CS_IE ((UINT8) 0x40) /* Interrupt Enable */
|
||||
#define ZCIO_CS_SIUS ((UINT8) 0x40) /* Set Interrupt Under Service */
|
||||
#define ZCIO_CS_CLIUS ((UINT8) 0x60) /* CLear Interrupt Under Service */
|
||||
#define ZCIO_CS_IUS ((UINT8) 0x80) /* Interrupt Under Service */
|
||||
#define ZCIO_CS_SIP ((UINT8) 0x80) /* Set Interrupt Pending */
|
||||
#define ZCIO_CS_CLIP ((UINT8) 0xa0) /* CLear Interrupt Pending */
|
||||
#define ZCIO_CS_SIE ((UINT8) 0xc0) /* Set Interrupt Enable */
|
||||
#define ZCIO_CS_CLIE ((UINT8) 0xe0) /* CLear Interrupt Enable */
|
||||
|
||||
|
||||
/* Data Direction register values (port A, B and C) */
|
||||
|
||||
#define ZCIO_DD_OUT ((UINT8) ZERO) /* OUTput bit */
|
||||
#define ZCIO_DD_IN ((UINT8) 0xff) /* INput bit */
|
||||
|
||||
|
||||
/* Data Path Polarity register values (port A, B and C) */
|
||||
|
||||
#define ZCIO_DPP_NONINV ((UINT8) ZERO) /* NON-INVerting */
|
||||
#define ZCIO_DPP_INVERT ((UINT8) 0xff) /* INVerting */
|
||||
|
||||
|
||||
/* Port Handshake Specification register values (port A and B) */
|
||||
|
||||
#define ZCIO_PHS_RWS_RWD ((UINT8) ZERO) /* Request/Wait Disabled */
|
||||
#define ZCIO_PHS_DTS_2 ((UINT8) ZERO) /* 2 PCLK cycles */
|
||||
#define ZCIO_PHS_HTS_IH ((UINT8) ZERO) /* Interlocked Handshake */
|
||||
#define ZCIO_PHS_DTS_4 ((UINT8) 0x01) /* 4 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_6 ((UINT8) 0x02) /* 6 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_8 ((UINT8) 0x03) /* 8 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_10 ((UINT8) 0x04) /* 10 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_12 ((UINT8) 0x05) /* 12 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS_14 ((UINT8) 0x06) /* 14 PCLK cycles */
|
||||
#define ZCIO_PHS_DTS ((UINT8) 0x07) /* Deskew Time Specification */
|
||||
#define ZCIO_PHS_DTS_16 ((UINT8) 0x07) /* 16 PCLK cycles */
|
||||
#define ZCIO_PHS_RWS_OW ((UINT8) 0x08) /* Output Wait */
|
||||
#define ZCIO_PHS_RWS_IW ((UINT8) 0x18) /* Input Wait */
|
||||
#define ZCIO_PHS_RWS_SR ((UINT8) 0x20) /* Special Request */
|
||||
#define ZCIO_PHS_RWS_OR ((UINT8) 0x28) /* Output Request */
|
||||
#define ZCIO_PHS_RWS_IR ((UINT8) 0x38) /* Input Request */
|
||||
#define ZCIO_PHS_RWS ((UINT8) 0x38) /* Request/Wait Specification */
|
||||
#define ZCIO_PHS_HTS_SH ((UINT8) 0x40) /* Strobed Handshake */
|
||||
#define ZCIO_PHS_HTS_PH ((UINT8) 0x80) /* Pulsed Handshake */
|
||||
#define ZCIO_PHS_HTS_3WH ((UINT8) 0xc0) /* 3-Wire Handshake */
|
||||
#define ZCIO_PHS_HTS ((UINT8) 0xc0) /* Handshake Type Specification */
|
||||
|
||||
|
||||
/* Interrupt Vector register values (port A and B and C/Ts) */
|
||||
|
||||
#define ZCIO_IV_ERR ((UINT8) ZERO) /* Error */
|
||||
#define ZCIO_IV_CT3 ((UINT8) ZERO) /* Counter/Timer 3 */
|
||||
#define ZCIO_IV_CT2 ((UINT8) 0x02) /* Counter/Timer 2 */
|
||||
#define ZCIO_IV_PMF ((UINT8) 0x02) /* Pattern Match Flag */
|
||||
#define ZCIO_IV_IRF ((UINT8) 0x04) /* Input Register Full */
|
||||
#define ZCIO_IV_CT1 ((UINT8) 0x04) /* Counter/Timer 1 */
|
||||
#define ZCIO_IV_CTE ((UINT8) 0x06) /* Counter/Timer Error */
|
||||
#define ZCIO_IV_ORE ((UINT8) 0x08) /* Output Register Empty */
|
||||
|
||||
|
||||
/* Port Mode Specification register values (port A and B) */
|
||||
|
||||
#define ZCIO_PMS_PTS_BIT ((UINT8) ZERO) /* BIT port */
|
||||
#define ZCIO_PMS_PMS_DPM ((UINT8) ZERO) /* Disable Pattern Match */
|
||||
#define ZCIO_PMS_LPM ((UINT8) 0x01) /* Latch on Pattern Match */
|
||||
#define ZCIO_PMS_DTE ((UINT8) 0x01) /* Deskew Timer Enable */
|
||||
#define ZCIO_PMS_PMS_AND ((UINT8) 0x02) /* "AND" mode */
|
||||
#define ZCIO_PMS_PMS_OR ((UINT8) 0x04) /* "OR" mode */
|
||||
#define ZCIO_PMS_PMS ((UINT8) 0x06) /* Pattern Mode Specification */
|
||||
#define ZCIO_PMS_PMS_PEV ((UINT8) 0x06) /* "Priority Encoded Vector" mode */
|
||||
#define ZCIO_PMS_IMO ((UINT8) 0x08) /* Interrupt on Match Only */
|
||||
#define ZCIO_PMS_SB ((UINT8) 0x10) /* Single Buffered mode */
|
||||
#define ZCIO_PMS_ITB ((UINT8) 0x20) /* Interrupt on Two Bytes */
|
||||
#define ZCIO_PMS_PTS_IN ((UINT8) 0x40) /* INput port */
|
||||
#define ZCIO_PMS_PTS_OUT ((UINT8) 0x80) /* OUTput port */
|
||||
#define ZCIO_PMS_PTS_BI ((UINT8) 0xc0) /* BIdirectal port */
|
||||
#define ZCIO_PMS_PTS ((UINT8) 0xc0) /* Port Type Select */
|
||||
|
||||
|
||||
/* Pattern Mask resigter values (port A and B) */
|
||||
|
||||
#define ZCIO_PM_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
|
||||
#define ZCIO_PM_ANY ((UINT8) ZERO) /* Any Transition (^ or v) */
|
||||
#define ZCIO_PM_ZERO ((UINT8) 0xff) /* Zero (0) */
|
||||
#define ZCIO_PM_ONE ((UINT8) 0xff) /* One (1) */
|
||||
#define ZCIO_PM_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
|
||||
#define ZCIO_PM_1TO0 ((UINT8) 0xff) /* One to Zero Transition (v) */
|
||||
|
||||
/* Pattern Polarity register values (port A and B) */
|
||||
|
||||
#define ZCIO_PP_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
|
||||
#define ZCIO_PP_ANY ((UINT8) ZERO) /* Any Transition (^ or v) */
|
||||
#define ZCIO_PP_ZERO ((UINT8) ZERO) /* Zero (0) */
|
||||
#define ZCIO_PP_1TO0 ((UINT8) ZERO) /* One to Zero Transition (v) */
|
||||
#define ZCIO_PP_ONE ((UINT8) 0xff) /* One (1) */
|
||||
#define ZCIO_PP_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
|
||||
|
||||
/* Pattern Transition register values (port A and B) */
|
||||
|
||||
#define ZCIO_PT_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
|
||||
#define ZCIO_PT_ZERO ((UINT8) ZERO) /* Zero (0) */
|
||||
#define ZCIO_PT_ONE ((UINT8) ZERO) /* One (1) */
|
||||
#define ZCIO_PT_ANY ((UINT8) 0xff) /* Any Transition (^ or v) */
|
||||
#define ZCIO_PT_1TO0 ((UINT8) 0xff) /* One to Zero Transition (v) */
|
||||
#define ZCIO_PT_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
|
||||
|
||||
/* Special I/O Control register values (port A B and C) */
|
||||
|
||||
#define ZCIO_SIO_NORMAL ((UINT8) ZERO) /* NORMAL input or output */
|
||||
#define ZCIO_SIO_ODRAIN ((UINT8) 0xff) /* output with Open DRAIN */
|
||||
#define ZCIO_SIO_1CATCH ((UINT8) 0xff) /* input with 1's CATCHer */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCz8536h */
|
||||
Reference in New Issue
Block a user