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neelimap
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/* shSciSio.h - header file for Renesas SH on-chip SCI serial driver */
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/*
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* Copyright (c) 1996-2006, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01t,29apr10,pad Moved extern C statement after include statements.
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01s,18nov03,h_k added SCI_SCR_CKE and SCI_SMR_CKS definitions.
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01r,10nov03,h_k corrected the comment for the BRR formula.
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01q,06nov03,h_k added SH7705 support. (SPR #91873)
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01p,15feb01,hk add #ifdef SCI_TYPE_SH7604 to adjust baud rate for SH7604.
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01o,09nov00,csi modification to optimize SMR and BRR define
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01n,30aug00,zl added 30MHz PCLK support for SH7600
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01m,20aug00,hk merged SH7040 to SH7600.
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01l,04aug00,rsh Add frequency defines for sh7729
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01k,31may00,frf SH7751 for T2
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01j,29dec98,hk merged for SH7750,SH7729,SH7700,SH7600,SH7410,SH7040,SH7000.
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01i,10aug98,jmb add 57600 baud for Manta-DSP.
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01h,09jul98,jmb add support for Manta-SH3 frequencies.
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01g,01jun98,jmb added "options" to support SIO_HW_OPTS_GET.
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01f,19may98,jmc added support for SH-DSP and SH3-DSP.
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01g,18sep98,hk fixed SH7750 support for 33.33MHz PCLK.
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01f,02jul98,st added SH7750 support.
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01e,14jan98,jmc added baud rate table entries for 20/10/5MHz.
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01d,25apr97,hk changed SH704X to SH7040.
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01c,21mar97,hk added SCI_BAUD typedef. enhanced defs for smr and brr.
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01b,10mar97,hk renamed this header as shSciSio.h from shSio.h. changed
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SH_CHAN to SCI_CHAN. deleted SH_DUSART. changed function
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prototype names to shSciXyz. changed definition layout.
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01a,16dec96,kn derived from templateSio.h
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*/
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#ifndef __INCshSciSioh
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#define __INCshSciSioh
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#include <sioLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* device channel structure */
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typedef struct
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{
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/* always goes first */
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SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
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/* callbacks */
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STATUS (*getTxChar) ();
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STATUS (*putRcvChar) ();
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void * getTxArg;
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void * putRcvArg;
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/* register addresses */
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volatile UINT8 * smr; /* serial mode register */
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volatile UINT8 * brr; /* bit rate register */
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volatile UINT8 * scr; /* serial control register */
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volatile UINT8 * tdr; /* transmit data register */
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volatile UINT8 * ssr; /* serial status register */
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volatile UINT8 * rdr; /* receive data register */
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int mode; /* current mode (interrupt or poll) */
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int baud; /* baud rate */
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UINT options; /* data format */
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} SCI_CHAN;
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/* entry structure for baud-rate table */
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typedef struct
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{
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int rate; /* baud-rate to be set */
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UINT8 cksVal; /* clock select bits for smr */
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UINT8 brrVal; /* value to set in brr */
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} SCI_BAUD;
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/* bit values for smr (serial mode register) */
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#define SCI_SMR_ASYNC 0x00 /* async mode */
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#define SCI_SMR_SYNC 0x80 /* synchronous mode */
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#define SCI_SMR_8_BITS 0x00 /* 8 bits data */
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#define SCI_SMR_7_BITS 0x40 /* 7 bits data */
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#define SCI_SMR_PAR_DIS 0x00 /* parity disable */
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#define SCI_SMR_PAR_EN 0x20 /* parity enable */
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#define SCI_SMR_PAR_EVEN 0x00 /* even parity */
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#define SCI_SMR_PAR_ODD 0x10 /* odd parity */
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#define SCI_SMR_1_STOP 0x00 /* 1 stop bit */
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#define SCI_SMR_2_STOP 0x08 /* 2 stop bit */
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#define SCI_SMR_MP_DIS 0x00 /* multiprocessor format disable */
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#define SCI_SMR_MP_EN 0x04 /* multiprocessor format enable */
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#define SCI_SMR_CKS 0x03 /* clock select bits */
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#define SCI_SMR_CKS_MASK 0xfc /* mask for clock select bits */
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#ifdef SYS_PCLK_FREQ
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# define SCI_FREQ SYS_PCLK_FREQ
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#else
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# ifdef SCI_TYPE_SH7604
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# define SCI_FREQ (SYS_CPU_FREQ / 4)
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# else /* SH704x, SH705x */
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# define SCI_FREQ SYS_CPU_FREQ
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# endif
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#endif
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/*
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* To calculate BRR value, the following formula used.
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* BRR = (FREQ / (FORM_VAL * 2^(2n-1)) * BaudRate)) - 1
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*
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* In the following macros are used
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* SMR_VALUE is n
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* CLK_DIVIDE(y) 4^n
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*
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* In the BRR_VALUE macro the extra mutiplication, division and addition
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* is used to get correct rounding.
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*/
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#ifndef BRR_FORM_VAL
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#define BRR_FORM_VAL 64
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#endif
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#define SMR_VALUE(x) (((SCI_FREQ/(BRR_FORM_VAL*32*(x))) >= 64) ? 3 : \
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((SCI_FREQ/(BRR_FORM_VAL*32*(x))) >= 16) ? 2 : \
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((SCI_FREQ/(BRR_FORM_VAL*32*(x))) >= 4) ? 1 : 0)
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#define CLK_DIVIDE(y) (((SCI_FREQ/(BRR_FORM_VAL*32*(y))) >= 64) ? 64 : \
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((SCI_FREQ/(BRR_FORM_VAL*32*(y))) >= 16) ? 16 : \
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((SCI_FREQ/(BRR_FORM_VAL*32*(y))) >= 4) ? 4 : 1)
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#define BRR_FORMULA(s) (((20*SCI_FREQ)/ \
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(BRR_FORM_VAL*CLK_DIVIDE(s)*(s))-5)/10)
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#define BRR_VALUE(z) ((BRR_FORMULA(z) > 255) ? 0 : BRR_FORMULA(z))
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#define SCI_SMR_CKS_50 SMR_VALUE(50)
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#define SCI_SMR_CKS_75 SMR_VALUE(75)
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#define SCI_SMR_CKS_110 SMR_VALUE(110)
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#define SCI_SMR_CKS_134 SMR_VALUE(134)
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#define SCI_SMR_CKS_150 SMR_VALUE(150)
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#define SCI_SMR_CKS_200 SMR_VALUE(200)
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#define SCI_SMR_CKS_300 SMR_VALUE(300)
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#define SCI_SMR_CKS_600 SMR_VALUE(600)
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#define SCI_SMR_CKS_1200 SMR_VALUE(1200)
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#define SCI_SMR_CKS_1800 SMR_VALUE(1800)
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#define SCI_SMR_CKS_2400 SMR_VALUE(2400)
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#define SCI_SMR_CKS_3600 SMR_VALUE(3600)
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#define SCI_SMR_CKS_4800 SMR_VALUE(4800)
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#define SCI_SMR_CKS_7200 SMR_VALUE(7200)
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#define SCI_SMR_CKS_9600 SMR_VALUE(9600)
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#define SCI_SMR_CKS_19200 SMR_VALUE(19200)
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#define SCI_SMR_CKS_31250 SMR_VALUE(31250)
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#define SCI_SMR_CKS_38400 SMR_VALUE(38400)
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#define SCI_SMR_CKS_57600 SMR_VALUE(57600)
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#define SCI_SMR_CKS_115200 SMR_VALUE(115200)
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#define SCI_SMR_CKS_500000 SMR_VALUE(500000)
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/* bit values for brr (bit rate register) */
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#define SCI_BRR_50 BRR_VALUE(50)
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#define SCI_BRR_75 BRR_VALUE(75)
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#define SCI_BRR_110 BRR_VALUE(110)
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#define SCI_BRR_134 BRR_VALUE(134)
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#define SCI_BRR_150 BRR_VALUE(150)
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#define SCI_BRR_200 BRR_VALUE(200)
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#define SCI_BRR_300 BRR_VALUE(300)
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#define SCI_BRR_600 BRR_VALUE(600)
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#define SCI_BRR_1200 BRR_VALUE(1200)
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#define SCI_BRR_1800 BRR_VALUE(1800)
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#define SCI_BRR_2400 BRR_VALUE(2400)
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#define SCI_BRR_3600 BRR_VALUE(3600)
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#define SCI_BRR_4800 BRR_VALUE(4800)
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#define SCI_BRR_7200 BRR_VALUE(9600)
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#define SCI_BRR_9600 BRR_VALUE(9600)
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#define SCI_BRR_19200 BRR_VALUE(19200)
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#define SCI_BRR_31250 BRR_VALUE(31250)
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#define SCI_BRR_38400 BRR_VALUE(38400)
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#define SCI_BRR_57600 BRR_VALUE(57600)
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#define SCI_BRR_115200 BRR_VALUE(115200)
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#define SCI_BRR_500000 BRR_VALUE(500000)
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/* bit values for scr (serial control register) */
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#define SCI_SCR_TIE 0x80 /* transmit interrupt enable */
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#define SCI_SCR_RIE 0x40 /* receive interrupt enable */
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#define SCI_SCR_TXE 0x20 /* transmit enable */
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#define SCI_SCR_RXE 0x10 /* receive enable */
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/* #define SCI_SCR_MPIE 0x08 /@ multiprocessor interrupt enable */
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#define SCI_SCR_TEIE 0x04 /* transmit end interrupt enable */
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#define SCI_SCR_CKE 0x03 /* clock enable bits */
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/* bit values for ssr (serial status register) */
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#define SCI_SSR_TDRE 0x80 /* transmit data register empty */
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#define SCI_SSR_RDRF 0x40 /* receive data register full */
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#define SCI_SSR_ORER 0x20 /* overrun error */
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#define SCI_SSR_FER 0x10 /* framing error */
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#define SCI_SSR_PER 0x08 /* parity error */
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#define SCI_SSR_TEND 0x04 /* transmit end */
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/* #define SCI_SSR_MPB 0x02 /@ multiprocessor bit */
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/* #define SCI_SSR_MPBT 0x01 /@ multiprocessor bit transfer */
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/* function prototypes */
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extern void shSciDevInit (SCI_CHAN *pChan);
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extern void shSciIntRcv (SCI_CHAN *pChan);
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extern void shSciIntTx (SCI_CHAN *pChan);
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extern void shSciIntErr (SCI_CHAN *pChan);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCshSciSioh */
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