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/* ixp400Sio.h - Intel IXP400 UART header file */
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/*
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Copyright (c) 2002-2004 Wind River Systems, Inc. All rights reserved.
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Certain portions of these files may be copyright (c) 2002-2004 Intel
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Corporation.
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*/
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/*
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modification history
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--------------------
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01e,25aug05,m_h SIO for ixdp4xx XSCALE processors
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01d,20jul05,m_h serial driver for ixdp465 and related XSCALE BSPs
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01c,20dec04,pai Updated copyright notice.
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01b,30jan03,jb3 Fix SPR 85040 Serialdata corruption.
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01a,05jun02,jb initial version...
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*/
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#ifndef __INCixp400Sioh
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#define __INCixp400Sioh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/******************************************************************************
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*
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* Register descriptions
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*
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******************************************************************************/
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#ifndef _ASMLANGUAGE
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/* Register offsets from base address */
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#define RBR (0x00) /* receiver buffer register (read only) */
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#define THR (0x00) /* transmit holding register (write only) */
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#define IER (0x01) /* interrupt enable register (r/w) */
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#define IIR (0x02) /* interrupt identification register (read only) */
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#define FCR (0x02) /* FIFO control register (write only) */
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#define LCR (0x03) /* line control register (r/w) */
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#define MCR (0x04) /* modem control register (r/w) */
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#define LSR (0x05) /* line status register (read only) */
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#define MSR (0x06) /* modem status register (read only) */
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#define SCR (0x07) /* scratch pad register (r/w) */
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#define DLL (0x00) /* divisor latch lower byte (r/w) */
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#define DLM (0x01) /* divisor latch upper bytes (r/w) */
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/* Line Control Register */
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#define CHAR_LEN_5 0x00 /* 5bit data length (default) */
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#define CHAR_LEN_6 0x01 /* 6bit data length */
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#define CHAR_LEN_7 0x02 /* 7bit data length */
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#define CHAR_LEN_8 0x03 /* 8bit data length */
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#define LCR_STB_1 0x00 /* 1 stop bit */
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#define LCR_STB_2 0x04 /* 2 stop bits */
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#define LCR_PEN 0x08 /* parity enable */
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#define LCR_PDIS 0x00 /* parity disable */
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#define LCR_EPS 0x10 /* even parity select */
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#define LCR_STCKP 0x20 /* sticky parity select */
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#define LCR_SBRK 0x40 /* set break control */
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#define LCR_DLAB 0x80 /* divisor latch access enable */
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/* Line Status Register */
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#define LSR_DR 0x01 /* data ready */
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#define LSR_OE 0x02 /* overrun error */
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#define LSR_PE 0x04 /* parity error */
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#define LSR_FE 0x08 /* framing error */
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#define LSR_BI 0x10 /* break interrupt */
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#define LSR_TDRQ 0x20 /* transmit data request */
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#define LSR_TEMT 0x40 /* transmitter empty */
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#define LSR_FIFOE 0x80 /* in FIFO mode, set when PE, FE or BI error */
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/* Interrupt Enable Register */
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#define IER_RAVIE 0x01 /* received data available int enable */
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#define IER_TIE 0x02 /* transmitter data request int enable */
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#define IER_RLSE 0x04 /* receiver line status int enable */
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#define IER_MIE 0x08 /* modem status int enable */
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#define IER_RTOIE 0x10 /* receiver timeout int enable */
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#define IER_NRZIE 0x20 /* NZR coding enable */
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#define IER_UUE 0x40 /* UART Unit enable */
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#define IER_DMAE 0x80 /* DMA Requests enable */
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/* Interrupt Identification Register */
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#define IIR_IP 0x00 /* interrupt pending */
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#define IIR_RLS 0x06 /* received line status int */
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#define IIR_RDA 0x04 /* received data available int */
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#define IIR_TIMEOUT 0x0C /* receive data timeout (FIFO mode only) */
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#define IIR_THRE 0x02 /* transmit data request int */
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#define IIR_MSTAT 0x00 /* modem status int */
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#define IIR_FIFOES 0xC0 /* FIFO mode enable status */
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/* Modem Control Register */
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#define MCR_RTS 0x02 /* request to send output */
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#define MCR_OUT1 0x04 /* output #1 */
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#define MCR_OUT2 0x08 /* output #2 */
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#define MCR_LOOP 0x10 /* loopback mode enable */
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/* Modem Status Register */
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#define MSR_DCTS 0x01 /* clear to send change */
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#define MSR_CTS 0x10 /* complement of cts input */
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/* FIFO Control Register */
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#define FCR_TRFIFOE 0x01 /* enable xmit and rcvr FIFOs */
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#define FCR_RESETRF 0x02 /* reset receiver FIFO */
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#define FCR_RESETTF 0x04 /* reset trasmitter FIFO */
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#define FCR_ITL_1 0x00 /* 1byte receiver trigger level */
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#define FCR_ITL_8 0x40 /* 8byte receiver trigger level */
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#define FCR_ITL_16 0x80 /* 16byte receiver trigger level */
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#define FCR_ITL_32 0xC0 /* 32byte receiver trigger level */
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/*
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* Max iterations for servicing chars during ISR. This value should not be greater
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* than 32 i.e. half the UART FIFO size.
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* #define IXP400_SIO_MAX_CNT 30
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*/
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#define IXP400_SIO_MAX_CNT 32
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#define IXP400_SIO_MAX_RX_CNT 63
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#define IXP400_SIO_MAX_TX_CNT 31
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typedef struct /* IXP400_SIO_CHAN */
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{
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/* always goes first */
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SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
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/* callbacks */
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void * getTxArg;
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void * putRcvArg;
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STATUS (*getTxChar) (); /* pointer to xmitr function */
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STATUS (*putRcvChar) (); /* pointer to rcvr function */
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UINT8 *regs; /* IXP400 UART registers */
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UINT8 level; /* 8259a interrupt level for this device */
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UINT8 ier; /* copy of ier */
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UINT8 lcr; /* copy of lcr */
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UINT8 mcr; /* copy of mcr */
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UINT16 channelMode; /* such as INT, POLL modes */
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UINT16 regDelta; /* register address spacing */
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int baudRate;
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UINT32 xtal; /* UART clock frequency */
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UINT32 options; /* hardware setup options */
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#ifdef IXP400_SIO_DEBUG
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UINT32 rxCount; /* UART statistics counters */
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UINT32 txCount;
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UINT32 overrunErr;
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UINT32 parityErr;
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UINT32 framingErr;
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UINT32 breakErr;
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#endif
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} IXP400_SIO_CHAN;
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern void ixp400SioInt (IXP400_SIO_CHAN *);
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extern void ixp400SioDevInit (IXP400_SIO_CHAN *);
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extern void ixp400SioStatsShow (IXP400_SIO_CHAN *);
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#else
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extern void ixp400SioInt ();
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extern void ixp400SioInit ();
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extern void ixp400SioStatsShow ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCixp400Sioh */
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