bjayesh/m241Neelima
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

original files of m241

Browse Source
This commit is contained in:
neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
12254 changed files with 7655111 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
vxworks-6.9/target/h/drv/sio/ambaSio.h
+94
View File
@@ -0,0 +1,94 @@
/* ambaSio.h - ARM AMBA UART header file */
/* Copyright 1997-2000, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,29apr10,pad Moved extern C statement after include statements.
01c,12apr00,jpd added include of sioLib.h to work with project builds.
01b,19nov97,jpd updated comments/documentation in line with latest standards.
01a,04sep97,jpd written from st16552Sio.h, version 01c.
*/
#ifndef __INCambaSioh
#define __INCambaSioh
/* Register description OF ARM AMBA UART */
#ifndef _ASMLANGUAGE
#include "vxWorks.h"
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Register offsets from base address */
#define UARTDR 0x00 /* UART data register (R/W) */
#define RXSTAT 0x04 /* Rx data status register (R/O) */
#define UMSEOI 0x04 /* Clr modem status changed int (W/O) */
#define H_UBRLCR 0x08 /* } High middle and low bytes (R/W) */
#define M_UBRLCR 0x0C /* } of bit rate and line (W/O) */
#define L_UBRLCR 0x10 /* } register (W/O) */
#define UARTCON 0x14 /* control register (R/W) */
#define UARTFLG 0x18 /* FIFO status register (R/O) */
/* bit definitions within H_UBRLCR register */
#define PARITY_NONE 0x00 /* set no parity */
#define ONE_STOP 0x00 /* set one stop bit */
#define FIFO_ENABLE 0x10 /* Enable both FIFOs */
#define WORD_LEN_5 (0x00 << 5) /* Set UART word lengths */
#define WORD_LEN_6 (0x01 << 5)
#define WORD_LEN_7 (0x02 << 5)
#define WORD_LEN_8 (0x03 << 5)
/* bit definitions within UARTCON register */
#define UART_ENABLE 0x01 /* Enable the UART */
/* bit definitions within UARTFLG register */
#define FLG_UTXFF (0x01 << 5) /* UART Tx FIFO Full */
#define FLG_URXFE (0x01 << 4) /* UART Rx FIFO Empty */
typedef struct AMBA_CHAN
{
/* must be first */
SIO_CHAN sio; /* standard SIO_CHAN element */
/* callbacks */
STATUS (*getTxChar) (); /* installed Tx callback routine */
STATUS (*putRcvChar) (); /* installed Rx callback routine */
void * getTxArg; /* argument to Tx callback routine */
void * putRcvArg; /* argument to Rx callback routine */
UINT32 * regs; /* AMBA registers */
UINT8 levelRx; /* Rx Interrupt level for this device */
UINT8 levelTx; /* Tx Interrupt level for this device */
UINT32 channelMode; /* such as INT, POLL modes */
int baudRate; /* the current baud rate */
UINT32 xtal; /* UART clock frequency */
} AMBA_CHAN;
/* function declarations */
extern void ambaIntTx (AMBA_CHAN *pChan);
extern void ambaIntRx (AMBA_CHAN *pChan);
extern void ambaDevInit (AMBA_CHAN *pChan);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCambaSioh */
vxworks-6.9/target/h/drv/sio/coldfireSio.h
+218
View File
@@ -0,0 +1,218 @@
/* coldfireSio.h - Motorola ColdFire internal UART header file */
/* Copyright 1984-1998, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,09jul98,gls Adapted to WRS coding conventions
01a,01may98,mem created, based on m5204Sio.h.
*/
/*
This file contains constants and defines for the UART contained in several
of the Motorola ColdFire ports.
*/
#ifndef __INCcoldfireSioh
#define __INCcoldfireSioh
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
SIO_DRV_FUNCS * pDrvFuncs; /* Driver functions */
/* CallBacks */
STATUS (*getTxChar)();
STATUS (*putRcvChar)();
void * getTxArg;
void * putRcvArg;
UINT clkRate; /* system clock rate */
UINT16 mode; /* SIO_MODE */
unsigned char intVec;
int options;
int intEnable;
UINT baudRate;
UCHAR oprCopy;
UCHAR acrCopy;
UCHAR imrCopy;
volatile UCHAR *mr; /* UART mode register */
volatile UCHAR *sr; /* UART status register */
volatile UCHAR *csr; /* UART clock select register */
volatile UCHAR *cr; /* UART command register */
volatile UCHAR *rb; /* UART receive buffer register */
volatile UCHAR *tb; /* UART transmit buffer register */
volatile UCHAR *ipcr; /* UART input port change register */
volatile UCHAR *acr; /* UART auxiliary control register */
volatile UCHAR *isr; /* UART interrupt status register */
volatile UCHAR *imr; /* UART interrupt mask register */
volatile UCHAR *bg1; /* UART baud generator prescale register 1 */
volatile UCHAR *bg2; /* UART baud generator prescale register 2 */
volatile UCHAR *ivr; /* UART interrupt vector register */
volatile UCHAR *ip; /* UART input port register */
volatile UCHAR *op1; /* UART output port set cmd */
volatile UCHAR *op2; /* UART output port reset cmd */
} COLDFIRE_CHAN;
#endif /* _ASMLANGUAGE */
/* register bit definitions */
/* MR1 - mode register 1 */
#define COLDFIRE_UART_MR1_BC0 (1 << 0) /* bits per char 0 */
#define COLDFIRE_UART_MR1_BC1 (1 << 1) /* bits per char 1 */
#define COLDFIRE_UART_MR1_PT (1 << 2) /* parity type */
#define COLDFIRE_UART_MR1_PM0 (1 << 3) /* parity mode 0 */
#define COLDFIRE_UART_MR1_PM1 (1 << 4) /* parity mode 1 */
#define COLDFIRE_UART_MR1_ERR (1 << 5) /* error mode */
#define COLDFIRE_UART_MR1_RX_IRQ (1 << 6) /* receiver interrupt select */
#define COLDFIRE_UART_MR1_RX_RTS (1 << 7) /* Rx RTS control */
/* Some common modes */
#define COLDFIRE_UART_MR1_BITS_CHAR_5 0
#define COLDFIRE_UART_MR1_BITS_CHAR_6 COLDFIRE_UART_MR1_BC0
#define COLDFIRE_UART_MR1_BITS_CHAR_7 COLDFIRE_UART_MR1_BC1
#define COLDFIRE_UART_MR1_BITS_CHAR_8 (COLDFIRE_UART_MR1_BC0 \
| COLDFIRE_UART_MR1_BC1)
#define COLDFIRE_UART_MR1_NO_PARITY (COLDFIRE_UART_MR1_PM1)
#define COLDFIRE_UART_MR1_PAR_MODE_MULTI (COLDFIRE_UART_MR1_PM0 \
| COLDFIRE_UART_MR1_PM1)
#define COLDFIRE_UART_MR1_EVEN_PARITY 0
#define COLDFIRE_UART_MR1_ODD_PARITY COLDFIRE_UART_MR1_PT
/* MR2 - mode register 2 */
#define COLDFIRE_UART_MR2_SB0 (1 << 0) /* stop bit control 0 */
#define COLDFIRE_UART_MR2_SB1 (1 << 1) /* stop bit control 1 */
#define COLDFIRE_UART_MR2_SB2 (1 << 2) /* stop bit control 2 */
#define COLDFIRE_UART_MR2_SB3 (1 << 3) /* stop bit control 3 */
#define COLDFIRE_UART_MR2_TX_CTS (1 << 4) /* Tx CTS control */
#define COLDFIRE_UART_MR2_TX_RTS (1 << 5) /* Tx RTS control */
#define COLDFIRE_UART_MR2_CM0 (1 << 6) /* channel mode 0 */
#define COLDFIRE_UART_MR2_CM1 (1 << 7) /* channel mode 1 */
/* Some common bit lengths */
#define COLDFIRE_UART_MR2_STOP_BITS_1 (COLDFIRE_UART_MR2_SB0 \
| COLDFIRE_UART_MR2_SB1 \
| COLDFIRE_UART_MR2_SB2)
#define COLDFIRE_UART_MR2_STOP_BITS_2 (COLDFIRE_UART_MR2_SB0 \
| COLDFIRE_UART_MR2_SB1 \
| COLDFIRE_UART_MR2_SB2 \
| COLDFIRE_UART_MR2_SB3)
/* SR - status register */
#define COLDFIRE_UART_SR_RXRDY (1 << 0) /* Rx ready */
#define COLDFIRE_UART_SR_FFULL (1 << 1) /* FIFO full */
#define COLDFIRE_UART_SR_TXRDY (1 << 2) /* Tx ready */
#define COLDFIRE_UART_SR_TXEMP (1 << 3) /* Tx empty */
#define COLDFIRE_UART_SR_OE (1 << 4) /* overrun error */
#define COLDFIRE_UART_SR_PE (1 << 5) /* parity error */
#define COLDFIRE_UART_SR_FE (1 << 6) /* framing error */
#define COLDFIRE_UART_SR_RB (1 << 7) /* received break */
/* CSR - clock select register */
#define COLDFIRE_UART_CSR_TCS0 (1 << 0) /* Tx clock select 0 */
#define COLDFIRE_UART_CSR_TCS1 (1 << 1) /* Tx clock select 1 */
#define COLDFIRE_UART_CSR_TCS2 (1 << 2) /* Tx clock select 2 */
#define COLDFIRE_UART_CSR_TCS3 (1 << 3) /* Tx clock select 3 */
#define COLDFIRE_UART_CSR_RCS0 (1 << 4) /* Rx clock select 0 */
#define COLDFIRE_UART_CSR_RCS1 (1 << 5) /* Rx clock select 1 */
#define COLDFIRE_UART_CSR_RCS2 (1 << 6) /* Rx clock select 2 */
#define COLDFIRE_UART_CSR_RCS3 (1 << 7) /* Rx clock select 3 */
#define COLDFIRE_UART_CSR_TIMER_TX (COLDFIRE_UART_CSR_TCS0 \
| COLDFIRE_UART_CSR_TCS2 \
| COLDFIRE_UART_CSR_TCS3)
#define COLDFIRE_UART_CSR_TIMER_RX (COLDFIRE_UART_CSR_RCS0 \
| COLDFIRE_UART_CSR_RCS2 \
| COLDFIRE_UART_CSR_RCS3)
/* CR - command register */
#define COLDFIRE_UART_CR_RC0 (1 << 0) /* receiver control bit 0 */
#define COLDFIRE_UART_CR_RC1 (1 << 1) /* receiver control bit 1 */
#define COLDFIRE_UART_CR_TC0 (1 << 2) /* transmitter control bit 0 */
#define COLDFIRE_UART_CR_TC1 (1 << 3) /* transmitter control bit 1 */
#define COLDFIRE_UART_CR_MISC0 (1 << 4) /* misc control bit 0 */
#define COLDFIRE_UART_CR_MISC1 (1 << 5) /* misc control bit 1 */
#define COLDFIRE_UART_CR_MISC2 (1 << 6) /* misc control bit 2 */
/* Some common commands */
#define COLDFIRE_UART_CR_TX_ENABLE (COLDFIRE_UART_CR_TC0)
#define COLDFIRE_UART_CR_TX_DISABLE (COLDFIRE_UART_CR_TC1)
#define COLDFIRE_UART_CR_RX_ENABLE (COLDFIRE_UART_CR_RC0)
#define COLDFIRE_UART_CR_RX_DISABLE (COLDFIRE_UART_CR_RC1)
#define COLDFIRE_UART_CR_RESET_MODE_PTR (COLDFIRE_UART_CR_MISC0)
#define COLDFIRE_UART_CR_RESET_RX (COLDFIRE_UART_CR_MISC1)
#define COLDFIRE_UART_CR_RESET_TX (COLDFIRE_UART_CR_MISC1 \
| COLDFIRE_UART_CR_MISC0)
#define COLDFIRE_UART_CR_RESET_ERR (COLDFIRE_UART_CR_MISC2)
#define COLDFIRE_UART_CR_RESET_BRK (COLDFIRE_UART_CR_MISC2 \
| COLDFIRE_UART_CR_MISC0)
/* ACR - auxiliary control register */
#define COLDFIRE_UART_ACR_IEC (1 << 0) /* input enable control */
/* IMR - interrupt mask register */
#define COLDFIRE_UART_IMR_TXRDY (1 << 0) /* transmitter ready */
#define COLDFIRE_UART_IMR_RXRDY (1 << 1) /* receiver ready */
#define COLDFIRE_UART_IMR_DB (1 << 2) /* delta break */
#define COLDFIRE_UART_IMR_COS (1 << 7) /* change of CTS state */
/* ISR - interrupt status register */
#define COLDFIRE_UART_ISR_TXRDY (1 << 0) /* transmitter ready */
#define COLDFIRE_UART_ISR_RXRDY (1 << 1) /* receiver ready */
#define COLDFIRE_UART_ISR_DB (1 << 2) /* delta break */
#define COLDFIRE_UART_ISR_COS (1 << 7) /* change of CTS state */
/* IP - input port register */
#define COLDFIRE_UART_IP_CTS (1 << 0) /* current CTS state */
/* OP1 - output set register */
#define COLDFIRE_UART_OP1_RTS (1 << 0) /* set RTS */
/* OP2 - output reset register */
#define COLDFIRE_UART_OP2_RTS (1 << 0) /* clear RTS */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT void coldfireDevInit (COLDFIRE_CHAN *pChan);
IMPORT void coldfireDevInit2 (COLDFIRE_CHAN *pChan);
IMPORT void coldfireInt (COLDFIRE_CHAN *pChan);
#else /* __STDC__ */
IMPORT void coldfireDevInit ();
IMPORT void coldfireDevInit2 ();
IMPORT void coldfireInt ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* __INCcoldfireSioh */
vxworks-6.9/target/h/drv/sio/evbNs16550Sio.h
+88
View File
@@ -0,0 +1,88 @@
/* evbNs16550Sio.h - header file for binary interface NS 16550 UART driver */
/* Copyright 1984-1996, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,02dec97,db changed type from char to UCHAR for element outByte() in
EVBNS16550_CHAN structure for compatibility with sysLib.h.
01a,07mar96,tam written (from i8250Sio.h)
*/
#ifndef __INCevbNs16550Sioh
#define __INCevbNs16550Sioh
#ifndef _ASMLANGUAGE
#include "vxWorks.h"
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* channel data structure */
typedef struct EVBNS16550_CHAN
{
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
STATUS (*getTxChar) ();
STATUS (*putRcvChar) ();
void * getTxArg;
void * putRcvArg;
UINT16 int_vec; /* interrupt vector number */
UINT16 channelMode; /* SIO_MODE_[INT | POLL] */
UCHAR (*inByte) (ULONG); /* routine to read a byte from register */
void (*outByte)(ULONG,UCHAR); /* routine to write a byte to register */
UINT32 clkFreq; /* baud rate generator clock */
int baudRate; /* baud rate */
ULONG lcr; /* UART line control register */
ULONG lst; /* UART line status register */
ULONG mdc; /* UART modem control register */
ULONG msr; /* UART modem status register */
ULONG ier; /* UART interrupt enable register */
ULONG iid; /* UART interrupt ID register */
ULONG brdl; /* UART baud rate register */
ULONG brdh; /* UART baud rate register */
ULONG data; /* UART data register */
} EVBNS16550_CHAN;
/* register definitions */
#define UART_THR 0x00 /* Transmitter holding reg. */
#define UART_RDR 0x00 /* Receiver data reg. */
#define UART_BRDL 0x00 /* Baud rate divisor (LSB) */
#define UART_BRDH 0x01 /* Baud rate divisor (MSB) */
#define UART_IER 0x01 /* Interrupt enable reg. */
#define UART_IID 0x02 /* Interrupt ID reg. */
#define UART_LCR 0x03 /* Line control reg. */
#define UART_MDC 0x04 /* Modem control reg. */
#define UART_LST 0x05 /* Line status reg. */
#define UART_MSR 0x06 /* Modem status reg. */
#if defined(__STDC__) || defined(__cplusplus)
extern void evbNs16550HrdInit(EVBNS16550_CHAN *pDev);
extern void evbNs16550Int (EVBNS16550_CHAN *pDev);
#else
extern void evbNs16550HrdInit();
extern void evbNs16550Int();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCevbNs16550Sioh */
vxworks-6.9/target/h/drv/sio/i8250Sio.h
+154
View File
@@ -0,0 +1,154 @@
/* i8250Sio.h - header file for binary interface Intel 8250 UART driver */
/* Copyright 1984-1993, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01e,29apr10,pad Moved extern C statement after include statements.
01d,03jun98,hdn changed I8250_IIR_MASK from 6 to 7 to fix the TX-int problem.
01c,22may97,db added macros for all i8250 registers(SPR #7542).
01b,15jun95,ms updated for new driver.
01a,15mar95,myz written (from i8250Serial.h)
*/
#ifndef __INCi8250Sioh
#define __INCi8250Sioh
#ifndef _ASMLANGUAGE
#include "vxWorks.h"
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* channel data structure */
typedef struct /* I8250_CHAN */
{
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
STATUS (*getTxChar) (); /* pointer to xmitr function */
STATUS (*putRcvChar) (); /* pointer tp rcvr function */
void * getTxArg;
void * putRcvArg;
UINT16 int_vec; /* interrupt vector number */
UINT16 channelMode; /* SIO_MODE_[INT | POLL] */
UCHAR (*inByte) (int); /* routine to read a byte from register */
void (*outByte)(int,char); /* routine to write a byte to register */
ULONG lcr; /* UART line control register */
ULONG lst; /* UART line status register */
ULONG mdc; /* UART modem control register */
ULONG msr; /* UART modem status register */
ULONG ier; /* UART interrupt enable register */
ULONG iid; /* UART interrupt ID register */
ULONG brdl; /* UART baud rate register */
ULONG brdh; /* UART baud rate register */
ULONG data; /* UART data register */
ULONG options; /* UART hardware options */
} I8250_CHAN;
typedef struct /* BAUD */
{
int rate; /* a baud rate */
int preset; /* counter preset value to write to DUSCC_CTPR[HL]A */
} BAUD;
/* register definitions */
#define UART_THR 0x00 /* Transmitter holding reg. */
#define UART_RDR 0x00 /* Receiver data reg. */
#define UART_BRDL 0x00 /* Baud rate divisor (LSB) */
#define UART_BRDH 0x01 /* Baud rate divisor (MSB) */
#define UART_IER 0x01 /* Interrupt enable reg. */
#define UART_IID 0x02 /* Interrupt ID reg. */
#define UART_LCR 0x03 /* Line control reg. */
#define UART_MDC 0x04 /* Modem control reg. */
#define UART_LST 0x05 /* Line status reg. */
#define UART_MSR 0x06 /* Modem status reg. */
/* equates for interrupt enable register */
#define I8250_IER_RXRDY 0x01 /* receiver data ready */
#define I8250_IER_TBE 0x02 /* transmit bit enable */
#define I8250_IER_LST 0x04 /* line status interrupts */
#define I8250_IER_MSI 0x08 /* modem status interrupts */
/* equates for interrupt identification register */
#define I8250_IIR_IP 0x01 /* interrupt pending bit */
#define I8250_IIR_MASK 0x07 /* interrupt id bits mask */
#define I8250_IIR_MSTAT 0x00 /* modem status interrupt */
#define I8250_IIR_THRE 0X02 /* transmit holding register empty */
#define I8250_IIR_RBRF 0x04 /* receiver buffer register full */
#define I8250_IIR_SEOB 0x06 /* serialization error or break */
/* equates for line control register */
#define I8250_LCR_CS5 0x00 /* 5 bits data size */
#define I8250_LCR_CS6 0x01 /* 6 bits data size */
#define I8250_LCR_CS7 0x02 /* 7 bits data size */
#define I8250_LCR_CS8 0x03 /* 8 bits data size */
#define I8250_LCR_2_STB 0x04 /* 2 stop bits */
#define I8250_LCR_1_STB 0x00 /* 1 stop bit */
#define I8250_LCR_PEN 0x08 /* parity enable */
#define I8250_LCR_PDIS 0x00 /* parity disable */
#define I8250_LCR_EPS 0x10 /* even parity slect */
#define I8250_LCR_SP 0x20 /* stick parity select */
#define I8250_LCR_SBRK 0x40 /* break control bit */
#define I8250_LCR_DLAB 0x80 /* divisor latch access enable */
/* equates for the modem control register */
#define I8250_MCR_DTR 0x01 /* dtr output */
#define I8250_MCR_RTS 0x02 /* rts output */
#define I8250_MCR_OUT1 0x04 /* output #1 */
#define I8250_MCR_OUT2 0x08 /* output #2 */
#define I8250_MCR_LOOP 0x10 /* loop back */
/* equates for line status register */
#define I8250_LSR_RXRDY 0x01 /* receiver data available */
#define I8250_LSR_OE 0x02 /* overrun error */
#define I8250_LSR_PE 0x04 /* parity error */
#define I8250_LSR_FE 0x08 /* framing error */
#define I8250_LSR_BI 0x10 /* break interrupt */
#define I8250_LSR_THRE 0x20 /* transmit holding register empty */
#define I8250_LSR_TEMT 0x40 /* transmitter empty */
/* equates for modem status register */
#define I8250_MSR_DCTS 0x01 /* cts change */
#define I8250_MSR_DDSR 0x02 /* dsr change */
#define I8250_MSR_DRI 0x04 /* ring change */
#define I8250_MSR_DDCD 0x08 /* data carrier change */
#define I8250_MSR_CTS 0x10 /* complement of cts */
#define I8250_MSR_DSR 0x20 /* complement of dsr */
#define I8250_MSR_RI 0x40 /* complement of ring signal */
#define I8250_MSR_DCD 0x80 /* complement of dcd */
#if defined(__STDC__) || defined(__cplusplus)
extern void i8250HrdInit(I8250_CHAN *pDev);
extern void i8250Int (I8250_CHAN *pDev);
#else
extern void i8250HrdInit();
extern void i8250Int();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCi8250h */
vxworks-6.9/target/h/drv/sio/ixp400Sio.h
+191
View File
@@ -0,0 +1,191 @@
/* ixp400Sio.h - Intel IXP400 UART header file */
/*
Copyright (c) 2002-2004 Wind River Systems, Inc. All rights reserved.
Certain portions of these files may be copyright (c) 2002-2004 Intel
Corporation.
*/
/*
modification history
--------------------
01e,25aug05,m_h SIO for ixdp4xx XSCALE processors
01d,20jul05,m_h serial driver for ixdp465 and related XSCALE BSPs
01c,20dec04,pai Updated copyright notice.
01b,30jan03,jb3 Fix SPR 85040 Serialdata corruption.
01a,05jun02,jb initial version...
*/
#ifndef __INCixp400Sioh
#define __INCixp400Sioh
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
*
* Register descriptions
*
******************************************************************************/
#ifndef _ASMLANGUAGE
/* Register offsets from base address */
#define RBR (0x00) /* receiver buffer register (read only) */
#define THR (0x00) /* transmit holding register (write only) */
#define IER (0x01) /* interrupt enable register (r/w) */
#define IIR (0x02) /* interrupt identification register (read only) */
#define FCR (0x02) /* FIFO control register (write only) */
#define LCR (0x03) /* line control register (r/w) */
#define MCR (0x04) /* modem control register (r/w) */
#define LSR (0x05) /* line status register (read only) */
#define MSR (0x06) /* modem status register (read only) */
#define SCR (0x07) /* scratch pad register (r/w) */
#define DLL (0x00) /* divisor latch lower byte (r/w) */
#define DLM (0x01) /* divisor latch upper bytes (r/w) */
/* Line Control Register */
#define CHAR_LEN_5 0x00 /* 5bit data length (default) */
#define CHAR_LEN_6 0x01 /* 6bit data length */
#define CHAR_LEN_7 0x02 /* 7bit data length */
#define CHAR_LEN_8 0x03 /* 8bit data length */
#define LCR_STB_1 0x00 /* 1 stop bit */
#define LCR_STB_2 0x04 /* 2 stop bits */
#define LCR_PEN 0x08 /* parity enable */
#define LCR_PDIS 0x00 /* parity disable */
#define LCR_EPS 0x10 /* even parity select */
#define LCR_STCKP 0x20 /* sticky parity select */
#define LCR_SBRK 0x40 /* set break control */
#define LCR_DLAB 0x80 /* divisor latch access enable */
/* Line Status Register */
#define LSR_DR 0x01 /* data ready */
#define LSR_OE 0x02 /* overrun error */
#define LSR_PE 0x04 /* parity error */
#define LSR_FE 0x08 /* framing error */
#define LSR_BI 0x10 /* break interrupt */
#define LSR_TDRQ 0x20 /* transmit data request */
#define LSR_TEMT 0x40 /* transmitter empty */
#define LSR_FIFOE 0x80 /* in FIFO mode, set when PE, FE or BI error */
/* Interrupt Enable Register */
#define IER_RAVIE 0x01 /* received data available int enable */
#define IER_TIE 0x02 /* transmitter data request int enable */
#define IER_RLSE 0x04 /* receiver line status int enable */
#define IER_MIE 0x08 /* modem status int enable */
#define IER_RTOIE 0x10 /* receiver timeout int enable */
#define IER_NRZIE 0x20 /* NZR coding enable */
#define IER_UUE 0x40 /* UART Unit enable */
#define IER_DMAE 0x80 /* DMA Requests enable */
/* Interrupt Identification Register */
#define IIR_IP 0x00 /* interrupt pending */
#define IIR_RLS 0x06 /* received line status int */
#define IIR_RDA 0x04 /* received data available int */
#define IIR_TIMEOUT 0x0C /* receive data timeout (FIFO mode only) */
#define IIR_THRE 0x02 /* transmit data request int */
#define IIR_MSTAT 0x00 /* modem status int */
#define IIR_FIFOES 0xC0 /* FIFO mode enable status */
/* Modem Control Register */
#define MCR_RTS 0x02 /* request to send output */
#define MCR_OUT1 0x04 /* output #1 */
#define MCR_OUT2 0x08 /* output #2 */
#define MCR_LOOP 0x10 /* loopback mode enable */
/* Modem Status Register */
#define MSR_DCTS 0x01 /* clear to send change */
#define MSR_CTS 0x10 /* complement of cts input */
/* FIFO Control Register */
#define FCR_TRFIFOE 0x01 /* enable xmit and rcvr FIFOs */
#define FCR_RESETRF 0x02 /* reset receiver FIFO */
#define FCR_RESETTF 0x04 /* reset trasmitter FIFO */
#define FCR_ITL_1 0x00 /* 1byte receiver trigger level */
#define FCR_ITL_8 0x40 /* 8byte receiver trigger level */
#define FCR_ITL_16 0x80 /* 16byte receiver trigger level */
#define FCR_ITL_32 0xC0 /* 32byte receiver trigger level */
/*
* Max iterations for servicing chars during ISR. This value should not be greater
* than 32 i.e. half the UART FIFO size.
* #define IXP400_SIO_MAX_CNT 30
*/
#define IXP400_SIO_MAX_CNT 32
#define IXP400_SIO_MAX_RX_CNT 63
#define IXP400_SIO_MAX_TX_CNT 31
typedef struct /* IXP400_SIO_CHAN */
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
void * getTxArg;
void * putRcvArg;
STATUS (*getTxChar) (); /* pointer to xmitr function */
STATUS (*putRcvChar) (); /* pointer to rcvr function */
UINT8 *regs; /* IXP400 UART registers */
UINT8 level; /* 8259a interrupt level for this device */
UINT8 ier; /* copy of ier */
UINT8 lcr; /* copy of lcr */
UINT8 mcr; /* copy of mcr */
UINT16 channelMode; /* such as INT, POLL modes */
UINT16 regDelta; /* register address spacing */
int baudRate;
UINT32 xtal; /* UART clock frequency */
UINT32 options; /* hardware setup options */
#ifdef IXP400_SIO_DEBUG
UINT32 rxCount; /* UART statistics counters */
UINT32 txCount;
UINT32 overrunErr;
UINT32 parityErr;
UINT32 framingErr;
UINT32 breakErr;
#endif
} IXP400_SIO_CHAN;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void ixp400SioInt (IXP400_SIO_CHAN *);
extern void ixp400SioDevInit (IXP400_SIO_CHAN *);
extern void ixp400SioStatsShow (IXP400_SIO_CHAN *);
#else
extern void ixp400SioInt ();
extern void ixp400SioInit ();
extern void ixp400SioStatsShow ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCixp400Sioh */
vxworks-6.9/target/h/drv/sio/ixp425Sio.h
+184
View File
@@ -0,0 +1,184 @@
/* ixp425Sio.h - Intel IXP425 UART header file */
/* Copyright 2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,30jan03,jb3 Fix SPR 85040 Serialdata corruption.
01a,05jun02,jb initial version...
*/
#ifndef __INCixp425Sioh
#define __INCixp425Sioh
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
*
* Register descriptions
*
******************************************************************************/
#ifndef _ASMLANGUAGE
/* Register offsets from base address */
#define RBR (0x00) /* receiver buffer register (read only) */
#define THR (0x00) /* transmit holding register (write only) */
#define IER (0x01) /* interrupt enable register (r/w) */
#define IIR (0x02) /* interrupt identification register (read only) */
#define FCR (0x02) /* FIFO control register (write only) */
#define LCR (0x03) /* line control register (r/w) */
#define MCR (0x04) /* modem control register (r/w) */
#define LSR (0x05) /* line status register (read only) */
#define MSR (0x06) /* modem status register (read only) */
#define SCR (0x07) /* scratch pad register (r/w) */
#define DLL (0x00) /* divisor latch lower byte (r/w) */
#define DLM (0x01) /* divisor latch upper bytes (r/w) */
/* Line Control Register */
#define CHAR_LEN_5 0x00 /* 5bit data length (default) */
#define CHAR_LEN_6 0x01 /* 6bit data length */
#define CHAR_LEN_7 0x02 /* 7bit data length */
#define CHAR_LEN_8 0x03 /* 8bit data length */
#define LCR_STB_1 0x00 /* 1 stop bit */
#define LCR_STB_2 0x04 /* 2 stop bits */
#define LCR_PEN 0x08 /* parity enable */
#define LCR_PDIS 0x00 /* parity disable */
#define LCR_EPS 0x10 /* even parity select */
#define LCR_STCKP 0x20 /* sticky parity select */
#define LCR_SBRK 0x40 /* set break control */
#define LCR_DLAB 0x80 /* divisor latch access enable */
/* Line Status Register */
#define LSR_DR 0x01 /* data ready */
#define LSR_OE 0x02 /* overrun error */
#define LSR_PE 0x04 /* parity error */
#define LSR_FE 0x08 /* framing error */
#define LSR_BI 0x10 /* break interrupt */
#define LSR_TDRQ 0x20 /* transmit data request */
#define LSR_TEMT 0x40 /* transmitter empty */
#define LSR_FIFOE 0x80 /* in FIFO mode, set when PE, FE or BI error */
/* Interrupt Enable Register */
#define IER_RAVIE 0x01 /* received data available int enable */
#define IER_TIE 0x02 /* transmitter data request int enable */
#define IER_RLSE 0x04 /* receiver line status int enable */
#define IER_MIE 0x08 /* modem status int enable */
#define IER_RTOIE 0x10 /* receiver timeout int enable */
#define IER_NRZIE 0x20 /* NZR coding enable */
#define IER_UUE 0x40 /* UART Unit enable */
#define IER_DMAE 0x80 /* DMA Requests enable */
/* Interrupt Identification Register */
#define IIR_IP 0x00 /* interrupt pending */
#define IIR_RLS 0x06 /* received line status int */
#define IIR_RDA 0x04 /* received data available int */
#define IIR_TIMEOUT 0x0C /* receive data timeout (FIFO mode only) */
#define IIR_THRE 0x02 /* transmit data request int */
#define IIR_MSTAT 0x00 /* modem status int */
#define IIR_FIFOES 0xC0 /* FIFO mode enable status */
/* Modem Control Register */
#define MCR_RTS 0x02 /* request to send output */
#define MCR_OUT1 0x04 /* output #1 */
#define MCR_OUT2 0x08 /* output #2 */
#define MCR_LOOP 0x10 /* loopback mode enable */
/* Modem Status Register */
#define MSR_DCTS 0x01 /* clear to send change */
#define MSR_CTS 0x10 /* complement of cts input */
/* FIFO Control Register */
#define FCR_TRFIFOE 0x01 /* enable xmit and rcvr FIFOs */
#define FCR_RESETRF 0x02 /* reset receiver FIFO */
#define FCR_RESETTF 0x04 /* reset trasmitter FIFO */
#define FCR_ITL_1 0x00 /* 1byte receiver trigger level */
#define FCR_ITL_8 0x40 /* 8byte receiver trigger level */
#define FCR_ITL_16 0x80 /* 16byte receiver trigger level */
#define FCR_ITL_32 0xC0 /* 32byte receiver trigger level */
/*
* Max iterations for servicing chars during ISR. This value should not be greater
* than 32 i.e. half the UART FIFO size.
* #define IXP425_SIO_MAX_CNT 30
*/
#define IXP425_SIO_MAX_CNT 32
#define IXP425_SIO_MAX_RX_CNT 63
#define IXP425_SIO_MAX_TX_CNT 31
typedef struct /* IXP425_SIO_CHAN */
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
void * getTxArg;
void * putRcvArg;
STATUS (*getTxChar) (); /* pointer to xmitr function */
STATUS (*putRcvChar) (); /* pointer to rcvr function */
UINT8 *regs; /* IXP425 UART registers */
UINT8 level; /* 8259a interrupt level for this device */
UINT8 ier; /* copy of ier */
UINT8 lcr; /* copy of lcr */
UINT8 mcr; /* copy of mcr */
UINT16 channelMode; /* such as INT, POLL modes */
UINT16 regDelta; /* register address spacing */
int baudRate;
UINT32 xtal; /* UART clock frequency */
UINT32 options; /* hardware setup options */
#ifdef IXP425_SIO_DEBUG
UINT32 rxCount; /* UART statistics counters */
UINT32 txCount;
UINT32 overrunErr;
UINT32 parityErr;
UINT32 framingErr;
UINT32 breakErr;
#endif
} IXP425_SIO_CHAN;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void ixp425SioInt (IXP425_SIO_CHAN *);
extern void ixp425SioDevInit (IXP425_SIO_CHAN *);
extern void ixp425SioStatsShow (IXP425_SIO_CHAN *);
#else
extern void ixp425SioInt ();
extern void ixp425SioInit ();
extern void ixp425SioStatsShow ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCixp425Sioh */
vxworks-6.9/target/h/drv/sio/m5200PscSio.h
+91
View File
@@ -0,0 +1,91 @@
/* m5200PscSio.h - Motorola MPC5200 internal UART header file */
/* Copyright 1984-2003, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,29apr10,pad Moved extern C statement after include statements.
01c,25Jun03,pkr created
*/
/*
This file contains constants for the UART contained in the Motorola MCF5200.
The constant SIO must defined when
including this header file.
*/
#ifndef __INCm5200PscSioh
#define __INCm5200PscSioh
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct
{
SIO_DRV_FUNCS * pDrvFuncs; /* Driver functions */
/* CallBacks */
STATUS (*getTxChar)();
STATUS (*putRcvChar)();
void * getTxArg;
void * putRcvArg;
UINT clkRate; /* system clock rate */
UINT16 mode; /* SIO_MODE */
VOIDFUNCPTR *intVec;
int options;
int intEnable;
UINT baudRate;
UCHAR acrCopy;
USHORT imrCopy;
int portNum;
volatile UCHAR *mr; /* UART mode register */
volatile USHORT *sr; /* UART status register */
volatile USHORT *csr; /* UART clock select register */
volatile UCHAR *cr; /* UART command register */
volatile ULONG *rb; /* UART receive buffer register */
volatile UCHAR *tb; /* UART transmit buffer register */
volatile UCHAR *ipcr; /* UART input port change register */
volatile UCHAR *acr; /* UART auxiliary control register */
volatile USHORT *isr; /* UART interrupt status register */
volatile USHORT *imr; /* UART interrupt mask register */
#if 0
volatile UCHAR *ivr; /* UART interrupt vector register */
#endif
volatile UCHAR *op1; /* UART output port set cmd */
volatile UCHAR *sicr; /* UART ??? */
volatile UCHAR *dp; /* UART divisor high */
volatile UCHAR *dl; /* UART divisor low */
volatile USHORT *rfalarm; /* UART ??? */
volatile USHORT *tfalarm; /* UART ??? */
} M5200_PSC_CHAN;
#endif /* _ASMLANGUAGE */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT void m5200PscSioDevInit (M5200_PSC_CHAN *pChan);
IMPORT void m5200PscSioDevInit2 (M5200_PSC_CHAN *pChan);
IMPORT void m5200PscSioInt (M5200_PSC_CHAN *pChan);
#else /* __STDC__ */
IMPORT void m5200PscSioDevInit ();
IMPORT void m5200PscSioDevInit2 ();
IMPORT void m5200PscSioInt ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* __INCm5200PscSioh */
vxworks-6.9/target/h/drv/sio/m8260Brg.h
+134
View File
@@ -0,0 +1,134 @@
/* m8260Brg.h - Motorola MPC8260 Baud Rate Generators header file */
/* Copyright 1984-1999 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,12sep99,ms_ created from m8260Cpm.h, 01d.
*/
/*
* This file contains constants for the Baud Rate Generators (BRGs)
* in the Motorola MPC8260 PowerQUICC II integrated Communications
* Processor
*/
#ifndef __INCm8260Brgh
#define __INCm8260Brgh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8; /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#endif /* M8260ABBREVIATIONS */
#ifndef M8260_32_WR
#define M8260_32_WR(addr, value) (* ((UINT32 *)(addr)) = ((UINT32) (value)))
#endif
#ifndef M8260_16_WR
#define M8260_16_WR(addr, value) (* ((UINT16 *)(addr)) = ((UINT16) (value)))
#endif
#ifndef M8260_8_WR
#define M8260_8_WR(addr, value) (* ((UINT8 *)(addr)) = ((UINT8) (value)))
#endif
#ifndef M8260_32_RD
#define M8260_32_RD(addr, value) ((value) = (* (UINT32 *) ((UINT32 *)(addr))))
#endif
#ifndef M8260_16_RD
#define M8260_16_RD(addr, value) ((value) = (* (UINT16 *) ((UINT16 *)(addr))))
#endif
#ifndef M8260_8_RD
#define M8260_8_RD(addr, value) ((value) = (* (UINT8 *) ((UINT8 *)(addr))))
#endif
#ifndef M8260_NTH_REG_WR_32
#define M8260_NTH_REG_WR_32(regVal, regBase, offsetNext, n) \
{ \
VINT32 *pReg = (VINT32 *) \
(immrVal + \
regBase + \
((n-1) * offsetNext)); \
M8260_32_WR(pReg, regVal); \
}
#endif
#define M8260_BRGC_WR(value, brgc) \
M8260_NTH_REG_WR_32(value, \
M8260_BRGC_BASE, \
M8260_BRGC_OFFSET_NEXT_BRGC, \
brgc)
/*
* MPC8260 internal register/memory map (section 17 of prelim. spec)
* note that these are offsets from the value stored in the IMMR
* register. Also note that in the MPC8260, the IMMR is not a special
* purpose register, but it is memory mapped.
*/
/* Baud Rate Generators */
#define M8260_BRGC_BASE 0x000119F0
#define M8260_BRGC_OFFSET_NEXT_BRGC 0x00000004
#define M8260_BRGC_RD(regVal, brg) \
{ \
VINT32 *pReg = (VINT32 *) \
(immrVal + \
M8260_BRGC_BASE + \
((brg - 1) * M8260_BRGC_OFFSET_NEXT_BRGC)); \
M8260_32_RD(pReg, regVal); \
}
#define M8260_BRGC_SET_BITS(bitmap) \
{ \
UINT32 regVal; \
VINT32 *pReg = (VINT32 *) \
(immrVal + \
M8260_BRGC_BASE + \
(scc * M8260_BRGC_OFFSET_NEXT_BRGC)); \
M8260_32_RD(pReg, regVal); \
M8260_32_WR(pReg, (regVal | bitmap)); \
}
/* macros used in the configuration registers */
#define M8260_BRGC_CD_MASK 0x00001FFE /* clock divider mask */
#define M8260_BRGC_CD_SHIFT 0x1 /* to shift CD into position */
#define M8260_BRGC_RST 0x00020000 /* Reset BRG */
#define M8260_BRGC_EN 0x00010000 /* Enable BRG count */
#define M8260_BRGC_EXTC_BRGCLK 0x0 /* clock comes from BRGCKL */
#define M8260_BRGC_EXTC_CLK3_9 0x1 /* clock comes from pin 3 or 9 */
#define M8260_BRGC_EXTC_CLK5_15 0x2 /* clock comes from pin 5 or 15 */
#define M8260_BRGC_EXTC_MASK 0x0000C000 /* External Clock Source Mask */
#define M8260_BRGC_EXTC_SHIFT 0xE /* shift EXTC 14 bits to position */
#define M8260_BRGC_ATB 0x00002000 /* 1 = Autobaud on Rx */
/* 0 = normal operation */
#define M8260_BRGC_DIV16 0x00000001 /* BRG Clock divide by 16 */
#ifdef __cplusplus
}
#endif
#endif /* __INCm8260Brgh */
vxworks-6.9/target/h/drv/sio/m8260Cp.h
+154
View File
@@ -0,0 +1,154 @@
/* m8260Cp.h - Motorola MPC8260 Communications Processor header file */
/* Copyright 1984-1999 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,12sep99,ms_ created from m8260Cpm.h, 01d.
*/
/*
* This file contains constants for the Communication Processor in
* the Motorola MPC8260 PowerQUICC II integrated Communications Processor
*/
#ifndef __INCm8260Cph
#define __INCm8260Cph
#ifdef __cplusplus
extern "C" {
#endif
#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8; /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#endif /* M8260ABBREVIATIONS */
/*
* MPC8260 internal register/memory map (section 17 of prelim. spec)
* note that these are offsets from the value stored in the IMMR
* register. Also note that in the MPC8260, the IMMR is not a special
* purpose register, but it is memory mapped.
*/
/* Command Register definitions (CPCR - 0x119C0) */
#define M8260_CPCR(base) (CAST(VUINT32 *)((base) + 0x119C0)) /* CPCR */
#define M8260_CPCR_LATENCY (65536 * 400) /* worst case exec latency */
#define M8260_CPCR_RESET 0x80000000 /* software reset command */
#define M8260_CPCR_PAGE_MSK 0x7c000000 /* RAM page number */
#define M8260_CPCR_SBC_MSK 0x03e00000 /* sub-block code */
#define M8260_CPCR_RES1 0x001e0000 /* reserved */
#define M8260_CPCR_FLG 0x00010000 /* flag - command executing */
#define M8260_CPCR_RES2 0x0000c000 /* reserved */
#define M8260_CPCR_MCN_MSK 0x00003fc0 /* MCC channel number */
#define M8260_CPCR_RES3 0x00000030 /* reserved */
#define M8260_CPCR_OP_MSK 0x0000000f /* command opcode */
#define M8260_CPCR_PAGE_SHIFT 0x1a /* get to the page field */
#define M8260_CPCR_SBC_SHIFT 0x15 /* get to the SBC field */
#define M8260_CPCR_MCN_SHIFT 0x6 /* get to the MCC field */
#define M8260_CPCR_OP_SHIFT 0x0 /* get to the opcode field */
#define M8260_CPCR_MCN_HDLC 0x0 /* protocol code: HDLC */
#define M8260_CPCR_MCN_ATM 0xa /* protocol code: ATM */
#define M8260_CPCR_MCN_ETH 0xc /* protocol code: ETH */
#define M8260_CPCR_MCN_TRANS 0xf /* protocol code: TRANS */
#define M8260_CPCR_OP(x) \
(((x) << M8260_CPCR_OP_SHIFT) & M8260_CPCR_OP_MSK)
#define M8260_CPCR_SBC(x) \
(((x) << M8260_CPCR_SBC_SHIFT) & M8260_CPCR_SBC_MSK)
#define M8260_CPCR_PAGE(x) \
(((x) << M8260_CPCR_PAGE_SHIFT) & M8260_CPCR_PAGE_MSK)
#define M8260_CPCR_MCN(x) \
(((x) << M8260_CPCR_MCN_SHIFT) & M8260_CPCR_MCN_MSK)
/* CPCR - Sub-block code */
#define M8260_CPCR_SBC_FCC1 0x10 /* FCC1 channel */
#define M8260_CPCR_SBC_ATM_FCC1 0x0e /* ATM on FCC1 */
#define M8260_CPCR_SBC_FCC2 0x11 /* FCC2 channel */
#define M8260_CPCR_SBC_ATM_FCC2 0x0e /* ATM on FCC2 */
#define M8260_CPCR_SBC_FCC3 0x12 /* FCC3 channel */
#define M8260_CPCR_SBC_SCC1 0x04 /* SCC1 channel */
#define M8260_CPCR_SBC_SCC2 0x05 /* SCC2 channel */
#define M8260_CPCR_SBC_SCC3 0x06 /* SCC3 channel */
#define M8260_CPCR_SBC_SCC4 0x07 /* SCC4 channel */
#define M8260_CPCR_SBC_SMC1 0x08 /* SMC1 channel */
#define M8260_CPCR_SBC_SMC2 0x09 /* SMC2 channel */
#define M8260_CPCR_SBC_RAND 0x0e /* RAND channel */
#define M8260_CPCR_SBC_SPI 0x0a /* SPI */
#define M8260_CPCR_SBC_I2C 0x0b /* I2C */
#define M8260_CPCR_SBC_TIMER 0x0f /* TIMER */
#define M8260_CPCR_SBC_MCC1 0x1c /* MCC1 channel */
#define M8260_CPCR_SBC_MCC2 0x1d /* MCC2 channel */
#define M8260_CPCR_SBC_IDMA1 0x14 /* IDMA1 channel */
#define M8260_CPCR_SBC_IDMA2 0x15 /* IDMA2 channel */
#define M8260_CPCR_SBC_IDMA3 0x16 /* IDMA3 channel */
#define M8260_CPCR_SBC_IDMA4 0x17 /* IDMA4 channel */
/* CPCR - Page code */
#define M8260_CPCR_PAGE_FCC1 0x04 /* FCC1 channel */
#define M8260_CPCR_PAGE_FCC2 0x05 /* FCC2 channel */
#define M8260_CPCR_PAGE_FCC3 0x06 /* FCC3 channel */
#define M8260_CPCR_PAGE_SCC1 0x00 /* SCC1 channel */
#define M8260_CPCR_PAGE_SCC2 0x01 /* SCC2 channel */
#define M8260_CPCR_PAGE_SCC3 0x02 /* SCC3 channel */
#define M8260_CPCR_PAGE_SCC4 0x03 /* SCC4 channel */
#define M8260_CPCR_PAGE_SMC1 0x07 /* SMC1 channel */
#define M8260_CPCR_PAGE_SMC2 0x08 /* SMC2 channel */
#define M8260_CPCR_PAGE_RAND 0x0a /* RAND channel */
#define M8260_CPCR_PAGE_SPI 0x09 /* SPI */
#define M8260_CPCR_PAGE_I2C 0x0a /* I2C */
#define M8260_CPCR_PAGE_TIMER 0x0a /* TIMER */
#define M8260_CPCR_PAGE_MCC1 0x07 /* MCC1 channel */
#define M8260_CPCR_PAGE_MCC2 0x08 /* MCC2 channel */
#define M8260_CPCR_PAGE_IDMA1 0x07 /* IDMA1 channel */
#define M8260_CPCR_PAGE_IDMA2 0x08 /* IDMA2 channel */
#define M8260_CPCR_PAGE_IDMA3 0x09 /* IDMA3 channel */
#define M8260_CPCR_PAGE_IDMA4 0x0a /* IDMA4 channel */
/* CPCR - opcodes */
#define M8260_CPCR_RT_INIT 0x0 /* Init rx and tx */
#define M8260_CPCR_RX_INIT 0x1 /* init rx only */
#define M8260_CPCR_TX_INIT 0x2 /* init tx only */
#define M8260_CPCR_HUNT 0x3 /* rx frame hunt mode */
#define M8260_CPCR_TX_STOP 0x4 /* stop tx */
#define M8260_CPCR_TX_GRSTOP 0x5 /* gracefully stop tx */
#define M8260_CPCR_TX_RESTART 0x6 /* restart tx */
#define M8260_CPCR_RX_CLOSE 0x7 /* close rx buffer */
#define M8260_CPCR_SET_GROUP 0x8 /* set group address */
#define M8260_CPCR_SET_TMR 0x8 /* set timer */
#define M8260_CPCR_GCI_TMO 0x9 /* gci timeout */
#define M8260_CPCR_IDMA_START 0x9 /* start idma */
#define M8260_CPCR_MCC_RX_STOP 0x9 /* stop rx on MCC */
#define M8260_CPCR_ATM_TX 0xa /* ATM transmit */
#define M8260_CPCR_BCS_RESET 0xa /* blk chk seq reset */
#define M8260_CPCR_GCI_ABRT 0xa /* gci abort request */
#define M8260_CPCR_IDMA_STOP 0xb /* stop idma */
#define M8260_CPCR_RANDOM 0xc /* random number */
#ifdef __cplusplus
}
#endif
#endif /* __INCm8260Cph */
vxworks-6.9/target/h/drv/sio/m8260CpmMux.h
+228
View File
@@ -0,0 +1,228 @@
/* m8260Mux.h - Motorola MPC8260 CPM Multiplexor header file */
/* Copyright 1984-1999 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,12sep99,ms_ created from m8260Cpm.h, 01d.
*/
/*
* This file contains constants for the Communications Processor Module's
* Multiplexor (CMX) in the Motorola MPC8260 PowerQUICC II integrated
* Communications Processor
*/
#ifndef __INCm8260CpmMuxh
#define __INCm8260CpmMuxh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8; /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#endif /* M8260ABBREVIATIONS */
/*
* MPC8260 internal register/memory map (section 17 of prelim. spec)
* note that these are offsets from the value stored in the IMMR
* register. Also note that in the MPC8260, the IMMR is not a special
* purpose register, but it is memory mapped.
*/
/* CPM mux FCC clock route register */
#define M8260_CMXFCR(base) (CAST(VUINT32 *)((base) + 0x11B04))
/* CPM mux SCC clock route register */
#define M8260_CMXSCR(base) (CAST(VUINT32 *)((base) + 0x11B08))
/* CMX FCC Clock Route Register bit definition (CMXFCR - 0x11B04) */
#define M8260_CMXFCR_GR1 0x80000000 /* Grant Support of FCC1 */
#define M8260_CMXFCR_FC1_MUX 0x40000000 /* FCC1 Connection - mux SI */
#define M8260_CMXFCR_R1CS_MSK 0x38000000 /* FCC1 Receive Clock Source */
#define M8260_CMXFCR_R1CS_BRG5 0x00000000 /* BRG5 clock source */
#define M8260_CMXFCR_R1CS_BRG6 0x08000000 /* BRG6 clock source */
#define M8260_CMXFCR_R1CS_BRG7 0x10000000 /* BRG7 clock source */
#define M8260_CMXFCR_R1CS_BRG8 0x18000000 /* BRG8 clock source */
#define M8260_CMXFCR_R1CS_CLK9 0x20000000 /* CLK9 clock source */
#define M8260_CMXFCR_R1CS_CLK10 0x28000000 /* CLK10 clock source */
#define M8260_CMXFCR_R1CS_CLK11 0x30000000 /* CLK11 clock source */
#define M8260_CMXFCR_R1CS_CLK12 0x38000000 /* CLK12 clock source */
#define M8260_CMXFCR_T1CS_MSK 0x07000000 /* FCC1 Transmit Clock Source */
#define M8260_CMXFCR_T1CS_BRG5 0x00000000 /* BRG5 clock source */
#define M8260_CMXFCR_T1CS_BRG6 0x01000000 /* BRG6 clock source */
#define M8260_CMXFCR_T1CS_BRG7 0x02000000 /* BRG7 clock source */
#define M8260_CMXFCR_T1CS_BRG8 0x03000000 /* BRG8 clock source */
#define M8260_CMXFCR_T1CS_CLK9 0x04000000 /* CLK9 clock source */
#define M8260_CMXFCR_T1CS_CLK10 0x05000000 /* CLK10 clock source */
#define M8260_CMXFCR_T1CS_CLK11 0x06000000 /* CLK11 clock source */
#define M8260_CMXFCR_T1CS_CLK12 0x07000000 /* CLK12 clock source */
#define M8260_CMXFCR_GR2 0x00800000 /* Grant Support of FCC2 */
#define M8260_CMXFCR_FC2_MUX 0x00400000 /* FCC2 Connection - mux SI */
#define M8260_CMXFCR_R2CS_MSK 0x00380000 /* FCC2 Receive Clock Source */
#define M8260_CMXFCR_R2CS_BRG5 0x00000000 /* BRG5 clock source */
#define M8260_CMXFCR_R2CS_BRG6 0x00080000 /* BRG6 clock source */
#define M8260_CMXFCR_R2CS_BRG7 0x00100000 /* BRG7 clock source */
#define M8260_CMXFCR_R2CS_BRG8 0x00180000 /* BRG8 clock source */
#define M8260_CMXFCR_R2CS_CLK13 0x00200000 /* CLK13 clock source */
#define M8260_CMXFCR_R2CS_CLK14 0x00280000 /* CLK14 clock source */
#define M8260_CMXFCR_R2CS_CLK15 0x00300000 /* CLK15 clock source */
#define M8260_CMXFCR_R2CS_CLK16 0x00380000 /* CLK16 clock source */
#define M8260_CMXFCR_T2CS_MSK 0x00070000 /* FCC2 Transmit Clock Source */
#define M8260_CMXFCR_T2CS_BRG5 0x00000000 /* BRG5 clock source */
#define M8260_CMXFCR_T2CS_BRG6 0x00010000 /* BRG6 clock source */
#define M8260_CMXFCR_T2CS_BRG7 0x00020000 /* BRG7 clock source */
#define M8260_CMXFCR_T2CS_BRG8 0x00030000 /* BRG8 clock source */
#define M8260_CMXFCR_T2CS_CLK13 0x00040000 /* CLK13 clock source */
#define M8260_CMXFCR_T2CS_CLK14 0x00050000 /* CLK14 clock source */
#define M8260_CMXFCR_T2CS_CLK15 0x00060000 /* CLK15 clock source */
#define M8260_CMXFCR_T2CS_CLK16 0x00070000 /* CLK16 clock source */
#define M8260_CMXFCR_GR3 0x00008000 /* Grant Support of FCC3 */
#define M8260_CMXFCR_FC3_MUX 0x00004000 /* FCC3 Connection - mux SI */
#define M8260_CMXFCR_R3CS_MSK 0x00003800 /* FCC3 Receive Clock Source */
#define M8260_CMXFCR_R3CS_BRG5 0x00000000 /* BRG5 clock source */
#define M8260_CMXFCR_R3CS_BRG6 0x00000800 /* BRG6 clock source */
#define M8260_CMXFCR_R3CS_BRG7 0x00001000 /* BRG7 clock source */
#define M8260_CMXFCR_R3CS_BRG8 0x00001800 /* BRG8 clock source */
#define M8260_CMXFCR_R3CS_CLK13 0x00002000 /* CLK13 clock source */
#define M8260_CMXFCR_R3CS_CLK14 0x00002800 /* CLK14 clock source */
#define M8260_CMXFCR_R3CS_CLK15 0x00003000 /* CLK15 clock source */
#define M8260_CMXFCR_R3CS_CLK16 0x00003800 /* CLK16 clock source */
#define M8260_CMXFCR_T3CS_MSK 0x00000700 /* FCC3 Transmit Clock Source */
#define M8260_CMXFCR_T3CS_BRG5 0x00000000 /* BRG5 clock source */
#define M8260_CMXFCR_T3CS_BRG6 0x00000100 /* BRG6 clock source */
#define M8260_CMXFCR_T3CS_BRG7 0x00000200 /* BRG7 clock source */
#define M8260_CMXFCR_T3CS_BRG8 0x00000300 /* BRG8 clock source */
#define M8260_CMXFCR_T3CS_CLK13 0x00000400 /* CLK13 clock source */
#define M8260_CMXFCR_T3CS_CLK14 0x00000500 /* CLK14 clock source */
#define M8260_CMXFCR_T3CS_CLK15 0x00000600 /* CLK15 clock source */
#define M8260_CMXFCR_T3CS_CLK16 0x00000700 /* CLK16 clock source */
/* CMX SCC Clock Route Register bit definition (CMXSCR - 0x11B08) */
#define M8260_CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
#define M8260_CMXSCR_SC1_MUX 0x40000000 /* SCC1 Connection - mux SI */
#define M8260_CMXSCR_R1CS_MSK 0x38000000 /* SCC1 Receive Clock Source */
#define M8260_CMXSCR_R1CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_R1CS_BRG2 0x08000000 /* BRG2 clock source */
#define M8260_CMXSCR_R1CS_BRG3 0x10000000 /* BRG3 clock source */
#define M8260_CMXSCR_R1CS_BRG4 0x18000000 /* BRG4 clock source */
#define M8260_CMXSCR_R1CS_CLK11 0x20000000 /* CLK11 clock source */
#define M8260_CMXSCR_R1CS_CLK12 0x28000000 /* CLK12 clock source */
#define M8260_CMXSCR_R1CS_CLK3 0x30000000 /* CLK3 clock source */
#define M8260_CMXSCR_R1CS_CLK4 0x38000000 /* CLK4 clock source */
#define M8260_CMXSCR_T1CS_MSK 0x07000000 /* SCC1 Transmit Clock Source */
#define M8260_CMXSCR_T1CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_T1CS_BRG2 0x01000000 /* BRG2 clock source */
#define M8260_CMXSCR_T1CS_BRG3 0x02000000 /* BRG3 clock source */
#define M8260_CMXSCR_T1CS_BRG4 0x03000000 /* BRG4 clock source */
#define M8260_CMXSCR_T1CS_CLK11 0x04000000 /* CLK11 clock source */
#define M8260_CMXSCR_T1CS_CLK12 0x05000000 /* CLK12 clock source */
#define M8260_CMXSCR_T1CS_CLK3 0x06000000 /* CLK3 clock source */
#define M8260_CMXSCR_T1CS_CLK4 0x07000000 /* CLK4 clock source */
#define M8260_CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
#define M8260_CMXSCR_SC2_MUX 0x00400000 /* SCC2 Connection - mux SI */
#define M8260_CMXSCR_R2CS_MSK 0x00380000 /* SCC2 Receive Clock Source */
#define M8260_CMXSCR_R2CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_R2CS_BRG2 0x00080000 /* BRG2 clock source */
#define M8260_CMXSCR_R2CS_BRG3 0x00100000 /* BRG3 clock source */
#define M8260_CMXSCR_R2CS_BRG4 0x00180000 /* BRG4 clock source */
#define M8260_CMXSCR_R2CS_CLK11 0x00200000 /* CLK11 clock source */
#define M8260_CMXSCR_R2CS_CLK12 0x00280000 /* CLK12 clock source */
#define M8260_CMXSCR_R2CS_CLK3 0x00300000 /* CLK3 clock source */
#define M8260_CMXSCR_R2CS_CLK4 0x00380000 /* CLK4 clock source */
#define M8260_CMXSCR_T2CS_MSK 0x00070000 /* SCC2 Transmit Clock Source */
#define M8260_CMXSCR_T2CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_T2CS_BRG2 0x00010000 /* BRG2 clock source */
#define M8260_CMXSCR_T2CS_BRG3 0x00020000 /* BRG3 clock source */
#define M8260_CMXSCR_T2CS_BRG4 0x00030000 /* BRG4 clock source */
#define M8260_CMXSCR_T2CS_CLK11 0x00040000 /* CLK11 clock source */
#define M8260_CMXSCR_T2CS_CLK12 0x00050000 /* CLK12 clock source */
#define M8260_CMXSCR_T2CS_CLK3 0x00060000 /* CLK3 clock source */
#define M8260_CMXSCR_T2CS_CLK4 0x00070000 /* CLK4 clock source */
#define M8260_CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
#define M8260_CMXSCR_SC3_MUX 0x00004000 /* SCC3 Connection - mux SI */
#define M8260_CMXSCR_R3CS_MSK 0x00003800 /* SCC3 Receive Clock Source */
#define M8260_CMXSCR_R3CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_R3CS_BRG2 0x00000800 /* BRG2 clock source */
#define M8260_CMXSCR_R3CS_BRG3 0x00001000 /* BRG3 clock source */
#define M8260_CMXSCR_R3CS_BRG4 0x00001800 /* BRG4 clock source */
#define M8260_CMXSCR_R3CS_CLK5 0x00002000 /* CLK5 clock source */
#define M8260_CMXSCR_R3CS_CLK6 0x00002800 /* CLK6 clock source */
#define M8260_CMXSCR_R3CS_CLK7 0x00003000 /* CLK7 clock source */
#define M8260_CMXSCR_R3CS_CLK8 0x00003800 /* CLK8 clock source */
#define M8260_CMXSCR_T3CS_MSK 0x00000700 /* SCC3 Transmit Clock Source */
#define M8260_CMXSCR_T3CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_T3CS_BRG2 0x00000100 /* BRG2 clock source */
#define M8260_CMXSCR_T3CS_BRG3 0x00000200 /* BRG3 clock source */
#define M8260_CMXSCR_T3CS_BRG4 0x00000300 /* BRG4 clock source */
#define M8260_CMXSCR_T3CS_CLK5 0x00000400 /* CLK5 clock source */
#define M8260_CMXSCR_T3CS_CLK6 0x00000500 /* CLK6 clock source */
#define M8260_CMXSCR_T3CS_CLK7 0x00000600 /* CLK7 clock source */
#define M8260_CMXSCR_T3CS_CLK8 0x00000700 /* CLK8 clock source */
#define M8260_CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
#define M8260_CMXSCR_SC4_MUX 0x00000040 /* SCC4 Connection - mux SI */
#define M8260_CMXSCR_R4CS_MSK 0x00000038 /* SCC4 Receive Clock Source */
#define M8260_CMXSCR_R4CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_R4CS_BRG2 0x00000008 /* BRG2 clock source */
#define M8260_CMXSCR_R4CS_BRG3 0x00000010 /* BRG3 clock source */
#define M8260_CMXSCR_R4CS_BRG4 0x00000018 /* BRG4 clock source */
#define M8260_CMXSCR_R4CS_CLK1 0x00000020 /* CLK1 clock source */
#define M8260_CMXSCR_R4CS_CLK2 0x00000028 /* CLK2 clock source */
#define M8260_CMXSCR_R4CS_CLK3 0x00000030 /* CLK3 clock source */
#define M8260_CMXSCR_R4CS_CLK4 0x00000038 /* CLK4 clock source */
#define M8260_CMXSCR_T4CS_MSK 0x00000007 /* SCC4 Transmit Clock Source */
#define M8260_CMXSCR_T4CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSCR_T4CS_BRG2 0x00000001 /* BRG2 clock source */
#define M8260_CMXSCR_T4CS_BRG3 0x00000002 /* BRG3 clock source */
#define M8260_CMXSCR_T4CS_BRG4 0x00000003 /* BRG4 clock source */
#define M8260_CMXSCR_T4CS_CLK1 0x00000004 /* CLK1 clock source */
#define M8260_CMXSCR_T4CS_CLK2 0x00000005 /* CLK2 clock source */
#define M8260_CMXSCR_T4CS_CLK3 0x00000006 /* CLK3 clock source */
#define M8260_CMXSCR_T4CS_CLK4 0x00000007 /* CLK4 clock source */
/* CMX SMC Clock Route Register bit definition (CMXSMR - 0x11B0C) */
#define M8260_CMXSMR_SMC1_MUX 0x80000000 /* SMC1 Connection mux*/
#define M8260_CMXSMR_SMC1CS_MSK 0x30000000 /* SMC1 Clock Source */
#define M8260_CMXSMR_SMC1CS_BRG1 0x00000000 /* BRG1 clock source */
#define M8260_CMXSMR_SMC1CS_BRG7 0x10000000 /* BRG7 clock source */
#define M8260_CMXSMR_SMC1CS_CLK7 0x20000000 /* CLK7 clock source */
#define M8260_CMXSMR_SMC1CS_CLK9 0x30000000 /* CLK9 clock source */
#define M8260_CMXSMR_SMC2_MUX 0x08000000 /* SMC2 Connection mux*/
#define M8260_CMXSMR_SMC2CS_MSK 0x03000000 /* SMC2 Clock Source */
#define M8260_CMXSMR_SMC2CS_BRG2 0x00000000 /* BRG2 clock source */
#define M8260_CMXSMR_SMC2CS_BRG8 0x01000000 /* BRG8 clock source */
#define M8260_CMXSMR_SMC2CS_CLK19 0x02000000 /* CLK19 clock source */
#define M8260_CMXSMR_SMC2CS_CLK20 0x03000000 /* CLK20 clock source */
#ifdef __cplusplus
}
#endif
#endif /* __INCm8260CpmMuxh */
vxworks-6.9/target/h/drv/sio/m8260Scc.h
+271
View File
@@ -0,0 +1,271 @@
/* m8260Scc.h - Motorola MPC8260 Serial Communications Controller header file */
/* Copyright 1984-1999 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,12sep99,ms_ created from m8260Cpm.h, 01d.
*/
/*
* This file contains constants for the Serial Communications Controllers
* (SCCs) in the Motorola MPC8260 PowerQUICC II integrated Communications
* Processor
*/
#ifndef __INCm8260Scch
#define __INCm8260Scch
#ifdef __cplusplus
extern "C" {
#endif
#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8; /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#endif /* M8260ABBREVIATIONS */
/*
* MPC8260 internal register/memory map (section 17 of prelim. spec)
* note that these are offsets from the value stored in the IMMR
* register. Also note that in the MPC8260, the IMMR is not a special
* purpose register, but it is memory mapped.
*/
/* SCC Parameter Ram */
#define M8260_SCC_PRAM_BASE 0x00008000
#define M8260_SCC_PRAM_OFFSET_NEXT_PRAM 0x00000100
#define M8260_SCC_PRAM_RBASE 0x00000000
#define M8260_SCC_PRAM_TBASE 0x00000002
#define M8260_SCC_PRAM_RFCR 0x00000004
#define M8260_SCC_PRAM_TFCR 0x00000005
#define M8260_SCC_PRAM_MRBLR 0x00000006
#define M8260_SCC_UART_PRAM_PAREC 0x0000003E
#define M8260_SCC_UART_PRAM_FRMEC 0x00000040
#define M8260_SCC_UART_PRAM_NOSEC 0x00000042
#define M8260_SCC_UART_PRAM_BRKEC 0x00000044
/* SCC - Serial Communication Controller */
#define M8260_SCC_BASE 0x00011A00
#define M8260_SCC_OFFSET_NEXT_SCC 0x00000020
#define M8260_GSMR_L_OFFSET 0x00000000
#define M8260_GSMR_H_OFFSET 0x00000004
#define M8260_PSMR_OFFSET 0x00000008
#define M8260_TODR_OFFSET 0x0000000C
#define M8260_DSR_OFFSET 0x0000000E
#define M8260_SCCE_OFFSET 0x00000010
#define M8260_SCCM_OFFSET 0x00000014
#define M8260_SCCS_OFFSET 0x00000017
/* General SCC Mode Register definitions */
#define M8260_SCC_GSMRL_HDLC 0x00000000 /* HDLC mode */
/* AppleTalk mode (LocalTalk) */
#define M8260_SCC_GSMRL_APPLETALK 0x00000002
/* SS7 mode (microcode) */
#define M8260_SCC_GSMRL_SS7 0x00000003
#define M8260_SCC_GSMRL_UART 0x00000004 /* UART mode */
/* Profi-Bus mode (microcode) */
#define M8260_SCC_GSMRL_PROFI_BUS 0x00000005
/* async HDLC mode (microcode)*/
#define M8260_SCC_GSMRL_ASYNC_HDLC 0x00000006
#define M8260_SCC_GSMRL_V14 0x00000007 /* V.14 mode */
#define M8260_SCC_GSMRL_BISYNC 0x00000008 /* BISYNC mode */
/* DDCMP mode (microcode) */
#define M8260_SCC_GSMRL_DDCMP 0x00000009
/* enable bits for transmit and receive */
#define M8260_SCC_GSMRL_ENT 0x00000010 /* enable transmitter */
#define M8260_SCC_GSMRL_ENR 0x00000020 /* enable receiver */
/* local loopback mode */
#define M8260_SCC_GSMRL_LOOPBACK 0x00000040
/* automatic echo mode */
#define M8260_SCC_GSMRL_ECHO 0x00000080
/* transmitter encoding method*/
#define M8260_SCC_GSMRL_TENC 0x00000700
/* receiver encoding method */
#define M8260_SCC_GSMRL_RENC 0x00003800
/* receive DPLL clock x8 */
#define M8260_SCC_GSMRL_RDCR_X8 0x00004000
/* receive DPLL clock x16 */
#define M8260_SCC_GSMRL_RDCR_X16 0x00008000
/* receive DPLL clock x32 */
#define M8260_SCC_GSMRL_RDCR_X32 0x0000c000
/* transmit DPLL clock x8 */
#define M8260_SCC_GSMRL_TDCR_X8 0x00010000
/* transmit DPLL clock x16 */
#define M8260_SCC_GSMRL_TDCR_X16 0x00020000
/* transmit DPLL clock x32 */
#define M8260_SCC_GSMRL_TDCR_X32 0x00030000
#define M8260_SCC_GSMRL_TEND 0x00040000 /* transmitter frame ending */
#define M8260_SCC_GSMRL_TPP_00 0x00180000 /* Tx preamble pattern = 00 */
#define M8260_SCC_GSMRL_TPP_10 0x00080000 /* Tx preamble pattern = 10 */
#define M8260_SCC_GSMRL_TPP_01 0x00100000 /* Tx preamble pattern = 01 */
#define M8260_SCC_GSMRL_TPP_11 0x00180000 /* Tx preamble pattern = 11 */
/* no Tx preamble (default) */
#define M8260_SCC_GSMRL_TPL_NONE 0x00000000
/* Tx preamble = 1 byte */
#define M8260_SCC_GSMRL_TPL_8 0x00200000
#define M8260_SCC_GSMRL_TPL_16 0x00400000 /* Tx preamble = 2 bytes */
#define M8260_SCC_GSMRL_TPL_32 0x00600000 /* Tx preamble = 4 bytes */
#define M8260_SCC_GSMRL_TPL_48 0x00800000 /* Tx preamble = 6 bytes */
#define M8260_SCC_GSMRL_TPL_64 0x00a00000 /* Tx preamble = 8 bytes */
#define M8260_SCC_GSMRL_TPL_128 0x00c00000 /* Tx preamble = 16 bytes */
#define M8260_SCC_GSMRL_TINV 0x01000000 /* DPLL transmit input invert */
#define M8260_SCC_GSMRL_RINV 0x02000000 /* DPLL receive input invert */
#define M8260_SCC_GSMRL_TSNC 0x0c000000 /* transmit sense */
#define M8260_SCC_GSMRL_TCI 0x10000000 /* transmit clock invert */
#define M8260_SCC_GSMRL_EDGE 0x60000000 /* adjustment edge +/- */
#define M8260_SCC_GSMRH_RSYN 0x00000001 /* receive sync timing*/
#define M8260_SCC_GSMRH_RTSM 0x00000002 /* RTS* mode */
#define M8260_SCC_GSMRH_SYNL 0x0000000c /* sync length */
#define M8260_SCC_GSMRH_TXSY 0x00000010 /* transmitter/receiver sync */
#define M8260_SCC_GSMRH_RFW 0x00000020 /* Rx FIFO width */
#define M8260_SCC_GSMRH_TFL 0x00000040 /* transmit FIFO length */
#define M8260_SCC_GSMRH_CTSS 0x00000080 /* CTS* sampling */
#define M8260_SCC_GSMRH_CDS 0x00000100 /* CD* sampling */
#define M8260_SCC_GSMRH_CTSP 0x00000200 /* CTS* pulse */
#define M8260_SCC_GSMRH_CDP 0x00000400 /* CD* pulse */
#define M8260_SCC_GSMRH_TTX 0x00000800 /* transparent transmitter */
#define M8260_SCC_GSMRH_TRX 0x00001000 /* transparent receiver */
#define M8260_SCC_GSMRH_REVD 0x00002000 /* reverse data */
#define M8260_SCC_GSMRH_TCRC 0x0000c000 /* transparent CRC */
#define M8260_SCC_GSMRH_GDE 0x00010000 /* glitch detect enable */
/* SCC UART Protocol Specific Mode Register definitions */
#define M8260_SCC_UART_PSMR_TPM_ODD 0x0000 /* odd parity mode (Tx) */
#define M8260_SCC_UART_PSMR_TPM_LOW 0x0001 /* low parity mode (Tx) */
#define M8260_SCC_UART_PSMR_TPM_EVEN 0x0002 /* even parity mode (Tx) */
#define M8260_SCC_UART_PSMR_TPM_HIGH 0x0003 /* high parity mode (Tx) */
#define M8260_SCC_UART_PSMR_RPM_ODD 0x0000 /* odd parity mode (Rx) */
#define M8260_SCC_UART_PSMR_RPM_LOW 0x0004 /* low parity mode (Rx) */
#define M8260_SCC_UART_PSMR_RPM_EVEN 0x0008 /* even parity mode (Rx) */
#define M8260_SCC_UART_PSMR_RPM_HIGH 0x000c /* high parity mode (Rx) */
#define M8260_SCC_UART_PSMR_PEN 0x0010 /* parity enable */
#define M8260_SCC_UART_PSMR_DRT 0x0040 /* disable Rx while Tx */
#define M8260_SCC_UART_PSMR_SYN 0x0080 /* synchronous mode */
#define M8260_SCC_UART_PSMR_RZS 0x0100 /* receive zero stop bits */
#define M8260_SCC_UART_PSMR_FRZ 0x0200 /* freeze transmission */
#define M8260_SCC_UART_PSMR_UM_NML 0x0000 /* noraml UART operation */
#define M8260_SCC_UART_PSMR_UM_MULT_M 0x0400 /* multidrop non-auto mode */
#define M8260_SCC_UART_PSMR_UM_MULT_A 0x0c00 /* multidrop automatic mode */
#define M8260_SCC_UART_PSMR_CL_5BIT 0x0000 /* 5 bit character length */
#define M8260_SCC_UART_PSMR_CL_6BIT 0x1000 /* 6 bit character length */
#define M8260_SCC_UART_PSMR_CL_7BIT 0x2000 /* 7 bit character length */
#define M8260_SCC_UART_PSMR_CL_8BIT 0x3000 /* 8 bit character length */
#define M8260_SCC_UART_PSMR_SL 0x4000 /* 1 or 2 bit stop length */
#define M8260_SCC_UART_PSMR_FLC 0x8000 /* flow control */
/* SCC UART Event and Mask Register definitions */
#define M8260_SCC_UART_SCCX_RX 0x0001 /* buffer received */
#define M8260_SCC_UART_SCCX_TX 0x0002 /* buffer transmitted */
#define M8260_SCC_UART_SCCX_BSY 0x0004 /* busy condition */
#define M8260_SCC_UART_SCCX_CCR 0x0008 /* control character received */
#define M8260_SCC_UART_SCCX_BRK_S 0x0020 /* break start */
#define M8260_SCC_UART_SCCX_BRK_E 0x0040 /* break end */
#define M8260_SCC_UART_SCCX_GRA 0x0080 /* graceful stop complete */
#define M8260_SCC_UART_SCCX_IDL 0x0100 /* idle sequence stat changed */
#define M8260_SCC_UART_SCCX_AB 0x0200 /* autobaud lock */
#define M8260_SCC_UART_SCCX_GL_T 0x0800 /* glitch on Tx */
#define M8260_SCC_UART_SCCX_GL_R 0x1000 /* glitch on Rx */
#define M8260_SCC_UART_SCCX_ALL_EVENTS 0xFFFF /* all events */
/* SCC UART Receive Buffer Descriptor definitions */
#define M8260_SCC_UART_RX_BD_CD 0x0001 /* carrier detect loss */
#define M8260_SCC_UART_RX_BD_OV 0x0002 /* receiver overrun */
#define M8260_SCC_UART_RX_BD_PR 0x0008 /* parity error */
#define M8260_SCC_UART_RX_BD_FR 0x0010 /* framing error */
#define M8260_SCC_UART_RX_BD_BR 0x0020 /* break received */
#define M8260_SCC_UART_RX_BD_AM 0x0080 /* address match */
#define M8260_SCC_UART_RX_BD_ID 0x0100 /* buf closed on IDLES */
#define M8260_SCC_UART_RX_BD_CM 0x0200 /* continous mode */
#define M8260_SCC_UART_RX_BD_ADDR 0x0400 /* buffer contains address */
#define M8260_SCC_UART_RX_BD_CNT 0x0800 /* control character */
#define M8260_SCC_UART_RX_BD_INT 0x1000 /* interrupt generated */
#define M8260_SCC_UART_RX_BD_WRAP 0x2000 /* wrap back to first BD */
#define M8260_SCC_UART_RX_BD_EMPTY 0x8000 /* buffer is empty */
/* SCC UART Transmit Buffer Descriptor definitions */
#define M8260_SCC_UART_TX_BD_CT 0x0001 /* cts was lost during tx */
#define M8260_SCC_UART_TX_BD_NS 0x0080 /* no stop bit transmitted */
#define M8260_SCC_UART_TX_BD_PREAMBLE 0x0100 /* enable preamble */
#define M8260_SCC_UART_TX_BD_CM 0x0200 /* continous mode */
#define M8260_SCC_UART_TX_BD_ADDR 0x0400 /* buffer contains address */
#define M8260_SCC_UART_TX_BD_CTSR 0x0800 /* normal cts error reporting */
#define M8260_SCC_UART_TX_BD_INT 0x1000 /* interrupt generated */
#define M8260_SCC_UART_TX_BD_WRAP 0x2000 /* wrap back to first BD */
#define M8260_SCC_UART_TX_BD_READY 0x8000 /* buffer is being sent */
/* Miscellaneous SCC UART definitions */
#define M8260_SCC_POLL_OUT_DELAY 10000 /* polled mode delay */
#ifdef __cplusplus
}
#endif
#endif /* __INCm8260Scch */
vxworks-6.9/target/h/drv/sio/m8260Sio.h
+117
View File
@@ -0,0 +1,117 @@
/* m8260Sio.h - Motorola MPC8260 SIO header file */
/* Copyright 1984-2002, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01f,29apr10,pad Moved extern C statement after include statements.
01e,05jun02,pmr SPR 78051: fixed typo
01d,09may02,gjc Fixing SPR #75922.
01c,12sep99,ms_ move I/O Port definitions to m8260IOPort.h
01b,15jul99,ms_ fix to meet coding standards
01a,08mar99,ms_ adapted from h/drv/multi/ppc860Cpm.h
*/
/*
* This file contains constants for an SIO using the Serial
* Communications Controller (SCC) of the Communications Processor
* Module (CPM) of the Motorola MPC8260 PowerPC microcontroller.
*/
#ifndef __INCm8260Sioh
#define __INCm8260Sioh
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define DEFAULT_BAUD 9600
#ifndef SCC_BUF
#define SCC_BUF VINT8 /* byte so that offset works */
#endif
typedef struct
{
/* must be first */
SIO_DRV_FUNCS *pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (* getTxChar) (); /* pointer to xmit function */
STATUS (* putRcvChar) (); /* pointer to recv function */
void * getTxArg;
void * putRcvArg;
VINT16 channelMode; /* polled or interrupt driven */
int baudRate;
int sccNum; /* SCC associated with this channel */
VINT32 immrVal; /* Internal Memory Map Register */
char * pBdBase; /* Buffer Descriptor base */
char * rcvBufferAddr; /* address of receive buffer */
char * txBufferAddr; /* address of transmit buffer */
char ch;
VINT16 * pRBASE;
VINT16 * pTBASE;
} M8260_SCC_CHAN;
#define M8260_SCC_BD_SIZE 8 /* size, in bytes, of a single BD */
#define M8260_SCC_RCV_BD_OFF 0 /* offset from BD base to receive BD */
#define M8260_SCC_TX_BD_OFF M8260_SCC_BD_SIZE
/* offset from BD base to transmit BD, since there is just one BD each */
#define M8260_SCC_BD_STAT_OFF 0 /* offset to status field */
#define M8260_SCC_BD_LEN_OFF 2 /* offset to data length field */
#define M8260_SCC_BD_ADDR_OFF 4 /* offset to address pointer field */
#define M8260_SCC_NEXT_SCC_OFF 0x20 /* offset between SCCs */
#define M8260_SCC_32_WR(addr, value) (* ((UINT32 *)(addr)) = ((UINT32) (value)))
#define M8260_SCC_16_WR(addr, value) (* ((UINT16 *)(addr)) = ((UINT16) (value)))
#define M8260_SCC_8_WR(addr, value) (* ((UINT8 *)(addr)) = ((UINT8) (value)))
#define M8260_SCC_32_RD(addr, value) ((value) = (* (UINT32 *) ((UINT32 *)(addr))))
#define M8260_SCC_16_RD(addr, value) ((value) = (* (UINT16 *) ((UINT16 *)(addr))))
#define M8260_SCC_8_RD(addr, value) ((value) = (* (UINT8 *) ((UINT8 *)(addr))))
#if defined(__STDC__)
IMPORT void m8260SioDevInit (M8260_SCC_CHAN *);
IMPORT void m8260SioInt (M8260_SCC_CHAN *);
IMPORT UINT32 vxImmrGet (void);
#else /* __STDC__ */
IMPORT void m8260SioDevInit ();
IMPORT void m8260SioInt ();
IMPORT UINT32 vxImmrGet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCm8260Sioh */
vxworks-6.9/target/h/drv/sio/mb86940Sio.h
+75
View File
@@ -0,0 +1,75 @@
/* mb86940.h - Fujitsu SPARClite companion chip */
/* Copyright 1984-1991, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,29apr10,pad Moved extern C statement after include statements.
01a,31jul95,myz written
*/
/*
This file contains SIO data structures for the Fujitsu mb86940 companion chip.
*/
#ifndef __INCmb86940Sioh
#define __INCmb86940Sioh
#include "arch/sparc/mb86940.h"
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct MB86940_CHAN
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar) ();
STATUS (*putRcvChar) ();
void * getTxArg;
void * putRcvArg;
USHORT channelMode;
USHORT chan_num;
int baudRate;
volatile int *cp; /* control port I/O address */
volatile int *dp; /* data port I/O address */
USHORT txIntLevel;
USHORT rxIntLevel;
USHORT txIntVec;
USHORT rxIntVec;
UINT (*asiGeth) (void * );
void (*asiSeth) (void * , UINT );
STATUS (*baudSet) (int );
STATUS (*intEnable)(int);
STATUS (*intDisable)(int);
} MB86940_CHAN;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void mb86940DevInit (MB86940_CHAN *);
extern void mb86940IntRx (MB86940_CHAN *);
extern void mb86940IntTx (MB86940_CHAN *);
#else /* __STDC__ */
extern void mb86940DevInit ();
extern void mb86940IntRx ();
extern void mb86940IntTx ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* __INCmb86940h */
vxworks-6.9/target/h/drv/sio/ns16552Sio.h
+215
View File
@@ -0,0 +1,215 @@
/* ns16552.h - National Semiconductor 16552 DUART header file */
/* Copyright (c) 1995-2005, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,29apr10,pad Moved extern C statement after include statements.
01g,09nov05,mdo SPR#107022 - remove unnecessary padding.
01f,07sep04,mdo Documentation fixes for apigen
01e,11may04,rec remove manual errors
01d,12apr00,dra Add include of sioLib.h
01c,08may97,db added elements options and mcr to NS16550_CHAN structure to
implement hardware options & modem control(SPRs #7570, #7082).
01b,01nov95,myz removed #if CPU=I960XX ... in NS16550_CHAN structure
01a,24oct95,myz written from ns16552.h.
*/
#ifndef __INCns16552Sioh
#define __INCns16552Sioh
/*
*********************************************************************
* Copyright (c) 1990,1991 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and
* distribute this software and its documentation. Intel grants
* this permission provided that the above copyright notice
* appears in all copies and that both the copyright notice and
* this permission notice appear in supporting documentation. In
* addition, Intel grants this permission provided that you
* prominently mark as not part of the original any modifications
* made to this software or documentation, and that the name of
* Intel Corporation not be used in advertising or publicity
* pertaining to distribution of the software or the documentation
* without specific, written prior permission.
*
* Intel Corporation does not warrant, guarantee or make any
* representations regarding the use of, or the results of the use
* of, the software and documentation in terms of correctness,
* accuracy, reliability, currentness, or otherwise; and you rely
* on the software, documentation and results solely at your own risk.
*
*\NOMANUAL
**********************************************************************
*/
/*
******************************************************************************
*
* REGISTER DESCRIPTION OF NATIONAL 16552 DUART
*
* $Id: ns16552.h,v 2.1 1993/06/07 15:07:59 wise active $
*
*\NOMANUAL
*******************************************************************************
*/
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Register offsets from base address */
#define RBR 0x00 /* receiver buffer register */
#define THR 0x00 /* transmit holding register */
#define DLL 0x00 /* divisor latch */
#define IER 0x01 /* interrupt enable register */
#define DLM 0x01 /* divisor latch(MS) */
#define IIR 0x02 /* interrupt identification register */
#define FCR 0x02 /* FIFO control register */
#define LCR 0x03 /* line control register */
#define MCR 0x04 /* modem control register */
#define LSR 0x05 /* line status register */
#define MSR 0x06 /* modem status register */
#define SCR 0x07 /* scratch register */
#define BAUD_LO(baud) ((XTAL/(16*baud)) & 0xff)
#define BAUD_HI(baud) (((XTAL/(16*baud)) & 0xff00) >> 8)
/* Line Control Register */
#define CHAR_LEN_5 0x00 /* 5bits data size */
#define CHAR_LEN_6 0x01 /* 6bits data size */
#define CHAR_LEN_7 0x02 /* 7bits data size */
#define CHAR_LEN_8 0x03 /* 8bits data size */
#define LCR_STB 0x04 /* 2 stop bits */
#define ONE_STOP 0x00 /* one stop bit */
#define LCR_PEN 0x08 /* parity enable */
#define PARITY_NONE 0x00 /* parity disable */
#define LCR_EPS 0x10 /* even parity select */
#define LCR_SP 0x20 /* stick parity select */
#define LCR_SBRK 0x40 /* break control bit */
#define LCR_DLAB 0x80 /* divisor latch access enable */
#define DLAB LCR_DLAB
/* Line Status Register */
#define LSR_DR 0x01 /* data ready */
#define RxCHAR_AVAIL LSR_DR /* data ready */
#define LSR_OE 0x02 /* overrun error */
#define LSR_PE 0x04 /* parity error */
#define LSR_FE 0x08 /* framing error */
#define LSR_BI 0x10 /* break interrupt */
#define LSR_THRE 0x20 /* transmit holding register empty */
#define LSR_TEMT 0x40 /* transmitter empty */
#define LSR_FERR 0x80 /* in fifo mode, set when PE,FE or BI error */
/* Interrupt Identification Register */
#define IIR_IP 0x01
#define IIR_ID 0x0e
#define IIR_RLS 0x06 /* received line status */
#define Rx_INT IIR_RLS /* received line status */
#define IIR_RDA 0x04 /* received data available */
#define RxFIFO_INT IIR_RDA /* received data available */
#define IIR_THRE 0x02 /* transmit holding register empty */
#define TxFIFO_INT IIR_THRE
#define IIR_MSTAT 0x00 /* modem status */
#define IIR_TIMEOUT 0x0c /* char receive timeout */
/* Interrupt Enable Register */
#define IER_ERDAI 0x01 /* received data avail. & timeout int */
#define RxFIFO_BIT IER_ERDAI
#define IER_ETHREI 0x02 /* transmitter holding register empty int */
#define TxFIFO_BIT IER_ETHREI
#define IER_ELSI 0x04 /* receiver line status int enable */
#define Rx_BIT IER_ELSI
#define IER_EMSI 0x08 /* modem status int enable */
/* Modem Control Register */
#define MCR_DTR 0x01 /* dtr output */
#define DTR MCR_DTR
#define MCR_RTS 0x02 /* rts output */
#define MCR_OUT1 0x04 /* output #1 */
#define MCR_OUT2 0x08 /* output #2 */
#define MCR_LOOP 0x10 /* loopback enable */
/* Modem Status Register */
#define MSR_DCTS 0x01 /* cts change */
#define MSR_DDSR 0x02 /* dsr change */
#define MSR_TERI 0x04 /* ring indicator change */
#define MSR_DDCD 0x08 /* data carrier indicator change */
#define MSR_CTS 0x10 /* complement of cts */
#define MSR_DSR 0x20 /* complement of dsr */
#define MSR_RI 0x40 /* complement of ring signal */
#define MSR_DCD 0x80 /* complement of dcd */
/* FIFO Control Register */
#define FCR_EN 0x01 /* enable xmit and rcvr */
#define FIFO_ENABLE FCR_EN
#define FCR_RXCLR 0x02 /* clears rcvr fifo */
#define RxCLEAR FCR_RXCLR
#define FCR_TXCLR 0x04 /* clears xmit fifo */
#define TxCLEAR FCR_TXCLR
#define FCR_DMA 0x08 /* dma */
#define FCR_RXTRIG_L 0x40 /* rcvr fifo trigger lvl low */
#define FCR_RXTRIG_H 0x80 /* rcvr fifo trigger lvl high */
typedef struct /* NS16550_CHAN * */
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar) (); /* pointer to xmitr function */
STATUS (*putRcvChar) (); /* pointer to rcvr function */
void * getTxArg;
void * putRcvArg;
UINT8 *regs; /* NS16552 registers */
UINT8 level; /* 8259a interrupt level for this device */
UINT8 ier; /* copy of ier */
UINT8 lcr; /* copy of lcr, not used by ns16552 driver */
UINT8 mcr; /* copy of modem control register */
UINT16 channelMode; /* such as INT, POLL modes */
UINT16 regDelta; /* register address spacing */
int baudRate;
UINT32 xtal; /* UART clock frequency */
UINT32 options; /* hardware setup options */
} NS16550_CHAN;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void ns16550Int (NS16550_CHAN *);
extern void ns16550DevInit (NS16550_CHAN *);
#else
extern void ns16550Int ();
extern void ns16550DevInit ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCns16552Sioh */
vxworks-6.9/target/h/drv/sio/ppc403Sio.h
+179
View File
@@ -0,0 +1,179 @@
/* ppc403Sio.h - header file for PPC403GA SPU driver */
/* Copyright 1984-1996, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,29apr10,pad Moved extern C statement after include statements.
01a,13feb96,tam written (from i8250Sio.h)
*/
#ifndef __INCppc403Sioh
#define __INCppc403Sioh
#ifndef _ASMLANGUAGE
#include "vxWorks.h"
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* channel data structure */
typedef struct PPC403_CHAN
{
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
STATUS (*getTxChar) ();
STATUS (*putRcvChar) ();
void * getTxArg;
void * putRcvArg;
UINT16 int_vec; /* interrupt vector number */
UCHAR (*inByte) (int); /* routine to read a byte from reg. */
void (*outByte)(int,char); /* routine to write a byte to reg. */
int baudRate; /* baud rate */
UINT32 clkFreq; /* baud rate generator clock */
uint_t mode; /* SIO_MODE_[INT | POLL] */
volatile char *spctl; /* spu control register */
volatile char *sphs; /* spu handshake status register */
volatile char *spls; /* spu line status register */
volatile char *sprb; /* spu receive buffer */
volatile char *sprc; /* spu receiver command register */
volatile char *sptb; /* spu transfer buffer */
volatile char *sptc; /* spu transfer command register */
} PPC403_CHAN;
#define _TY_RX_VEC 4
#define _TY_RX_INT_LVL 4
#define _TY_TX_VEC 5
#define _TY_TX_INT_LVL 5
#define DEFAULT_BAUD 9600 /* default uart baud rate */
/* register definitions */
/* memory mapped i/o registers */
#define _PPC403GA_SPLS 0x40000000 /* line status register read/clear */
#define _PPC403GA_SPHS 0x40000002 /* handshake status register r/clear */
#define _PPC403GA_BRDH 0x40000004 /* baudrate divisor high reg r/w */
#define _PPC403GA_BRDL 0x40000005 /* baudrate divisor low reg r/w */
#define _PPC403GA_SPCTL 0x40000006 /* control register r/w */
#define _PPC403GA_SPRC 0x40000007 /* receiver command register r/w */
#define _PPC403GA_SPTC 0x40000008 /* transmitter command register r/w */
#define _PPC403GA_SPRB 0x40000009 /* receive buffer r */
#define _PPC403GA_SPTB 0x40000009 /* transmit buffer w */
/* masks and definitions for serial port control register */
#define _SPCTL_LM_MASK 0xc0 /* loop back modes */
#define _SPCTL_DTR_MASK 0x20 /* data terminal ready 0-inactive */
#define _SPCTL_RTS_MASK 0x10 /* request to send 0-inactive */
#define _SPCTL_DB_MASK 0x08 /* data bits mask */
#define _SPCTL_PE_MASK 0x04 /* parity enable */
#define _SPCTL_PTY_MASK 0x02 /* parity */
#define _SPCTL_SB_MASK 0x01 /* stop bit mask */
#define _SPCTL_LM_NORM 0x00 /* normal operation */
#define _SPCTL_LM_LOOP 0x40 /* internal loopback mode */
#define _SPCTL_LM_ECHO 0x80 /* automatic echo mode */
#define _SPCTL_LM_RES 0xc0 /* reserved */
#define _SPCTL_DTR_ACTIVE _SPCTL_DTR_MASK /* DTR is active */
#define _SPCTL_RTS_ACTIVE _SPCTL_RTS_MASK /* RTS is active */
#define _SPCTL_DB_8_BITS _SPCTL_DB_MASK /* 8 data bits */
#define _SPCTL_DB_7_BITS 0x00 /* 7 data bits */
#define _SPCTL_PE_ENABLE _SPCTL_PE_MASK /* parity enabled */
#define _SPCTL_PTY_EVEN 0x00 /* even parity */
#define _SPCTL_PTY_ODD _SPCTL_PTY_MASK /* odd parity */
#define _SPCTL_SB_1_BIT 0x00 /* one stop bit */
#define _SPCTL_SB_2_BIT _SPCTL_SB_MASK /* two stop bit */
/* serial port handshake register */
#define _SPHS_DIS_MASK 0x80 /* DSR input inactive error mask */
#define _SPHS_CS_MASK 0x40 /* CTS input inactive error mask */
#define _SPHS_DIS_ACT 0x00 /* dsr input is active */
#define _SPHS_DIS_INACT _SPHS_DIS_MASK /* dsr input is inactive */
#define _SPHS_CS_ACT 0x00 /* cts input is active */
#define _SPHS_CS_INACT _SPHS_CS_MASK /* cts input is active */
/* serial port line status register */
#define _SPLS_RBR_MASK 0x80 /* receive buffer ready mask */
#define _SPLS_FE_MASK 0x40 /* framing error */
#define _SPLS_OE_MASK 0x20 /* overrun error */
#define _SPLS_PE_MASK 0x10 /* parity error */
#define _SPLS_LB_MASK 0x08 /* line break */
#define _SPLS_TBR_MASK 0x04 /* transmit buffer ready */
#define _SPLS_TSR_MASK 0x02 /* transmit shift register ready */
#define _SPLS_RBR_FULL _SPLS_RBR_MASK /* receive buffer is full */
#define _SPLS_FE_ERROR _SPLS_FE_MASK /* framing error detected */
#define _SPLS_OE_ERROR _SPLS_OE_MASK /* overrun error detected */
#define _SPLS_PE_ERROR _SPLS_PE_MASK /* parity error detected */
#define _SPLS_LB_BREAK _SPLS_LB_MASK /* line break detected */
#define _SPLS_TBR_EMPTY _SPLS_TBR_MASK /* transmit buffer is ready */
#define _SPLS_TSR_EMPTY _SPLS_TSR_MASK /* transmit shift register is empty */
#define _SPLS_RX_ERR (_SPLS_LB_BREAK | _SPLS_FE_MASK | _SPLS_OE_MASK | \
_SPLS_PE_MASK)
/* serial port reciever command register */
#define _SPRC_ER_MASK 0x80 /* enable receiver mask */
#define _SPRC_DME_MASK 0x60 /* dma mode */
#define _SPRC_EIE_MASK 0x10 /* error interrupt enable mask */
#define _SPRC_PME_MASK 0x08 /* pause mode mask */
#define _SPRC_ER_ENABLE _SPRC_ER_MASK /* receiver enabled */
#define _SPRC_DME_DISABLE 0x00 /* dma disabled */
#define _SPRC_DME_RXRDY 0x20 /* dma disabled, RxRDY interrupt enabled*/
#define _SPRC_DME_ENABLE2 0x40 /* dma enabled,receiver src channel 2 */
#define _SPRC_DME_ENABLE3 0x60 /* dma enabled,receiver src channel 3 */
#define _SPRC_PME_HARD _SPRC_PME_MASK /* RTS controlled by hardware */
#define _SPRC_PME_SOFT 0x00 /* RTS controlled by software */
/* serial port transmit command register */
#define _SPTC_ET_MASK 0x80 /* transmiter enable mask */
#define _SPTC_DME_MASK 0x60 /* dma mode mask */
#define _SPTC_TIE_MASK 0x10 /* empty interrupt enable mask */
#define _SPTC_EIE_MASK 0x08 /* error interrupt enable mask */
#define _SPTC_SPE_MASK 0x04 /* stop/pause mask */
#define _SPTC_TB_MASK 0x02 /* transmit break mask */
#define _SPTC_ET_ENABLE _SPTC_ET_MASK /* transmiter enabled */
#define _SPTC_DME_DISABLE 0x00 /* transmiter disabled, TBR intr disabled */
#define _SPTC_DME_TBR 0x20 /* transmiter disabled, TBR intr enabled*/
#define _SPTC_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */
#define _SPTC_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */
#if defined(__STDC__) || defined(__cplusplus)
extern void ppc403DevInit (PPC403_CHAN *pDev);
extern void ppc403IntRd (PPC403_CHAN *pDev);
extern void ppc403IntWr (PPC403_CHAN *pDev);
#else
extern void ppc403DevInit ();
extern void ppc403IntRd ();
extern void ppc403IntWr ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCppc403Sioh */
vxworks-6.9/target/h/drv/sio/ppc555SciSio.h
+175
View File
@@ -0,0 +1,175 @@
/* ppc555SciSio.h - header file for ppc555Sci serial driver */
/* Copyright 1984-1997, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,29apr10,pad Moved extern C statement after include statements.
01a,22mar99,zl written based on templateSio.h, m68332Sio.h and m68332.h
*/
#ifndef __INCppc555SciSioh
#define __INCppc555SciSioh
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#include "drv/multi/ppc555Siu.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Additional hardware options to the ones in sioLib.h
*/
#define QUEUED 0x100
/*
* QSM - Register definitions for the Queued Serial Module (QSM)
*/
#define PPC555_QSM_MCR(base) ((VUINT16 *) (base + 0x305000))
#define PPC555_QSM_TEST(base) ((VUINT16 *) (base + 0x305002))
#define PPC555_QSM_DSCI_ILR(base) ((VUINT16 *) (base + 0x305004))
#define PPC555_QSM_QSPI_ILR(base) ((VUINT16 *) (base + 0x305006))
#define PPC555_QSM_SCI1_CR0(base) ((VUINT16 *) (base + 0x305008))
#define PPC555_QSM_SCI1_CR1(base) ((VUINT16 *) (base + 0x30500a))
#define PPC555_QSM_SCI1_SR(base) ((VUINT16 *) (base + 0x30500c))
#define PPC555_QSM_SCI1_DR(base) ((VUINT16 *) (base + 0x30500e))
#define PPC555_QSM_QPDR(base) ((VUINT16 *) (base + 0x305014))
#define PPC555_QSM_QPAR(base) ((VUINT8 *) (base + 0x305016))
#define PPC555_QSM_QDDR(base) ((VUINT8 *) (base + 0x305017))
#define PPC555_QSM_SPCR0(base) ((VUINT16 *) (base + 0x305018))
#define PPC555_QSM_SPCR1(base) ((VUINT16 *) (base + 0x30501a))
#define PPC555_QSM_SPCR2(base) ((VUINT16 *) (base + 0x30501c))
#define PPC555_QSM_SPCR3(base) ((VUINT8 *) (base + 0x30501e))
#define PPC555_QSM_SPSR(base) ((VUINT8 *) (base + 0x30501f))
#define PPC555_QSM_SCI2_CR0(base) ((VUINT16 *) (base + 0x305020))
#define PPC555_QSM_SCI2_CR1(base) ((VUINT16 *) (base + 0x305022))
#define PPC555_QSM_SCI2_SR(base) ((VUINT16 *) (base + 0x305024))
#define PPC555_QSM_SCI2_DR(base) ((VUINT16 *) (base + 0x305026))
#define PPC555_QSM_QSCI1_CR(base) ((VUINT16 *) (base + 0x305028))
#define PPC555_QSM_QSCI1_SR(base) ((VUINT16 *) (base + 0x30502a))
#define PPC555_QSM_QSCI1_SCTQ(base) ((VUINT16 *) (base + 0x30502c))
#define PPC555_QSM_QSCI1_SCRQ(base) ((VUINT16 *) (base + 0x30504c))
/* QSM_DSCI_ILR - DSCI Interrupt Level Register */
#define QSM_QILR_SCI_MSK 0x8f00 /* SCI interrupt level mask */
#define QSM_QILR_SCI_SHIFT 8 /* SCI interrupt level shift */
/* QSM_SCCR0 - Control Register 0 */
#define QSM_SCCR0_OTHR 0x8000 /* Select baud rate source clk */
#define QSM_SCCR0_LNKBD 0x4000 /* Link baud */
#define QSM_SCCR0_SCBR_MSK 0x1FFF /* Baud rate mask */
/* QSM_SCCR1 - Control Register 1 */
#define QSM_SCCR1_SBK 0x0001 /* send break */
#define QSM_SCCR1_RWU 0x0002 /* receiver wakeup enable */
#define QSM_SCCR1_RE 0x0004 /* receiver enable */
#define QSM_SCCR1_TE 0x0008 /* transmitter enable */
#define QSM_SCCR1_ILIE 0x0010 /* idle-line interrupt enable */
#define QSM_SCCR1_RIE 0x0020 /* receiver interrupt enable */
#define QSM_SCCR1_TCIE 0x0040 /* transmit complete interrupt enable */
#define QSM_SCCR1_TIE 0x0080 /* transmit interrupt enable */
#define QSM_SCCR1_WAKE 0x0100 /* wakeup by address mark */
#define QSM_SCCR1_M 0x0200 /* mode select: 0= 8 data bits, 1 = 9 */
#define QSM_SCCR1_PE 0x0400 /* parity enable */
#define QSM_SCCR1_PT 0x0800 /* parity type: 1=Odd, 0=Even */
#define QSM_SCCR1_ILT 0x1000 /* idle line detect type */
#define QSM_SCCR1_WOMS 0x2000 /* wired or mode for SCI Pins */
#define QSM_SCCR1_LOOPS 0x4000 /* test SCI operation */
/* QSM_SCSR - Status Register */
#define QSM_SCSR_PF 0x0001 /* parity error flag */
#define QSM_SCSR_FE 0x0002 /* framing error flag */
#define QSM_SCSR_NF 0x0004 /* noise error flag */
#define QSM_SCSR_OR 0x0008 /* overrun error flag */
#define QSM_SCSR_IDLE 0x0010 /* idle-line detected flag */
#define QSM_SCSR_RAF 0x0020 /* receiver active flag */
#define QSM_SCSR_RDRF 0x0040 /* receive data register full flag */
#define QSM_SCSR_TC 0x0080 /* transmit complete */
#define QSM_SCSR_TDRE 0x0100 /* transmit date register empty flag */
/* QSM_QSCCR - Queued SCI Control Register */
#define QSM_QSCCR_QTPNT_MSK 0xF000 /* Queue transmit pointer */
#define QSM_QSCCR_QTHFI 0x0800 /* Rcv queue top-half full intr. */
#define QSM_QSCCR_QBHFI 0x0400 /* Rcv queue bottom-half full intr. */
#define QSM_QSCCR_QTHEI 0x0200 /* Xmt queue top-half empty intr. */
#define QSM_QSCCR_QBHEI 0x0100 /* Xmt queue bottom-half empty intr. */
#define QSM_QSCCR_QTE 0x0040 /* Queue transmit enable */
#define QSM_QSCCR_QRE 0x0020 /* Queue receive enable */
#define QSM_QSCCR_QTWE 0x0010 /* Queue transmit wrap enable */
#define QSM_QSCCR_QTSZ_MSK 0x000F /* Queue transfer size */
/* QSM_SCSR - Queued SCI Status Register */
#define QSM_QSCSR_QOR 0x1000 /* Receiver queue overrun error */
#define QSM_QSCSR_QTHF 0x0800 /* Receiver queue top-half full */
#define QSM_QSCSR_QBHF 0x0400 /* Receiver queue bottom-half full */
#define QSM_QSCSR_QTHE 0x0200 /* Xmitter queue top-half empty */
#define QSM_QSCSR_QBHE 0x0100 /* Xmitter queue bottom-half empty */
#define QSM_QSCSR_QRPNT_MSK 0x00F0 /* Queue receive pointer */
#define QSM_QSCSR_QPEND_MSK 0x000F /* Queue pending */
/*
* device and channel structures
*/
typedef struct
{
/* must be first */
SIO_CHAN sio; /* standard SIO_CHAN element */
/* callbacks */
STATUS (*getTxChar) ();
STATUS (*putRcvChar) ();
void * getTxArg;
void * putRcvArg;
/* register addresses */
volatile UINT16 * sccr0; /* control register 0 */
volatile UINT16 * sccr1; /* control register 1 */
volatile UINT16 * scsr; /* status register */
volatile UINT16 * scdr; /* data register */
volatile UINT16 * scilr; /* interrupt level register */
volatile UINT16 * qsccr; /* queued control register */
volatile UINT16 * qscsr; /* queued status register */
volatile UINT16 * scrq; /* receive queue */
volatile UINT16 * sctq; /* transmit queue */
/* misc */
int intLevel;
int baudRate;
int clockRate; /* CPU clock frequency (Hz) */
int mode; /* current mode (interrupt or poll) */
int options; /* Hardware options */
} PPC555SCI_CHAN;
/*
* function prototypes
*/
IMPORT void ppc555SciDevInit (PPC555SCI_CHAN *pChan);
IMPORT void ppc555SciDevInit2(PPC555SCI_CHAN *pChan);
IMPORT void ppc555SciInt (PPC555SCI_CHAN *pChan);
#endif /* _ASMLANGUAGE */
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif /* __INCppc555SciSioh */
vxworks-6.9/target/h/drv/sio/ppc860Sio.h
+684
View File
@@ -0,0 +1,684 @@
/* Copyright 1984-1998, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,29apr10,pad Moved extern C statement after include statements.
01g,07jan99,cn fixed properly SPR# 22503 and SPR# 24296.
01f,22oct98,cn added missing parenthesis in some defines (SPR# 22503).
01e,13apr98,map moved SCC device definitions to ../multi/ppc860Cpm.h
renamed SCC_DEV to SCC_UART_DEV
01d,26mar98,map added SMC, SCC, PIP defines.
01c,24may96,tpr changed statusMode from VINT16 to VUINT16.
01b,22apr96,cah change definitions to be offsets from a known #define
constant, rather than from a run-time IMMR register value.
Changes are required in sysSerial.c for this as well.
01a,11apr96,cah created.
*/
/*
* This file contains constants for the Motorola MPC860 PowerPC
* microcontroller chip.
*/
#ifndef __INCppc860Sioh
#define __INCppc860Sioh
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#include "drv/multi/ppc860Cpm.h"
#include "drv/multi/ppc860Siu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* device and channel structures */
/*
* The PPC860SMC_CHAN structure defines a serial I/O channel which
* describes the (TBD) registers for a given channel.
* Also the various SIO driver functions ( ioctl, txStarup, callbackInstall,
* pollInput, polloutput ) that this channel could utilize are declared
* here.
*/
/* roughly things copied in structure form from multi/m68360.h */
/* MPC860 Dual Ported Ram addresses */
#define PPC860_DPR_SCC1(dprbase) ((VINT32 *) ((dprbase) + 0x1c00))
#define PPC860_DPR_I2C(dprbase) ((VINT32 *) ((dprbase) + 0x1c80))
#define PPC860_DPR_MISC(dprbase) ((VINT32 *) ((dprbase) + 0x1cb0))
#define PPC860_DPR_IDMA1(dprbase) ((VINT32 *) ((dprbase) + 0x1cc0))
#define PPC860_DPR_SCC2(dprbase) ((VINT32 *) ((dprbase) + 0x1d00))
#define PPC860_DPR_SPI(dprbase) ((VINT32 *) ((dprbase) + 0x1d80))
#define PPC860_DPR_TMR(dprbase) ((VINT32 *) ((dprbase) + 0x1db0))
#define PPC860_DPR_IDMA2(dprbase) ((VINT32 *) ((dprbase) + 0x1dc0))
#define PPC860_DPR_SCC3(dprbase) ((VINT32 *) ((dprbase) + 0x1e00))
#define PPC860_DPR_SMC1(dprbase) ((VINT32 *) ((dprbase) + 0x1e80))
#define PPC860_DPR_DSP1(dprbase) ((VINT32 *) ((dprbase) + 0x1ec0))
#define PPC860_DPR_SCC4(dprbase) ((VINT32 *) ((dprbase) + 0x1f00))
#define PPC860_DPR_SMC2(dprbase) ((VINT32 *) ((dprbase) + 0x1f80))
#define PPC860_DPR_DSP2(dprbase) ((VINT32 *) ((dprbase) + 0x1fc0))
/*
* dual-ported parameter RAM SMC offsets
* access these with SMC_RBASE(base_dpram_addr_of_this_SMC1)
* base_dpram_addr_of_this_SMC1 == PPC860_DPR_SMC1(dprbase)
* or == PPC860_DPR_SMC2(dprbase)
*/
#define SMC_RBASE(base) ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
#define SMC_TBASE(base) ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
#define SMC_RFCR(base) ((VINT8 *) ((base) + 0x04)) /* Rx Function Code */
#define SMC_TFCR(base) ((VINT8 *) ((base) + 0x05)) /* Tx Function Code */
#define SMC_MRBLR(base) ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
#define SMC_RSTATE(base) ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
#define SMC_RBPTR(base) ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
#define SMC_TSTATE(base) ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
#define SMC_TBPTR(base) ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
#define SMC_MAX_IDL(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
#define SMC_IDLC(base) ((VINT16 *) ((base) + 0x2A)) /* Temp Idle counter */
#define SMC_BRKLN(base) ((VINT16 *) ((base) + 0x2C)) /* Last Rx Break length*/
#define SMC_BRKEC(base) ((VINT16 *) ((base) + 0x2E)) /* Rx Brk Cond counter */
#define SMC_BRKCR(base) ((VINT16 *) ((base) + 0x30)) /* Break Count reg (Tx)*/
#define SMC_RMASK(base) ((VINT16 *) ((base) + 0x32)) /* Temp bit mask */
/* dual ported parameter RAM PIP offsets */
#define PIP_RBASE(base) ((VINT16 *)((base) + 0x00)) /* Rx Buff Descr Base */
#define PIP_TBASE(base) ((VINT16 *)((base) + 0x01)) /* Tx Buff Descr Base */
#define PIP_CFCR(base) ((VINT8 *)((base) + 0x04)) /* Cent. Function Code */
#define PIP_SMASK(base) ((VINT8 *)((base) + 0x05)) /* Status mask */
/*
* dual-ported parameter RAM SCC offsets
* access these with SCC_RBASE(base_dpram_addr_of_this_SCC1)
* base_dpram_addr_of_this_SCC1 == PPC860_DPR_SCC1(dprbase)
* or == PPC860_DPR_SCC1(dprbase)
*/
#define SCC_RBASE(base) ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
#define SCC_TBASE(base) ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
#define SCC_RFCR(base) ((VINT8 *) ((base) + 0x04)) /* Rx Function Code */
#define SCC_TFCR(base) ((VINT8 *) ((base) + 0x05)) /* Tx Function Code */
#define SCC_MRBLR(base) ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
#define SCC_RSTATE(base) ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
#define SCC_RBPTR(base) ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
#define SCC_TSTATE(base) ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
#define SCC_TBPTR(base) ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
#define SCC_RCRC(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
#define SCC_TCRC(base) ((VINT16 *) ((base) + 0x2C)) /* Max Idle characters */
#define SCC_MAX_IDL(base) ((VINT16 *) ((base) + 0x38)) /* Max Idle characters */
#define SCC_IDLC(base) ((VINT16 *) ((base) + 0x3A)) /* Temp Idle counter */
#define SCC_BRKCR(base) ((VINT16 *) ((base) + 0x3C)) /* Break Count Reg (Tx)*/
#define SCC_PAREC(base) ((VINT16 *) ((base) + 0x3E)) /* Rx Parity Err Cnt */
#define SCC_FRMEC(base) ((VINT16 *) ((base) + 0x40)) /* Rx Frame Err Cnt */
#define SCC_NOSEC(base) ((VINT16 *) ((base) + 0x42)) /* Receive Noise Cnt */
/*
* dual-ported parameter RAM I2C offsets
* access these with I2C_RPBASE(base_dpram_addr_of_I2C)
*/
#define I2C_RPBASE(base) ((VINT16 *) ((char *)base + 0x2C))
typedef struct /* SMC_BUF */
{
VUINT16 statusMode; /* status and control */
VINT16 dataLength; /* length of data buffer in bytes */
u_char * dataPointer; /* points to data buffer */
} SMC_BUF;
typedef struct /* SMC_PARAM */
{ /* offset description*/
VINT16 rbase; /* 00 Rx buffer descriptor base address */
VINT16 tbase; /* 02 Tx buffer descriptor base address */
VINT8 rfcr; /* 04 Rx function code */
VINT8 tfcr; /* 05 Tx function code */
VINT16 mrblr; /* 06 maximum receive buffer length */
VINT32 rstate; /* 08 Rx internal state */
VINT32 res1; /* 0C Rx internal data pointer */
VINT16 rbptr; /* 10 Rx buffer descriptor pointer */
VINT16 res2; /* 12 reserved/internal */
VINT32 res3; /* 14 reserved/internal */
VINT32 tstate; /* 18 Tx internal state */
VINT32 res4; /* 1C reserved/internal */
VINT16 tbptr; /* 20 Tx buffer descriptor pointer */
VINT16 res5; /* 22 reserved/internal */
VINT32 res6; /* 24 reserved/internal */
VINT16 maxidl; /* 28 Maximum idle characters */
VINT16 idlc; /* 2A temporary idle counter */
VINT16 brkln; /* 2C last recv break length */
VINT16 brkec; /* 2E recv break condition counter */
VINT16 brkcr; /* 30 xmit break count register */
VINT16 r_mask; /* 32 temporary bit mask */
} SMC_PARAM;
typedef struct /* SMC */
{
SMC_PARAM param; /* SMC parameters */
} SMC;
typedef struct /* SMC_REG */
{
VINT16 smcmr; /* SMC Mode register */
VINT8 res1[2]; /* reserved */
VINT8 smce; /* SMC Event register */
VINT8 res2[3]; /* reserved */
VINT8 smcm; /* SMC Mask register */
} SMC_REG;
/* SMC device descriptor */
typedef struct /* SMC_DEV */
{
int smcNum; /* number of SMC device (1 or 2)*/
int txBdNum; /* number of transmit buf descriptors */
int rxBdNum; /* number of receive buf descriptors */
SMC_BUF * txBdBase; /* transmit BD base address */
SMC_BUF * rxBdBase; /* receive BD base address */
u_char * txBufBase; /* transmit buffer base address */
u_char * rxBufBase; /* receive buffer base address */
VINT32 txBufSize; /* transmit buffer size */
VINT32 rxBufSize; /* receive buffer size */
int txBdNext; /* next transmit BD to fill */
int rxBdNext; /* next receive BD to read */
volatile SMC * pSmc; /* SMC parameter RAM. Must point */
/* at DPRAM area for SMC1 or SMC2 */
volatile SMC_REG * pSmcReg; /* SMC registers must point at */
/* SMCMR1 or SMCMR2 */
VINT32 intMask; /* interrupt acknowledge mask */
} SMC_DEV;
/* SCC device descriptor */
typedef struct /* SCC_UART_DEV */
{
int sccNum; /* number of SCC device */
int txBdNum; /* number of transmit buf descriptors */
int rxBdNum; /* number of receive buf descriptors */
SCC_BUF * txBdBase; /* transmit BD base address */
SCC_BUF * rxBdBase; /* receive BD base address */
u_char * txBufBase; /* transmit buffer base address */
u_char * rxBufBase; /* receive buffer base address */
VINT32 txBufSize; /* transmit buffer size */
VINT32 rxBufSize; /* receive buffer size */
int txBdNext; /* next transmit BD to fill */
int rxBdNext; /* next receive BD to read */
volatile SCC * pScc; /* SCC parameter RAM */
volatile SCC_REG * pSccReg; /* SCC registers */
VINT32 intMask; /* interrupt acknowledge mask */
} SCC_UART_DEV;
typedef struct /* I2C_PARAM */
{ /* offset description */
VINT16 rbase; /* 00 Rx buffer descriptors base address */
VINT16 tbase; /* 02 Tx buffer descriptors base address */
VINT8 rfcr; /* 04 Rx function code */
VINT8 tfcr; /* 05 Tx function code */
VINT16 mrblr; /* 06 maximum receive buffer length */
VINT32 ris; /* 08 Rx internal state */
VINT32 ridp; /* 0c Rx internal data pointer */
VINT16 rbptr; /* 10 Rx buffer descriptor pointer */
VINT16 ribc; /* 12 Rx internal byte count */
VINT32 rt; /* 14 Rx temp */
VINT32 tis; /* 18 Tx internal state */
VINT32 tidp; /* 1c Tx internal data pointer */
VINT16 tbptr; /* 20 Tx buffer descriptor pointer */
VINT16 tibc; /* 22 Tx internal byte count */
VINT32 tt; /* 24 Tx temp */
VINT32 notused; /* 28 not used */
VINT16 rpbase; /* 2c relocatable parameter RAM base */
VINT16 reserved; /* 2e reserved */
} I2C_PARAM;
/* standard dual-mode serial driver header structure follows */
typedef struct ppc860_chan /* PPC860SMC_CHAN */
{
/* always goes first */
SIO_DRV_FUNCS *pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar)(); /* pointer to a xmitr function */
STATUS (*putRcvChar)();/* pointer to a recvr function */
void * getTxArg;
void * putRcvArg;
VINT16 int_vec; /* interrupt vector number */
VINT16 channelMode; /* SIO_MODE */
int baudRate;
int clockRate; /* CPU clock frequency (Hz) */
int bgrNum; /* number of BRG being used */
VINT32 * pBaud; /* BRG registers */
VINT32 regBase; /* register/DPR base address */
SMC_DEV uart; /* UART SCC device */
} PPC860SMC_CHAN;
/* serial procedures */
IMPORT void ppc860DevInit (PPC860SMC_CHAN *);
IMPORT void ppc860Int (PPC860SMC_CHAN *);
IMPORT void ppc800DevInit (PPC860SMC_CHAN *);
IMPORT void ppc800Int (PPC860SMC_CHAN *);
/* standard dual-mode serial driver header structure follows - SCC */
typedef struct ppc860Scc_chan /* PPC860SCC_CHAN */
{
/* always goes first */
SIO_DRV_FUNCS *pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar)(); /* pointer to a xmitr function */
STATUS (*putRcvChar)();/* pointer to a recvr function */
void * getTxArg;
void * putRcvArg;
VINT16 int_vec; /* interrupt vector number */
VINT16 channelMode; /* SIO_MODE */
int baudRate;
int clockRate; /* CPU clock frequency (Hz) */
int bgrNum; /* number of BRG being used */
VINT32 * pBaud; /* BRG registers */
VINT32 regBase; /* register/DPR base address */
SCC_UART_DEV uart; /* UART SCC device */
} PPC860SCC_CHAN;
/* function declarations */
IMPORT void ppc860SccInt (PPC860SCC_CHAN *);
IMPORT void ppc860SccDevInit (PPC860SCC_CHAN *);
/* channels */
#define PPC860_CHANNEL_A 0
#define PPC860_CHANNEL_B 1
#define PPC860SMC_N_CHANS 2 /* number of serial channels on chip */
/* SIO -- mpc860 serial channel chip -- register definitions */
/* Buffer Descriptor Pointer Definitions */
/* Receive BD status bits 16-bit value */
#define BD_RX_EMPTY_BIT 0x8000 /* buffer is empty */
#define BD_RX_WRAP_BIT 0x2000 /* last BD in chain */
#define BD_RX_INTERRUPT_BIT 0x1000 /* set interrupt when filled */
#define BD_RX_CON_MODE_BIT 0x0200 /* Continuous Mode bit */
#define BD_RX_IDLE_CLOSE_BIT 0x0100 /* Close on IDLE recv bit */
#define BD_RX_BREAK_CLOSE_BIT 0x0020 /* Close on break recv bit */
#define BD_RX_FRAME_CLOSE_BIT 0x0010 /* Close on frame error bit */
#define BD_RX_PARITY_ERROR_BIT 0x0008 /* Parity error in last byte */
#define BD_RX_OVERRUN_ERROR_BIT 0x0002 /* Overrun occurred */
/* Transmit BD status bits 16-bit value */
#define BD_TX_READY_BIT 0x8000 /* Transmit ready/busy bit */
#define BD_TX_WRAP_BIT 0x2000 /* last BD in chain */
#define BD_TX_INTERRUPT_BIT 0x1000 /* set interrupt when emptied */
#define BD_TX_CON_MODE_BIT 0x0200 /* Continuous Mode bit */
#define BD_TX_PREAMBLE_BIT 0x0100 /* send preamble sequence */
#define BD_STATUS_OFFSET 0x00 /* two bytes */
#define BD_DATA_LENGTH_OFFSET 0x02 /* two bytes */
#define BD_BUF_POINTER_OFFSET 0x04 /* four bytes */
/*
* MPC860 internal register/memory map (section 17 of prelim. spec)
* note that these are offsets from the value stored in the IMMR
* register, which is in the PowerPC special register address space
* at register number 638
*/
/**** SIU module configuration ***/
#define MPC860_SIUMCR(base) ((VINT32 *) ((base) + 0x00))
/**** System Protection Control ***/
#define MPC860_SYPCR(base) ((VINT32 *) ((base) + 0x04))
/**** SW watch dog timer value ***/
#define MPC860_SWT(base) ((VINT32 *) ((base) + 0x08))
/*** Software service reg ***/
#define MPC860_SWSR(base) ((VINT16 *) ((base) + 0x0E))
/*** Interrupt pending reg ***/
#define MPC860_SIPEND(base) ((VINT32 *) ((base) + 0x10))
/*** Interrupt Mask reg ***/
#define MPC860_SIMASK(base) ((VINT32 *) ((base) + 0x14))
/*** Interrupt Edge level mask ***/
#define MPC860_SIEL(base) ((VINT32 *) ((base) + 0x18))
/*** Interrupt Vector reg ***/
#define MPC860_SIVEC(base) ((VINT32 *) ((base) + 0x1C))
/*** Transfer error status ***/
#define MPC860_TESR(base) ((VINT32 *) ((base) + 0x20))
/*** SDMA Config reg ***/
#define MPC860_SDCR(base) ((VINT32 *) ((base) + 0x30))
/*** CP Interrupt vector reg ***/
#define MPC860_CIVR(base) ((VINT16 *) ((base) + 0x930))
/*** CP Interrupt config reg ***/
#define MPC860_CICR(base) ((VINT32 *) ((base) + 0x940))
/*** CP Interrupt pending reg ***/
#define MPC860_CIPR(base) ((VINT32 *) ((base) + 0x944))
/*** CP Interrupt mask reg ***/
#define MPC860_CIMR(base) ((VINT32 *) ((base) + 0x948))
/*** CP Interrupt in-service reg ***/
#define MPC860_CISR(base) ((VINT32 *) ((base) + 0x94C))
/*** Port A data direction reg ***/
#define MPC860_PADIR(base) ((VINT16 *) ((base) + 0x950))
/*** Port A pin assign reg ***/
#define MPC860_PAPAR(base) ((VINT16 *) ((base) + 0x952))
/*** Port A open drain reg ***/
#define MPC860_PAODR(base) ((VINT16 *) ((base) + 0x954))
/*** Port A data reg ***/
#define MPC860_PADAT(base) ((VINT16 *) ((base) + 0x956))
/*** Port C data direction reg ***/
#define MPC860_PCDIR(base) ((VINT16 *) ((base) + 0x960))
/*** Port C pin assign reg ***/
#define MPC860_PCPAR(base) ((VINT16 *) ((base) + 0x962))
/*** Port C special options reg ***/
#define MPC860_PCSO(base) ((VINT16 *) ((base) + 0x964))
/*** Port C data reg ***/
#define MPC860_PCDAT(base) ((VINT16 *) ((base) + 0x966))
/*** Port C interrupt control reg ***/
#define MPC860_PCINT(base) ((VINT16 *) ((base) + 0x968))
/*** Port D data direction reg ***/
#define MPC860_PDDIR(base) ((VINT16 *) ((base) + 0x970))
/*** Port D pin assign reg ***/
#define MPC860_PDPAR(base) ((VINT16 *) ((base) + 0x972))
/*** Port D data reg ***/
#define MPC860_PDDAT(base) ((VINT16 *) ((base) + 0x976))
/*** Comm processor cmd reg ***/
#define MPC860_CPCR(base) ((VINT16 *) ((base) + 0x9C0))
/*** RISC config reg ***/
#define MPC860_RCCR(base) ((VINT16 *) ((base) + 0x9C4))
/*** RISC dev support status reg ***/
#define MPC860_RMDS(base) ((VINT8 *) ((base) + 0x9C7))
/*** RISC ucode dev spt control reg ***/
#define MPC860_RMDR(base) ((VINT32 *) ((base) + 0x9C8))
/*** RISC controller trap reg 1 ***/
#define MPC860_RCTR1(base) ((VINT16 *) ((base) + 0x9CC))
/*** RISC controller trap reg 2 ***/
#define MPC860_RCTR2(base) ((VINT16 *) ((base) + 0x9CE))
/*** RISC controller trap reg 3 ***/
#define MPC860_RCTR3(base) ((VINT16 *) ((base) + 0x9D0))
/*** RISC controller trap reg 4 ***/
#define MPC860_RCTR4(base) ((VINT16 *) ((base) + 0x9D2))
/*** RISC Timers event reg ***/
#define MPC860_RTER(base) ((VINT16 *) ((base) + 0x9D6))
/*** RISC Timers mask reg ***/
#define MPC860_RTMR(base) ((VINT16 *) ((base) + 0x9DA))
/*** baud rate generation register set ***/
/*** BRG1 configuration reg ***/
#define MPC860_BRGC1(base) ((VINT32 *) ((base) + 0x9F0))
/*** BRG2 configuration reg ***/
#define MPC860_BRGC2(base) ((VINT32 *) ((base) + 0x9F4))
/*** BRG3 configuration reg ***/
#define MPC860_BRGC3(base) ((VINT32 *) ((base) + 0x9F8))
/*** BRG4 configuration reg ***/
#define MPC860_BRGC4(base) ((VINT32 *) ((base) + 0x9FC))
/*** SCC1 Mode reg low ***/
#define MPC860_GSMR_L1(base) ((VINT32 *) ((base) + 0xA00))
/*** SCC1 Mode reg High ***/
#define MPC860_GSMR_H1(base) ((VINT32 *) ((base) + 0xA04))
/*** SCC1 Protocol Specific Mode reg ***/
#define MPC860_PSMR1(base) ((VINT16 *) ((base) + 0xA08))
/*** SCC1 Transmit-On-Demand reg ***/
#define MPC860_TODR1(base) ((VINT16 *) ((base) + 0xA0C))
/*** SCC1 Data Synchronization reg ***/
#define MPC860_DSR1(base) ((VINT16 *) ((base) + 0xA0E))
/*** SCC1 Event reg ***/
#define MPC860_SCCE1(base) ((VINT16 *) ((base) + 0xA10))
/*** SCC1 Mask reg ***/
#define MPC860_SCCM1(base) ((VINT16 *) ((base) + 0xA14))
/*** SCC1 Status reg ***/
#define MPC860_SCCS1(base) ((VINT8 *) ((base) + 0xA17))
/*** SCC2 Mode reg low ***/
#define MPC860_GSMR_L2(base) ((VINT32 *) ((base) + 0xA20))
/*** SCC2 Mode reg High ***/
#define MPC860_GSMR_H2(base) ((VINT32 *) ((base) + 0xA24))
/*** SCC2 Protocol Specific Mode reg ***/
#define MPC860_PSMR2(base) ((VINT16 *) ((base) + 0xA28))
/*** SCC2 Transmit-On-Demand reg ***/
#define MPC860_TODR2(base) ((VINT16 *) ((base) + 0xA2C))
/*** SCC2 Data Synchronization reg ***/
#define MPC860_DSR2(base) ((VINT16 *) ((base) + 0xA2E))
/*** SCC2 Event reg ***/
#define MPC860_SCCE2(base) ((VINT16 *) ((base) + 0xA30))
/*** SCC2 Mask reg ***/
#define MPC860_SCCM2(base) ((VINT16 *) ((base) + 0xA34))
/*** SCC2 Status reg ***/
#define MPC860_SCCS2(base) ((VINT8 *) ((base) + 0xA37))
/*** SCC3 Mode reg low ***/
#define MPC860_GSMR_L3(base) ((VINT32 *) ((base) + 0xA40))
/*** SCC3 Mode reg High ***/
#define MPC860_GSMR_H3(base) ((VINT32 *) ((base) + 0xA44))
/*** SCC3 Protocol Specific Mode reg ***/
#define MPC860_PSMR3(base) ((VINT16 *) ((base) + 0xA48))
/*** SCC3 Transmit-On-Demand reg ***/
#define MPC860_TODR3(base) ((VINT16 *) ((base) + 0xA4C))
/*** SCC3 Data Synchronization reg ***/
#define MPC860_DSR3(base) ((VINT16 *) ((base) + 0xA4E))
/*** SCC3 Event reg ***/
#define MPC860_SCCE3(base) ((VINT16 *) ((base) + 0xA50))
/*** SCC3 Mask reg ***/
#define MPC860_SCCM3(base) ((VINT16 *) ((base) + 0xA54))
/*** SCC3 Status reg ***/
#define MPC860_SCCS3(base) ((VINT8 *) ((base) + 0xA57))
/*** SCC4 Mode reg low ***/
#define MPC860_GSMR_L4(base) ((VINT32 *) ((base) + 0xA60))
/*** SCC4 Mode reg High ***/
#define MPC860_GSMR_H4(base) ((VINT32 *) ((base) + 0xA64))
/*** SCC4 Protocol Specific Mode reg ***/
#define MPC860_PSMR4(base) ((VINT16 *) ((base) + 0xA68))
/*** SCC4 Transmit-On-Demand reg ***/
#define MPC860_TODR4(base) ((VINT16 *) ((base) + 0xA6C))
/*** SCC4 Data Synchronization reg ***/
#define MPC860_DSR4(base) ((VINT16 *) ((base) + 0xA6E))
/*** SCC4 Event reg ***/
#define MPC860_SCCE4(base) ((VINT16 *) ((base) + 0xA70))
/*** SCC4 Mask reg ***/
#define MPC860_SCCM4(base) ((VINT16 *) ((base) + 0xA74))
/*** SCC4 Status reg ***/
#define MPC860_SCCS4(base) ((VINT8 *) ((base) + 0xA77))
/*** SMC1 Mode reg ***/
#define MPC860_SMCMR1(base) ((VINT16 *) ((base) + 0xA82))
/*** SMC1 Event reg ***/
#define MPC860_SMCE1(base) ((VINT8 *) ((base) + 0xA86))
/*** SMC1 Mask reg ***/
#define MPC860_SMCM1(base) ((VINT8 *) ((base) + 0xA8A))
/*** SMC2 Mode reg ***/
#define MPC860_SMCMR2(base) ((VINT16 *) ((base) + 0xA92))
/*** SMC2 or PIP Event reg ***/
#define MPC860_SMCE2(base) ((VINT8 *) ((base) + 0xA96))
/*** SMC2 Mask reg ***/
#define MPC860_SMCM2(base) ((VINT8 *) ((base) + 0xA9A))
/*** SPI Mode reg ***/
#define MPC860_SPMODE(base) ((VINT16 *) ((base) + 0xAA0))
/*** SPI Event reg ***/
#define MPC860_SPIE(base) ((VINT8 *) ((base) + 0xAA6))
/*** SPI Mask reg ***/
#define MPC860_SPIM(base) ((VINT8 *) ((base) + 0xAAA))
/*** SPI Command reg ***/
#define MPC860_SPCOM(base) ((VINT8 *) ((base) + 0xAAD))
/*** PIP Configuration reg ***/
#define MPC860_PIPC(base) ((VINT16 *) ((base) + 0xAB2))
/*** PIP Timing params reg ***/
#define MPC860_PTPR(base) ((VINT16 *) ((base) + 0xAB6))
/*** Port B data direction reg ***/
#define MPC860_PBDIR(base) ((VINT32 *) ((base) + 0xAB8))
/*** Port B pin assign reg ***/
#define MPC860_PBPAR(base) ((VINT32 *) ((base) + 0xABC))
/*** Port B open drain reg ***/
#define MPC860_PBODR(base) ((VINT16 *) ((base) + 0xAC2))
/*** Port B Data register ***/
#define MPC860_PBDAT(base) ((VINT32 *) ((base) + 0xAC4))
/*** SI Mode reg ***/
#define MPC860_SIMODE(base) ((VINT32 *) ((base) + 0xAE0))
/*** SI Global Mode reg ***/
#define MPC860_SIGMR(base) ((VINT8 *) ((base) + 0xAE4))
/*** SI Status reg ***/
#define MPC860_SISTR(base) ((VINT8 *) ((base) + 0xAE6))
/*** SI Command reg ***/
#define MPC860_SICMR(base) ((VINT8 *) ((base) + 0xAE7))
/*** SI Clock route reg ***/
#define MPC860_SICR(base) ((VINT32 *) ((base) + 0xAEC))
/*** SI RAM pointers reg ***/
#define MPC860_SIRP(base) ((VINT32 *) ((base) + 0xAF0))
/*** SI Routing RAM base addr ***/
#define MPC860_SIRAM_BASE(base) ((base) + 0xC00)
/*** Data Param RAM base addr ***/
#define MPC860_DPRAM_BASE(base) ((base) + 0x2000)
/* Register Equates By Bit */
/* Equates for Baud Rate Generation Registers */
#define MPC860_BRGC_RST 0x20000 /* 1 = reset BRG */
#define MPC860_BRGC_ENABLE_CNT 0x10000 /* 1 = enable clocks to BRG */
#define MPC860_BRGC_BRGCLK_SRC 0x00000 /* Baud Rate Gen clock src */
#define MPC860_BRGC_CLK2_SRC 0x04000 /* CLK2 pin = BRG source */
#define MPC860_BRGC_CLK6_SRC 0x08000 /* CLK6 pin = BRG source */
#define MPC860_BRGC_AUTOBAUD 0x02000 /* 1 = autobaud on Rx */
/* 0 = normal operation */
#define MPC860_BRGC_CLKDIV_MASK 0x01FFE /* 12 bit value */
#define MPC860_BRGC_CLKDIV_SHIFT 0x1 /* shifted up one bit */
#define MPC860_BRGC_PRESCALE_16 0x00001 /* 1 = divide-by-16 clock */
/* Equates for SIMODE register */
#define MPC860_SIMODE_SMC2_MUX 0x80000000 /* connected to mux SI */
#define MPC860_SIMODE_SMC2_NMSI 0x00000000 /* connected to mux SI */
#define MPC860_SIMODE_SMC2_BRG1 0x00000000 /* BRG1 is clock source */
#define MPC860_SIMODE_SMC2_BRG2 0x10000000 /* BRG2 is clock source */
#define MPC860_SIMODE_SMC2_BRG3 0x20000000 /* BRG3 is clock source */
#define MPC860_SIMODE_SMC2_BRG4 0x30000000 /* BRG4 is clock source */
#define MPC860_SIMODE_SMC2_CLK5 0x40000000 /* CLK5 is clock source */
#define MPC860_SIMODE_SMC2_CLK6 0x50000000 /* CLK6 is clock source */
#define MPC860_SIMODE_SMC2_CLK7 0x60000000 /* CLK7 is clock source */
#define MPC860_SIMODE_SMC2_CLK8 0x70000000 /* CLK8 is clock source */
#define MPC860_SIMODE_SMC1_MUX 0x00008000 /* connected to mux SI */
#define MPC860_SIMODE_SMC1_NMSI 0x00000000 /* connected to mux SI */
#define MPC860_SIMODE_SMC1_BRG1 0x00000000 /* BRG1 is clock source */
#define MPC860_SIMODE_SMC1_BRG2 0x00001000 /* BRG2 is clock source */
#define MPC860_SIMODE_SMC1_BRG3 0x00002000 /* BRG3 is clock source */
#define MPC860_SIMODE_SMC1_BRG4 0x00003000 /* BRG4 is clock source */
#define MPC860_SIMODE_SMC1_CLK1 0x00004000 /* CLK1 is clock source */
#define MPC860_SIMODE_SMC1_CLK2 0x00005000 /* CLK2 is clock source */
#define MPC860_SIMODE_SMC1_CLK3 0x00006000 /* CLK3 is clock source */
#define MPC860_SIMODE_SMC1_CLK4 0x00007000 /* CLK4 is clock source */
#define MPC860_SIMODE_TDMB_NORM 0x00000000 /* normal operation */
#define MPC860_SIMODE_TDMB_ECHO 0x04000000 /* auto echo */
#define MPC860_SIMODE_TDMB_LOOP 0x08000000 /* internal loopback */
#define MPC860_SIMODE_TDMB_LCTR 0x0C000000 /* loopback control */
/*
* Equates for SMCE SM UART-mode Event Register
* writing a one to these location clears an event/interrupt
*/
#define MPC860_SMCE_UART_BRK_EVENT 0x10 /* break char received */
#define MPC860_SMCE_UART_BSY_EVENT 0x04 /* char discarded no bufs */
#define MPC860_SMCE_UART_TX_EVENT 0x02 /* char transmitted */
#define MPC860_SMCE_UART_RX_EVENT 0x01 /* char received */
#define MPC860_SMCE_UART_ALL_EVENTS ( \
MPC860_SMCE_UART_BRK_EVENT | \
MPC860_SMCE_UART_BSY_EVENT | \
MPC860_SMCE_UART_TX_EVENT | \
MPC860_SMCE_UART_RX_EVENT )
/*
* Equates for SMCM SM UART-mode Mask Register
* writing a one to these locations masks an event/interrupt
*/
#define MPC860_SMCM_UART_BRK_MASK 0x10 /* break char received */
#define MPC860_SMCM_UART_BSY_MASK 0x04 /* char discarded no bufs */
#define MPC860_SMCM_UART_TX_MASK 0x02 /* char transmitted */
#define MPC860_SMCM_UART_RX_MASK 0x01 /* char received */
/* Equates for CICR register CP interrupt configuration register */
#define MPC860_CICR_IRL_LEVEL_0 0x00000000 /* highest interrupt level */
#define MPC860_CICR_IRL_LEVEL_1 0x00020000
#define MPC860_CICR_IRL_LEVEL_2 0x00040000
#define MPC860_CICR_IRL_LEVEL_3 0x00060000
#define MPC860_CICR_IRL_LEVEL_4 0x00080000 /* standard value */
#define MPC860_CICR_IRL_LEVEL_5 0x000A0000
#define MPC860_CICR_IRL_LEVEL_6 0x000C0000
#define MPC860_CICR_IRL_LEVEL_7 0x000E0000 /* lowest */
#define MPC860_CICR_HP_SRC_STD 0x0001F000 /* highest priority int */
#define MPC860_CICR_MASTER_IEN 0x00000080 /* master interrupt enable */
/* Equates for CIMR register CP interrupt mask register */
#define MPC860_CIMR_SCC1_MASK 0x40000000 /* mask SCC1 interrupt */
#define MPC860_CIMR_SCC2_MASK 0x20000000 /* mask SCC2 interrupt */
#define MPC860_CIMR_SMC1_MASK 0x00000010 /* mask SMC1 interrupt */
#define MPC860_CIMR_SMC2_MASK 0x00000008 /* mask SMC2 interrupt */
/* Equates for RFCR register receive function code register */
#define MPC860_RFCR_DEC_LE 0x00 /* DEC little endian mode */
#define MPC860_RFCR_PPC_LE 0x08 /* PPC little endian mode */
/* reverse transmission order of */
/* bytes compared to DEC/Intel mode */
#define MPC860_RFCR_MOT_BE 0x18 /* big endian mode */
/* Equates for TFCR register transmission function code register */
#define MPC860_TFCR_DEC_LE 0x00 /* DEC little endian mode */
#define MPC860_TFCR_PPC_LE 0x08 /* PPC little endian mode */
/* reverse transmission order of */
/* bytes compared to DEC/Intel mode */
#define MPC860_TFCR_MOT_BE 0x18 /* big endian mode */
/* Equates for SMC Mode Register SMCMR */
#define MPC860_SMCMR_CLEN_MASK 0x7800 /* # bits in char minus one */
/* set to # data bits + # parity */
/* bits + # stop bits */
#define MPC860_SMCMR_CLEN_STD 0x4800 /* for 8-N-1 std serial I/O */
#define MPC860_SMCMR_STOPLEN_1 0x0000 /* stop length = 1 */
#define MPC860_SMCMR_STOPLEN_2 0x0400 /* stop length = 2 */
#define MPC860_SMCMR_NO_PARITY 0x0000 /* parity disabled */
#define MPC860_SMCMR_PARITY 0x0200 /* parity enabled */
#define MPC860_SMCMR_PARITY_ODD 0x0000 /* odd parity if enabled */
#define MPC860_SMCMR_PARITY_EVEN 0x0100 /* even parity if enabled */
#define MPC860_SMCMR_GCI_MODE 0x0000 /* GCI or SCIT mode */
#define MPC860_SMCMR_UART_MODE 0x0020 /* UART mode */
#define MPC860_SMCMR_TRANS_MODE 0x0030 /* totally transparent mode */
#define MPC860_SMCMR_NORM_MODE 0x0000 /* normal operation mode */
#define MPC860_SMCMR_LOOP_MODE 0x0004 /* local loopback mode */
#define MPC860_SMCMR_ECHO_MODE 0x0008 /* echo mode */
#define MPC860_SMCMR_TX_ENABLE 0x0002 /* enable transmitter */
#define MPC860_SMCMR_TX_DISABLE 0x0000 /* disable transmitter */
#define MPC860_SMCMR_RX_ENABLE 0x0001 /* enable receiver */
#define MPC860_SMCMR_RX_DISABLE 0x0000 /* disable receiver */
#define MPC860_SMCMR_STD_MODE ( \
MPC860_SMCMR_CLEN_STD | \
MPC860_SMCMR_STOPLEN_1 | \
MPC860_SMCMR_NO_PARITY | \
MPC860_SMCMR_UART_MODE | \
MPC860_SMCMR_NORM_MODE )
#define MPC860_SCMCR_STD_MODE_ENABLED ( \
MPC860_SMCMR_STD_MODE | \
MPC860_SMCMR_TX_ENABLE | \
MPC860_SMCMR_RX_ENABLE )
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCppc860Sioh */
vxworks-6.9/target/h/drv/sio/rm9000x2glSio.h
+212
View File
@@ -0,0 +1,212 @@
/* rm9000x2glSio.h - rm9000x2gl DUART header file */
/* Copyright 2005, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,13apr05,rlg fix for misplacement of assembly if def, discoverd in build of bootroms
01a,05apr05,rlg created for rm9000x2gl (yosemite). Created from the
wind river ns16552Sio.h file, version 01f,07sep04.
*/
#ifndef __INCrm9000x2glSioh
#define __INCrm9000x2glSioh
/*
*********************************************************************
* Copyright (c) 1990,1991 Intel Corporation
*
* Intel hereby grants you permission to copy, modify, and
* distribute this software and its documentation. Intel grants
* this permission provided that the above copyright notice
* appears in all copies and that both the copyright notice and
* this permission notice appear in supporting documentation. In
* addition, Intel grants this permission provided that you
* prominently mark as not part of the original any modifications
* made to this software or documentation, and that the name of
* Intel Corporation not be used in advertising or publicity
* pertaining to distribution of the software or the documentation
* without specific, written prior permission.
*
* Intel Corporation does not warrant, guarantee or make any
* representations regarding the use of, or the results of the use
* of, the software and documentation in terms of correctness,
* accuracy, reliability, currentness, or otherwise; and you rely
* on the software, documentation and results solely at your own risk.
*
*\NOMANUAL
**********************************************************************
*/
/*
******************************************************************************
*
* REGISTER DESCRIPTION OF RM9000x2gl DUART
*
* $Id: rm9000x2gl.h,v 1.0 1993/06/07 15:07:59 wise active $
*
*\NOMANUAL
*******************************************************************************
*/
/* Register offsets from base address */
#define RBR 0x08 /* receiver buffer register */
#define THR 0x0C /* transmit holding register */
#define DLL 0x10 /* divisor latch */
#define IER 0x14 /* interrupt enable register */
#define DLM 0x18 /* divisor latch(MS) */
#define IIR 0x1C /* interrupt identification register */
#define FCR 0x20 /* FIFO control register */
#define LCR 0x24 /* line control register */
#define MCR 0x28 /* modem control register */
#define LSR 0x2C /* line status register */
#define MSR 0x30 /* modem status register */
#define SCR 0x34 /* scratch register */
#define BAUD_LO(baud) ((XTAL/(16*baud)) & 0xff)
#define BAUD_HI(baud) (((XTAL/(16*baud)) & 0xff00) >> 8)
/* Line Control Register */
#define CHAR_LEN_5 0x00 /* 5bits data size */
#define CHAR_LEN_6 0x01 /* 6bits data size */
#define CHAR_LEN_7 0x02 /* 7bits data size */
#define CHAR_LEN_8 0x03 /* 8bits data size */
#define LCR_STB 0x04 /* 2 stop bits */
#define ONE_STOP 0x00 /* one stop bit */
#define LCR_PEN 0x08 /* parity enable */
#define PARITY_NONE 0x00 /* parity disable */
#define LCR_EPS 0x10 /* even parity select */
#define LCR_SP 0x20 /* stick parity select */
#define LCR_SBRK 0x40 /* break control bit */
#define LCR_DLAB 0x80 /* divisor latch access enable */
#define DLAB LCR_DLAB
/* Line Status Register */
#define LSR_DR 0x01 /* data ready */
#define RxCHAR_AVAIL LSR_DR /* data ready */
#define LSR_OE 0x02 /* overrun error */
#define LSR_PE 0x04 /* parity error */
#define LSR_FE 0x08 /* framing error */
#define LSR_BI 0x10 /* break interrupt */
#define LSR_THRE 0x20 /* transmit holding register empty */
#define LSR_TEMT 0x40 /* transmitter empty */
#define LSR_FERR 0x80 /* in fifo mode, set when PE,FE or BI error */
/* Interrupt Identification Register */
#define IIR_IP 0x01
#define IIR_ID 0x0e
#define IIR_RLS 0x06 /* received line status */
#define Rx_INT IIR_RLS /* received line status */
#define IIR_RDA 0x04 /* received data available */
#define RxFIFO_INT IIR_RDA /* received data available */
#define IIR_THRE 0x02 /* transmit holding register empty */
#define TxFIFO_INT IIR_THRE
#define IIR_MSTAT 0x00 /* modem status */
#define IIR_TIMEOUT 0x0c /* char receive timeout */
/* Interrupt Enable Register */
#define IER_ERDAI 0x01 /* received data avail. & timeout int */
#define RxFIFO_BIT IER_ERDAI
#define IER_ETHREI 0x02 /* transmitter holding register empty int */
#define TxFIFO_BIT IER_ETHREI
#define IER_ELSI 0x04 /* receiver line status int enable */
#define Rx_BIT IER_ELSI
#define IER_EMSI 0x08 /* modem status int enable */
/* Modem Control Register */
#define MCR_DTR 0x01 /* dtr output */
#define DTR MCR_DTR
#define MCR_RTS 0x02 /* rts output */
#define MCR_OUT1 0x04 /* output #1 */
#define MCR_OUT2 0x08 /* output #2 */
#define MCR_LOOP 0x10 /* loopback enable */
/* Modem Status Register */
#define MSR_DCTS 0x01 /* cts change */
#define MSR_DDSR 0x02 /* dsr change */
#define MSR_TERI 0x04 /* ring indicator change */
#define MSR_DDCD 0x08 /* data carrier indicator change */
#define MSR_CTS 0x10 /* complement of cts */
#define MSR_DSR 0x20 /* complement of dsr */
#define MSR_RI 0x40 /* complement of ring signal */
#define MSR_DCD 0x80 /* complement of dcd */
/* FIFO Control Register */
#define FCR_EN 0x01 /* enable xmit and rcvr */
#define FIFO_ENABLE FCR_EN
#define FCR_RXCLR 0x02 /* clears rcvr fifo */
#define RxCLEAR FCR_RXCLR
#define FCR_TXCLR 0x04 /* clears xmit fifo */
#define TxCLEAR FCR_TXCLR
#define FCR_DMA 0x08 /* dma */
#define FCR_RXTRIG_L 0x40 /* rcvr fifo trigger lvl low */
#define FCR_RXTRIG_H 0x80 /* rcvr fifo trigger lvl high */
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct /* RM9000x2gl_CHAN * */
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar) (); /* pointer to xmitr function */
STATUS (*putRcvChar) (); /* pointer to rcvr function */
void * getTxArg;
void * putRcvArg;
UINT8 *regs; /* RM9000x2gl registers */
UINT8 level; /* 8259a interrupt level for this device */
UINT8 ier; /* copy of ier */
UINT8 lcr; /* copy of lcr, not used by rm9000x2gl driver */
UINT8 mcr; /* copy of modem control register */
UINT8 pad1;
UINT16 channelMode; /* such as INT, POLL modes */
UINT16 regDelta; /* register address spacing */
int baudRate;
UINT32 xtal; /* UART clock frequency */
UINT32 options; /* hardware setup options */
} RM9000x2gl_CHAN;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void rm9000x2glInt (RM9000x2gl_CHAN *);
extern void rm9000x2glDevInit (RM9000x2gl_CHAN *);
#else
extern void rm9000x2glInt ();
extern void rm9000x2glDevInit ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCrm9000x2glSioh */
vxworks-6.9/target/h/drv/sio/shSciSio.h
+222
View File
@@ -0,0 +1,222 @@
/* shSciSio.h - header file for Renesas SH on-chip SCI serial driver */
/*
* Copyright (c) 1996-2006, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01t,29apr10,pad Moved extern C statement after include statements.
01s,18nov03,h_k added SCI_SCR_CKE and SCI_SMR_CKS definitions.
01r,10nov03,h_k corrected the comment for the BRR formula.
01q,06nov03,h_k added SH7705 support. (SPR #91873)
01p,15feb01,hk add #ifdef SCI_TYPE_SH7604 to adjust baud rate for SH7604.
01o,09nov00,csi modification to optimize SMR and BRR define
01n,30aug00,zl added 30MHz PCLK support for SH7600
01m,20aug00,hk merged SH7040 to SH7600.
01l,04aug00,rsh Add frequency defines for sh7729
01k,31may00,frf SH7751 for T2
01j,29dec98,hk merged for SH7750,SH7729,SH7700,SH7600,SH7410,SH7040,SH7000.
01i,10aug98,jmb add 57600 baud for Manta-DSP.
01h,09jul98,jmb add support for Manta-SH3 frequencies.
01g,01jun98,jmb added "options" to support SIO_HW_OPTS_GET.
01f,19may98,jmc added support for SH-DSP and SH3-DSP.
01g,18sep98,hk fixed SH7750 support for 33.33MHz PCLK.
01f,02jul98,st added SH7750 support.
01e,14jan98,jmc added baud rate table entries for 20/10/5MHz.
01d,25apr97,hk changed SH704X to SH7040.
01c,21mar97,hk added SCI_BAUD typedef. enhanced defs for smr and brr.
01b,10mar97,hk renamed this header as shSciSio.h from shSio.h. changed
SH_CHAN to SCI_CHAN. deleted SH_DUSART. changed function
prototype names to shSciXyz. changed definition layout.
01a,16dec96,kn derived from templateSio.h
*/
#ifndef __INCshSciSioh
#define __INCshSciSioh
#include <sioLib.h>
#ifdef __cplusplus
extern "C" {
#endif
/* device channel structure */
typedef struct
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar) ();
STATUS (*putRcvChar) ();
void * getTxArg;
void * putRcvArg;
/* register addresses */
volatile UINT8 * smr; /* serial mode register */
volatile UINT8 * brr; /* bit rate register */
volatile UINT8 * scr; /* serial control register */
volatile UINT8 * tdr; /* transmit data register */
volatile UINT8 * ssr; /* serial status register */
volatile UINT8 * rdr; /* receive data register */
int mode; /* current mode (interrupt or poll) */
int baud; /* baud rate */
UINT options; /* data format */
} SCI_CHAN;
/* entry structure for baud-rate table */
typedef struct
{
int rate; /* baud-rate to be set */
UINT8 cksVal; /* clock select bits for smr */
UINT8 brrVal; /* value to set in brr */
} SCI_BAUD;
/* bit values for smr (serial mode register) */
#define SCI_SMR_ASYNC 0x00 /* async mode */
#define SCI_SMR_SYNC 0x80 /* synchronous mode */
#define SCI_SMR_8_BITS 0x00 /* 8 bits data */
#define SCI_SMR_7_BITS 0x40 /* 7 bits data */
#define SCI_SMR_PAR_DIS 0x00 /* parity disable */
#define SCI_SMR_PAR_EN 0x20 /* parity enable */
#define SCI_SMR_PAR_EVEN 0x00 /* even parity */
#define SCI_SMR_PAR_ODD 0x10 /* odd parity */
#define SCI_SMR_1_STOP 0x00 /* 1 stop bit */
#define SCI_SMR_2_STOP 0x08 /* 2 stop bit */
#define SCI_SMR_MP_DIS 0x00 /* multiprocessor format disable */
#define SCI_SMR_MP_EN 0x04 /* multiprocessor format enable */
#define SCI_SMR_CKS 0x03 /* clock select bits */
#define SCI_SMR_CKS_MASK 0xfc /* mask for clock select bits */
#ifdef SYS_PCLK_FREQ
# define SCI_FREQ SYS_PCLK_FREQ
#else
# ifdef SCI_TYPE_SH7604
# define SCI_FREQ (SYS_CPU_FREQ / 4)
# else /* SH704x, SH705x */
# define SCI_FREQ SYS_CPU_FREQ
# endif
#endif
/*
* To calculate BRR value, the following formula used.
* BRR = (FREQ / (FORM_VAL * 2^(2n-1)) * BaudRate)) - 1
*
* In the following macros are used
* SMR_VALUE is n
* CLK_DIVIDE(y) 4^n
*
* In the BRR_VALUE macro the extra mutiplication, division and addition
* is used to get correct rounding.
*/
#ifndef BRR_FORM_VAL
#define BRR_FORM_VAL 64
#endif
#define SMR_VALUE(x) (((SCI_FREQ/(BRR_FORM_VAL*32*(x))) >= 64) ? 3 : \
((SCI_FREQ/(BRR_FORM_VAL*32*(x))) >= 16) ? 2 : \
((SCI_FREQ/(BRR_FORM_VAL*32*(x))) >= 4) ? 1 : 0)
#define CLK_DIVIDE(y) (((SCI_FREQ/(BRR_FORM_VAL*32*(y))) >= 64) ? 64 : \
((SCI_FREQ/(BRR_FORM_VAL*32*(y))) >= 16) ? 16 : \
((SCI_FREQ/(BRR_FORM_VAL*32*(y))) >= 4) ? 4 : 1)
#define BRR_FORMULA(s) (((20*SCI_FREQ)/ \
(BRR_FORM_VAL*CLK_DIVIDE(s)*(s))-5)/10)
#define BRR_VALUE(z) ((BRR_FORMULA(z) > 255) ? 0 : BRR_FORMULA(z))
#define SCI_SMR_CKS_50 SMR_VALUE(50)
#define SCI_SMR_CKS_75 SMR_VALUE(75)
#define SCI_SMR_CKS_110 SMR_VALUE(110)
#define SCI_SMR_CKS_134 SMR_VALUE(134)
#define SCI_SMR_CKS_150 SMR_VALUE(150)
#define SCI_SMR_CKS_200 SMR_VALUE(200)
#define SCI_SMR_CKS_300 SMR_VALUE(300)
#define SCI_SMR_CKS_600 SMR_VALUE(600)
#define SCI_SMR_CKS_1200 SMR_VALUE(1200)
#define SCI_SMR_CKS_1800 SMR_VALUE(1800)
#define SCI_SMR_CKS_2400 SMR_VALUE(2400)
#define SCI_SMR_CKS_3600 SMR_VALUE(3600)
#define SCI_SMR_CKS_4800 SMR_VALUE(4800)
#define SCI_SMR_CKS_7200 SMR_VALUE(7200)
#define SCI_SMR_CKS_9600 SMR_VALUE(9600)
#define SCI_SMR_CKS_19200 SMR_VALUE(19200)
#define SCI_SMR_CKS_31250 SMR_VALUE(31250)
#define SCI_SMR_CKS_38400 SMR_VALUE(38400)
#define SCI_SMR_CKS_57600 SMR_VALUE(57600)
#define SCI_SMR_CKS_115200 SMR_VALUE(115200)
#define SCI_SMR_CKS_500000 SMR_VALUE(500000)
/* bit values for brr (bit rate register) */
#define SCI_BRR_50 BRR_VALUE(50)
#define SCI_BRR_75 BRR_VALUE(75)
#define SCI_BRR_110 BRR_VALUE(110)
#define SCI_BRR_134 BRR_VALUE(134)
#define SCI_BRR_150 BRR_VALUE(150)
#define SCI_BRR_200 BRR_VALUE(200)
#define SCI_BRR_300 BRR_VALUE(300)
#define SCI_BRR_600 BRR_VALUE(600)
#define SCI_BRR_1200 BRR_VALUE(1200)
#define SCI_BRR_1800 BRR_VALUE(1800)
#define SCI_BRR_2400 BRR_VALUE(2400)
#define SCI_BRR_3600 BRR_VALUE(3600)
#define SCI_BRR_4800 BRR_VALUE(4800)
#define SCI_BRR_7200 BRR_VALUE(9600)
#define SCI_BRR_9600 BRR_VALUE(9600)
#define SCI_BRR_19200 BRR_VALUE(19200)
#define SCI_BRR_31250 BRR_VALUE(31250)
#define SCI_BRR_38400 BRR_VALUE(38400)
#define SCI_BRR_57600 BRR_VALUE(57600)
#define SCI_BRR_115200 BRR_VALUE(115200)
#define SCI_BRR_500000 BRR_VALUE(500000)
/* bit values for scr (serial control register) */
#define SCI_SCR_TIE 0x80 /* transmit interrupt enable */
#define SCI_SCR_RIE 0x40 /* receive interrupt enable */
#define SCI_SCR_TXE 0x20 /* transmit enable */
#define SCI_SCR_RXE 0x10 /* receive enable */
/* #define SCI_SCR_MPIE 0x08 /@ multiprocessor interrupt enable */
#define SCI_SCR_TEIE 0x04 /* transmit end interrupt enable */
#define SCI_SCR_CKE 0x03 /* clock enable bits */
/* bit values for ssr (serial status register) */
#define SCI_SSR_TDRE 0x80 /* transmit data register empty */
#define SCI_SSR_RDRF 0x40 /* receive data register full */
#define SCI_SSR_ORER 0x20 /* overrun error */
#define SCI_SSR_FER 0x10 /* framing error */
#define SCI_SSR_PER 0x08 /* parity error */
#define SCI_SSR_TEND 0x04 /* transmit end */
/* #define SCI_SSR_MPB 0x02 /@ multiprocessor bit */
/* #define SCI_SSR_MPBT 0x01 /@ multiprocessor bit transfer */
/* function prototypes */
extern void shSciDevInit (SCI_CHAN *pChan);
extern void shSciIntRcv (SCI_CHAN *pChan);
extern void shSciIntTx (SCI_CHAN *pChan);
extern void shSciIntErr (SCI_CHAN *pChan);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCshSciSioh */
vxworks-6.9/target/h/drv/sio/shScifSio.h
+163
View File
@@ -0,0 +1,163 @@
/* shScifSio.h - header file for Renesas SH on-chip SCIF serial driver */
/*
* Copyright (c) 1984-2006, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01r,29apr10,pad Moved extern C statement after include statements.
01q,10mar06,h_k updated for SH7785. (SPR#118883)
01p,18oct05,h_k added SH7710 and SH7705 support. (SPR #90076)
01o,05nov02,h_k added tfdr2 to SCIF_CHAN for SH7760 support. (SPR #105971)
01n,06mar02,h_k added lsr2 and ss2r2 to SCIF_CHAN and SCIF_LSR2_ORER and
SCIF_SS2R2_ORER definitions (SPR #73777).
01m,15nov00,csi modification to optimize SMR and BRR define
01l,30aug00,zl added 30MHz PCLK support for SH7600
01k,04aug00,rsh Add 33.33Mhz frequency defines for sh7729
01j,31may00,frf SH7751 for T2
01i,05mar99,hk Sorted out CPU conditional order.
01h,26nov98,hk Added support for SH7750.
01g,10aug98,jmb reg size fix.
01f,10aug98,jmb bugfix.
01e,10aug98,jmb Added support for Manta-DSP.
01d,30jul98,jmb Added support for Manta-SH3 frequencies.
01c,30may98,jmb Added options to support multiple data formats.
01b,23may98,jmb Fixed decl's and FCR2 macros, transmit triggers.
01a,20may98,jmb Created.
*/
#ifndef __INCshScifSioh
#define __INCshScifSioh
#include <sioLib.h>
#include <drv/sio/shSciSio.h>
#ifdef __cplusplus
extern "C" {
#endif
#if (CPU==SH7750)
#define SZ_SMR2 UINT16
#define SZ_SCR2 UINT16
#define SZ_FCR2 UINT16
#else
# ifndef SZ_SMR2
# define SZ_SMR2 UINT8
# endif
# ifndef SZ_SCR2
# define SZ_SCR2 UINT8
# endif
# ifndef SZ_FCR2
# define SZ_FCR2 UINT8
# endif
#endif
/* device channel structure */
typedef struct
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar) ();
STATUS (*putRcvChar) ();
void * getTxArg;
void * putRcvArg;
/* info */
int mode; /* current mode (interrupt or poll) */
int baud; /* baud rate */
UINT options; /* data format options */
/* register addresses */
volatile SZ_SMR2 * smr2; /* serial mode register */
volatile UINT8 * brr2; /* bit rate register */
volatile SZ_SCR2 * scr2; /* serial control register */
volatile UINT8 * sfdr2; /* transmit FIFO data register */
volatile UINT16 * ssr2; /* serial status register */
volatile UINT8 * frdr2; /* receive FIFO data register */
volatile SZ_FCR2 * fcr2; /* FIFO control register */
volatile UINT16 * fdr2; /* data count set register */
volatile UINT16 * lsr2; /* line status register */
volatile UINT8 * ss2r2; /* serial status 2 register */
volatile UINT16 * tfdr2; /* transmit data count set register */
} SCIF_CHAN;
/* Maximum FIFO length */
#ifndef SCIF_FIFO_LEN
#define SCIF_FIFO_LEN 16
#endif
/* Extra bit values for scr (serial control register) */
#ifndef SCIF_SCR2_EXIE
#define SCIF_SCR2_EXIE 0
#endif
/* Bit values for FIFO control register */
#define SCIF_FCR2_RTRG 0xc0 /* Read mask for receive trigger */
#define SCIF_FCR2_RTRG_1 0x00 /* 1 char in FIFO triggers receive */
#define SCIF_FCR2_RTRG_4 0x40 /* 4 chars in FIFO triggers receive */
#define SCIF_FCR2_RTRG_8 0x80 /* 8 chars in FIFO triggers receive */
#define SCIF_FCR2_RTRG_14 0xc0 /* 14 chars in FIFO triggers receive */
#define SCIF_FCR2_TTRG 0x30 /* Read mask for transmit trigger */
#define SCIF_FCR2_TTRG_8 0x00 /* */
#define SCIF_FCR2_TTRG_4 0x10 /* */
#define SCIF_FCR2_TTRG_2 0x20 /* */
#define SCIF_FCR2_TTRG_1 0x30 /* */
#ifndef SCIF_FCR2_TRG_DEFAULT
#define SCIF_FCR2_TRG_DEFAULT (SCIF_FCR2_RTRG | SCIF_FCR2_TTRG)
#endif
#define SCIF_FCR2_MCE 0x8 /* Enable RTS/CTS signals */
#define SCIF_FCR2_TFRST 0x4 /* Clear transmit FIFO on reset */
#define SCIF_FCR2_RFRST 0x2 /* Clear receive RIFO on reset */
#define SCIF_FCR2_LOOP 0x1 /* Loopback mode */
/* bit values for ssr (serial status register) */
#define SCIF_SSR2_ER 0x80 /* framing or parity error */
#define SCIF_SSR2_TEND 0x40 /* tranmission end indicator */
#define SCIF_SSR2_TDFE 0x20 /* transmit data FIFO empty */
#define SCIF_SSR2_BRK 0x10 /* break signal received */
#define SCIF_SSR2_FER 0x08 /* framing error */
#define SCIF_SSR2_PER 0x04 /* parity error */
#define SCIF_SSR2_RDF 0x02 /* receive FIFO full */
#define SCIF_SSR2_DR 0x01 /* data ready in receive FIFO */
/* bit value for lsr (line status register) */
#define SCIF_LSR2_ORER 0x1 /* overrun error */
/* bit value for ss2r (serial status 2 register) */
#define SCIF_SS2R2_ORER 0x1 /* overrun error */
/* function prototypes */
extern void shScifDevInit (SCIF_CHAN *pChan);
extern void shScifIntRcv (SCIF_CHAN *pChan);
extern void shScifIntTx (SCIF_CHAN *pChan);
extern void shScifIntErr (SCIF_CHAN *pChan);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCshScifSioh */
vxworks-6.9/target/h/drv/sio/templateSio.h
+78
View File
@@ -0,0 +1,78 @@
/* templateSio.h - header file for template serial driver */
/* Copyright 1984-2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01f,26apr02,dat Adding cplusplus protection, SPR 75017
01e,29sep01,dat Rework for adaptor type struct, new API is just
create and destroy.
01d,01jul97,db added registers and defines for modem control.
01c,24feb97,dat used SIO_CHAN as first structure element,
instead of SIO_DRV_FUNCS *.
01b,17dec96,dat added 'options' to chan structure.
01a,02aug95,ms written.
*/
#ifndef __INCtemplateSioh
#define __INCtemplateSioh
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* This driver for a generic SIO device only uses 8 bit reads/writes.
* These are the register offsets for our fictitious device.
*
* Control Register 0x0 (write)
* Status Register 0x0 (read)
* Data register 0x1 (read/write)
* Modem Status Register 0x2 (read)
* Modem Control Register 0x2 (write)
* Baud Rate Control Reg. 0x3 (read/write)
*
* The template driver uses 3 interrupt vectors.
* Receive Interrupt 0x0
* Transmit Interrupt 0x1
* Error/Modem Interrupt 0x2
*
* Other adaptor functions used include:
* intConnect, intDisconnect.
*/
#define TEMPLATE_CSR_ID 0x0 /* register offsets */
#define TEMPLATE_DATA_ID 0x1
#define TEMPLATE_MSR_ID 0x2
#define TEMPLATE_BAUD_ID 0x3
#define TEMPLATE_RXINT_ID 0x0 /* vector offsets */
#define TEMPLATE_TXINT_ID 0x1
#define TEMPLATE_ERRINT_ID 0x2
/*
* Here is the real API for creating and destroying an instance of a template
* SIO device. Use the standard sioLib functions
* for manipulating the device. The only really device specific
* functions are for creation and destruction.
*/
IMPORT SIO_CHAN * templateSioCreate /* create an instance */
(
UINT32 ioBase, /* device adaptor specific data */
UINT32 vecBase, /* vector base number */
UINT32 intLevel, /* interrupt level for vectors */
UINT32 clkFreq /* device clock frequency */
);
IMPORT STATUS templateSioDestroy /* destroy an instance */
(SIO_CHAN *); /* must be a template SIO type object */
#ifdef __cplusplus
}
#endif
#endif /* __INCtemplateSioh */
vxworks-6.9/target/h/drv/sio/z8530Sio.h
+342
View File
@@ -0,0 +1,342 @@
/* z8530Sio.h - header file for binary interface z8530 driver */
/* Copyright 1984-1994 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,20may97,db added element options to Z8530_CHAN structure to
implement hardware options & modem control(SPR #1037).
01c,13oct95,ms added comments for what fields need to be set by the BSP
01b,15jun95,ms updated for new driver structure
01a,20dec94,ms written (from z8530Serial.h).
*/
#ifndef __INCwdbz8530h
#define __INCwdbz8530h
#include "sioLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* device and channel structures */
/* The BSP must initilize all Z8530_CHAN fields which say "BSP:" */
typedef struct /* Z8530_CHAN */
{
/* always goes first */
SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */
/* callbacks */
STATUS (*getTxChar) (); /* pointer to xmitr function */
STATUS (*putRcvChar) (); /* pointer to rcvr functione */
void * getTxArg;
void * putRcvArg;
/* control and data register addresses */
volatile char * cr; /* BSP: control register I/O address */
volatile char * dr; /* BSP: data port I/O address */
/* misc values */
int baudFreq; /* BSP: baud clock frequency */
int baudRate; /* baud rate */
int options; /* hardware options */
char writeReg5; /* BSP: write register 5 value */
char writeReg11; /* BSP: write register 11 value */
char writeReg14; /* BSP: write register 14 value */
/* interrupt/polled mode configuration info */
uint_t mode; /* SIO_MODE_[INT | POLL] */
char intVec; /* BSP: interrupt vector address */
char intType; /* BSP: type of vector to supply from 8530 */
uint_t channel; /* channel number (0 or 1) */
} Z8530_CHAN;
typedef struct
{
Z8530_CHAN portA; /* port A device descriptor */
Z8530_CHAN portB; /* port B device descriptor */
} Z8530_DUSART;
/* channels */
#define SCC_CHANNEL_A 0
#define SCC_CHANNEL_B 1
/* bit values for write register 0 */
/* command register */
#define SCC_WR0_SEL_WR0 0x00
#define SCC_WR0_SEL_WR1 0x01
#define SCC_WR0_SEL_WR2 0x02
#define SCC_WR0_SEL_WR3 0x03
#define SCC_WR0_SEL_WR4 0x04
#define SCC_WR0_SEL_WR5 0x05
#define SCC_WR0_SEL_WR6 0x06
#define SCC_WR0_SEL_WR7 0x07
#define SCC_WR0_SEL_WR8 0x08
#define SCC_WR0_SEL_WR9 0x09
#define SCC_WR0_SEL_WR10 0x0a
#define SCC_WR0_SEL_WR11 0x0b
#define SCC_WR0_SEL_WR12 0x0c
#define SCC_WR0_SEL_WR13 0x0d
#define SCC_WR0_SEL_WR14 0x0e
#define SCC_WR0_SEL_WR15 0x0f
#define SCC_WR0_NULL_CODE 0x00
#define SCC_WR0_RST_INT 0x10
#define SCC_WR0_SEND_ABORT 0x18
#define SCC_WR0_EN_INT_RX 0x20
#define SCC_WR0_RST_TX_INT 0x28
#define SCC_WR0_ERR_RST 0x30
#define SCC_WR0_RST_HI_IUS 0x38
#define SCC_WR0_RST_RX_CRC 0x40
#define SCC_WR0_RST_TX_CRC 0x80
#define SCC_WR0_RST_TX_UND 0xc0
/* write register 2 */
/* interrupt vector */
/* bit values for write register 1 */
/* tx/rx interrupt and data transfer mode definition */
#define SCC_WR1_EXT_INT_EN 0x01
#define SCC_WR1_TX_INT_EN 0x02
#define SCC_WR1_PARITY 0x04
#define SCC_WR1_RX_INT_DIS 0x00
#define SCC_WR1_RX_INT_FIR 0x08
#define SCC_WR1_INT_ALL_RX 0x10
#define SCC_WR1_RX_INT_SPE 0x18
#define SCC_WR1_RDMA_RECTR 0x20
#define SCC_WR1_RDMA_FUNC 0x40
#define SCC_WR1_RDMA_EN 0x80
/* bit values for write register 3 */
/* receive parameters and control */
#define SCC_WR3_RX_EN 0x01
#define SCC_WR3_SYNC_CHAR 0x02
#define SCC_WR3_ADR_SEARCH 0x04
#define SCC_WR3_RX_CRC_EN 0x08
#define SCC_WR3_ENTER_HUNT 0x10
#define SCC_WR3_AUTO_EN 0x20
#define SCC_WR3_RX_5_BITS 0x00
#define SCC_WR3_RX_7_BITS 0x40
#define SCC_WR3_RX_6_BITS 0x80
#define SCC_WR3_RX_8_BITS 0xc0
/* bit values for write register 4 */
/* tx/rx misc parameters and modes */
#define SCC_WR4_PAR_EN 0x01
#define SCC_WR4_PAR_EVEN 0x02
#define SCC_WR4_SYNC_EN 0x00
#define SCC_WR4_1_STOP 0x04
#define SCC_WR4_2_STOP 0x0c
#define SCC_WR4_8_SYNC 0x00
#define SCC_WR4_16_SYNC 0x10
#define SCC_WR4_SDLC 0x20
#define SCC_WR4_EXT_SYNC 0x30
#define SCC_WR4_1_CLOCK 0x00
#define SCC_WR4_16_CLOCK 0x40
#define SCC_WR4_32_CLOCK 0x80
#define SCC_WR4_64_CLOCK 0xc0
/* bit values for write register 5 */
/* transmit parameter and controls */
#define SCC_WR5_TX_CRC_EN 0x01
#define SCC_WR5_RTS 0x02
#define SCC_WR5_SDLC 0x04
#define SCC_WR5_TX_EN 0x08
#define SCC_WR5_SEND_BRK 0x10
#define SCC_WR5_TX_5_BITS 0x00
#define SCC_WR5_TX_7_BITS 0x20
#define SCC_WR5_TX_6_BITS 0x40
#define SCC_WR5_TX_8_BITS 0x60
#define SCC_WR5_DTR 0x80
/* write register 6 */
/* sync chars or sdlc address field */
/* write register 7 */
/* sync char or sdlc flag */
/* write register 8 */
/* transmit buffer */
/* bit values for write register 9 */
/* master interrupt control */
#define SCC_WR9_VIS 0x01
#define SCC_WR9_NV 0x02
#define SCC_WR9_DLC 0x04
#define SCC_WR9_MIE 0x08
#define SCC_WR9_STATUS_HI 0x10
#define SCC_WR9_NO_RST 0x00
#define SCC_WR9_CH_B_RST 0x40
#define SCC_WR9_CH_A_RST 0x80
#define SCC_WR9_HDWR_RST 0xc0
/* bit values for write register 10 */
/* misc tx/rx control bits */
#define SCC_WR10_6_BIT_SYNC 0x01
#define SCC_WR10_LOOP_MODE 0x02
#define SCC_WR10_ABORT_UND 0x04
#define SCC_WR10_MARK_IDLE 0x08
#define SCC_WR10_ACT_POLL 0x10
#define SCC_WR10_NRZ 0x00
#define SCC_WR10_NRZI 0x20
#define SCC_WR10_FM1 0x40
#define SCC_WR10_FM0 0x60
#define SCC_WR10_CRC_PRESET 0x80
/* bit values for write register 11 */
/* clock mode control */
#define SCC_WR11_OUT_XTAL 0x00
#define SCC_WR11_OUT_TX_CLK 0x01
#define SCC_WR11_OUT_BR_GEN 0x02
#define SCC_WR11_OUT_DPLL 0x03
#define SCC_WR11_TRXC_OI 0x04
#define SCC_WR11_TX_RTXC 0x00
#define SCC_WR11_TX_TRXC 0x08
#define SCC_WR11_TX_BR_GEN 0x10
#define SCC_WR11_TX_DPLL 0x18
#define SCC_WR11_RX_RTXC 0x00
#define SCC_WR11_RX_TRXC 0x20
#define SCC_WR11_RX_BR_GEN 0x40
#define SCC_WR11_RX_DPLL 0x60
#define SCC_WR11_RTXC_XTAL 0x80
/* write register 12 */
/* lower byte of baud rate generator time constant */
/* write register 13 */
/* upper byte of baud rate generator time constant */
/* bit values for write register 14 */
/* misc control bits */
#define SCC_WR14_BR_EN 0x01
#define SCC_WR14_BR_SRC 0x02
#define SCC_WR14_DTR_FUNC 0x04
#define SCC_WR14_AUTO_ECHO 0x08
#define SCC_WR14_LCL_LOOP 0x10
#define SCC_WR14_NULL 0x00
#define SCC_WR14_SEARCH 0x20
#define SCC_WR14_RST_CLK 0x40
#define SCC_WR14_DIS_DPLL 0x60
#define SCC_WR14_SRC_BR 0x80
#define SCC_WR14_SRC_RTXC 0xa0
#define SCC_WR14_FM_MODE 0xc0
#define SCC_WR14_NRZI 0xe0
/* bit values for write register 15 */
/* external/status interrupt control */
#define SCC_WR15_ZERO_CNT 0x02
#define SCC_WR15_CD_IE 0x08
#define SCC_WR15_SYNC_IE 0x10
#define SCC_WR15_CTS_IE 0x20
#define SCC_WR15_TX_UND_IE 0x40
#define SCC_WR15_BREAK_IE 0x80
/* bit values for read register 0 */
/* tx/rx buffer status and external status */
#define SCC_RR0_RX_AVAIL 0x01
#define SCC_RR0_ZERO_CNT 0x02
#define SCC_RR0_TX_EMPTY 0x04
#define SCC_RR0_CD 0x08
#define SCC_RR0_SYNC 0x10
#define SCC_RR0_CTS 0x20
#define SCC_RR0_TX_UND 0x40
#define SCC_RR0_BREAK 0x80
/* bit values for read register 1 */
#define SCC_RR1_ALL_SENT 0x01
#define SCC_RR1_RES_CD_2 0x02
#define SCC_RR1_RES_CD_1 0x01
#define SCC_RR1_RES_CD_0 0x08
#define SCC_RR1_PAR_ERR 0x10
#define SCC_RR1_RX_OV_ERR 0x20
#define SCC_RR1_CRC_ERR 0x40
#define SCC_RR1_END_FRAME 0x80
/* read register 2 */
/* interrupt vector */
/* bit values for read register 3 */
/* interrupt pending register */
#define SCC_RR3_B_EXT_IP 0x01
#define SCC_RR3_B_TX_IP 0x02
#define SCC_RR3_B_RX_IP 0x04
#define SCC_RR3_A_EXT_IP 0x08
#define SCC_RR3_A_TX_IP 0x10
#define SCC_RR3_A_RX_IP 0x20
/* read register 8 */
/* receive data register */
/* bit values for read register 10 */
/* misc status bits */
#define SCC_RR10_ON_LOOP 0x02
#define SCC_RR10_LOOP_SEND 0x10
#define SCC_RR10_2_CLK_MIS 0x40
#define SCC_RR10_1_CLK_MIS 0x80
/* read register 12 */
/* lower byte of time constant */
/* read register 13 */
/* upper byte of time constant */
/* bit values for read register 15 */
/* external/status ie bits */
#define SCC_RR15_ZERO_CNT 0x02
#define SCC_RR15_CD_IE 0x08
#define SCC_RR15_SYNC_IE 0x10
#define SCC_RR15_CTS_IE 0x20
#define SCC_RR15_TX_UND_IE 0x40
#define SCC_RR15_BREAK_IE 0x80
#if defined(__STDC__) || defined(__cplusplus)
extern void z8530DevInit (Z8530_DUSART *pDusart);
extern void z8530IntWr (Z8530_CHAN * pChan);
extern void z8530IntRd (Z8530_CHAN * pChan);
extern void z8530IntEx (Z8530_CHAN * pChan);
extern void z8530Int (Z8530_DUSART *pDusart);
#else /* __STDC__ */
extern void z8530DevInit ();
extern void z8530IntWr ();
extern void z8530IntRd ();
extern void z8530IntEx ();
extern void z8530Int ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* __INCwdbz8530h */