original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,86 @@
|
||||
/* hd146818.h - Hitachi 146818 RTC Real Time Clock header */
|
||||
|
||||
/* Copyright 1991-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,22sep92,rrr added support for c++
|
||||
01d,26may92,rrr the tree shuffle
|
||||
01c,04oct91,rrr passed through the ansification filter
|
||||
-fixed #else and #endif
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01b,07jun91,hdn defined HD146818_REG_OFFSET.
|
||||
01a,26feb91,hdn written.
|
||||
*/
|
||||
|
||||
#ifndef __INChd146818h
|
||||
#define __INChd146818h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define HD146818_REG_OFFSET 3
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
typedef struct
|
||||
{
|
||||
UCHAR pad0[HD146818_REG_OFFSET];
|
||||
UCHAR seconds;
|
||||
UCHAR pad1[HD146818_REG_OFFSET];
|
||||
UCHAR secAlarm;
|
||||
UCHAR pad2[HD146818_REG_OFFSET];
|
||||
UCHAR minutes;
|
||||
UCHAR pad3[HD146818_REG_OFFSET];
|
||||
UCHAR minAlarm;
|
||||
UCHAR pad4[HD146818_REG_OFFSET];
|
||||
UCHAR hours;
|
||||
UCHAR pad5[HD146818_REG_OFFSET];
|
||||
UCHAR hrAlarm;
|
||||
UCHAR pad6[HD146818_REG_OFFSET];
|
||||
UCHAR dayOfWeek;
|
||||
UCHAR pad7[HD146818_REG_OFFSET];
|
||||
UCHAR date;
|
||||
UCHAR pad8[HD146818_REG_OFFSET];
|
||||
UCHAR month;
|
||||
UCHAR pad9[HD146818_REG_OFFSET];
|
||||
UCHAR year;
|
||||
UCHAR pad10[HD146818_REG_OFFSET];
|
||||
UCHAR controlA;
|
||||
UCHAR pad11[HD146818_REG_OFFSET];
|
||||
UCHAR controlB;
|
||||
UCHAR pad12[HD146818_REG_OFFSET];
|
||||
UCHAR controlC;
|
||||
UCHAR pad13[HD146818_REG_OFFSET];
|
||||
UCHAR controlD;
|
||||
} RTC;
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/* bit values for control register A */
|
||||
#define RTC_UIP 0x80
|
||||
#define RTC_1MHZ 0x10
|
||||
#define RTC_32KHZ 0x20
|
||||
#define RTC_DV_RESET 0x60
|
||||
|
||||
/* bit values for control register B */
|
||||
#define RTC_SET 0x80
|
||||
#define RTC_PIE 0x40
|
||||
#define RTC_AIE 0x20
|
||||
#define RTC_UIE 0x10
|
||||
#define RTC_SQWE 0x08
|
||||
#define RTC_DM 0x04
|
||||
#define RTC_24 0x02
|
||||
#define RTC_DSE 0x01
|
||||
|
||||
/* bit values for control register C */
|
||||
#define RTC_IRQF 0x80
|
||||
#define RTC_PF 0x40
|
||||
#define RTC_AF 0x20
|
||||
#define RTC_UF 0x10
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INChd146818h */
|
||||
@@ -0,0 +1,167 @@
|
||||
/* n8570.h - National Semiconductor real time clock */
|
||||
|
||||
/* Copyright 1984-1994 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,02mar93.eve upgraded for 5.1
|
||||
01a,19mar90,trl written
|
||||
*/
|
||||
|
||||
#ifndef __INCn8570h
|
||||
#define __INCn8570h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* registers */
|
||||
|
||||
#define DP8570_MSR(base) ((char *) (base) + 0)
|
||||
#define DP8570_TIM0_CNTRL(base) ((char *) (base) + 1)
|
||||
#define DP8570_REALTIME_MODE(base) ((char *) (base) + 1)
|
||||
#define DP8570_TIM1_CNTRL(base) ((char *) (base) + 2)
|
||||
#define DP8570_OUTPUT_MODE(base) ((char *) (base) + 2)
|
||||
#define DP8570_PER_FLAG(base) ((char *) (base) + 3)
|
||||
#define DP8570_INT_CNTRL0(base) ((char *) (base) + 3)
|
||||
#define DP8570_INT_ROUTING(base) ((char *) (base) + 4)
|
||||
#define DP8570_INT_CNTRL1(base) ((char *) (base) + 4)
|
||||
#define DP8570_100s_SEC(base) ((char *) (base) + 5)
|
||||
#define DP8570_SEC_CNT(base) ((char *) (base) + 6)
|
||||
#define DP8570_MIN_CNT(base) ((char *) (base) + 7)
|
||||
#define DP8570_HOUR_CNT(base) ((char *) (base) + 8)
|
||||
#define DP8570_DAY_OF_MONTH_CNT(base) ((char *) (base) + 9)
|
||||
#define DP8570_MONTH_CNT(base) ((char *) (base) + 10)
|
||||
#define DP8570_YEAR_CNT(base) ((char *) (base) + 11)
|
||||
#define DP8570_UNITS_JULIAN_CNT(base) ((char *) (base) + 12)
|
||||
#define DP8570_100s_JULIAN_CNT(base) ((char *) (base) + 13)
|
||||
#define DP8570_DAY_OF_WEEK_CNT(base) ((char *) (base) + 14)
|
||||
#define DP8570_TIM0_LSB(base) ((char *) (base) + 15)
|
||||
#define DP8570_TIM0_MSB(base) ((char *) (base) + 16)
|
||||
#define DP8570_TIM1_LSB(base) ((char *) (base) + 17)
|
||||
#define DP8570_TIM1_MSB(base) ((char *) (base) + 18)
|
||||
#define DP8570_SEC_CMP(base) ((char *) (base) + 19)
|
||||
#define DP8570_MIN_CMP(base) ((char *) (base) + 20)
|
||||
#define DP8570_HOUR_CMP(base) ((char *) (base) + 21)
|
||||
#define DP8570_DAY_OF_MONTH_CMP(base) ((char *) (base) + 22)
|
||||
#define DP8570_MONTH_CMP(base) ((char *) (base) + 23)
|
||||
#define DP8570_DAY_OF_WEEK_CMP(base) ((char *) (base) + 24)
|
||||
#define DP8570_SEC_TIME_SAVE(base) ((char *) (base) + 25)
|
||||
#define DP8570_MIN_TIME_SAVE(base) ((char *) (base) + 26)
|
||||
#define DP8570_HOUR_TIME_SAVE(base) ((char *) (base) + 27)
|
||||
#define DP8570_DAY_OF_MONTH_TIME_SAVE(base) ((char *) (base) + 28)
|
||||
#define DP8570_MONTH_TIME_SAVE(base) ((char *) (base) + 29)
|
||||
#define DP8570_ONE_BYTE_RAM(base) ((char *) (base) + 30)
|
||||
#define DP8570_TEST_REG(base) ((char *) (base) + 31)
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/* main status register */
|
||||
|
||||
#define DP8570_INT_PENDING 0x01
|
||||
#define DP8570_PWR_FAIL_INT 0x02
|
||||
#define DP8570_PERIODIC_INT 0x04
|
||||
#define DP8570_ALARM_INT 0x08
|
||||
#define DP8570_TIMER0_INT 0x10
|
||||
#define DP8570_TIMER1_INT 0x20
|
||||
#define DP8570_REG_SET_1_SEL 0x40
|
||||
#define DP8570_RAM_PAGE_SEL 0x80
|
||||
|
||||
|
||||
/* timer 0/1 control register */
|
||||
|
||||
#define DP8570_TIMER_START_STOP 0x01
|
||||
#define DP8570_MODE_SEL_M0 0x02
|
||||
#define DP8570_MODE_SEL_M1 0x04
|
||||
#define DP8570_INPUT_CLK_SEL_C0 0x08
|
||||
#define DP8570_INPUT_CLK_SEL_C1 0x10
|
||||
#define DP8570_INPUT_CLK_SEL_C2 0x20
|
||||
#define DP8570_TIMER_READ 0x40
|
||||
#define DP8570_COUNT_HOLD_GATE 0x80
|
||||
|
||||
|
||||
/* periodic flag register */
|
||||
|
||||
#define DP8570_MINUTES_FLAG 0x01
|
||||
#define DP8570_10s_SECONDS_FLAG 0x02
|
||||
#define DP8570_SECONDS_FLAG 0x04
|
||||
#define DP8570_10e_SECONDS_FLAG 0x08
|
||||
#define DP8570_100e_SECONDS_FLAG 0x10
|
||||
#define DP8570_MILLISECONDS_FLAG 0x20
|
||||
#define DP8570_OSCILLATOR_FAILED 0x40
|
||||
#define DP8570_TEST_MODE 0x80
|
||||
|
||||
|
||||
/* interrupt routing register */
|
||||
|
||||
#define DP8570_PWR_FAIL_ROUTE 0x01
|
||||
#define DP8570_PERIODIC_ROUTE 0x02
|
||||
#define DP8570_ALARM_ROUTE 0x04
|
||||
#define DP8570_TIMER0_ROUTE 0x08
|
||||
#define DP8570_TIMER1_ROUTE 0x10
|
||||
#define DP8570_PWR_FAIL_DELAY 0x20
|
||||
#define DP8570_LOW_BATTERY_FLAG 0x40
|
||||
#define DP8570_TIME_SAVE_ENABLE 0x80
|
||||
|
||||
|
||||
/* real time mode register */
|
||||
|
||||
#define DP8570_LEAP_YEAR_LSB 0x01
|
||||
#define DP8570_LEAP_YEAR_MSB 0x02
|
||||
#define DP8570_12_24_HOUR_MODE 0x04
|
||||
#define DP8570_CLK_START_STOP 0x08
|
||||
#define DP8570_INT_OP 0x10
|
||||
#define DP8570_TIMER_PF_OP 0x20
|
||||
#define DP8570_OSCILLATOR_FREQ1 0x40
|
||||
#define DP8570_OSCILLATOR_FREQ2 0x80
|
||||
|
||||
|
||||
/* output mode register */
|
||||
|
||||
#define DP8570_T1_ACTIVE_HIGH 0x01
|
||||
#define DP8570_T1_PUSH_PULL 0x02
|
||||
#define DP8570_INT_ACTIVE_HIGH 0x04
|
||||
#define DP8570_INT_PUSH_PULL 0x08
|
||||
#define DP8570_MFO_ACTIVE_HIGH 0x10
|
||||
#define DP8570_MFO_PUSH_PULL 0x20
|
||||
#define DP8570_MFO_TIMER0 0x40
|
||||
#define DP8570_MFO_OSCILLATOR 0x80
|
||||
|
||||
|
||||
/* interrupt control register 0 */
|
||||
|
||||
#define DP8570_MINUTES_ENABLE 0x01
|
||||
#define DP8570_10s_SECONDS_ENABLE 0x02
|
||||
#define DP8570_SECONDS_ENABLE 0x04
|
||||
#define DP8570_10e_SECONDS_ENABLE 0x08
|
||||
#define DP8570_100e_SECONDS_ENABLE 0x10
|
||||
#define DP8570_MILLISECONDS_ENABLE 0x20
|
||||
#define DP8570_TIMER0_ENABLE 0x40
|
||||
#define DP8570_TIMER1_ENABLE 0x80
|
||||
|
||||
|
||||
/* interrupt control register 1 */
|
||||
|
||||
#define DP8570_SECOND_CMP_ENABLE 0x01
|
||||
#define DP8570_MINUTE_CMP_ENABLE 0x02
|
||||
#define DP8570_HOURS_CMP_ENABLE 0x04
|
||||
#define DP8570_DOM_CMP_ENABLE 0x08
|
||||
#define DP8570_MONTH_CMP_ENABLE 0x10
|
||||
#define DP8570_DOY_CMP_ENABLE 0x20
|
||||
#define DP8570_ALARM_INT_ENABLE 0x40
|
||||
#define DP8570_PWR_FAIL_INT_ENABLE 0x80
|
||||
|
||||
/* miscellaneous */
|
||||
|
||||
#define DP8570_PAGE0_RAM_START 0x13
|
||||
#define DP8570_PAGE1_RAM_START 0x01
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCn8570h */
|
||||
@@ -0,0 +1,79 @@
|
||||
/* rtc64613.h - Seiko-Epson rtc64613 RTC header file */
|
||||
|
||||
/* Copyright 1991-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01d,22sep92,rrr added support for c++
|
||||
01c,26may92,rrr the tree shuffle
|
||||
01b,04oct91,rrr passed through the ansification filter
|
||||
-fixed #else and #endif
|
||||
-changed ASMLANGUAGE to _ASMLANGUAGE
|
||||
-changed copyright notice
|
||||
01a,23may91,hdn written.
|
||||
*/
|
||||
|
||||
#ifndef __INCrtc64613h
|
||||
#define __INCrtc64613h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define RTC64613_REG_OFFSET 3
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
typedef struct
|
||||
{
|
||||
UCHAR pad0[RTC64613_REG_OFFSET];
|
||||
UCHAR hz64;
|
||||
UCHAR pad1[RTC64613_REG_OFFSET];
|
||||
UCHAR second;
|
||||
UCHAR pad2[RTC64613_REG_OFFSET];
|
||||
UCHAR minute;
|
||||
UCHAR pad3[RTC64613_REG_OFFSET];
|
||||
UCHAR hour;
|
||||
UCHAR pad4[RTC64613_REG_OFFSET];
|
||||
UCHAR dayWeek;
|
||||
UCHAR pad5[RTC64613_REG_OFFSET];
|
||||
UCHAR date;
|
||||
UCHAR pad6[RTC64613_REG_OFFSET];
|
||||
UCHAR month;
|
||||
UCHAR pad7[RTC64613_REG_OFFSET];
|
||||
UCHAR year;
|
||||
UCHAR pad8[RTC64613_REG_OFFSET];
|
||||
UCHAR alarmHz64;
|
||||
UCHAR pad9[RTC64613_REG_OFFSET];
|
||||
UCHAR alarmSecond;
|
||||
UCHAR pad10[RTC64613_REG_OFFSET];
|
||||
UCHAR alarmMinute;
|
||||
UCHAR pad11[RTC64613_REG_OFFSET];
|
||||
UCHAR alarmHour;
|
||||
UCHAR pad12[RTC64613_REG_OFFSET];
|
||||
UCHAR alarmDayWeek;
|
||||
UCHAR pad13[RTC64613_REG_OFFSET];
|
||||
UCHAR alarmDate;
|
||||
UCHAR pad14[RTC64613_REG_OFFSET];
|
||||
UCHAR controlA;
|
||||
UCHAR pad15[RTC64613_REG_OFFSET];
|
||||
UCHAR controlB;
|
||||
} RTC;
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
/* bit value for control A register */
|
||||
#define RTC_CARRY_FLAG 0x80
|
||||
#define RTC_CARRY_INT 0x10
|
||||
#define RTC_ALARM_INT 0x08
|
||||
#define RTC_ALARM_FLAG 0x01
|
||||
|
||||
/* bit value for control B register */
|
||||
#define RTC_TEST_MODE 0x08
|
||||
#define RTC_ADJUST 0x04
|
||||
#define RTC_RESET 0x02
|
||||
#define RTC_START_STOP 0x01
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCrtc64613h */
|
||||
@@ -0,0 +1,50 @@
|
||||
/* s62421.h - Seiko 62421 real time clock */
|
||||
|
||||
/* Copyright 1984-1992 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,22sep92,rrr added support for c++
|
||||
01d,26may92,rrr the tree shuffle
|
||||
01c,04oct91,rrr passed through the ansification filter
|
||||
-changed copyright notice
|
||||
01b,05oct90,shl added copyright notice.
|
||||
made #endif ANSI style.
|
||||
01a,28nov88,jcf written.
|
||||
*/
|
||||
|
||||
/*
|
||||
This file contains constants for the Seiko 62421.
|
||||
*/
|
||||
|
||||
#ifndef __INCs62421h
|
||||
#define __INCs62421h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* RTC 62421 register definition */
|
||||
|
||||
#define RTC_1_SEC(base) ((char *) ((base) + 0x0)) /* 1 sec. digit */
|
||||
#define RTC_10_SEC(base) ((char *) ((base) + 0x1)) /* 10 sec. digit */
|
||||
#define RTC_1_MIN(base) ((char *) ((base) + 0x2)) /* 1 min. digit */
|
||||
#define RTC_10_MIN(base) ((char *) ((base) + 0x3)) /* 10 min. digit */
|
||||
#define RTC_1_HR(base) ((char *) ((base) + 0x4)) /* 1 hour digit */
|
||||
#define RTC_10_HR(base) ((char *) ((base) + 0x5)) /* pm/am+10 hr digit */
|
||||
#define RTC_1_DAY(base) ((char *) ((base) + 0x6)) /* 1 day digit */
|
||||
#define RTC_10_DAY(base) ((char *) ((base) + 0x7)) /* 10 day digit */
|
||||
#define RTC_1_MON(base) ((char *) ((base) + 0x8)) /* 1 month digit */
|
||||
#define RTC_10_MON(base) ((char *) ((base) + 0x9)) /* 10 month digit */
|
||||
#define RTC_1_YR(base) ((char *) ((base) + 0xa)) /* 1 year digit */
|
||||
#define RTC_10_YR(base) ((char *) ((base) + 0xb)) /* 10 year digit */
|
||||
#define RTC_WEEK(base) ((char *) ((base) + 0xc)) /* week */
|
||||
#define RTC_CTR_D(base) ((char *) ((base) + 0xd)) /* control d */
|
||||
#define RTC_CTR_E(base) ((char *) ((base) + 0xe)) /* control e */
|
||||
#define RTC_CTR_F(base) ((char *) ((base) + 0xf)) /* control f */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCs62421h */
|
||||
Reference in New Issue
Block a user