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neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
12254 changed files with 7655111 additions and 0 deletions
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vxworks-6.9/target/h/drv/intrCtl/hd644232.h
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/* hd644232.h - Hitachi 644232 IRC Interrupt Request Controller header */
/* Copyright 1991-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01e,22sep92,rrr added support for c++
01d,26may92,rrr the tree shuffle
01c,04oct91,rrr passed through the ansification filter
-fixed #else and #endif
-changed ASMLANGUAGE to _ASMLANGUAGE
-changed copyright notice
01b,07jun91,hdn defined HD644232_REG_OFFSET.
01a,09feb91,hdn written.
*/
#ifndef __INChd644232h
#define __INChd644232h
#ifdef __cplusplus
extern "C" {
#endif
#define HD644232_REG_OFFSET 3
#ifndef _ASMLANGUAGE
typedef struct
{
UCHAR pad0[HD644232_REG_OFFSET];
UCHAR lmr1;
UCHAR pad1[HD644232_REG_OFFSET];
UCHAR lmr2;
UCHAR pad2[HD644232_REG_OFFSET];
UCHAR lmr3;
UCHAR pad3[HD644232_REG_OFFSET];
UCHAR lmr4;
UCHAR pad4[HD644232_REG_OFFSET];
UCHAR lmr5;
UCHAR pad5[HD644232_REG_OFFSET];
UCHAR lmr6;
UCHAR pad6[HD644232_REG_OFFSET];
UCHAR vmr;
UCHAR pad7[HD644232_REG_OFFSET];
UCHAR vsr;
UCHAR pad8[HD644232_REG_OFFSET];
UCHAR vnr;
UCHAR pad9[HD644232_REG_OFFSET];
UCHAR tmr;
UCHAR pad10[HD644232_REG_OFFSET];
UCHAR imr;
UCHAR pad11[HD644232_REG_OFFSET];
UCHAR irr;
UCHAR pad12[HD644232_REG_OFFSET];
UCHAR bmr;
UCHAR pad13[HD644232_REG_OFFSET];
UCHAR brr;
} IRC;
#endif /* _ASMLANGUAGE */
/* Local Interrupt Request */
#define IRC_LIR0 0x01
#define IRC_LIR1 0x02
#define IRC_LIR2 0x04
#define IRC_LIR3 0x08
#define IRC_LIR4 0x10
#define IRC_LIR5 0x20
#define IRC_LIR6 0x40
/* default values */
#define IRC_VMR_AUTOVEC 0xff
#define IRC_TMR_EDGE 0xff
#define IRC_IMR_DISABLE 0x7f
#define IRC_BMR_DISABLE 0xff
#define IRC_BMR_ENABLE 0x00
#ifdef __cplusplus
}
#endif
#endif /* __INChd644232h */
vxworks-6.9/target/h/drv/intrCtl/i82378Ibc.h
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/* i82378.h - i82378 IBC (ISA Bridge Controller) driver */
/* Copyright 1984-1996 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,30oct96,tam added IBC_READ_BYTE and IBC_WRITE_BYTE definitions (spr #7415).
01b,11oct96,tam added _ASMLANGUAGE conditional.
01a,29jan96,tam written.
*/
#ifndef __INCi82378Ibch
#define __INCi82378Ibch
#ifdef __cplusplus
extern "C" {
#endif
/*
* The macro IBC_BASE_ADRS, PIC_REG_ADDR_INTERVAL & PIT_REG_ADDR_INTERVAL
* must be defined when including this header.
*/
/* default definitions */
#define CAST
#define PIC_ADRS(base,reg) (CAST (base+(reg*PIC_REG_ADDR_INTERVAL)))
/* register definitions */
#define PIC_port1(base) PIC_ADRS(base,0x00) /* port 1. */
#define PIC_port2(base) PIC_ADRS(base,0x01) /* port 2. */
/* hardware register access macros */
#ifndef IBC_BYTE_READ /* reads IBC register */
# define IBC_BYTE_READ(addr,pData) (*pData = *(UCHAR *)(addr))
#endif
#ifndef IBC_BYTE_WRITE /* write to IBC register */
# define IBC_BYTE_WRITE(addr,data) *(UCHAR *)(addr) = (data); EIEIO
#endif
/* alias */
#define PIC_IMASK(base) PIC_port2(base) /* Interrupt mask. */
#define PIC_IACK(base) PIC_port1(base) /* Interrupt acknowledge. */
#define PIC_ISR_MASK(base) PIC_port1(base) /* in-service register mask */
#define PIC_IRR_MASK(base) PIC_port1(base) /* interrupt request reg */
#define OCW3_DEF 0x08 /* 3rd default control word */
#define OCW3_PCB 0x04 /* Polling Control Bit */
#define OCW3_ISR 0x03 /* Read in-service reg */
#define OCW3_IRR 0x02 /* Read inter request reg */
#define ISA_INTR_ACK_REG (CPU_PCI_IACK_ADRS + 0x1ff0)
#define i82378_INT1_CTRL (IBC_BASE_ADRS + 0x0020) /* pic1 82378 */
#define i82378_INT1_MASK (IBC_BASE_ADRS + 0x0021)
#define i82378_INT1_ELC (IBC_BASE_ADRS + 0x04d0)
#define i82378_INT2_CTRL (IBC_BASE_ADRS + 0x00a0) /* pic2 82378 */
#define i82378_INT2_MASK (IBC_BASE_ADRS + 0x00a1)
#define i82378_INT2_ELC (IBC_BASE_ADRS + 0x04d1)
#define i82378_TMR1_CNT0 (IBC_BASE_ADRS + 0x0040) /* timer */
#define i82378_TMR1_CNT1 (IBC_BASE_ADRS + 0x0041)
#define i82378_TMR1_CNT2 (IBC_BASE_ADRS + 0x0042)
#define i82378_TMR1_CMOD (IBC_BASE_ADRS + 0x0043)
#define i82378_RST_IRQ12 (IBC_BASE_ADRS + 0x0060)
#define i82378_NMI_SCTRL (IBC_BASE_ADRS + 0x0061)
#define i82378_PCOP (IBC_BASE_ADRS + 0x0c04)
#define i82378_TMCP (IBC_BASE_ADRS + 0x0c01)
/* programmable interrupt controller (PIC) */
#define PIC1_BASE_ADR i82378_INT1_CTRL
#define PIC2_BASE_ADR i82378_INT2_CTRL
/* programmable interrupt timers */
#define PIT_BASE_ADR i82378_TMR1_CNT0 /* timeraddrs */
#define PIT_CLOCK 1193180
/* typedefs */
#ifndef _ASMLANGUAGE
typedef struct intHandlerDesc /* interrupt handler desciption */
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
struct intHandlerDesc * next; /* next interrupt handler & argument */
} INT_HANDLER_DESC;
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCi82378Ibch */
vxworks-6.9/target/h/drv/intrCtl/i8259.h
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/* i8259.h - Intel 8259a PIC (Programmable Interrupt Controller) */
/* Copyright 1984-2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,23apr02,hdn added prototypes for new BOI/EOI rtn (spr 76411)
01g,08mar02,hdn added prototype i8259Init() for HTT (spr 73738)
01f,28may97,hdn copied i8259a.h to i8259.h for APIC support.
01e,17mar97,hdn added function declarations.
01d,03jan95,vin added PIC_ISR_MASK, PIC_IRR_MASK, OCW3
01c,16aug93,hdn deleted PIC_BASE_ADRS macros.
01b,16jun93,hdn updated to 5.1.
01a,15may92,hdn written.
*/
#ifndef __INCi8259h
#define __INCi8259h
#ifdef __cplusplus
extern "C" {
#endif
/*
* The macro PIC_REG_ADDR_INTERVAL must be defined
* when including this header.
*/
/* default definitions */
#define CAST
#define PIC_ADRS(base,reg) (CAST (base+(reg*PIC_REG_ADDR_INTERVAL)))
/* register definitions */
#define PIC_port1(base) PIC_ADRS(base,0x00) /* port 1. */
#define PIC_port2(base) PIC_ADRS(base,0x01) /* port 2. */
/* alias */
#define PIC_IMASK(base) PIC_port2(base) /* Interrupt mask. */
#define PIC_IACK(base) PIC_port1(base) /* Interrupt acknowledge. */
#define PIC_ISR_MASK(base) PIC_port1(base) /* in-service register mask */
#define PIC_IRR_MASK(base) PIC_port1(base) /* interrupt request reg */
#define OCW3_DEF 0x08 /* 3rd default control word */
#define OCW3_PCB 0x04 /* Polling Control Bit */
#define OCW3_ISR 0x03 /* Read in-service reg */
#define OCW3_IRR 0x02 /* Read inter request reg */
#define I8259_EOI 0x20 /* EOI bit in OCW2 */
#ifndef _ASMLANGUAGE
#if defined(__STDC__) || defined(__cplusplus)
IMPORT VOID i8259Init (void);
IMPORT int sysIntLevel (int arg);
IMPORT VOID sysIntLock (void);
IMPORT VOID sysIntUnlock (void);
IMPORT VOID i8259IntBoi (int irqNo);
IMPORT VOID i8259IntBoiEem (int irqNo);
IMPORT VOID i8259IntBoiSmm (int irqNo);
IMPORT VOID i8259IntEoiSmm (int irqNo);
IMPORT VOID i8259IntEoiMaster (int irqNo);
IMPORT VOID i8259IntEoiSlave (int irqNo);
IMPORT VOID i8259IntEoiSlaveNfnm (int irqNo);
IMPORT VOID i8259IntEoiSlaveSfnm (int irqNo);
#else
IMPORT VOID i8259Init ();
IMPORT int sysIntLevel ();
IMPORT VOID sysIntLock ();
IMPORT VOID sysIntUnlock ();
IMPORT VOID i8259IntBoi ();
IMPORT VOID i8259IntBoiEem ();
IMPORT VOID i8259IntBoiSmm ();
IMPORT VOID i8259IntEoiSmm ();
IMPORT VOID i8259IntEoiMaster ();
IMPORT VOID i8259IntEoiSlave ();
IMPORT VOID i8259IntEoiSlaveNfnm ();
IMPORT VOID i8259IntEoiSlaveSfnm ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCi8259h */
vxworks-6.9/target/h/drv/intrCtl/i8259a.h
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/* i8259a.h - Intel 8259a PIC (Programmable Interrupt Controller) */
/* Copyright 1984-1996 Wind River Systems, Inc. */
/*
modification history
--------------------
01e,17mar97,hdn added function declarations.
01d,03jan95,vin added PIC_ISR_MASK, PIC_IRR_MASK, OCW3
01c,16aug93,hdn deleted PIC_BASE_ADRS macros.
01b,16jun93,hdn updated to 5.1.
01a,15may92,hdn written.
*/
#ifndef __INCi8259ah
#define __INCi8259ah
#ifdef __cplusplus
extern "C" {
#endif
/*
* The macro PIC_REG_ADDR_INTERVAL must be defined
* when including this header.
*/
/* default definitions */
#define CAST
#define PIC_ADRS(base,reg) (CAST (base+(reg*PIC_REG_ADDR_INTERVAL)))
/* register definitions */
#define PIC_port1(base) PIC_ADRS(base,0x00) /* port 1. */
#define PIC_port2(base) PIC_ADRS(base,0x01) /* port 2. */
/* alias */
#define PIC_IMASK(base) PIC_port2(base) /* Interrupt mask. */
#define PIC_IACK(base) PIC_port1(base) /* Interrupt acknowledge. */
#define PIC_ISR_MASK(base) PIC_port1(base) /* in-service register mask */
#define PIC_IRR_MASK(base) PIC_port1(base) /* interrupt request reg */
#define OCW3_DEF 0x08 /* 3rd default control word */
#define OCW3_PCB 0x04 /* Polling Control Bit */
#define OCW3_ISR 0x03 /* Read in-service reg */
#define OCW3_IRR 0x02 /* Read inter request reg */
#ifndef _ASMLANGUAGE
#if defined(__STDC__) || defined(__cplusplus)
IMPORT int sysIntLevel (void);
IMPORT VOID sysIntLock (void);
IMPORT VOID sysIntUnlock (void);
#else
IMPORT int sysIntLevel ();
IMPORT VOID sysIntLock ();
IMPORT VOID sysIntUnlock ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCi8259ah */
vxworks-6.9/target/h/drv/intrCtl/ioApic.h
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/* ioApic.h - Intel IO APIC/xAPIC (Advanced PIC) */
/* Copyright 1984-2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01f,26jul06,scm update for pentium/xeon support...
01e,15may02,hdn removed ifdef for IOAPIC_DATA
01d,08mar02,hdn added prototypes for HTT (spr 73738)
01c,26jun01,hdn added support for Pentium4 IO xAPIC
01b,25may98,hdn re-written
01a,30jun97,sub written
*/
#ifndef __INCioApich
#define __INCioApich
#ifdef __cplusplus
extern "C" {
#endif
/* IO APIC direct register offset */
#define IOAPIC_IND 0x00 /* Index Register */
#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
#define IOAPIC_IRQPA 0x20 /* IRQ Pin Assertion Register */
#define IOAPIC_EOI 0x40 /* EOI Register */
/* IO APIC indirect register offset */
#define IOAPIC_ID 0x00 /* IOAPIC ID */
#define IOAPIC_VERS 0x01 /* IOAPIC Version */
#define IOAPIC_ARB 0x02 /* IOAPIC Arbitration ID */
#define IOAPIC_BOOT 0x03 /* IOAPIC Boot Configuration */
#define IOAPIC_REDTBL 0x10 /* Redirection Table (24 * 64bit) */
/* Interrupt delivery type */
#define IOAPIC_DT_APIC 0x0 /* APIC serial bus */
#define IOAPIC_DT_FS 0x1 /* Front side bus message*/
/* Version register bits */
#define IOAPIC_MRE_MASK 0x00ff0000 /* Max Red. entry mask */
#define IOAPIC_PRQ 0x00008000 /* this has IRQ reg */
#define IOAPIC_VERSION 0x000000ff /* version number */
/* Redirection table entry number */
#define MAX_REDTABLE_ENTRIES 32
/* Redirection table entry bits: upper 32 bit */
#define IOAPIC_DESTINATION 0xff000000
/* Redirection table entry bits: lower 32 bit */
#define IOAPIC_INT_MASK 0x00010000
#define IOAPIC_LEVEL 0x00008000
#define IOAPIC_EDGE 0x00000000
#define IOAPIC_REMOTE 0x00004000
#define IOAPIC_LOW 0x00002000
#define IOAPIC_HIGH 0x00000000
#define IOAPIC_LOGICAL 0x00000800
#define IOAPIC_PHYSICAL 0x00000000
#define IOAPIC_FIXED 0x00000000
#define IOAPIC_LOWEST 0x00000100
#define IOAPIC_SMI 0x00000200
#define IOAPIC_NMI 0x00000400
#define IOAPIC_INIT 0x00000500
#define IOAPIC_EXTINT 0x00000700
#define IOAPIC_VEC_MASK 0x000000ff
#ifndef _ASMLANGUAGE
/* variable declarations */
IMPORT UINT32 ioApicVersion[MAX_IOAPICS]; /* IO APIC version register per APIC */
IMPORT UINT8 ioApicRedNum[MAX_IOAPICS]; /* IO APIC redirection table number per APIC */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS ioApicInit (void);
IMPORT VOID ioApicEnable (BOOL enable);
IMPORT STATUS ioApicIrqSet (INT32 irq, INT32 destApicId, INT32 sourceApicId);
IMPORT STATUS ioApicRedGet (INT32 irq, INT32 * pUpper32, INT32 * pLower32, INT32 ioApicId);
IMPORT STATUS ioApicRedSet (INT32 irq, INT32 upper32, INT32 lower32, INT32 ioApicId);
IMPORT INT32 ioApicGet (UINT32 index, UINT32 data, INT32 offset);
IMPORT void ioApicSet (UINT32 index, UINT32 data, INT32 offset, INT32 value);
#else
IMPORT STATUS ioApicInit ();
IMPORT VOID ioApicEnable ();
IMPORT STATUS ioApicIrqSet ();
IMPORT STATUS ioApicRedGet ();
IMPORT STATUS ioApicRedSet ();
IMPORT INT32 ioApicGet ();
IMPORT void ioApicSet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCioApich */
vxworks-6.9/target/h/drv/intrCtl/ixp400IntrCtl.h
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/* ixp400IntrCtl.h - interrupt controller driver Ixp400 */
/*
Copyright (c) 2002-2004 Wind River Systems, Inc. All rights reserved.
Certain portions of these files may be copyright (c) 2002-2004 Intel
Corporation.
*/
/*
modification history
--------------------
01e,26sep07,jrp APIGEN Cleanup
01d,24aug05,m_h interrupt controller for ixdp465 and related XSCALE BSPs
01c,20dec04,pai Updated copyright notice.
01b,24jul03,m_h PSM now named NPE
01a,05jun02,jb initial version...
*/
#ifndef __INCixp400IntrCtlh
#define __INCixp400IntrCtlh
#include "ixp400.h"
#ifdef __cplusplus
extern "C" {
#endif
/* typedefs */
#ifndef _ASMLANGUAGE
#endif /* _ASMLANGUAGE */
/* macros to convert interrupt vectors <-> interrupt numbers */
#ifdef IVEC_TO_INUM
#undef IVEC_TO_INUM
#endif
#define IVEC_TO_INUM(intVec) ((int) (intVec))
#ifdef INUM_TO_IVEC
#undef INUM_TO_IVEC
#endif
#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *) (intNum))
/*
* Define Ixp400 Interrupt registers
*/
/*
Interrupt Controller Register Definitions.
*/
#define IXP400_ICPR ( IXP400_INTC_BASE + 0x0 ) /* Interrupt Status Reg. */
#define IXP400_ICMR ( IXP400_INTC_BASE + 0x4 ) /* Interrupt Enable Reg. */
#define IXP400_ICLR ( IXP400_INTC_BASE + 0x8 ) /* Interrupt Select Reg IRQ/FIQ */
#define IXP400_ICIP ( IXP400_INTC_BASE + 0xC ) /* IRQ Status Reg. */
#define IXP400_ICFP ( IXP400_INTC_BASE + 0x10 ) /* FIQ Status Reg. */
#define IXP400_ICHR ( IXP400_INTC_BASE + 0x14 ) /* Interrupt Priority Reg. */
#define IXP400_ICIH ( IXP400_INTC_BASE + 0x18 ) /* IRQ Highest Pri Int Reg. */
#define IXP400_ICFH ( IXP400_INTC_BASE + 0x1C ) /* FIQ Highest Pri Int Reg. */
/* the following register are for handling INTR 31-63 */
#ifdef IX_DEVICE_IXP465
#define IXP400_ICPR_UPPER ( IXP400_INTC_BASE + 0x20 ) /* Interrupt Status Reg. #2 */
#define IXP400_ICMR_UPPER ( IXP400_INTC_BASE + 0x24 ) /* Interrupt Enable Reg. #2 */
#define IXP400_ICLR_UPPER ( IXP400_INTC_BASE + 0x28 ) /* Interrupt Select Reg IRQ/FIQ #2 */
#define IXP400_ICIP_UPPER ( IXP400_INTC_BASE + 0x2C ) /* IRQ Status Reg. #2 */
#define IXP400_ICFP_UPPER ( IXP400_INTC_BASE + 0x30 ) /* FIQ Status Reg. #2 */
#define IXP400_ERROR_EN2 ( IXP400_INTC_BASE + 0x34 ) /* for interrupts 31-63, error priority enable */
/* used to raise priority above all others */
#endif
#define IXP400_INT_LVL_NPEA (0)
#define IXP400_INT_LVL_NPEB (1)
#define IXP400_INT_LVL_NPEC (2)
#define IXP400_INT_LVL_QM1 (3)
#define IXP400_INT_LVL_QM2 (4)
#define IXP400_INT_LVL_TIMER1 (5)
#define IXP400_INT_LVL_GPIO0 (6)
#define IXP400_INT_LVL_GPIO1 (7)
#define IXP400_INT_LVL_PCI_INT (8)
#define IXP400_INT_LVL_PCI_DMA1 (9)
#define IXP400_INT_LVL_PCI_DMA2 (10)
#define IXP400_INT_LVL_TIMER2 (11)
#define IXP400_INT_LVL_USB (12)
#define IXP400_INT_LVL_UART2 (13)
#define IXP400_INT_LVL_TIMESTAMP (14)
#define IXP400_INT_LVL_UART1 (15)
#define IXP400_INT_LVL_WDOG (16)
#define IXP400_INT_LVL_AHB_PMU (17)
#define IXP400_INT_LVL_XSCALE_PMU (18)
#define IXP400_INT_LVL_GPIO2 (19)
#define IXP400_INT_LVL_GPIO3 (20)
#define IXP400_INT_LVL_GPIO4 (21)
#define IXP400_INT_LVL_GPIO5 (22)
#define IXP400_INT_LVL_GPIO6 (23)
#define IXP400_INT_LVL_GPIO7 (24)
#define IXP400_INT_LVL_GPIO8 (25)
#define IXP400_INT_LVL_GPIO9 (26)
#define IXP400_INT_LVL_GPIO10 (27)
#define IXP400_INT_LVL_GPIO11 (28)
#define IXP400_INT_LVL_GPIO12 (29)
#define IXP400_INT_LVL_INT1 (30)
#define IXP400_INT_LVL_INT2 (31)
#ifdef IX_DEVICE_IXP465
#define IXP400_INT_LVL_USB_HOST (32)
#define IXP400_INT_LVL_I2C (33)
#define IXP400_INT_LVL_SSP (34)
#define IXP400_INT_LVL_TSYNC (35)
#define IXP400_INT_LVL_EAU_DONE (36)
#define IXP400_INT_LVL_SHA_HASHING_DONE (37)
#define IXP400_INT_LVL_RSVD_38 (38)
#define IXP400_INT_LVL_RSVD_39 (39)
#define IXP400_INT_LVL_RSVD_40 (40)
#define IXP400_INT_LVL_RSVD_41 (41)
#define IXP400_INT_LVL_RSVD_42 (42)
#define IXP400_INT_LVL_RSVD_43 (43)
#define IXP400_INT_LVL_RSVD_44 (44)
#define IXP400_INT_LVL_RSVD_45 (45)
#define IXP400_INT_LVL_RSVD_46 (46)
#define IXP400_INT_LVL_RSVD_47 (47)
#define IXP400_INT_LVL_RSVD_48 (48)
#define IXP400_INT_LVL_RSVD_49 (49)
#define IXP400_INT_LVL_RSVD_50 (50)
#define IXP400_INT_LVL_RSVD_51 (51)
#define IXP400_INT_LVL_RSVD_52 (52)
#define IXP400_INT_LVL_RSVD_53 (53)
#define IXP400_INT_LVL_RSVD_54 (54)
#define IXP400_INT_LVL_RSVD_55 (55)
#define IXP400_INT_LVL_RSVD_56 (56)
#define IXP400_INT_LVL_RSVD_57 (57)
#define IXP400_INT_LVL_SWCP (58)
#define IXP400_INT_LVL_RSVD_59 (59)
#define IXP400_INT_LVL_AQM (60)
#define IXP400_INT_LVL_MCU (61)
#define IXP400_INT_LVL_EBC (62)
#define IXP400_INT_LVL_RSVD_63 (63)
#endif
/* Bit definitions for Interrupt Pending/Mask/Status registers */
#define IXP400_INTC_NPEA (1 << IXP400_INT_LVL_NPEA)
#define IXP400_INTC_NPEB (1 << IXP400_INT_LVL_NPEB)
#define IXP400_INTC_NPEC (1 << IXP400_INT_LVL_NPEC)
#define IXP400_INTC_QM1 (1 << IXP400_INT_LVL_QM1)
#define IXP400_INTC_QM2 (1 << IXP400_INT_LVL_QM2)
#define IXP400_INTC_TIMER1 (1 << IXP400_INT_LVL_TIMER1)
#define IXP400_INTC_GPIO0 (1 << IXP400_INT_LVL_GPIO0)
#define IXP400_INTC_GPIO1 (1 << IXP400_INT_LVL_GPIO1)
#define IXP400_INTC_PCI_INT (1 << IXP400_INT_LVL_PCI_INT)
#define IXP400_INTC_PCI_DMA1 (1 << IXP400_INT_LVL_PCI_DMA1)
#define IXP400_INTC_PCI_DMA2 (1 << IXP400_INT_LVL_PCI_DMA2)
#define IXP400_INTC_TIMER2 (1 << IXP400_INT_LVL_TIMER2)
#define IXP400_INTC_USB (1 << IXP400_INT_LVL_USB)
#define IXP400_INTC_UART2 (1 << IXP400_INT_LVL_UART2)
#define IXP400_INTC_TIMESTAMP (1 << IXP400_INT_LVL_TIMESTAMP)
#define IXP400_INTC_UART1 (1 << IXP400_INT_LVL_UART1)
#define IXP400_INTC_WDOG (1 << IXP400_INT_LVL_WDOG)
#define IXP400_INTC_AHB_PMU (1 << IXP400_INT_LVL_AHB_PMU)
#define IXP400_INTC_XSCALE_PMU (1 << IXP400_INT_LVL_XSCALE_PMU)
#define IXP400_INTC_GPIO2 (1 << IXP400_INT_LVL_GPIO2)
#define IXP400_INTC_GPIO3 (1 << IXP400_INT_LVL_GPIO3)
#define IXP400_INTC_GPIO4 (1 << IXP400_INT_LVL_GPIO4)
#define IXP400_INTC_GPIO5 (1 << IXP400_INT_LVL_GPIO5)
#define IXP400_INTC_GPIO6 (1 << IXP400_INT_LVL_GPIO6)
#define IXP400_INTC_GPIO7 (1 << IXP400_INT_LVL_GPIO7)
#define IXP400_INTC_GPIO8 (1 << IXP400_INT_LVL_GPIO8)
#define IXP400_INTC_GPIO9 (1 << IXP400_INT_LVL_GPIO9)
#define IXP400_INTC_GPIO10 (1 << IXP400_INT_LVL_GPIO10)
#define IXP400_INTC_GPIO11 (1 << IXP400_INT_LVL_GPIO11)
#define IXP400_INTC_GPIO12 (1 << IXP400_INT_LVL_GPIO12)
#define IXP400_INTC_SW_INT1 (1 << IXP400_INT_LVL_INT1)
#define IXP400_INTC_SW_INT2 (1 << IXP400_INT_LVL_INT2)
#ifdef IX_DEVICE_IXP465
#define IXP400_INTC_USB_HOST (1 << (IXP400_INT_LVL_USB_HOST - 32))
#define IXP400_INTC_I2C (1 << (IXP400_INT_LVL_I2C - 32))
#define IXP400_INTC_SSP (1 << (IXP400_INT_LVL_SSP - 32))
#define IXP400_INTC_TSYNC (1 << (IXP400_INT_LVL_RSVD_TSYNC - 32))
#define IXP400_INTC_EAU_DONE (1 << (IXP400_INT_LVL_RSVD_EAU_DONE - 32))
#define IXP400_INTC_SHA_HASHING_DONE (1 << (IXP400_INT_LVL_RSVD_SHA_HASHING_DONE - 32))
#define IXP400_INTC_RSVD_38 (1 << (IXP400_INT_LVL_RSVD_38 - 32))
#define IXP400_INTC_RSVD_39 (1 << (IXP400_INT_LVL_RSVD_39 - 32))
#define IXP400_INTC_RSVD_40 (1 << (IXP400_INT_LVL_RSVD_40 - 32))
#define IXP400_INTC_RSVD_41 (1 << (IXP400_INT_LVL_RSVD_41 - 32))
#define IXP400_INTC_RSVD_42 (1 << (IXP400_INT_LVL_RSVD_42 - 32))
#define IXP400_INTC_RSVD_43 (1 << (IXP400_INT_LVL_RSVD_43 - 32))
#define IXP400_INTC_RSVD_44 (1 << (IXP400_INT_LVL_RSVD_44 - 32))
#define IXP400_INTC_RSVD_45 (1 << (IXP400_INT_LVL_RSVD_45 - 32))
#define IXP400_INTC_RSVD_46 (1 << (IXP400_INT_LVL_RSVD_46 - 32))
#define IXP400_INTC_RSVD_47 (1 << (IXP400_INT_LVL_RSVD_47 - 32))
#define IXP400_INTC_RSVD_48 (1 << (IXP400_INT_LVL_RSVD_48 - 32))
#define IXP400_INTC_RSVD_49 (1 << (IXP400_INT_LVL_RSVD_49 - 32))
#define IXP400_INTC_RSVD_50 (1 << (IXP400_INT_LVL_RSVD_50 - 32))
#define IXP400_INTC_RSVD_51 (1 << (IXP400_INT_LVL_RSVD_51 - 32))
#define IXP400_INTC_RSVD_52 (1 << (IXP400_INT_LVL_RSVD_52 - 32))
#define IXP400_INTC_RSVD_53 (1 << (IXP400_INT_LVL_RSVD_53 - 32))
#define IXP400_INTC_RSVD_54 (1 << (IXP400_INT_LVL_RSVD_54 - 32))
#define IXP400_INTC_RSVD_55 (1 << (IXP400_INT_LVL_RSVD_55 - 32))
#define IXP400_INTC_RSVD_56 (1 << (IXP400_INT_LVL_RSVD_56 - 32))
#define IXP400_INTC_RSVD_57 (1 << (IXP400_INT_LVL_RSVD_57 - 32))
#define IXP400_INTC_SWCP (1 << (IXP400_INT_LVL_SWCP - 32))
#define IXP400_INTC_RSVD_59 (1 << (IXP400_INT_LVL_RSVD_59 - 32))
#define IXP400_INTC_AQM (1 << (IXP400_INT_LVL_AQM - 32))
#define IXP400_INTC_MCU (1 << (IXP400_INT_LVL_MCU - 32))
#define IXP400_INTC_EBC (1 << (IXP400_INT_LVL_EBC - 32))
#define IXP400_INTC_RSVD_63 (1 << (IXP400_INT_LVL_RSVD_63 - 32))
#endif
/* Vector definitions */
#define IXP400_INT_NUM_LEVELS_LOWER (32)
#if IX_DEVICE_IXP465
#define IXP400_INT_NUM_LEVELS (64)
#else
#define IXP400_INT_NUM_LEVELS (IXP400_INT_NUM_LEVELS_LOWER)
#endif
#define IXP400_INT_MODE INT_NON_PREEMPT_MODEL
#define INT_VEC_NPEA IVEC_TO_INUM(IXP400_INT_LVL_NPEA)
#define INT_VEC_NPEB IVEC_TO_INUM(IXP400_INT_LVL_NPEB)
#define INT_VEC_NPEC IVEC_TO_INUM(IXP400_INT_LVL_NPEC)
#define INT_VEC_QM1 IVEC_TO_INUM(IXP400_INT_LVL_QM1 )
#define INT_VEC_QM2 IVEC_TO_INUM(IXP400_INT_LVL_QM2 )
#define INT_VEC_TIMER1 IVEC_TO_INUM(IXP400_INT_LVL_TIMER1)
#define INT_VEC_GPIO0 IVEC_TO_INUM(IXP400_INT_LVL_GPIO0)
#define INT_VEC_GPIO1 IVEC_TO_INUM(IXP400_INT_LVL_GPIO1)
#define INT_VEC_PCI IVEC_TO_INUM(IXP400_INT_LVL_PCI)
#define INT_VEC_PCI_DMA1 IVEC_TO_INUM(IXP400_INT_LVL_PCI_DMA1)
#define INT_VEC_PCI_DMA2 IVEC_TO_INUM(IXP400_INT_LVL_PCI_DMA2)
#define INT_VEC_TIMER2 IVEC_TO_INUM(IXP400_INT_LVL_TIMER2)
#define INT_VEC_APB_DMA IVEC_TO_INUM(IXP400_INT_LVL_APB_DMA)
#define INT_VEC_USB IVEC_TO_INUM(IXP400_INT_LVL_USB)
#define INT_VEC_UART1 IVEC_TO_INUM(IXP400_INT_LVL_UART1)
#define INT_VEC_TIMESTAMP IVEC_TO_INUM(IXP400_INT_LVL_TIMESTAMP)
#define INT_VEC_UART2 IVEC_TO_INUM(IXP400_INT_LVL_UART2)
#define INT_VEC_WDOG IVEC_TO_INUM(IXP400_INT_LVL_WDOG)
#define INT_VEC_AHB_PMU IVEC_TO_INUM(IXP400_INT_LVL_AHB_PMU)
#define INT_VEC_XSCALE_PMU IVEC_TO_INUM(IXP400_INT_LVL_XSCALE_PMU)
#define INT_VEC_GPIO2 IVEC_TO_INUM(IXP400_INT_LVL_GPIO2)
#define INT_VEC_GPIO3 IVEC_TO_INUM(IXP400_INT_LVL_GPIO3)
#define INT_VEC_GPIO4 IVEC_TO_INUM(IXP400_INT_LVL_GPIO4)
#define INT_VEC_GPIO5 IVEC_TO_INUM(IXP400_INT_LVL_GPIO5)
#define INT_VEC_GPIO6 IVEC_TO_INUM(IXP400_INT_LVL_GPIO6)
#define INT_VEC_GPIO7 IVEC_TO_INUM(IXP400_INT_LVL_GPIO7)
#define INT_VEC_GPIO8 IVEC_TO_INUM(IXP400_INT_LVL_GPIO8)
#define INT_VEC_GPIO9 IVEC_TO_INUM(IXP400_INT_LVL_GPIO9)
#define INT_VEC_GPIO10 IVEC_TO_INUM(IXP400_INT_LVL_GPIO10)
#define INT_VEC_GPIO11 IVEC_TO_INUM(IXP400_INT_LVL_GPIO11)
#define INT_VEC_GPIO12 IVEC_TO_INUM(IXP400_INT_LVL_GPIO12)
#define INT_VEC_INT1 IVEC_TO_INUM(IXP400_INT_LVL_INT1)
#define INT_VEC_INT2 IVEC_TO_INUM(IXP400_INT_LVL_INT2)
#if IX_DEVICE_IXP465
#define INT_VEC_USB_HOST IVEC_TO_INUM(IXP400_INT_LVL_USB_HOST)
#define INT_VEC_I2C IVEC_TO_INUM(IXP400_INT_LVL_I2C)
#define INT_VEC_SSP IVEC_TO_INUM(IXP400_INT_LVL_SSP)
#define INT_VEC_TSYNC IVEC_TO_INUM(IXP400_INT_LVL_TSYNC)
#define INT_VEC_EAU_DONE IVEC_TO_INUM(IXP400_INT_LVL_EAU_DONE)
#define INT_VEC_SHA_HASHING_DONE IVEC_TO_INUM(IXP400_INT_LVL_SHA_HASHING_DONE)
#define INT_VEC_RSVD_38 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_38)
#define INT_VEC_RSVD_39 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_39)
#define INT_VEC_RSVD_40 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_40)
#define INT_VEC_RSVD_41 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_41)
#define INT_VEC_RSVD_42 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_42)
#define INT_VEC_RSVD_43 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_43)
#define INT_VEC_RSVD_44 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_44)
#define INT_VEC_RSVD_45 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_45)
#define INT_VEC_RSVD_46 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_46)
#define INT_VEC_RSVD_47 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_47)
#define INT_VEC_RSVD_48 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_48)
#define INT_VEC_RSVD_49 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_49)
#define INT_VEC_RSVD_50 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_50)
#define INT_VEC_RSVD_51 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_51)
#define INT_VEC_RSVD_52 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_52)
#define INT_VEC_RSVD_53 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_53)
#define INT_VEC_RSVD_54 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_54)
#define INT_VEC_RSVD_55 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_55)
#define INT_VEC_RSVD_56 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_56)
#define INT_VEC_RSVD_57 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_57)
#define INT_VEC_SWCP IVEC_TO_INUM(IXP400_INT_LVL_SWCP)
#define INT_VEC_RSVD_59 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_59)
#define INT_VEC_AQM IVEC_TO_INUM(IXP400_INT_LVL_AQM)
#define INT_VEC_MCU IVEC_TO_INUM(IXP400_INT_LVL_MCU)
#define INT_VEC_EBC IVEC_TO_INUM(IXP400_INT_LVL_EBC)
#define INT_VEC_RSVD_63 IVEC_TO_INUM(IXP400_INT_LVL_RSVD_63)
#endif
/*
* Set the default value of ICHP - Interrupt highest priorty encoding register.
*/
#ifndef IXP400_ICHR_INIT_VALUE
#define IXP400_ICHR_INIT_VALUE (0x00fac688)
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCIxp400IntrCtrl */
vxworks-6.9/target/h/drv/intrCtl/loApic.h
+289
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@@ -0,0 +1,289 @@
/* loApic.h - Intel Pentium[234] Local APIC/xAPIC (Advanced PIC) */
/* Copyright 1997-1998, 2001-2002, 2006, 2008, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01i,29jul10,pad Moved extern C statement after include statements.
01h,27aug08,jpb Renamed VSB header file
01g,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01f,08sep06,scm update local apic id for cluster & cpu id...
01e,26jul06,scm update for pentium/xeon support...
01d,08mar02,hdn added prototypes for HTT (spr 73738)
01c,21jun01,hdn added support for Pentium4 Local xAPIC
01b,25may98,hdn re-written
01a,26jun97,sub written
*/
#ifndef __INCloApich
#define __INCloApich
#include <vsbConfig.h>
/* Local APIC Register Offset */
#define LOAPIC_ID 0x020 /* Local APIC ID Reg */
#define LOAPIC_VER 0x030 /* Local APIC Version Reg */
#define LOAPIC_TPR 0x080 /* Task Priority Reg */
#define LOAPIC_APR 0x090 /* Arbitration Priority Reg */
#define LOAPIC_PPR 0x0a0 /* Processor Priority Reg */
#define LOAPIC_EOI 0x0b0 /* EOI Reg */
#define LOAPIC_LDR 0x0d0 /* Logical Destination Reg */
#define LOAPIC_DFR 0x0e0 /* Destination Format Reg */
#define LOAPIC_SVR 0x0f0 /* Spurious Interrupt Reg */
#define LOAPIC_ISR 0x100 /* In-service Reg */
#define LOAPIC_TMR 0x180 /* Trigger Mode Reg */
#define LOAPIC_IRR 0x200 /* Interrupt Request Reg */
#define LOAPIC_ESR 0x280 /* Error Status Reg */
#define LOAPIC_ICRLO 0x300 /* Interrupt Command Reg */
#define LOAPIC_ICRHI 0x310 /* Interrupt Command Reg */
#define LOAPIC_TIMER 0x320 /* LVT (Timer) */
#define LOAPIC_THERMAL 0x330 /* LVT (Thermal) */
#define LOAPIC_PMC 0x340 /* LVT (PMC) */
#define LOAPIC_LINT0 0x350 /* LVT (LINT0) */
#define LOAPIC_LINT1 0x360 /* LVT (LINT1) */
#define LOAPIC_ERROR 0x370 /* LVT (ERROR) */
#define LOAPIC_TIMER_ICR 0x380 /* Timer Initial Count Reg */
#define LOAPIC_TIMER_CCR 0x390 /* Timer Current Count Reg */
#define LOAPIC_TIMER_CONFIG 0x3e0 /* Timer Divide Config Reg */
/* IA32_APIC_BASE MSR Bits */
#define LOAPIC_BASE_MASK 0xfffff000 /* LO APIC Base Addr mask */
#define LOAPIC_GLOBAL_ENABLE 0x00000800 /* LO APIC Global Enable */
#define LOAPIC_BSP 0x00000100 /* LO APIC BSP */
/* Local APIC ID Register Bits */
#ifdef _WRS_CONFIG_SMP
#define LOAPIC_ID_MASK 0x1f000000 /* ID [28-24] mask */
#define LOAPIC_CLUSTER_ID_MASK 0x18000000 /* CLUSTER ID [28-27] mask */
#define LOAPIC_PHY_PRC_ID_MASK 0x06000000 /* PHYSICAL PROCESSOR ID [26-25] mask */
#define LOAPIC_LOG_PRC_ID_MASK 0x01000000 /* LOGICAL PROCESSOR ID [24] mask */
#else
#define LOAPIC_ID_MASK 0x0f000000 /* LO APIC ID mask */
#endif /* _WRS_CONFIG_SMP */
/* Local APIC Version Register Bits */
#define LOAPIC_VERSION_MASK 0x000000ff /* LO APIC Version mask */
#define LOAPIC_MAXLVT_MASK 0x00ff0000 /* LO APIC Max LVT mask */
#define LOAPIC_PENTIUM4 0x00000014 /* LO APIC in Pentium4 */
#define LOAPIC_LVT_PENTIUM4 5 /* LO APIC LVT - Pentium4 */
#define LOAPIC_LVT_P6 4 /* LO APIC LVT - P6 */
#define LOAPIC_LVT_P5 3 /* LO APIC LVT - P5 */
/* Local APIC Vector Table Bits */
#define LOAPIC_VECTOR 0x000000ff /* vectorNo */
#define LOAPIC_MODE 0x00000700 /* delivery mode */
#define LOAPIC_FIXED 0x00000000 /* delivery mode: FIXED */
#define LOAPIC_SMI 0x00000200 /* delivery mode: SMI */
#define LOAPIC_NMI 0x00000400 /* delivery mode: NMI */
#define LOAPIC_EXT 0x00000700 /* delivery mode: ExtINT */
#define LOAPIC_IDLE 0x00000000 /* delivery status: Idle */
#define LOAPIC_PEND 0x00001000 /* delivery status: Pend */
#define LOAPIC_HIGH 0x00000000 /* polarity: High */
#define LOAPIC_LOW 0x00002000 /* polarity: Low */
#define LOAPIC_REMOTE 0x00004000 /* remote IRR */
#define LOAPIC_EDGE 0x00000000 /* trigger mode: Edge */
#define LOAPIC_LEVEL 0x00008000 /* trigger mode: Level */
#define LOAPIC_MASK 0x00010000 /* mask */
/* Local APIC Spurious-Interrupt Register Bits */
#define LOAPIC_ENABLE 0x100 /* APIC Enabled */
#define LOAPIC_FOCUS_DISABLE 0x200 /* Focus Processor Checking */
/* Local APIC Timer Bits */
#define LOAPIC_TIMER_DIVBY_2 0x0 /* Divide by 2 */
#define LOAPIC_TIMER_DIVBY_4 0x1 /* Divide by 4 */
#define LOAPIC_TIMER_DIVBY_8 0x2 /* Divide by 8 */
#define LOAPIC_TIMER_DIVBY_16 0x3 /* Divide by 16 */
#define LOAPIC_TIMER_DIVBY_32 0x8 /* Divide by 32 */
#define LOAPIC_TIMER_DIVBY_64 0x9 /* Divide by 64 */
#define LOAPIC_TIMER_DIVBY_128 0xa /* Divide by 128 */
#define LOAPIC_TIMER_DIVBY_1 0xb /* Divide by 1 */
#define LOAPIC_TIMER_DIVBY_MASK 0xf /* mask bits */
#define LOAPIC_TIMER_PERIODIC 0x00020000 /* Timer Mode: Periodic */
/* Local Vector's lock-unlock macro used in loApicIntLock/Unlock */
#define LOCKED_TIMER 0x01
#define LOCKED_PMC 0x02
#define LOCKED_LINT0 0x04
#define LOCKED_LINT1 0x08
#define LOCKED_ERROR 0x10
#define LOCKED_THERMAL 0x20
/* Interrupt Command Register: delivery mode and status */
#define MODE_FIXED 0x0 /* delivery mode: Fixed */
#define MODE_LOWEST 0x1 /* delivery mode: Lowest */
#define MODE_SMI 0x2 /* delivery mode: SMI */
#define MODE_NMI 0x4 /* delivery mode: NMI */
#define MODE_INIT 0x5 /* delivery mode: INIT */
#define MODE_STARTUP 0x6 /* delivery mode: StartUp */
#define STATUS_PEND 0x1000 /* delivery status: Pend */
/* MP Configuration Table Entries */
#define MP_ENTRY_CPU 0 /* Entry Type: CPU */
#define MP_ENTRY_BUS 1 /* Entry Type: BUS */
#define MP_ENTRY_IOAPIC 2 /* Entry Type: IO APIC */
#define MP_ENTRY_IOINTERRUPT 3 /* Entry Type: IO INT */
#define MP_ENTRY_LOINTERRUPT 4 /* Entry Type: LO INT */
/* Extended MP Configuration Table Entries */
#define EXT_MP_ENTRY_SASM 128 /* Entry Type: System Address Space Map */
#define EXT_MP_ENTRY_BHD 129 /* Entry Type: Bus Hierarchy Descriptor */
#define EXT_MP_ENTRY_CBASM 130 /* Entry Type: Comp Address Space Modifier */
/* MP Configuration Table CPU Flags */
#define MP_CPU_FLAGS_BP 0x02
/* IMCR related bits */
#define IMCR_ADRS 0x22 /* IMCR addr reg */
#define IMCR_DATA 0x23 /* IMCR data reg */
#define IMCR_REG_SEL 0x70 /* IMCR reg select */
#define IMCR_IOAPIC_ON 0x01 /* IMCR IOAPIC route enable */
#define IMCR_IOAPIC_OFF 0x00 /* IMCR IOAPIC route disable */
#ifndef _ASMLANGUAGE
#ifdef __cplusplus
extern "C" {
#endif
/* MultiProcessor Specification version 1.4 */
typedef struct /* MP Floating Pointer Structure */
{
char signature [4]; /* "_MP_" */
UINT32 configTableAddr; /* address of the MP configuration table */
UINT8 length; /* length of the floating pointer structure */
UINT8 specRev; /* version number of the MP specification */
UINT8 cksum; /* checksum of the pointer structure */
UINT8 featureByte[5]; /* MP feature bytes 1 - 5 */
} MP_FPS;
typedef struct /* MP Configuration Table Header */
{
char mpSignature[4]; /* "PCMP" */
UINT16 tableLength; /* length of the base configuration table */
UINT8 specRevision; /* version number of the MP specification */
UINT8 cksum; /* checksum of the base configuration table */
char oemId[8]; /* string that identifies the manufacturer */
char prodId[12]; /* string that identifies the product */
UINT32 oemTablePtr; /* address to an OEM configuration table */
UINT16 oemTableSize; /* size of the OEM configuration table */
UINT16 entryCount; /* number of entries in the variable table */
UINT32 localApicBaseAddr; /* address of the Local APIC */
UINT16 extendedTableLength; /* length of the extended entries */
UINT8 extendedTableCksum; /* checksum of the extended table entries */
UINT8 reserved;
} MP_HEADER;
typedef struct /* MP Config Table Entry for CPU's */
{
UINT8 entryType; /* 0 identifies a processor entry */
UINT8 localApicId; /* Local APIC ID number */
UINT8 localApicVersion; /* Local APIC's version number */
UINT8 cpuFlags; /* EN: usable, BP: boot-processor */
UINT32 cpuSig; /* stepping, model, family of the CPU */
UINT32 featureFlags; /* feature definition flag */
UINT32 reserved[2];
} MP_CPU;
typedef struct /* MP Config Table Entry for IO APIC's */
{
UINT8 entryType; /* 2 identifies an IO APIC entry */
UINT8 ioApicId; /* ID of this IO APIC */
UINT8 ioApicVersion; /* version of this IO APIC */
UINT8 ioApicFlags; /* usable or not */
UINT32 ioApicBaseAddress; /* address of this IO APIC */
} MP_IOAPIC;
typedef struct
{
UINT8 entryType;
UINT8 busId;
UINT8 busType[6];
} MP_BUS;
typedef struct
{
UINT8 entryType;
UINT8 interruptType;
UINT16 interruptFlags;
UINT8 sourceBusId;
UINT8 sourceBusIrq;
UINT8 destApicId;
UINT8 destApicIntIn;
} MP_INTERRUPT;
typedef MP_INTERRUPT MP_IOINTERRUPT;
typedef MP_INTERRUPT MP_LOINTERRUPT;
/* logical ID to base address */
#define LID_TO_BASE(apic) ((UINT32)mpApicAddrTable[apic])
/* irq to bus irq */
#define IRQ_TO_BIRQ(apic, irq) mpApicIrqToBusIrq(apic, irq)
/* offset within sysInumTbl depends on the logical apic id */
#define IRQ_OFFSET(apic) (mpApicBaseIrq[apic])
/* number of required interrupt entries */
#define NUM_REDIRECTION_ENTRIES(apic) (mpApicRedEntries[apic])
#define NUM_IOAPICS (mpApicNioApic)
#ifdef __cplusplus
}
#endif
#include "mpApic.h"
#ifdef __cplusplus
extern "C" {
#endif
/* variable declarations */
IMPORT UINT32 loApicBase; /* default Local APIC addr */
IMPORT UINT32 ioApicBase; /* default IO APIC index addr */
IMPORT UINT32 ioApicData; /* default IO APIC data addr */
IMPORT UINT32 loApicId; /* local APIC Id */
IMPORT UINT32 loApicVersion; /* local APIC Version */
IMPORT UINT32 loApicMaxLvt; /* local APIC Max LVT */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT void loApicInit (void);
IMPORT void loApicEnable (BOOL enable);
IMPORT STATUS loApicIpi (INT32 apicId, INT32 shortHand, INT32 trigger,
INT32 level, INT32 destMode, INT32 deliMode,
INT32 vectorNo);
#else
IMPORT void loApicInit ();
IMPORT void loApicEnable ();
IMPORT STATUS loApicIpi ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* __INCloApich */
vxworks-6.9/target/h/drv/intrCtl/m5200Intr.h
+220
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@@ -0,0 +1,220 @@
/* m5200Intr.h - Motorola MPC5200 interrupt header file */
/* Copyright 1991-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,15feb05,j_b INUM_PERIPHERAL_LAST corrected
01a,03jul03,pkr derived from ppc860Intr.h
*/
#ifndef __INCm5200Intrh
#define __INCm5200Intrh
#ifdef __cplusplus
extern "C" {
#endif
/* interrupt number definitions */
/* Peripheral Interrupts */
#define INUM_PERIPHERAL_FIRST 0
#define INUM_BESTCOMM 0
#define INUM_PSC1 1
#define INUM_PSC2 2
#define INUM_PSC3 3
#define INUM_PSC6 4
#define INUM_ETH 5
#define INUM_USB 6
#define INUM_ATA 7
#define INUM_PCI_CTL 8
#define INUM_PCI_RX 9
#define INUM_PCI_TX 10
#define INUM_PSC4 11
#define INUM_PSC5 12
#define INUM_SPI_MODF 13
#define INUM_SPI_SPIF 14
#define INUM_I2C1 15
#define INUM_I2C2 16
#define INUM_CAN1 17
#define INUM_CAN2 18
#define INUM_IR_RX 19
#define INUM_IR_TX 20
#define INUM_XLB 21
#define INUM_BDLC 22
#define INUM_BESTCOMM_LP 23
#define INUM_PERIPHERAL_LAST INUM_BESTCOMM_LP
/* External Interrupts to Main Controller */
#define INUM_MAIN_FIRST 32
#define INUM_SLT1 32
#define INUM_IRQ1 33
#define INUM_IRQ2 34
#define INUM_IRQ3 35
#define _INUM_LO 36 /* internal only */
#define INUM_RTC_pint 37
#define INUM_RTC_sint 38
#define INUM_GPIO_std 39
#define INUM_GPIO_wkup 40
#define INUM_TMR0 41
#define INUM_TMR1 42
#define INUM_TMR2 43
#define INUM_TMR3 44
#define INUM_TMR4 45
#define INUM_TMR5 46
#define INUM_TMR6 47
#define INUM_TMR7 48
#define INUM_MAIN_LAST 48
/* Critical Interrupts to Main Controller */
#define INUM_CRITICAL_FIRST 49
#define INUM_IRQ0 49
#define INUM_SLT0 50
#define _INUM_HI 51 /* internal only */
#define INUM_CCS 52
#define INUM_CRITICAL_LAST 52
/* Bestcomm Interrupts (to share a common table */
#define INUM_SDMA_FIRST 53
#define INUM_SDMA_TEA 53
#define INUM_SDMA_TASK0 54
#define INUM_SDMA_TASK1 55
#define INUM_SDMA_TASK2 56
#define INUM_SDMA_TASK3 57
#define INUM_SDMA_TASK4 58
#define INUM_SDMA_TASK5 59
#define INUM_SDMA_TASK6 60
#define INUM_SDMA_TASK7 61
#define INUM_SDMA_TASK8 62
#define INUM_SDMA_TASK9 63
#define INUM_SDMA_TASK10 64
#define INUM_SDMA_TASK11 65
#define INUM_SDMA_TASK12 66
#define INUM_SDMA_TASK13 67
#define INUM_SDMA_TASK14 68
#define INUM_SDMA_TASK15 69
#define INUM_SDMA_LAST 69
#define SDMA_TASKNO_TO_INUM(TASKNO) (INUM_SDMA_TASK0+TASKNO)
#define NUM_VEC_MAX 69
/* vectors */
#define IV_BESTCOMM INUM_TO_IVEC (INUM_BESTCOMM)
#define IV_PSC1 INUM_TO_IVEC (INUM_PSC1)
#define IV_PSC2 INUM_TO_IVEC (INUM_PSC2)
#define IV_PSC3 INUM_TO_IVEC (INUM_PSC3)
#define IV_PSC6 INUM_TO_IVEC (INUM_PSC6)
#define IV_ETH INUM_TO_IVEC (INUM_ETH)
#define IV_USB INUM_TO_IVEC (INUM_USB)
#define IV_ATA INUM_TO_IVEC (INUM_ATA)
#define IV_PCI_CTL INUM_TO_IVEC (INUM_PCI_CTL)
#define IV_PCI_RX INUM_TO_IVEC (INUM_PCI_RX)
#define IV_PCI_TX INUM_TO_IVEC (INUM_PCI_TX)
#define IV_PSC4 INUM_TO_IVEC (INUM_PSC4)
#define IV_PSC5 INUM_TO_IVEC (INUM_PSC5)
#define IV_SPI_MODF INUM_TO_IVEC (INUM_SPI_MODF)
#define IV_SPI_SPIF INUM_TO_IVEC (INUM_SPI_SPIF)
#define IV_I2C1 INUM_TO_IVEC (INUM_I2C1)
#define IV_I2C2 INUM_TO_IVEC (INUM_I2C2)
#define IV_CAN1 INUM_TO_IVEC (INUM_CAN1)
#define IV_CAN2 INUM_TO_IVEC (INUM_CAN2)
#define IV_IR_RX INUM_TO_IVEC (INUM_IR_RX)
#define IV_IR_TX INUM_TO_IVEC (INUM_IR_TX)
#define IV_XLB INUM_TO_IVEC (INUM_XLB)
#define IV_BDLC INUM_TO_IVEC (INUM_BDLC)
#define IV_BESTCOMM_LP INUM_TO_IVEC (INUM_BESTCOMM_LP)
#define IV_RESERVED24 INUM_TO_IVEC (INUM_RESERVED24)
#define IV_RESERVED25 INUM_TO_IVEC (INUM_RESERVED25)
#define IV_RESERVED26 INUM_TO_IVEC (INUM_RESERVED26)
#define IV_RESERVED27 INUM_TO_IVEC (INUM_RESERVED27)
#define IV_RESERVED28 INUM_TO_IVEC (INUM_RESERVED28)
#define IV_RESERVED29 INUM_TO_IVEC (INUM_RESERVED29)
#define IV_RESERVED30 INUM_TO_IVEC (INUM_RESERVED30)
#define IV_RESERVED31 INUM_TO_IVEC (INUM_RESERVED31)
#define IV_SLT1 INUM_TO_IVEC (INUM_SLT1)
#define IV_IRQ1 INUM_TO_IVEC (INUM_IRQ1)
#define IV_IRQ2 INUM_TO_IVEC (INUM_IRQ2)
#define IV_IRQ3 INUM_TO_IVEC (INUM_IRQ3)
#define IV_RTC_pint INUM_TO_IVEC (INUM_RTC_pint)
#define IV_RTC_sint INUM_TO_IVEC (INUM_RTC_sint)
#define IV_GPIO_std INUM_TO_IVEC (INUM_GPIO_std)
#define IV_GPIO_wkup INUM_TO_IVEC (INUM_GPIO_wkup)
#define IV_TMR0 INUM_TO_IVEC (INUM_TMR0)
#define IV_TMR1 INUM_TO_IVEC (INUM_TMR1)
#define IV_TMR2 INUM_TO_IVEC (INUM_TMR2)
#define IV_TMR3 INUM_TO_IVEC (INUM_TMR3)
#define IV_TMR4 INUM_TO_IVEC (INUM_TMR4)
#define IV_TMR5 INUM_TO_IVEC (INUM_TMR5)
#define IV_TMR6 INUM_TO_IVEC (INUM_TMR6)
#define IV_TMR7 INUM_TO_IVEC (INUM_TMR7)
#define IV_IRQ0 INUM_TO_IVEC (INUM_IRQ0)
#define IV_SLT0 INUM_TO_IVEC (INUM_SLT0)
#define IV_CCS INUM_TO_IVEC (INUM_CCS)
#define IV_SDMA_TEA INUM_TO_IVEC (INUM_SDMA_TEA)
#define IV_SDMA_TASK0 INUM_TO_IVEC (INUM_SDMA_TASK0)
#define IV_SDMA_TASK1 INUM_TO_IVEC (INUM_SDMA_TASK1)
#define IV_SDMA_TASK2 INUM_TO_IVEC (INUM_SDMA_TASK2)
#define IV_SDMA_TASK3 INUM_TO_IVEC (INUM_SDMA_TASK3)
#define IV_SDMA_TASK4 INUM_TO_IVEC (INUM_SDMA_TASK4)
#define IV_SDMA_TASK5 INUM_TO_IVEC (INUM_SDMA_TASK5)
#define IV_SDMA_TASK6 INUM_TO_IVEC (INUM_SDMA_TASK6)
#define IV_SDMA_TASK7 INUM_TO_IVEC (INUM_SDMA_TASK7)
#define IV_SDMA_TASK8 INUM_TO_IVEC (INUM_SDMA_TASK8)
#define IV_SDMA_TASK9 INUM_TO_IVEC (INUM_SDMA_TASK9)
#define IV_SDMA_TASK10 INUM_TO_IVEC (INUM_SDMA_TASK10)
#define IV_SDMA_TASK11 INUM_TO_IVEC (INUM_SDMA_TASK11)
#define IV_SDMA_TASK12 INUM_TO_IVEC (INUM_SDMA_TASK12)
#define IV_SDMA_TASK13 INUM_TO_IVEC (INUM_SDMA_TASK13)
#define IV_SDMA_TASK14 INUM_TO_IVEC (INUM_SDMA_TASK14)
#define SDMA_TASKNO_TO_IVEC(TASKNO) INUM_TO_IVEC(SDMA_TASKNO_TO_INUM(TASKNO))
/* other defines */
#define USE_CRITICAL_INTERRUPT 0
#define INTR_LEVEL_DEFAULT 3
/* typedefs */
/* interrupt handler */
#ifndef _ASMLANGUAGE
typedef struct intr_handler
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
} INTR_HANDLER;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS m5200IntrInit (void);
IMPORT int m5200IntrSetLevel(int, int);
IMPORT void m5200IntAck(int);
#else
IMPORT STATUS m5200IntrInit ();
IMPORT STATUS m5200IntrSetLevel();
IMPORT void m5200IntAck();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#define _EXC_INFO_XLB 0x10000 /* mach check from XLB, info in DAR/DSISR */
#ifdef __cplusplus
}
#endif
#endif /* __INCm5200Intrh */
vxworks-6.9/target/h/drv/intrCtl/m8260IntrCtl.h
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/* m8260IntrCtl.h - MPC 8260 interrupt controller header file */
/* Copyright 1991-2003 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,16jan03,dtr Adding PCI interrupt for HIP4 part.
01g,17sep99,ms_ remove period in __INCm8260Intr
01f,17sep99,ms_ try removing config.h
01e,15jul99,ms_ make compliant with our coding standards
01d,17apr99,ms_ final EAR cleanup
01c,15apr99,ms_ add default interrupt priority ordering
01b,13apr99,ms_ redefine IVEC_TO_INUM and INUM_TO_IVEC to use the numbers as
shown in the
MPC8260 user's manaul
01a,21jan99,ms_ adapted from ppc860Intr.h
*/
#ifndef __INCm8260IntrCtlh
#define __INCm8260IntrCtlh
#include "vxWorks.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#ifdef IVEC_TO_INUM
# undef IVEC_TO_INUM
#endif /* IVEC_TO_INUM */
#ifdef INUM_TO_IVEC
# undef INUM_TO_IVEC
#endif /* INUM_TO_IVEC */
#define IVEC_TO_INUM(intVec) (m8260IvecToInum(intVec))
#define INUM_TO_IVEC(intNum) (m8260InumToIvec(intNum))
/* Interrupt Controller Registers */
#define M8260_SICR(base) ((VINT32 *) ((base) + 0x010C00))
#define M8260_SIVEC(base) ((VINT32 *) ((base) + 0x010C04))
#define M8260_SIPNR_H(base) ((VINT32 *) ((base) + 0x010C08))
#define M8260_SIPNR_L(base) ((VINT32 *) ((base) + 0x010C0C))
#define M8260_SIPRR(base) ((VINT32 *) ((base) + 0x010C10))
#define M8260_SCPRR_H(base) ((VINT32 *) ((base) + 0x010C14))
#define M8260_SCPRR_L(base) ((VINT32 *) ((base) + 0x010C18))
#define M8260_SIMR_H(base) ((VINT32 *) ((base) + 0x010C1C))
#define M8260_SIMR_L(base) ((VINT32 *) ((base) + 0x010C20))
#define M8260_SIEXR(base) ((VINT32 *) ((base) + 0x010C24))
/* interrupt numbers */
#define INUM_ERROR 0 /* Error */
#define INUM_I2C 1 /* I2C */
#define INUM_SPI 2 /* SPI */
#define INUM_RISC_TIMER 3 /* Risc Timer Table */
#define INUM_SMC1 4 /* SMC 1 */
#define INUM_SMC2 5 /* SMC 2 */
#define INUM_IDMA1 6 /* IDMA1 */
#define INUM_IDMA2 7 /* IDMA2 */
#define INUM_IDMA3 8 /* IDMA3 */
#define INUM_IDMA4 9 /* IDMA4 */
#define INUM_SDMA 10 /* SDMA */
#define INUM_RESERVED11 11 /* reserved */
#define INUM_TIMER1 12 /* Timer 1 */
#define INUM_TIMER2 13 /* Timer 2 */
#define INUM_TIMER3 14 /* Timer 3 */
#define INUM_TIMER4 15 /* Timer 4 */
#define INUM_TMCNT 16 /* TMCNT */
#define INUM_PIT 17 /* PIT */
#define INUM_PCI 18 /* PCI Error/DMA/Messages */
#define INUM_IRQ1 19 /* IRQ 1 interrupt */
#define INUM_IRQ2 20 /* IRQ 2 interrupt */
#define INUM_IRQ3 21 /* IRQ 3 interrupt */
#define INUM_IRQ4 22 /* IRQ 4 interrupt */
#define INUM_IRQ5 23 /* IRQ 5 interrupt */
#define INUM_IRQ6 24 /* IRQ 6 interrupt */
#define INUM_IRQ7 25 /* IRQ 7 interrupt */
#define INUM_RESERVED26 26 /* reserved */
#define INUM_FCC1 27 /* FCC1 */
#define INUM_FCC2 28 /* FCC2 */
#define INUM_FCC3 29 /* FCC3 */
#define INUM_RESERVED30 30 /* reserved */
#define INUM_MCC1 31 /* MCC1 */
#define INUM_MCC2 32 /* MCC2 */
#define INUM_RESERVED33 33 /* reserved */
#define INUM_RESERVED34 34 /* reserved */
#define INUM_SCC1 35 /* SCC1 */
#define INUM_SCC2 36 /* SCC2 */
#define INUM_SCC3 37 /* SCC3 */
#define INUM_SCC4 38 /* SCC4 */
#define INUM_RESERVED39 39 /* reserved */
#define INUM_PC15 40 /* Parallel I/O [15] */
#define INUM_PC14 41 /* Parallel I/O [14] */
#define INUM_PC13 42 /* Parallel I/O [13] */
#define INUM_PC12 43 /* Parallel I/O [12] */
#define INUM_PC11 44 /* Parallel I/O [11] */
#define INUM_PC10 45 /* Parallel I/O [10] */
#define INUM_PC9 46 /* Parallel I/O [9] */
#define INUM_PC8 47 /* Parallel I/O [8] */
#define INUM_PC7 48 /* Parallel I/O [7] */
#define INUM_PC6 49 /* Parallel I/O [6] */
#define INUM_PC5 50 /* Parallel I/O [5] */
#define INUM_PC4 51 /* Parallel I/O [4] */
#define INUM_PC3 52 /* Parallel I/O [3] */
#define INUM_PC2 53 /* Parallel I/O [2] */
#define INUM_PC1 54 /* Parallel I/O [1] */
#define INUM_PC0 55 /* Parallel I/O [0] */
#define INUM_MAX INUM_PC0
#define IVEC_MAX (INUM_PC0 + 8)
/* SICR Masks*/
#define MPC8260_CICR_SCCDP_MSK 0xc00000 /* SCCd Priority Order Mask */
#define MPC8260_CICR_SCCDP_SCC1 0x000000 /* SCC1 asserts the SCCd */
#define MPC8260_CICR_SCCDP_SCC2 0x400000 /* SCC2 asserts the SCCd */
#define MPC8260_CICR_SCCDP_SCC3 0x800000 /* SCC3 asserts the SCCd */
#define MPC8260_CICR_SCCDP_SCC4 0xc00000 /* SCC4 asserts the SCCd */
#define MPC8260_CICR_SCCCP_MSK 0x300000 /* SCCc Priority Order Mask */
#define MPC8260_CICR_SCCCP_SCC1 0x000000 /* SCC1 asserts the SCCc */
#define MPC8260_CICR_SCCCP_SCC2 0x100000 /* SCC2 asserts the SCCc */
#define MPC8260_CICR_SCCCP_SCC3 0x200000 /* SCC3 asserts the SCCc */
#define MPC8260_CICR_SCCCP_SCC4 0x300000 /* SCC4 asserts the SCCc */
#define MPC8260_CICR_SCCBP_MSK 0x0c0000 /* SCCb Priority Order Mask */
#define MPC8260_CICR_SCCBP_SCC1 0x000000 /* SCC1 asserts the SCCb */
#define MPC8260_CICR_SCCBP_SCC2 0x040000 /* SCC2 asserts the SCCb */
#define MPC8260_CICR_SCCBP_SCC3 0x080000 /* SCC3 asserts the SCCb */
#define MPC8260_CICR_SCCBP_SCC4 0x0c0000 /* SCC4 asserts the SCCb */
#define MPC8260_CICR_SCCAP_MSK 0x030000 /* SCCa Priority Order Mask */
#define MPC8260_CICR_SCCAP_SCC1 0x000000 /* SCC1 asserts the SCCa */
#define MPC8260_CICR_SCCAP_SCC2 0x010000 /* SCC2 asserts the SCCa */
#define MPC8260_CICR_SCCAP_SCC3 0x020000 /* SCC3 asserts the SCCa */
#define MPC8260_CICR_SCCAP_SCC4 0x030000 /* SCC4 asserts the SCCa */
#define MPC8260_CICR_IRL_MSK 0x00e000 /* Interrupt Request Level */
#define MPC8260_CICR_IRL_LVL0 0x000000 /* Interrupt Request Level 0 */
#define MPC8260_CICR_IRL_LVL1 0x002000 /* Interrupt Request Level 1 */
#define MPC8260_CICR_IRL_LVL2 0x004000 /* Interrupt Request Level 2 */
#define MPC8260_CICR_IRL_LVL3 0x006000 /* Interrupt Request Level 3 */
#define MPC8260_CICR_IRL_LVL4 0x008000 /* Interrupt Request Level 4 */
#define MPC8260_CICR_IRL_LVL5 0x00a000 /* Interrupt Request Level 5 */
#define MPC8260_CICR_IRL_LVL6 0x00c000 /* Interrupt Request Level 6 */
#define MPC8260_CICR_IRL_LVL7 0x00e000 /* Interrupt Request Level 7 */
#define MPC8260_CICR_HP_MSK 0x001f00 /* Highest Priority */
#define MPC8260_CICR_IEN 0x000080 /* Interrupt Enable */
#define MPC8260_CICR_SPS 0x000001 /* Spread Priority Scheme */
/* interrupt handler */
#ifndef _ASMLANGUAGE
typedef struct intr_handler
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
} INTR_HANDLER;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS m8260IntrInit ();
extern STATUS m8260IntDisable (int );
IMPORT STATUS m8260IntEnable (int );
extern int m8260IvecToInum(VOIDFUNCPTR *);
extern VOIDFUNCPTR * m8260InumToIvec(int);
#else
IMPORT STATUS m8260IntrInit ();
extern STATUS m8260IntDisable ();
IMPORT STATUS m8260IntEnable ();
extern int m8260IvecToInum();
extern VOIDFUNCPTR * m8260InumToIvec();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCm8260IntrCtlh */
vxworks-6.9/target/h/drv/intrCtl/mpApic.h
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/* mpApic.h - Intel MP APIC/xAPIC (Advanced PIC) */
/* Copyright 2006, 2008, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01g,29apr10,pad Moved extern C statement after include statements.
01f,27aug08,jpb Renamed VSB header file
01e,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01d,30oct06,scm rename mpApicNcpu to vxCpuCount...
01c,31aug06,scm add support for CPU ID translation table...
01b,26jul06,scm update for pentium/xeon support...
01a,26jul06,hdn written...
*/
#ifndef __INCmpApich
#define __INCmpApich
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
#define BUILT_IN_APIC 0
/* Maximum Number of IOAPICs in the system */
#ifndef MAX_IOAPICS
#define MAX_IOAPICS 16
#endif
#ifndef _ASMLANGUAGE
/* variable declarations */
IMPORT MP_FPS *mpApicFps;
#ifdef _WRS_CONFIG_SMP
IMPORT unsigned int vxCpuCount; /* number of CPUs (MP Table) */
#endif /* _WRS_CONFIG_SMP */
IMPORT UINT32 mpApicNioApic; /* number of IO APICs (MP Table) */
IMPORT UINT32 mpApicNbus; /* number of buses (MP Table) */
IMPORT UINT32 mpApicNioint; /* number of io interrupts (MP Table) */
IMPORT UINT32 mpApicNloint; /* number of local interrupts (MP Table) */
IMPORT UINT32 *mpApicAddrTable[]; /* logical apic id to address mapping */
#ifdef _WRS_CONFIG_SMP
IMPORT UINT8 mpCpuIndexTable[]; /* cpu Id translation */
IMPORT UINT8 mploApicIndexTable[]; /* loApic Id translation */
#endif /* _WRS_CONFIG_SMP */
IMPORT UINT8 mpApicLogicalTable[]; /* recorded id mapping */
IMPORT UINT8 mpApicRedEntries[];
IMPORT UINT8 mpApicBaseIrq[];
IMPORT MP_INTERRUPT *mpApicInterruptTable;
IMPORT MP_BUS *mpApicBusTable;
#if defined(__STDC__) || defined(__cplusplus)
STATUS mpApicMpConfigTableInit(void);
INT8 *mpApicScan(INT8* match, INT8 * start, INT8 * end);
UINT32 mpApicIrqToBusIrq(UINT32 ioApicId, UINT32 irq);
#else
IMPORT STATUS mpApicMpConfigTableInit();
IMPORT INT8 *mpApicScan();
IMPORT UINT32 mpApicIrqToBusIrq(UINT32 ioApicId, UINT32 irq);
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmpApich */
vxworks-6.9/target/h/drv/intrCtl/mpc107Epic.h
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/* mpc107Epic.h - MPC107 EPIC register definitions */
/* Copyright 1984-2000, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,11sep00,rcs correct include path errors
01a,06jun00,bri written
*/
#ifndef __INCmpc107Epich
#define __INCmpc107Epich
/* includes */
#include "drv/multi/mpc107.h"
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
/* MPC107 configuration registers for EPIC && other definitions */
#define INTERRUPT_TABLESIZE 256 /* Interrupt Table Size */
#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */
#define MPC107_EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature report */
#define MPC107_EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */
#define MPC107_EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config */
#define MPC107_EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */
#define MPC107_EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */
#define MPC107_EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */
#define MPC107_EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */
/*
* Definitions of Global Timer Registers :
* Global Timer Current Count Register (GTCCR)
* Global Timer Base Count Register (GTBCR)
* Global Timer Vector/Priority Register (GTVPR)
* Global Timer Destination Register (GTDR)
*/
#define MPC107_EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100) /* GTCCR0 */
#define MPC107_EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110) /* GTBCRO */
#define MPC107_EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120) /* GTVPR0 */
#define MPC107_EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130) /* GTDR0 */
#define MPC107_EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140) /* GTCCR1 */
#define MPC107_EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150) /* GTBCR1*/
#define MPC107_EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160) /* GTVPR1*/
#define MPC107_EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170) /* GTDR1*/
#define MPC107_EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180) /* GTCCR2 */
#define MPC107_EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190) /* GTBCR2 */
#define MPC107_EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0) /* GTVPR2 */
#define MPC107_EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0) /* GTDR2 */
#define MPC107_EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0) /* GTCCR3 */
#define MPC107_EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0) /* GTBCR3 */
#define MPC107_EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0) /* GTVPR3 */
#define MPC107_EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0) /* GTDR3 */
/*
* External Interrupts Vector /Priority Registers (IVPR) and
* Destination Registers (IDR)
*/
#define MPC107_EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200) /* IVPR0 */
#define MPC107_EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210) /* IDR0 */
#define MPC107_EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220) /* IVPR1 */
#define MPC107_EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230) /* IDR1 */
#define MPC107_EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240) /* IVPR2 */
#define MPC107_EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250) /* IDR2 */
#define MPC107_EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260) /* IVPR3 */
#define MPC107_EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270) /* IDR3 */
#define MPC107_EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280) /* IVPR4 */
#define MPC107_EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290) /* IDR4 */
/*
* Serial Interrupts Vector /Priority Registers (SVPR) and
* Destination Registers (SDR)
*/
#define MPC107_EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200) /* SVPR0 */
#define MPC107_EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210) /* SDR0 */
#define MPC107_EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220) /* SVPR1 */
#define MPC107_EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230) /* SDR1 */
#define MPC107_EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240) /* SVPR2 */
#define MPC107_EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250) /* SDR2 */
#define MPC107_EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260) /* SVPR3 */
#define MPC107_EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270) /* SDR3 */
#define MPC107_EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280) /* SVPR4 */
#define MPC107_EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290) /* SDR4 */
#define MPC107_EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0) /* SVPR5 */
#define MPC107_EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0) /* SDR5 */
#define MPC107_EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0) /* SVPR6 */
#define MPC107_EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0) /* SDR6 */
#define MPC107_EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0) /* SVPR7 */
#define MPC107_EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0) /* SDR7 */
#define MPC107_EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300) /* SVPR8 */
#define MPC107_EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310) /* SDR8 */
#define MPC107_EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320) /* SVPR9 */
#define MPC107_EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330) /* SDR9 */
#define MPC107_EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340) /* SVPR10 */
#define MPC107_EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350) /* SDR10 */
#define MPC107_EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360) /* SVPR11 */
#define MPC107_EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370) /* SDR11 */
#define MPC107_EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380) /* SVPR12 */
#define MPC107_EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390) /* SDR12 */
#define MPC107_EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0) /* SVPR13 */
#define MPC107_EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0) /* SDR13 */
#define MPC107_EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0) /* SVPR14 */
#define MPC107_EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0) /* SDR14 */
#define MPC107_EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0) /* SVPR15 */
#define MPC107_EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0) /* SDR15 */
/*
* IIC Interrupts Vector /Priority Registers (IIVPR) and
* Destination Registers (IIDR)
*/
#define MPC107_EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* IIVPR0 */
#define MPC107_EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* IIDR0 */
/*
* DMA Interrupts Vector /Priority Registers (IIVPR) and
* Destination Registers (IIDR) - Channel Zero
*/
#define MPC107_EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040) /* IIVPR1 */
#define MPC107_EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050) /* IIDR1 */
/*
* DMA Interrupts Vector /Priority Registers (IIVPR) and
* Destination Registers (IIDR) - Channel One
*/
#define MPC107_EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060) /* IIVPR2 */
#define MPC107_EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070) /* IIDR2 */
/*
* Message Unit Interrupts Vector /Priority Registers (IIVPR) and
* Destination Registers (IIDR)
*/
#define MPC107_EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* IIVPR3 */
#define MPC107_EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* IIDR3 */
/* General Register Definitions */
#define MPC107_EPIC_PROC_CTASK_PRI_REG \
(EPIC_EUMBBAR + 0x20080) /* Proccesor current task Register */
#define MPC107_EPIC_PROC_INT_ACK_REG \
(EPIC_EUMBBAR + 0x200a0) /* Interrupt acknowledge Register */
#define MPC107_EPIC_PROC_EOI_REG \
(EPIC_EUMBBAR + 0x200b0) /* End of interrupt Register */
/* General Definitions */
#define MPC107_EPIC_VEC_REG_INTERVAL 0x20 /* Distance between interrupt */
/* vector registers */
#define MPC107_EPIC_VEC_REG(irq) (MPC107_EPIC_EX_INT0_VEC_REG + \
(irq * MPC107_EPIC_VEC_REG_INTERVAL))
#define MPC107_EPIC_DIRECT_IRQ 0 /* Direct IRQ */
#define MPC107_INT_VEC_IRQ0 5 /* Maximum Ext Interrupts */
#define MPC107_EPIC_INTER_IN_SERVICE 2 /* Interrupt in service */
#define MPC107_EPIC_INTERNAL_INTERRUPT 20 /* Internal Interrupts */
#define MPC107_EPIC_EXTERNAL_INTERRUPT 21 /* External Interrupts */
#define MPC107_EPIC_INV_INTER_SOURCE 22 /* Invalid Interrupt Source */
#define MPC107_EPIC_MAX_EXT_IRQS 5 /* Maximum No. of ext.Interrupts */
#define MPC107_EPIC_PRIORITY_MIN 0 /* minimum level of priority */
#define MPC107_EPIC_PRIORITY_MAX 15 /* maximum level of priority */
#define MPC107_EPIC_PRIORITY_GENERAL 12 /* General priority */
#define MPC107_EPIC_INV_PRIO_ERROR ((ULONG)(-1)) /* Invalid Priority */
#define MPC107_EPIC_IVPRO_INT_NUM 0 /* External Interrupt 0 */
#define MPC107_EPIC_IVPR1_INT_NUM 1 /* External Interrupt 1 */
#define MPC107_EPIC_IVPR2_INT_NUM 2 /* External Interrupt 2 */
#define MPC107_EPIC_IVPR3_INT_NUM 3 /* External Interrupt 3 */
#define MPC107_EPIC_IVPR4_INT_NUM 4 /* External Interrupt 4 */
#define MPC107_EPIC_SVPRO_INT_NUM 0 /* Serial Interrupt 0 */
#define MPC107_EPIC_SVPR1_INT_NUM 1 /* Serial Interrupt 1 */
#define MPC107_EPIC_SVPR2_INT_NUM 2 /* Serial Interrupt 2 */
#define MPC107_EPIC_SVPR3_INT_NUM 3 /* Serial Interrupt 3 */
#define MPC107_EPIC_SVPR4_INT_NUM 4 /* Serial Interrupt 4 */
#define MPC107_EPIC_SVPR5_INT_NUM 5 /* Serial Interrupt 5 */
#define MPC107_EPIC_SVPR6_INT_NUM 6 /* Serial Interrupt 6 */
#define MPC107_EPIC_SVPR7_INT_NUM 7 /* Serial Interrupt 7 */
#define MPC107_EPIC_SVPR8_INT_NUM 8 /* Serial Interrupt 8 */
#define MPC107_EPIC_SVPR9_INT_NUM 9 /* Serial Interrupt 9 */
#define MPC107_EPIC_SVPR1O_INT_NUM 10 /* Serial Interrupt 10 */
#define MPC107_EPIC_SVPR11_INT_NUM 11 /* Serial Interrupt 11 */
#define MPC107_EPIC_SVPR12_INT_NUM 12 /* Serial Interrupt 12 */
#define MPC107_EPIC_SVPR13_INT_NUM 13 /* Serial Interrupt 13 */
#define MPC107_EPIC_SVPR14_INT_NUM 14 /* Serial Interrupt 14 */
#define MPC107_EPIC_SVPR15_INT_NUM 15 /* Serial Interrupt 15 */
#define MPC107_EPIC_IIC_INT_VECT 0x71 /* IIC Interrupt */
#define MPC107_EPIC_DMA0_INT_VECT 0x72 /* DMA Channel 0 Interrupt */
#define MPC107_EPIC_DMA1_INT_VECT 0x73 /* DMA Channel 1 Interrupt */
#define MPC107_EPIC_MU_INT_VECT 0x76 /* Message Unit Interrupt */
/* Bit definitions */
/* Global Configuration Register Bit Definitions */
#define MPC107_EPIC_GCR_RESET 0x80000000 /* EPIC reset bit */
#define MPC107_EPIC_GCR_MODE_MIXED 0x20000000 /* EPIC Mixed Mode bit */
/* Interrupt Configuration Register Bit Definitions */
#define MPC107_EPIC_ICR_SEI 0x08000000 /* Serial Interrupt Enable */
#define MPC107_EPIC_ICR_CLK_RATIO_MSK \
(0x40000000 | 0x20000000 | 0x10000000) /* Clock Ratio Mask Bits */
#define MPC107_EPIC_ICR_CLK_RATIO(val) \
(((val) << 28) & MPC107_EPIC_ICR_CLK_RATIO_MSK) /* Clock Ratio Shift */
/* Interrupt Vector/Priority Register Bit Definitions */
#define MPC107_EPIC_IVPR_INTR_MSK 0x80000000 /* Interrupt Mask bit */
#define MPC107_EPIC_IVPR_INTR_ACTIVE 0x40000000 /* Interrupt Activity Bit */
#define MPC107_EPIC_IVPR_INTR_POLARITY 0x00800000 /* Interrupt Polarity Bit */
#define MPC107_EPIC_IVPR_INTR_SENSE 0x00400000 /* Interrupt Sense Bit */
#define MPC107_EPIC_IVPR_POLARITY(p) ((p) << 23) /* Int Polarity Shift */
#define MPC107_EPIC_IVPR_SENS(s) ((s) << 22) /* Int Sense Shift */
#define MPC107_EPIC_IVPR_PRIORITY_MSK \
(0x00080000 | 0x00040000 | 0x00020000 | 0x00010000) /* Priority Mask */
#define MPC107_EPIC_IVPR_PRIORITY(p) \
(((p) << 16) & MPC107_EPIC_IVPR_PRIORITY_MSK)/* Priority Shift */
#define MPC107_EPIC_IVPR_VECTOR_MSK (0xff) /* Vector Mask */
#define MPC107_EPIC_IVPR_VECTOR(vec) \
((vec) & MPC107_EPIC_IVPR_VECTOR_MSK) /* Vector Mask */
#define MPC107_EPIC_INT_ACT_LOW 0 /* Active low Interrupt */
#define MPC107_EPIC_INT_ACT_HIGH 1 /* Active high Interrupt */
#define MPC107_EPIC_SENSE_LVL 1 /* Level Sensitive */
#define MPC107_EPIC_SENSE_EDG 0 /* Edge Sensitive */
#define MPC107_EPIC_INT_POLARITY 0x0 /* Interrupt polarity */
/* Global Timer Vector/Priority register Bit Definitions */
#define MPC107_EPIC_TM_VECREG_INTMASK 0x80000000 /* Interrupt Mask Bit */
/* Global Timer Base Count Register Bit Definitions */
#define MPC107_EPIC_TM_BASE_COUNT_CI 0x80000000 /* Count Inhibit Bit */
#define MPC107_EPIC_TM_CUR_COUNT_TB 0x80000000 /* toggle bit */
/* typedefs */
/* interrupt handler description */
typedef struct intHandlerDesc
{
VOIDFUNCPTR vec; /* interrupt vector */
INT32 arg; /* interrupt handler argument */
struct intHandlerDesc * next; /* pointer to the next handler */
} INT_HANDLER_DESC;
/* function declarations */
IMPORT VOID mpc107EpicInit (ULONG IRQType, ULONG clkRatio);
IMPORT VOID mpc107EpicIntrInit (VOID);
IMPORT STATUS mpc107EpicIntConnect (VOIDFUNCPTR *vector,
VOIDFUNCPTR routine,
INT32 parameter );
IMPORT STATUS mpc107EpicIntDisconnect (VOIDFUNCPTR * vector,
VOIDFUNCPTR routine);
IMPORT VOID mpc107EpicIntHandler (VOID);
#ifdef __cplusplus
}
#endif
#endif /* __INCmpc107Epich */
vxworks-6.9/target/h/drv/intrCtl/ppc555Intr.h
+72
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/* ppc509Intr.h - PowerPC 509 interrupt header file */
/* Copyright 1991-1999 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,16mar99,zl written.
*/
#ifndef __INCppc509Intrh
#define __INCppc509Intrh
#ifdef __cplusplus
extern "C" {
#endif
/* interrupt number definitions */
#define LEVELN_PRIORITY_LVL(n) (2*n + 1)
#define IRQN_PRIORITY_LVL(n) (2*n)
#define INT_LEVEL0 0 /* level 0 interrupt */
#define INT_LEVEL1 1 /* level 1 interrupt */
#define INT_LEVEL2 2 /* level 2 interrupt */
#define INT_LEVEL3 3 /* level 3 interrupt */
#define INT_LEVEL4 4 /* level 4 interrupt */
#define INT_LEVEL5 5 /* level 5 interrupt */
#define INT_LEVEL6 6 /* level 6 interrupt */
#define INT_LEVEL7 7 /* level 7 interrupt */
#define INT_IRQ0 0 /* IRQ 0 interrupt */
#define INT_IRQ1 1 /* IRQ 1 interrupt */
#define INT_IRQ2 2 /* IRQ 2 interrupt */
#define INT_IRQ3 3 /* IRQ 3 interrupt */
#define INT_IRQ4 4 /* IRQ 4 interrupt */
#define INT_IRQ5 5 /* IRQ 5 interrupt */
#define INT_IRQ6 6 /* IRQ 6 interrupt */
#define INT_IRQ7 7 /* IRQ 7 interrupt */
#define NUM_VEC_MAX 64
/* typedefs */
/* interrupt handler */
#ifndef _ASMLANGUAGE
typedef struct intr_handler
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
} INTR_HANDLER;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS ppc509IntrInit (void);
#else
IMPORT STATUS ppc509IntrInit ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCppc509Intrh */
vxworks-6.9/target/h/drv/intrCtl/ppc860Intr.h
+127
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/* ppc860Intr.h - PowerPC 860 interrupt header file */
/* Copyright 1991-1998 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,09nov98,cn added IVEC_TO_IRQ, IVEC_TO_ILEVEL macros.
01c,09mar98,map added IV_RESERVED59, 60 for compatiblity [SPR# 20114]
01b,10jun97,map added IV_SCC[34] definitions [SPR# 8450]
01a,17apr96,tpr written.
*/
#ifndef __INCppc860Intrh
#define __INCppc860Intrh
#ifdef __cplusplus
extern "C" {
#endif
/* interrupt number definitions */
#define IV_IRQ0 INUM_TO_IVEC (0) /* IRQ 0 interrupt */
#define IV_LEVEL0 INUM_TO_IVEC (1) /* level 0 interrupt */
#define IV_IRQ1 INUM_TO_IVEC (2) /* IRQ 1 interrupt */
#define IV_LEVEL1 INUM_TO_IVEC (3) /* level 1 interrupt */
#define IV_IRQ2 INUM_TO_IVEC (4) /* IRQ 2 interrupt */
#define IV_LEVEL2 INUM_TO_IVEC (5) /* level 2 interrupt */
#define IV_IRQ3 INUM_TO_IVEC (6) /* IRQ 3 interrupt */
#define IV_LEVEL3 INUM_TO_IVEC (7) /* level 3 interrupt */
#define IV_IRQ4 INUM_TO_IVEC (8) /* IRQ 4 interrupt */
#define IV_LEVEL4 INUM_TO_IVEC (9) /* level 4 interrupt */
#define IV_IRQ5 INUM_TO_IVEC (10) /* IRQ 5 interrupt */
#define IV_LEVEL5 INUM_TO_IVEC (11) /* level 5 interrupt */
#define IV_IRQ6 INUM_TO_IVEC (12) /* IRQ 6 interrupt */
#define IV_LEVEL6 INUM_TO_IVEC (13) /* level 6 interrupt */
#define IV_IRQ7 INUM_TO_IVEC (14) /* IRQ 7 interrupt */
#define IV_LEVEL7 INUM_TO_IVEC (15) /* level 7 interrupt */
#define IV_RESERVE0 INUM_TO_IVEC (16) /* reserved */
#define IV_RESERVE1 INUM_TO_IVEC (17) /* reserved */
#define IV_RESERVE2 INUM_TO_IVEC (18) /* reserved */
#define IV_RESERVE3 INUM_TO_IVEC (19) /* reserved */
#define IV_RESERVE4 INUM_TO_IVEC (20) /* reserved */
#define IV_RESERVE5 INUM_TO_IVEC (21) /* reserved */
#define IV_RESERVE6 INUM_TO_IVEC (22) /* reserved */
#define IV_RESERVE7 INUM_TO_IVEC (23) /* reserved */
#define IV_RESERVE8 INUM_TO_IVEC (24) /* reserved */
#define IV_RESERVE9 INUM_TO_IVEC (25) /* reserved */
#define IV_RESERVE10 INUM_TO_IVEC (26) /* reserved */
#define IV_RESERVE11 INUM_TO_IVEC (27) /* reserved */
#define IV_RESERVE12 INUM_TO_IVEC (28) /* reserved */
#define IV_RESERVE13 INUM_TO_IVEC (29) /* reserved */
#define IV_RESERVE14 INUM_TO_IVEC (30) /* reserved */
#define IV_RESERVE15 INUM_TO_IVEC (31) /* reserved */
#define IV_ERROR INUM_TO_IVEC (32) /* Error */
#define IV_PC4 INUM_TO_IVEC (33) /* Parallel I/O [4] */
#define IV_PC5 INUM_TO_IVEC (34) /* Parallel I/O [5] */
#define IV_SMC2_PIP INUM_TO_IVEC (35) /* SMC 2/PIP */
#define IV_SMC1 INUM_TO_IVEC (36) /* SMC 1 */
#define IV_SPI INUM_TO_IVEC (37) /* SPI */
#define IV_PC6 INUM_TO_IVEC (38) /* Parallel I/O [6] */
#define IV_TIMER4 INUM_TO_IVEC (39) /* Timer 4 */
#define IV_RESERVED40 INUM_TO_IVEC (40) /* reserved */
#define IV_PC7 INUM_TO_IVEC (41) /* Parallel I/O [7] */
#define IV_PC8 INUM_TO_IVEC (42) /* Parallel I/O [8] */
#define IV_PC9 INUM_TO_IVEC (43) /* Parallel I/O [9] */
#define IV_TIMER3 INUM_TO_IVEC (44) /* Timer 3 */
#define IV_RESERVED45 INUM_TO_IVEC (45) /* reserved */
#define IV_PC10 INUM_TO_IVEC (46) /* Parallel I/O [10] */
#define IV_PC11 INUM_TO_IVEC (47) /* Parallel I/O [11] */
#define IV_I2C INUM_TO_IVEC (48) /* I2C */
#define IV_RISC_TIMER_TABLE INUM_TO_IVEC (49) /* Risc Timer Table */
#define IV_TIMER2 INUM_TO_IVEC (50) /* Timer 2 */
#define IV_RESERVED51 INUM_TO_IVEC (51) /* reserved */
#define IV_IDMA2 INUM_TO_IVEC (52) /* IDMA2 */
#define IV_IDMA1 INUM_TO_IVEC (53) /* IDMA1 */
#define IV_SDMA INUM_TO_IVEC (54) /* SDMA bus error */
#define IV_PC12 INUM_TO_IVEC (55) /* Parallel I/O [12] */
#define IV_PC13 INUM_TO_IVEC (56) /* Parallel I/O [13] */
#define IV_TIMER1 INUM_TO_IVEC (57) /* Timer 1 */
#define IV_PC14 INUM_TO_IVEC (58) /* Parallel I/O [14] */
#define IV_SCC4 INUM_TO_IVEC (59) /* SCC4 */
#define IV_RESERVED59 IV_SCC4
#define IV_SCC3 INUM_TO_IVEC (60) /* SCC3 */
#define IV_RESERVED60 IV_SCC3
#define IV_SCC2 INUM_TO_IVEC (61) /* SCC2 */
#define IV_SCC1 INUM_TO_IVEC (62) /* SCC1 */
#define IV_PC15 INUM_TO_IVEC (63) /* Parallel I/O [15] */
#define NUM_VEC_MAX 64
/* macro to get to the IRQ/ILEVEL from the vector number */
#define IVEC_TO_IRQ(x) (int) (x >> 1) /* interrupt request*/
#define IVEC_TO_ILEVEL(x) (int) (x >> 1) /* interrupt level */
/* typedefs */
/* interrupt handler */
#ifndef _ASMLANGUAGE
typedef struct intr_handler
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
} INTR_HANDLER;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS ppc860IntrInit (VOIDFUNCPTR *);
#else
IMPORT STATUS ppc860IntrInit ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCppc860Intrh */
vxworks-6.9/target/h/drv/intrCtl/qeIntrCtl.h
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/* qeIntrCtl.h - Quicc Engine interrupt controller header file */
/* Copyright (c) Wind River Systems, Inc. */
/*
modification history
--------------------
01a,10jan05,dtr adapted from m85xxIntrCtl.
*/
#ifndef __INCqeIntrCtlh
#define __INCqeIntrCtlh
#include "vxWorks.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#ifdef QE_IVEC_TO_INUM
# undef QE_IVEC_TO_INUM
#endif /* IVEC_TO_INUM */
#ifdef QE_INUM_TO_IVEC
# undef QE_INUM_TO_IVEC
#endif /* INUM_TO_IVEC */
#define QE_IVEC_TO_INUM(intVec) (qeIvecToInum(intVec))
#define QE_INUM_TO_IVEC(intNum) (qeInumToIvec(intNum))
/* This offset used to allow intConnect/Enable etc to direct a call to the
* quiccEngine controller vs the e300 or e500 interrupt controller
* append this to int<func> call vector/intNum.
* eg intEnable(QE_INUM_UCC1 + QE_INUM_OFFSET)
*/
#define QE_INUM_OFFSET IVEC_MAX
#define QE_INUM_ERROR 0
#define QE_INUM_SPI2 1
#define QE_INUM_SPI1 2
#define QE_INUM_RTT 3
#define QE_INUM_SDMA 10
#define QE_INUM_USB 11
#define QE_INUM_TIMER1 12
#define QE_INUM_TIMER2 13
#define QE_INUM_TIMER3 14
#define QE_INUM_TIMER4 15
#define QE_INUM_VT 20
#define QE_INUM_EXT1 25
#define QE_INUM_EXT2 26
#define QE_INUM_EXT3 27
#define QE_INUM_EXT4 28
#define QE_INUM_UCC1 32
#define QE_INUM_UCC2 33
#define QE_INUM_UCC3 34
#define QE_INUM_UCC4 35
#define QE_INUM_MCC1 36
#define QE_INUM_UCC5 40
#define QE_INUM_UCC6 41
#define QE_INUM_UCC7 42
#define QE_INUM_UCC8 43
#define QE_INUM_MAX 64
#define QE_IVEC_MAX 64
#if 0
#define QE_CICR 0x80 /* interrupt configuration Register */
#define QE_CIVEC 0x84
#define QE_CRIPNR 0x88
#define QE_CIPNR 0x8C
#define QE_CIPXCC 0x90
#define QE_CIPYCC 0x94
#define QE_CIPWCC 0x98
#define QE_CIPZCC 0x9C
#define QE_CIMR 0xA0
#define QE_CRIMR 0xA4
#define QE_CICNR 0xA8
#define QE_CIPRTA 0xB0
#define QE_CIPRTB 0xB4
#define QE_CRIC 0xBC
#define QE_CHIVEC 0xE0
#else
#define QE_CICR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x80)) /* interrupt configuration Register */
#define QE_CIVEC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x84))
#define QE_CRIPNR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x88))
#define QE_CIPNR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x8C))
#define QE_CIPXCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x90))
#define QE_CIPYCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x94))
#define QE_CIPWCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x98))
#define QE_CIPZCC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0x9C))
#define QE_CIMR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xA0))
#define QE_CRIMR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xA4))
#define QE_CICNR(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xA8))
#define QE_CIPRTA(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xB0))
#define QE_CIPRTB(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xB4))
#define QE_CRIC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xBC))
#define QE_CHIVEC(base) ((VUINT32 *) ((base) + QUICC_ENGINE_BA + 0xE0))
#endif
#ifndef _ASMLANGUAGE
typedef struct qe_intr_handler
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
void *pNext;
} QE_INTR_HANDLER;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS qeIntrInit ();
extern STATUS qeIntDisable (int );
IMPORT STATUS qeIntEnable (int );
extern int qeIvecToInum(VOIDFUNCPTR *);
extern VOIDFUNCPTR * qeInumToIvec(int);
#else
IMPORT STATUS qeIntrInit ();
extern STATUS qeIntDisable ();
IMPORT STATUS qeIntEnable ();
extern int qeIvecToInum();
extern VOIDFUNCPTR * qeInumToIvec();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCqeIntrCtlh */
vxworks-6.9/target/h/drv/intrCtl/quiccIntrCtl.h
+202
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@@ -0,0 +1,202 @@
/* quiccIntrCtl.h - PowerQuicc interrupt controller header file */
/* Copyright (c) 2005-2007 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,05sep07,dtr WIND0045894 - INUM_CPIO1 to INUM_GPIO1.
01b,09may06,dtr Add 8360 support.
01a,10jan05,dtr adapted from m85xxIntrCtl.
*/
#ifndef __INCquiccIntrCtlh
#define __INCquiccIntrCtlh
#include "vxWorks.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
#ifdef IVEC_TO_INUM
# undef IVEC_TO_INUM
#endif /* IVEC_TO_INUM */
#ifdef INUM_TO_IVEC
# undef INUM_TO_IVEC
#endif /* INUM_TO_IVEC */
#define IVEC_TO_INUM(intVec) (quiccIvecToInum(intVec))
#define INUM_TO_IVEC(intNum) (quiccInumToIvec(intNum))
#ifdef PQ2PRO
#define INUM_UART1 9
#define INUM_UART2 10
#define INUM_SEC 11
#define INUM_I2C1 14
#define INUM_I2C2 15
#define INUM_SPI 16
#define INUM_IRQ1 17
#define INUM_IRQ2 18
#define INUM_IRQ3 19
#define INUM_IRQ4 20
#define INUM_IRQ5 21
#define INUM_IRQ6 22
#define INUM_IRQ7 23
#define INUM_TSEC1_TX 32
#define INUM_TSEC1_RX 33
#define INUM_TSEC1_ERR 34
#define INUM_TSEC2_TX 35
#define INUM_TSEC2_RX 36
#define INUM_TSEC2_ERR 37
#define INUM_USB2_DR 38
#define INUM_USB2_MPH 39
#define INUM_IRQ0 48
#define INUM_RTC_SEC 64
#define INUM_PIT 65
#define INUM_PCI1 66
#define INUM_PCI2 67
#define INUM_RTC_ALR 68
#define INUM_MU 69
#define INUM_SBA 70
#define INUM_DMA 71
#define INUM_GTM4 72
#define INUM_GTM8 73
#define INUM_GPIO1 74
#define INUM_GPIO2 75
#define INUM_DDR 76
#define INUM_LBC 77
#define INUM_GTM2 78
#define INUM_GTM6 79
#define INUM_PMC 80
#define INUM_GTM3 84
#define INUM_GTM7 85
#define INUM_GTM1 90
#define INUM_GTM5 91
#define INUM_MAX 128
#define IVEC_MAX 128
#endif
#ifdef PQ2PRO_QE
#define INUM_UART1 9
#define INUM_UART2 10
#define INUM_SEC 11
#define INUM_I2C1 14
#define INUM_I2C2 15
#define INUM_IRQ1 17
#define INUM_IRQ2 18
#define INUM_IRQ3 19
#define INUM_IRQ4 20
#define INUM_IRQ5 21
#define INUM_IRQ6 22
#define INUM_IRQ7 23
#define INUM_QE_HIGH 32
#define INUM_QE_LOW 33
#define INUM_IRQ0 48
#define INUM_RTC_SEC 64 /* ??? */
#define INUM_PIT 65 /* ??? */
#define INUM_PCI1 66
#define INUM_RTC_ALR 68
#define INUM_MU 69
#define INUM_SBA 70
#define INUM_DMA 71
#define INUM_GTM4 72
#define INUM_GTM8 73
#define INUM_QE_PORTS 74
#define INUM_SDDR 75
#define INUM_DDR 76
#define INUM_LBC 77
#define INUM_GTM2 78
#define INUM_GTM6 79
#define INUM_PMC 80
#define INUM_GTM3 84
#define INUM_GTM7 85
#define INUM_GTM1 90
#define INUM_GTM5 91
#define INUM_MAX 128
#define IVEC_MAX 128
#endif
/* Interrupt Controller Registers */
#define QUICC_SICR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x000))
#define QUICC_SIVEC(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x004))
#define QUICC_SIPNR_H(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x008))
#define QUICC_SIPNR_L(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x00C))
#define QUICC_SIPRR_A(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x010))
#define QUICC_SIPRR_D(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x01C))
#define QUICC_SIMR_H(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x020))
#define QUICC_SIMR_L(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x024))
#define QUICC_SICNR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x028))
#define QUICC_SEPNR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x02C))
#define QUICC_SMPRR_A(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x030))
#define QUICC_SMPRR_B(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x034))
#define QUICC_SEMSR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x038))
#define QUICC_SECNR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x03C))
#define QUICC_SERSR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x040))
#define QUICC_SERMR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x044))
#define QUICC_SERCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x048))
#define QUICC_SIFCR_H(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x050))
#define QUICC_SIFCR_L(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x054))
#define QUICC_SEFCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x058))
#define QUICC_SERFR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x05C))
#define QUICC_SCVCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x060))
#define QUICC_SMVCR(base) ((VINT32 *) ((base) + SIC_REG_BA + 0x064))
/* interrupt handler */
#ifndef _ASMLANGUAGE
typedef struct intr_handler
{
VOIDFUNCPTR vec; /* interrupt vector */
int arg; /* interrupt handler argument */
void *pNext;
} INTR_HANDLER;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT STATUS quiccIntrInit ();
extern STATUS quiccIntDisable (int );
IMPORT STATUS quiccIntEnable (int );
extern int quiccIvecToInum(VOIDFUNCPTR *);
extern VOIDFUNCPTR * quiccInumToIvec(int);
#else
IMPORT STATUS quiccIntrInit ();
extern STATUS quiccIntDisable ();
IMPORT STATUS quiccIntEnable ();
extern int quiccIvecToInum();
extern VOIDFUNCPTR * quiccInumToIvec();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCquiccIntrCtlh */