original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,653 @@
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/* amd8111LanEnd.h - END style AMD 8111 LAN PCI Ethernet driver header */
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/*
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* Copyright (c) 1998-2005, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,01sep05,gtf modified for AMD8111 LAN END driver.
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01a,07dec98,snk added support 7997x[012] across architectures.
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written from 01b of lnPciEnd.h
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*/
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#ifndef __INCamd8111LanEndh
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#define __INCamd8111LanEndh
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#ifndef _ASMLANGUAGE
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#include <end.h>
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#include <cacheLib.h>
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#include <netinet/if_ether.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* board level/bus specific and architecture specific macros */
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#if (CPU_FAMILY == PPC)
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#ifndef AMD_LONG_WR
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#define AMD_LONG_WR(addr, value) (sysOutLong ((ULONG) addr, (ULONG) value))
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#endif
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#ifndef AMD_WORD_WR
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#define AMD_WORD_WR(addr, value) (sysOutWord ((ULONG) addr, (USHORT) value))
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#endif
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#ifndef AMD_BYTE_WR
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#define AMD_BYTE_WR(addr, value) (sysOutByte ((ULONG) addr, (UCHAR) value))
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#endif
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#ifndef AMD_LONG_RD
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#define AMD_LONG_RD(addr, value) (value = sysInLong ((ULONG) addr))
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#endif
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#ifndef AMD_WORD_RD
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#define AMD_WORD_RD(addr, value) (value = sysInWord ((ULONG) addr))
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#endif
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#ifndef AMD_BYTE_RD
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#define AMD_BYTE_RD(addr, value) (value = sysInByte ((ULONG) addr))
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#endif
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#endif /* CPU_FAMILY == PPC */
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#ifndef AMD_LONG_WR
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#define AMD_LONG_WR(addr, value) \
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(* (volatile UINT32 *) (addr) = ((UINT32) AMD_SWAP_LONG (value) ))
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#endif /* FEI_LONG_WR */
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#ifndef AMD_WORD_WR
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#define AMD_WORD_WR(addr, value) \
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(* (volatile UINT16 *) (addr) = ((UINT16) AMD_SWAP_WORD (value) ))
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#endif /* FEI_WORD_WR */
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#ifndef AMD_BYTE_WR
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#define AMD_BYTE_WR(addr, value) \
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(* (volatile UINT8 *) (addr) = (UINT8) (value) )
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#endif /* FEI_BYTE_WR */
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#ifndef AMD_LONG_RD
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#define AMD_LONG_RD(addr, value) \
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do { \
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UINT32 _temp_ = *(volatile UINT32 *)(addr); \
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(value) = (UINT32) AMD_SWAP_LONG (_temp_); \
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} while (0)
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#endif /* FEI_LONG_RD */
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#ifndef AMD_WORD_RD
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#define AMD_WORD_RD(addr, value) \
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do { \
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UINT16 _temp_ = *(volatile UINT16 *)(addr); \
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(value) = (UINT16) AMD_SWAP_WORD (_temp_); \
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} while (0)
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#endif /* FEI_WORD_RD */
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#ifndef AMD_BYTE_RD
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#define AMD_BYTE_RD(addr, value) \
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do { \
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(value) = (UINT8) (*(volatile UINT8 *)(addr)); \
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} while (0)
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#endif /* FEI_BYTE_RD */
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#if _BYTE_ORDER==_BIG_ENDIAN
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# define PCI_SWAP(x) ((amd8111LanBusEndianess) ? (int)(x) : LONGSWAP((int)(x)))
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#else
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# define PCI_SWAP(x) (x)
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#endif
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/* 32-bits */
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#define CHIPID (0x004)
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#define AUTO_POLL_VAL (0x098)
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/* 16-bites */
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#define AP0 (0x088)
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#define AP0_PHY0_ADDR_MASK 0x001f
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#define AP1 (0x08a)
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#define AP1_REG1_EN 0x8000
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#define AP1_REG1_ADDR_MASK 0x1f00
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#define AP1_PRE_SUP1 0x0040
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#define AP1_PHY1_DFLT 0x0020
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#define AP1_PHY1_ADDR_MASK 0x001f
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#define AP2 (0x08c)
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#define AP3 (0x08e)
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#define AP4 (0x090)
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#define AP5 (0x092)
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/* 32-bits */
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#define BADR (0x120)
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#define BADX0 (0x100)
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#define BADX1 (0x108)
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#define BADX2 (0x110)
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#define BADX3 (0x118)
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#define CMD0 (0x048)
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#define CMD0_RDMD0 0x00010000
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#define CMD0_TDMD3 0x00000800
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#define CMD0_TDMD2 0x00000400
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#define CMD0_TDMD1 0x00000200
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#define CMD0_TDMD0 0x00000100
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#define CMD0_UINTCMD 0x00000040
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#define CMD0_RX_FAST_SPND 0x00000020
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#define CMD0_TX_FAST_SPND 0x00000010
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#define CMD0_RX_SPND 0x00000008
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#define CMD0_TX_SPND 0x00000004
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#define CMD0_INTREN 0x00000002
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#define CMD0_RUN 0x00000001
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#define CMD2 (0x050)
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#define CMD2_CONDUIT_MODE 0x20000000
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#define CMD2_RPA 0x00100000
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#define CMD2_DRCVPA 0x00080000
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#define CMD2_DRCVBC 0x00040000
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#define CMD2_PROM 0x00020000
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#define CMD2_ASTRIP_RCV 0x00002000
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#define CMD2_RCV_DROP0 0x00001000
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#define CMD2_EMBA 0x00000800
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#define CMD2_DXMT2PD 0x00000400
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#define CMD2_LTINTEN 0x00000200
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#define CMD2_DXMTFCS 0x00000100
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#define CMD2_APAD_XMT 0x00000040
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#define CMD2_DRTY 0x00000020
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#define CMD2_INLOOP 0x00000010
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#define CMD2_EXLOOP 0x00000008
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#define CMD2_REXUFLO 0x00000002
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#define CMD3 (0x054)
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#define CMD3_JUMBO 0x00400000
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#define CMD3_VSIZE 0x00200000
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#define CMD3_VLONLY 0x00100000
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#define CMD3_VL_TAG_DEL 0x00080000
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#define CMD3_EN_PMGR 0x00004000
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#define CMD3_FORCE_FULL_DUPLEX 0x00001000
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#define CMD3_FORCE_LINK_STATUS 0x00000800
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#define CMD3_APEP 0x00000400
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#define CMD3_MPPLBA 0x00000200
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#define CMD3_BKPRS_EN 0x00000100
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#define CMD3_RESET_PHY_PULSE 0x00000004
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#define CMD3_RESET_PHY 0x00000002
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#define CMD3_PHY_RST_POL 0x00000001
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#define CMD7 (0x064)
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#define CMD7_PMAT_SAVE_MATCH 0x00000010
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#define CMD7_PMAT_MODE 0x00000008
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#define CMD7_MPEN_SW 0x00000002
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#define CMD7_LCMODE_SW 0x00000001
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#define CTRL1 (0x06c)
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#define CTRL1_RESET_PHY_WIDTH_MASK 0x001f0000
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#define CTRL1_XMTSP_MASK 0x00000300
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#define CTRL1_CACHE_ALIGN 0x00000010
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#define CTRL1_BURST_LIMIT_MASK 0x0000000f
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#define CTRL2 (0x070)
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#define CTRL2_FMDC_MASK 0x00000300
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#define CTRL2_XPHYRST 0x00000080
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#define CTRL2_XPHYANE 0x00000040
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#define CTRL2_XPHYFD 0x00000020
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#define CTRL2_XPHYSP_MASK 0x00000018
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#define CTRL2_APDW_MASK 0x00000007
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#define DLY_INT_A (0x0a8)
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#define DLY_INT_B (0x0ac)
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#define FLOW (0x0c8)
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/* 8-bits */
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#define IPG (0x18d)
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#define IFS1 (0x18c)
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/* 32-bits */
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#define INT0 (0x038)
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#define INT0_INTR 0x80000000
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#define INT0_INTPN 0x40000000
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#define INT0_LCINT 0x08000000
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#define INT0_APINT5 0x04000000
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#define INT0_APINT4 0x02000000
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#define INT0_APINT3 0x01000000
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#define INT0_APINT2 0x00800000
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#define INT0_APINT1 0x00400000
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#define INT0_APINT0 0x00200000
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#define INT0_MIIPDINT 0x00100000
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#define INT0_MCCINT 0x00020000
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#define INT0_MREINT 0x00010000
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#define INT0_SPNDINT 0x00004000
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#define INT0_MPINT 0x00002000
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#define INT0_TINT3 0x00000800
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#define INT0_TINT2 0x00000400
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#define INT0_TINT1 0x00000200
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#define INT0_TINT0 0x00000100
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#define INT0_UINT 0x00000080
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#define INT0_STINT 0x00000010
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#define INT0_RINT0 0x00000001
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#define INTEN0 (0x040)
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#define INTEN0_LCINTEN 0x08000000
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#define INTEN0_APINT5EN 0x04000000
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#define INTEN0_APINT4EN 0x02000000
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#define INTEN0_APINT3EN 0x01000000
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#define INTEN0_APINT2EN 0x00400000
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#define INTEN0_APINT1EN 0x00200000
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#define INTEN0_APINT0EN 0x00100000
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#define INTEN0_MIIPDINTEN 0x00080000
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#define INTEN0_MCCINTEN 0x00020000
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#define INTEN0_MREINTEN 0x00010000
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#define INTEN0_SPNDINTEN 0x00004000
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#define INTEN0_MPNINTEN 0x00002000
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#define INTEN0_TINTEN3 0x00000800
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#define INTEN0_TINTEN2 0x00000400
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#define INTEN0_TINTEN1 0x00000200
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#define INTEN0_TINTEN0 0x00000100
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#define INTEN0_STINTEN 0x00000010
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#define INTEN0_RINTEN0 0x00000001
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/* 64-bits */
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#define LADRF_L (0x168)
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#define LADRF_H (0x16c)
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/* 16-bits */
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#define MIB_ADRS (0x014)
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#define MIB_CMD_ACTIVE 0x8000
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#define MIB_RD_CMD 0x2000
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#define MIB_CLEAR 0x1000
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#define MIB_ADDRESS_MASK 0x001f
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/* 32-bits */
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#define MIB_DATA (0x010)
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/* 48-bits */
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#define MAC_ADRS (0x160)
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/* 32-bits */
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#define PHY_ACCESS (0x0d0)
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/* 32-bits */
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#define ON_NOW_PTRN0 (0x190)
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#define ON_NOW_PTRN1 (0x194)
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/* 16-bits */
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#define RCV_RING_LEN (0x150)
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/* 16-bits */
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#define SRAM_BND (0x17a)
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#define SRAM_BND_DEFAULT 0x08
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#define SRAM_SIZE (0x178)
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#define SRAM_SIZE_DEFAULT 0x10
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/* 32-bits */
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#define STAT0 (0x030)
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#define STAT0_PMAT_DET 0x00010000
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#define STAT0_MP_DET 0x00008000
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#define STAT0_LC_DET 0x00004000
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#define STAT0_SPEED_MASK 0x00000380
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#define STAT0_FULL_DUPLEX 0x00000040
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#define STAT0_LINK_STATUS 0x00000020
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#define STAT0_AUTONEG_COMPLETE 0x00000010
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#define STAT0_MIIPD 0x00000008
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#define STAT0_RX_SUSPENDED 0x00000004
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#define STAT0_TX_SUSPENDED 0x00000002
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#define STAT0_RUNNING 0x00000001
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/* 16-bits */
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#define STVAL (0x0d8)
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/* 16-bits */
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#define XMT_RING0_LEN (0x140)
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#define XMT_RING1_LEN (0x144)
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#define XMT_RING2_LEN (0x148)
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#define XMT_RING3_LEN (0x14c)
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/* 32-bits */
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#define XMT_RING_LIMIT (0x07c)
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/* Bit Fields */
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typedef struct rxDesc
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{
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UINT32 RD[4] ;
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} AMD_RD ;
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typedef struct txDesc
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{
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UINT32 TD[4] ;
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} AMD_TD ;
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#define RD_USER_SPACE 0
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#define RD_WORD1 1
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#define RD_MCNT 1
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#define RD_WORD2 2
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#define RD_BCNT 2
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#define RD_FLAGS 2
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#define RD_RBADR 3
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/* Word 0x8 */
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#define RD_OWN 0x80000000
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#define RD_ERR 0x40000000
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#define RD_FRAM 0x20000000
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#define RD_OFLO 0x10000000
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#define RD_CRC 0x08000000
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#define RD_BUFF 0x04000000
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#define RD_STP 0x02000000
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#define RD_ENP 0x01000000
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#define RD_PAM 0x00400000
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#define RD_LAFM 0x00200000
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#define RD_BAM 0x00100000
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#define RD_TT_MASK 0x000c0000
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#define RD_BCNT_MASK 0x0000ffff
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|
||||
#define TD_WORD0 0
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#define TD_BCNT 0
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#define TD_FLAGS 0
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#define TD_WORD1 1
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#define TD_TCC 1
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#define TD_TCI 1
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#define TD_TBADR 2
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#define TD_USER_SPACE 3
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||||
|
||||
/* Word 0x0 */
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||||
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||||
#define TD_OWN 0x80000000
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#define TD_ADD_FCS 0x20000000
|
||||
#define TD_LTINT 0x10000000
|
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#define TD_PRI_LOCK 0x04000000
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||||
#define TD_STP 0x02000000
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||||
#define TD_ENP 0x01000000
|
||||
#define TD_KILL 0x00400000
|
||||
#define TD_BCNT_MASK 0x0000ffff
|
||||
|
||||
/* Word 0x4 */
|
||||
|
||||
#define TD_TCC_MASK 0x00030000
|
||||
#define TD_TCI_MASK 0x0000ffff
|
||||
|
||||
/* Control block definitions for AMD PCnet (Ethernet) chip. */
|
||||
|
||||
typedef union addrFilter /* logical address filter layout */
|
||||
{
|
||||
UINT8 lafBytes [8]; /* (8) bytes */
|
||||
UINT16 lafWords [4]; /* (4) 16-bit words */
|
||||
UINT32 lafDwords [2]; /* (2) 32-bit dwords */
|
||||
} ADDR_FILTER;
|
||||
|
||||
typedef enum filterModCmd /* addrFilterMod() commands */
|
||||
{
|
||||
AMD_LADRF_ADD, /* add a logical address */
|
||||
AMD_LADRF_DEL, /* delete a logical address */
|
||||
AMD_LADRF_ADD_ALL, /* add all logical addresses */
|
||||
AMD_LADRF_DEL_ALL /* delete all logical addresses */
|
||||
} FILTER_MOD_CMD;
|
||||
|
||||
/* CRC for logical address filter */
|
||||
|
||||
#define AMD_CRC_POLYNOMIAL (0xedb88320) /* Ethernet CRC polynomial */
|
||||
#define AMD_CRC_TO_LAF_IX(crc) ((crc) >> 26) /* get 6 MSBits */
|
||||
#define AMD_LAF_LEN (8) /* logical addr filter length */
|
||||
#define AMD_LA_LEN (6) /* logical address length */
|
||||
#define BITS_PER_LA (8 * AMD_LA_LEN) /* logical addr length bits */
|
||||
|
||||
|
||||
/* Definitions for the drvCtrl specific flags field */
|
||||
|
||||
#define LS_PROMISCUOUS_FLAG 0x1 /* set the promiscuous mode */
|
||||
#define LS_MEM_ALLOC_FLAG 0x2 /* allocating memory flag */
|
||||
#define LS_PAD_USED_FLAG 0x4 /* padding used flag */
|
||||
#define LS_RCV_HANDLING_FLAG 0x8 /* handling recv packet */
|
||||
#define LS_START_OUTPUT_FLAG 0x10 /* trigger output flag */
|
||||
#define LS_POLLING 0x20 /* polling flag */
|
||||
#define LS_MODE_MEM_IO_MAP 0x100 /* device registers memory mapped */
|
||||
#define LS_MODE_DWIO 0x200 /* device in 32 bit mode */
|
||||
#define LS_MODE_NOSWAP_MASTER 0x400 /* don't swap PCI master I/O ops */
|
||||
|
||||
/* descriptor size */
|
||||
|
||||
#define RD_SIZ sizeof(AMD_RD)
|
||||
#define TD_SIZ sizeof(AMD_TD)
|
||||
|
||||
/* How much work we're allowed to do in the RX handler (# of pkts processed) */
|
||||
|
||||
#define AMD_RX_LIMIT 32
|
||||
|
||||
/* How many descriptors we want to use up in a single gather-write transmit */
|
||||
|
||||
#define AMD_MAX_FRAGS 32
|
||||
|
||||
|
||||
/* */
|
||||
|
||||
typedef struct amd8111LanBoardInfoType
|
||||
{
|
||||
UINT32 vector; /* interrupt vector number */
|
||||
UINT32 baseAddr; /* memory base address for CSR */
|
||||
UINT32 pciMemAddr ; /* PCI memory base address from CPU */
|
||||
UCHAR enetAddr[6]; /* ethernet address */
|
||||
int (*intEnable)(int unit); /* board specific interrupt enable routine */
|
||||
int (*intDisable)(int unit); /* board specific interrupt disable routine */
|
||||
int (*intAck) (int unit); /* interrupt ack */
|
||||
STATUS (*intConnect) (VOIDFUNCPTR * vector, VOIDFUNCPTR routine, int parameter);
|
||||
STATUS (*intDisconnect) (VOIDFUNCPTR * vector, VOIDFUNCPTR routine, int parameter);
|
||||
UINT32 (*sysLocalToBus)(int unit,UINT32 localAdr);
|
||||
UINT32 (*sysBusToLocal)(int unit,UINT32 sysAdr);
|
||||
|
||||
/* configuration parameters, user can override in the BSP */
|
||||
UINT8 phyAddr; /* PHY device address, valid addresses: 0-32 */
|
||||
UINT8 phySpeed;
|
||||
UINT8 phyDpx;
|
||||
UINT8 fill0;
|
||||
} AMD8111_LAN_BOARD_INFO ;
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct amd8111LanDevice
|
||||
{
|
||||
END_OBJ endObj; /* The class we inherit from */
|
||||
|
||||
int unit; /* unit number of the device */
|
||||
|
||||
int rdNum ; /* total number of RDs */
|
||||
int rdIndex; /* current RD send index */
|
||||
int rringSize; /* RD ring size */
|
||||
int rringLen; /* RD ring length (bytes) */
|
||||
volatile AMD_RD * pRring; /* RD ring start */
|
||||
|
||||
int tdNum ; /* total number of TDs */
|
||||
int tdIndex; /* current TD transmit index */
|
||||
int tdIndexC; /* current TD cleaning index */
|
||||
int tringSize; /* TD ring size */
|
||||
int tringLen; /* TD ring length (bytes) */
|
||||
volatile AMD_TD * pTring; /* TD ring start */
|
||||
|
||||
int inum; /* interrupt number */
|
||||
int ilevel; /* interrupt level */
|
||||
|
||||
volatile char * pShMem; /* real ptr to shared memory */
|
||||
volatile char * pShMemEnd; /* real ptr to shared memory end */
|
||||
volatile char * memBase; /* PCnet memory pool base */
|
||||
volatile char * memAdrs; /* PCnet memory pool base */
|
||||
|
||||
UINT32 shMemPtoVOffset; /* bias to convert pShMem P->V */
|
||||
|
||||
UINT32 devAdrs; /* device structure address */
|
||||
|
||||
UINT32 chipId; /* (csr88|csr89) chip ID value */
|
||||
int memSize; /* PCnet memory pool size */
|
||||
int memWidth; /* width of data port */
|
||||
int offset; /* offset of data in the buffer */
|
||||
volatile UINT32 flags; /* Our local flags */
|
||||
UINT32 pciMemBase; /* memory base as seen from PCI*/
|
||||
UINT8 enetAddr[6]; /* ethernet address */
|
||||
CACHE_FUNCS cacheFuncs; /* cache function pointers */
|
||||
|
||||
volatile BOOL txBlocked; /* transmit flow control */
|
||||
volatile BOOL txCleaning; /* transmit descriptor cleaning */
|
||||
|
||||
CL_POOL_ID pClPoolId; /* cluster pool Id */
|
||||
M_CL_CONFIG mClCfg; /* mBlk & cluster config structure */
|
||||
CL_DESC clDesc; /* cluster descriptor table */
|
||||
|
||||
END_ERR lastError; /* Last error passed to muxError */
|
||||
volatile BOOL errorHandling; /* task level error handling */
|
||||
|
||||
M_BLK_ID * mBlks; /* saved mBlk pointers */
|
||||
|
||||
AMD8111_LAN_BOARD_INFO board ;
|
||||
|
||||
/* Hold current values of these registers */
|
||||
|
||||
UINT32 cmd0 ;
|
||||
UINT32 cmd2 ;
|
||||
UINT32 cmd3 ;
|
||||
UINT32 cmd7 ;
|
||||
UINT32 inten0 ;
|
||||
|
||||
} AMD8111_LAN_DRV_CTRL;
|
||||
|
||||
/*
|
||||
* MIB statistics. The variable positions correspond the the index position
|
||||
* required to access the given value. For example, rxvMissPkts is index 0,
|
||||
* rcvOctets is index 1 and so on.
|
||||
*/
|
||||
|
||||
typedef struct amd8111LanStatCounterType {
|
||||
UINT32 rcvMissPkts ; /* 0x0 */
|
||||
UINT32 rcvOctets ;
|
||||
UINT32 rcvBroadCastPkts ;
|
||||
UINT32 rcvMultiCastPkts ;
|
||||
UINT32 rcvUndersizePkts ;
|
||||
UINT32 rcvOversizePkts ;
|
||||
UINT32 rcvFragments ;
|
||||
UINT32 rcvJabbers ;
|
||||
UINT32 rcvUnicastPkts ;
|
||||
UINT32 rcvAlignmentErrors ;
|
||||
UINT32 rcvFCSErrors ;
|
||||
UINT32 rcvGoodOctets ;
|
||||
UINT32 rcvMACCtrl ;
|
||||
UINT32 rcvFlowCtrl ;
|
||||
UINT32 rcvPkts64Octets ;
|
||||
UINT32 rcvPkts65to127Octets ;
|
||||
UINT32 rcvPkts128to255ctets ; /* 0x10 */
|
||||
UINT32 rcvPkts256to511ctets ;
|
||||
UINT32 rcvPkts512to1023ctets ;
|
||||
UINT32 rcvPkts1024to1518ctets ;
|
||||
UINT32 rcvUnsupportedOpcode ;
|
||||
UINT32 rcvSymbolErrors ;
|
||||
UINT32 rcvDropPktsRing0 ;
|
||||
UINT32 reserved0[3] ;
|
||||
UINT32 rcvJumboPkts ;
|
||||
UINT32 reserved1[5] ;
|
||||
UINT32 xmtUnderrunPkts ; /* 0x20 */
|
||||
UINT32 xmtOctets ;
|
||||
UINT32 xmtPackets ;
|
||||
UINT32 xmtBroadCastPkts ;
|
||||
UINT32 xmtMultiCastPkts ;
|
||||
UINT32 xmtCollisions ;
|
||||
UINT32 xmtUnicastPkts ;
|
||||
UINT32 xmtOneCollision ;
|
||||
UINT32 xmtMultipleCollision ;
|
||||
UINT32 xmtDeferredTransmit ;
|
||||
UINT32 xmtLateCollision ;
|
||||
UINT32 xmtExcessiveDefer ;
|
||||
UINT32 xmtLossCarrier ;
|
||||
UINT32 xmtExcessiveCollision ;
|
||||
UINT32 xmtBackPressure ;
|
||||
UINT32 xmtFlowCtrl ;
|
||||
UINT32 xmtPkts64Octets ; /* 0x30 */
|
||||
UINT32 xmtPkts65to127Octets ;
|
||||
UINT32 xmtPkts128to255Octets ;
|
||||
UINT32 xmtPkts256to511Octets ;
|
||||
UINT32 xmtPkts512to1023Octets ;
|
||||
UINT32 xmtPkts1024to1518Octets ;
|
||||
UINT32 xmtOversizePkts ;
|
||||
UINT32 xmtJumboPkts ; /* 0x37 */
|
||||
|
||||
} AMD8111_LAN_STAT_COUNTER ;
|
||||
|
||||
/* Configuration items */
|
||||
|
||||
#define AMD_MIN_FBUF (100) /* Min sizeof first buffer in chain */
|
||||
|
||||
#define AMD_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + 6)
|
||||
|
||||
#define AMD_SPEED (10000000)
|
||||
|
||||
#define AMD_RD_RLEN (7) /* ring size as a ^ 2 => 128 RD's */
|
||||
#define AMD_TD_TLEN (7) /* ring size as a ^ 2 => 128 TD's */
|
||||
|
||||
#define AMD_RD_MIN (2) /* min descriptors 4 */
|
||||
#define AMD_TD_MIN (2) /* min descriptors 4 */
|
||||
|
||||
#define AMD_RD_MAX (9) /* max descriptors 512 */
|
||||
#define AMD_TD_MAX (9) /* max descriptors 512 */
|
||||
|
||||
#define AMD8111_LAN_DEV_NAME "amdPci" /* name of the device */
|
||||
#define AMD8111_LAN_DEV_NAME_LEN (7) /* length of the name string */
|
||||
#define AMD8111_LAN_APROM_SIZE (32) /* hardware Address PROM size bytes */
|
||||
|
||||
#define AMD_LITTLE_ENDIAN (0) /* little endian PCI bus */
|
||||
#define AMD_BIG_ENDIAN (1) /* big endian PCI bus */
|
||||
#define AMD_ACTIVE_LOW (0) /* active-low interrupt line */
|
||||
#define AMD_ACTIVE_HI (1) /* active-high interrupt line */
|
||||
|
||||
#define AMD_RD_OWNED(rd) ( PCI_SWAP ((rd)->RD [RD_FLAGS]) & RD_OWN )
|
||||
#define AMD_TD_OWNED(td) ( PCI_SWAP ((td)->TD [TD_FLAGS]) & TD_OWN )
|
||||
|
||||
#define AMD_PKT_LEN_GET(rd) ( PCI_SWAP ((rd)->RD [RD_MCNT]) & RD_BCNT_MASK )
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
IMPORT STATUS amd8111LanInitParse (AMD8111_LAN_DRV_CTRL * pDrvCtrl, char * initString);
|
||||
IMPORT END_OBJ * amd8111LanEndLoad (char * initString);
|
||||
|
||||
#else
|
||||
|
||||
IMPORT STATUS amd8111LanInitParse ();
|
||||
IMPORT END_OBJ * amd8111LanEndLoad ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCamd8111LanEndh */
|
||||
@@ -0,0 +1,311 @@
|
||||
/* auEnd.h - END based MAC Ethernet header */
|
||||
|
||||
/* Copyright 1998-2001, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
* This file has been developed or significantly modified by the
|
||||
* MIPS Center of Excellence Dedicated Engineering Staff.
|
||||
* This notice is as per the MIPS Center of Excellence Master Partner
|
||||
* Agreement, do not remove this notice without checking first with
|
||||
* WR/Platforms MIPS Center of Excellence engineering management.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,29apr10,pad Moved extern C statement after include statements.
|
||||
01h,03jun02,zmm Fix AU_DEV_NAME_LEN, SPR 78215.
|
||||
01g,14may02,zmm Global au1000 name changes. SPR 77333.
|
||||
01f,06may02,zmm Fix SPR 76824.
|
||||
01e,15nov01,zmm Supported auto-negotiation and cache coherent mode.
|
||||
Add base addresses of the Ethernet registers. SPR 71884.
|
||||
01d,11oct01,tlc Change register names according to new revision of Au1000
|
||||
Databook. General cleanup.
|
||||
01c,21sep01,agf add ring size warning;
|
||||
change MAC_ENABLE to use enableAdrs field
|
||||
01b,19jun01,zmm Put volatile in the MAC macros.
|
||||
01a,17may01,mem written.
|
||||
*/
|
||||
|
||||
#ifndef __INCauEndh
|
||||
#define __INCauEndh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include "end.h"
|
||||
#include "cacheLib.h"
|
||||
#include "netinet/if_ether.h"
|
||||
#include "miiLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* board level/bus specific and architecture specific macros */
|
||||
|
||||
#if _BYTE_ORDER==_BIG_ENDIAN
|
||||
# define PCI_SWAP(x) LONGSWAP((int)(x))
|
||||
#else
|
||||
# define PCI_SWAP(x) (x)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* WARNING --
|
||||
* logic in the source code depends on the following being a power of 2
|
||||
*/
|
||||
#define AU_N_TX_BUF 4 /* # of transmit buffers */
|
||||
#define AU_N_RX_BUF 4 /* # of receive buffers */
|
||||
|
||||
/* Device IO or memory mapped access and data registers */
|
||||
|
||||
#define AU_MAC_REG(reg) \
|
||||
(*(volatile UINT32 *)((UINT32)(pDrvCtrl->devAdrs)+(reg)))
|
||||
|
||||
#define AU_DMA_REG(reg) \
|
||||
(*(volatile UINT32 *)((UINT32)(pDrvCtrl->dmaAdrs)+(reg)))
|
||||
|
||||
#define AU_MAC_ENABLE \
|
||||
(*(volatile UINT32 *)((UINT32)(pDrvCtrl->enableAdrs)))
|
||||
|
||||
#define AU_MAC_CONTROL AU_MAC_REG(0x00)
|
||||
#define AU_MAC_ADDRESS_HIGH AU_MAC_REG(0x04)
|
||||
#define AU_MAC_ADDRESS_LOW AU_MAC_REG(0x08)
|
||||
#define AU_MULTICAST_HASH_ADDRESS_HIGH AU_MAC_REG(0x0c)
|
||||
#define AU_MULTICAST_HASH_ADDRESS_LOW AU_MAC_REG(0x10)
|
||||
#define AU_MII_CONTROL AU_MAC_REG(0x14)
|
||||
#define AU_MII_DATA AU_MAC_REG(0x18)
|
||||
#define AU_FLOW_CONTROL AU_MAC_REG(0x1c)
|
||||
#define AU_VLAN1_TAG AU_MAC_REG(0x20)
|
||||
#define AU_VLAN2_TAG AU_MAC_REG(0x24)
|
||||
|
||||
/* AU Dedicated MAC DMA registers */
|
||||
|
||||
#define AU_TX_STATUS(idx) AU_DMA_REG(0x00 + 0x10*(idx))
|
||||
#define AU_TX_ADDRESS(idx) AU_DMA_REG(0x04 + 0x10*(idx))
|
||||
#define AU_TX_LENGTH(idx) AU_DMA_REG(0x08 + 0x10*(idx))
|
||||
|
||||
#define AU_RX_STATUS(idx) AU_DMA_REG(0x0100 + 0x10*(idx))
|
||||
#define AU_RX_ADDRESS(idx) AU_DMA_REG(0x0104 + 0x10*(idx))
|
||||
|
||||
/* MAC Control bits */
|
||||
|
||||
#define AU_MAC_CONTROL_RA (1 << 31) /* receive all */
|
||||
#define AU_MAC_CONTROL_EM_BIG (1 << 30) /* big endian */
|
||||
#define AU_MAC_CONTROL_DO (1 << 23) /* disable receive own */
|
||||
#define AU_MAC_CONTROL_F (1 << 20) /* full duplex */
|
||||
#define AU_MAC_CONTROL_PM (1 << 19) /* pass multicast */
|
||||
#define AU_MAC_CONTROL_PR (1 << 18) /* promiscuous mode */
|
||||
#define AU_MAC_CONTROL_IF (1 << 17) /* inverse filtering */
|
||||
#define AU_MAC_CONTROL_PB (1 << 16) /* pass bad frames */
|
||||
#define AU_MAC_CONTROL_HO (1 << 15) /* hash-only filter */
|
||||
#define AU_MAC_CONTROL_HP (1 << 13) /* hash/perfect */
|
||||
#define AU_MAC_CONTROL_LC (1 << 12) /* late collision */
|
||||
#define AU_MAC_CONTROL_DB (1 << 11) /* disable broadcast */
|
||||
#define AU_MAC_CONTROL_DR (1 << 10) /* disable retry */
|
||||
#define AU_MAC_CONTROL_AP (1 << 8) /* auto pad strip */
|
||||
#define AU_MAC_CONTROL_BL(n) (((n)&3) << 6) /* backoff limit */
|
||||
#define AU_MAC_CONTROL_DC (1 << 5) /* deferral clock */
|
||||
#define AU_MAC_CONTROL_TE (1 << 3) /* Tx enable */
|
||||
#define AU_MAC_CONTROL_RE (1 << 2) /* Rx enable */
|
||||
#define AU_MAC_CONTROL_LB_NORMAL (0) /* normal mode */
|
||||
|
||||
/* MAC Enable bits */
|
||||
|
||||
#define AU_MAC_ENABLE_JP (1 << 6) /* Jumbo Packet Enable */
|
||||
#define AU_MAC_ENABLE_E2 (1 << 5) /* Enable 2 */
|
||||
#define AU_MAC_ENABLE_E1 (1 << 4) /* Enable 1 */
|
||||
#define AU_MAC_ENABLE_C (1 << 3) /* Non-Cacheable */
|
||||
#define AU_MAC_ENABLE_TS (1 << 2) /* Toss */
|
||||
#define AU_MAC_ENABLE_E0 (1 << 1) /* Enable 0 */
|
||||
#define AU_MAC_ENABLE_CE (1 << 0) /* Clocks Enable */
|
||||
|
||||
#define AU_MAC_ENABLE_RESET_ALL 0x00 /* Reset all */
|
||||
#define AU_MAC_ENABLE_CLOCKS_ONLY 0x41 /* only clocks */
|
||||
#define AU_MAC_ENABLE_NORMAL 0x37 /* Normal operation */
|
||||
|
||||
/* CRC for logical address filter */
|
||||
|
||||
#define AU_CRC_POLYNOMIAL 0xedb88320 /* CRC polynomial */
|
||||
#define AU_CRC_TO_LAF_IX(crc) ((crc) >> 26) /* get 6 MSBits */
|
||||
#define AU_LAF_LEN 8 /* logical addr filter legth */
|
||||
#define AU_LA_LEN 6 /* logical address length */
|
||||
#define MAC_ADDRS_SIZE 6
|
||||
|
||||
/* MII Defines */
|
||||
|
||||
#define AU_MAX_PHY 1
|
||||
|
||||
/* MII Control bits */
|
||||
|
||||
#define AU_MII_CONTROL_READ 0 /* Read */
|
||||
#define AU_MII_CONTROL_WRITE (1 << 1) /* Write */
|
||||
#define AU_MII_CONTROL_BUSY (1 << 0) /* Busy */
|
||||
|
||||
#define MII_MGMT_WR_OFF 17
|
||||
#ifndef MII_WRITE
|
||||
# define MII_WRITE ((ULONG) 0x00002000)
|
||||
#endif
|
||||
#ifndef MII_READ
|
||||
# define MII_READ ((ULONG) 0x00044000)
|
||||
#endif
|
||||
|
||||
#define MII_MGMT_WR ((ULONG) 0x00020000)
|
||||
#define MII_MGMT_CLOCK ((ULONG) 0x00010000)
|
||||
#define MII_READ_FRM ((ULONG) 0x60000000)
|
||||
#define MII_WRITE_FRM ((ULONG) 0x50020000)
|
||||
#define MII_PHY_CTRL_RES ((USHORT) 0x007F)
|
||||
#define MII_PHY_STAT_RES ((USHORT) 0x07C0)
|
||||
#define MII_PHY_NWAY_RES ((USHORT) 0x1C00)
|
||||
#define MII_PHY_NWAY_EXP_RES ((USHORT) 0xFFE0)
|
||||
#define MII_MGMT_DATA_IN ((ULONG) 0x00080000)
|
||||
#define MII_READ_DATA_MSK MII_MGMT_DATA_IN
|
||||
|
||||
#define DEC_MAX_PHY 32 /* max number of PHY devices */
|
||||
#define DEC_MAX_LINK_TOUT 6 /* max link timeout (in secs) */
|
||||
|
||||
#define MII_PREAMBLE ((ULONG) 0xFFFFFFFF)
|
||||
#define MII_LINK_STATUS 0x4
|
||||
|
||||
/* MII frame header format */
|
||||
|
||||
#define MII_SOF 0x4 /* start of frame */
|
||||
#define MII_RD 0x2 /* op-code: Read */
|
||||
#define MII_WR 0x1 /* op-code: Write */
|
||||
|
||||
/* MII PHY registers */
|
||||
|
||||
#define MII_PHY_CR 0x00 /* Control Register */
|
||||
#define MII_PHY_SR 0x01 /* Status Register */
|
||||
#define MII_PHY_ID0 0x02 /* Identifier Register 0 */
|
||||
#define MII_PHY_ID1 0x03 /* Identifier Register 1 */
|
||||
#define MII_PHY_ANA 0x04 /* Auto Negot'n Advertisement */
|
||||
#define MII_PHY_ANLPA 0x05 /* Auto Negot'n Link Partner Ability */
|
||||
#define MII_PHY_ANE 0x06 /* Auto Negot'n Expansion */
|
||||
|
||||
/* MII PHY Auto Negotiation Advertisement Register */
|
||||
|
||||
#define MII_PHY_ANA_TAF 0x03e0 /* Technology Ability Field */
|
||||
#define MII_PHY_ANA_T4AM 0x0200 /* T4 Technology Ability Mask */
|
||||
#define MII_PHY_ANA_TXAM 0x0180 /* TX Technology Ability Mask */
|
||||
#define MII_PHY_ANA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */
|
||||
#define MII_PHY_ANA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */
|
||||
#define MII_PHY_ANA_100M 0x0380 /* 100Mb Technology Ability Mask */
|
||||
#define MII_PHY_ANA_10M 0x0060 /* 10Mb Technology Ability Mask */
|
||||
#define MII_PHY_ANA_CSMA 0x0001 /* CSMA-CD Capable */
|
||||
|
||||
/* MII PHY Auto Negotiation Remote End Register */
|
||||
|
||||
#define MII_PHY_ANLPA_NP 0x8000 /* Next Page (Enable) */
|
||||
#define MII_PHY_ANLPA_ACK 0x4000 /* Remote Acknowledge */
|
||||
#define MII_PHY_ANLPA_RF 0x2000 /* Remote Fault */
|
||||
#define MII_PHY_ANLPA_TAF 0x03e0 /* Technology Ability Field */
|
||||
#define MII_PHY_ANLPA_T4AM 0x0200 /* T4 Technology Ability Mask */
|
||||
#define MII_PHY_ANLPA_TXAM 0x0180 /* TX Technology Ability Mask */
|
||||
#define MII_PHY_ANLPA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */
|
||||
#define MII_PHY_ANLPA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */
|
||||
#define MII_PHY_ANLPA_100M 0x0380 /* 100Mb Technology Ability Mask */
|
||||
#define MII_PHY_ANLPA_10M 0x0060 /* 10Mb Technology Ability Mask */
|
||||
#define MII_PHY_ANLPA_CSMA 0x0001 /* CSMA-CD Capable */
|
||||
|
||||
/* Special MII flag bit definitions, not the user flag bits */
|
||||
|
||||
#define AU_USR_MII_BUS_MON 0x01000000 /* monitor the MII bus */
|
||||
#define AU_USR_MII_AN_TBL 0x04000000 /* use auto-negotiation table */
|
||||
#define AU_USR_MII_NO_AN 0x08000000 /* do not auto-negotiate */
|
||||
#define AU_USR_MII_FD 0x10000000 /* allow full duplex */
|
||||
#define AU_USR_MII_100MB 0x20000000 /* allow 100 MB */
|
||||
#define AU_USR_MII_HD 0x40000000 /* allow half duplex */
|
||||
#define AU_USR_MII_10MB 0x80000000 /* allow 10 MB */
|
||||
|
||||
/* Definitions for the drvCtrl specific flags field */
|
||||
|
||||
#define AU_PROMISCUOUS_FLAG 0x1 /* set the promiscuous mode */
|
||||
#define AU_MEM_ALLOC_FLAG 0x2 /* allocating memory flag */
|
||||
#define AU_PAD_USED_FLAG 0x4 /* padding used flag */
|
||||
#define AU_RCV_HANDLING_FLAG 0x8 /* handling recv packet */
|
||||
#define AU_START_OUTPUT_FLAG 0x10 /* trigger output flag */
|
||||
#define AU_POLLING 0x20 /* polling flag */
|
||||
#define AU_MODE_MEM_IO_MAP 0x100 /* device registers memory mapped */
|
||||
#define AU_MODE_DWIO 0x200 /* device in 32 bit mode */
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct auDevice
|
||||
{
|
||||
END_OBJ endObj; /* The class we inherit from */
|
||||
int unit; /* unit number of the device */
|
||||
UINT32 flags; /* Our local flags */
|
||||
UINT8 enetAddr[6]; /* ethernet address */
|
||||
|
||||
int ivec; /* interrupt vector */
|
||||
int ilevel; /* interrupt level */
|
||||
UINT32 devAdrs; /* device structure address */
|
||||
UINT32 dmaAdrs; /* DMA device address */
|
||||
UINT32 enableAdrs; /* MAC enable register address */
|
||||
|
||||
char * pRxMem[AU_N_RX_BUF]; /* Base of receive buffers */
|
||||
char * pTxMem[AU_N_TX_BUF]; /* Base of transmit buffers */
|
||||
|
||||
char * pRxMemBase; /* Base address of receive buffers */
|
||||
char * pTxMemBase; /* Base address of transmit buffers */
|
||||
|
||||
int offset; /* offset of data in the buffer */
|
||||
|
||||
int rmdIndex; /* current RMD index */
|
||||
int rringSize; /* RMD ring size */
|
||||
|
||||
int tmdIndex; /* current TMD index */
|
||||
int tmdLastIndex; /* last TMD index */
|
||||
int tringSize; /* TMD ring size */
|
||||
|
||||
PHY_INFO *pPhyInfo; /* info on a MII-compliant PHY */
|
||||
UINT32 miiPhyFlags; /* MII-compliant PHY flags */
|
||||
UINT8 phyAddr; /* MII-compliant PHY address */
|
||||
MII_AN_ORDER_TBL * pMiiPhyTbl; /* MII-compliant PHY's table */
|
||||
|
||||
CACHE_FUNCS cacheFuncs; /* cache function pointers */
|
||||
BOOL txBlocked; /* transmit flow control */
|
||||
BOOL txCleaning; /* transmit descriptor cleaning */
|
||||
CL_POOL_ID pClPoolId; /* cluster pool Id */
|
||||
M_CL_CONFIG mClCfg; /* mBlk & cluster config structure */
|
||||
CL_DESC clDesc; /* cluster descriptor table */
|
||||
END_ERR lastError; /* Last error passed to muxError */
|
||||
BOOL errorHandling; /* task level error handling */
|
||||
u_short errorStat; /* error status */
|
||||
} AU_DRV_CTRL;
|
||||
|
||||
/* Configuration items */
|
||||
|
||||
#define BUS_LATENCY_COUNT 0x1000 /* Max BUS timeo len in 0.1 uSeconds */
|
||||
#define AU_MIN_FBUF 100 /* Minsize of first buffer in chain */
|
||||
#define AU_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + 6)
|
||||
#define AU_DMA_BUFSIZ 2048 /* Req'd by Au1000 DMA engine */
|
||||
#define AU_SPEED 10000000
|
||||
#define AU_RMD_RLEN 5 /* ring size as a ^ 2 -- 32 RMD's */
|
||||
#define AU_TMD_TLEN 5 /* ring size as a ^ 2 -- 32 TMD's */
|
||||
#define AU_RMD_MIN 2 /* min descriptors 4 */
|
||||
#define AU_TMD_MIN 2 /* min descriptors 4 */
|
||||
#define AU_RMD_MAX 9 /* max descriptors 512 */
|
||||
#define AU_TMD_MAX 9 /* max descriptors 512 */
|
||||
#define AU_DEV_NAME "au" /* name of the device */
|
||||
#define AU_DEV_NAME_LEN 3 /* length of the name string */
|
||||
#define AU_APROM_SIZE 32 /* hardware address prom size */
|
||||
|
||||
#define AU_PKT_LEN_GET(rmd) PCI_SWAP (rmd->rBufMskCnt) - 4;
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
IMPORT END_OBJ * auEndLoad (char * initString);
|
||||
IMPORT STATUS auInitParse (AU_DRV_CTRL * pDrvCtrl,
|
||||
char * initString);
|
||||
#else
|
||||
IMPORT END_OBJ * auEndLoad ();
|
||||
IMPORT STATUS auInitParse ();
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCauEndh */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,381 @@
|
||||
/* elt3c509End.h - 3Com EtherLink III END network interface header*/
|
||||
|
||||
/* Copyright 1998-2000, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,29apr10,pad Moved extern C statement after include statements.
|
||||
01d,02aug00,jkf moved statistic definitions to the driver, SPR#26952
|
||||
01c,11jun00,ham removed reference to etherLib.
|
||||
01b,10mar99,sbs added DEF_NUM_RX_FRAMES.
|
||||
01a,28sep98,snk written by mBedded Innovations Inc.
|
||||
*/
|
||||
|
||||
#ifndef __INCelt3c509Endh
|
||||
#define __INCelt3c509Endh
|
||||
|
||||
#include "netinet/if_ether.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* debug defines */
|
||||
|
||||
#undef DRV_DEBUG
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#define ELT_TIMING
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
/* defines */
|
||||
|
||||
#define EA_SIZE 6 /* one Ethernet address */
|
||||
#define EH_SIZE 14 /* ethernet header size */
|
||||
#define MAX_FRAME_SIZE (EH_SIZE + ETHERMTU) /* capacity of buffer */
|
||||
|
||||
#define DEF_NUM_RX_FRAMES 64 /* default number of receive frames */
|
||||
|
||||
#define ATTACHMENT_DEFAULT 0 /* use card as configured */
|
||||
#define ATTACHMENT_AUI 1 /* AUI (thick, DIX, DB-15) */
|
||||
#define ATTACHMENT_BNC 2 /* BNC (thin, 10BASE-2) */
|
||||
#define ATTACHMENT_RJ45 3 /* RJ-45 (twisted pair, TPE,10BASE-T)*/
|
||||
|
||||
/* Configuration items */
|
||||
|
||||
#define ELT3C509_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + 6)
|
||||
#define ELT3C509_SPEED 10000000
|
||||
#define ELT_PRODUCTID_3C589 0x9058 /* product ID for PCMCIA 3C589 */
|
||||
|
||||
/* naming items */
|
||||
|
||||
#define ELT3C509_DEV_NAME "elt"
|
||||
#define ELT3C509_DEV_NAME_LEN 4
|
||||
|
||||
/* flags */
|
||||
|
||||
#define ELT3C_PROMISCUOUS_FLAG 0x1
|
||||
#define ELT3C_RCV_HANDLING_FLAG 0x2
|
||||
#define ELT3C_POLLING 0x4
|
||||
|
||||
/* statistic block, see also driver source code */
|
||||
typedef struct
|
||||
{
|
||||
#ifdef ELT_TIMING
|
||||
UINT elt3c509Stats[40];
|
||||
#else
|
||||
UINT elt3c509Stats[30];
|
||||
#endif
|
||||
} ELT3C509_STAT;
|
||||
|
||||
/* ELT driver data structures */
|
||||
|
||||
typedef struct elt3c509_device
|
||||
{
|
||||
END_OBJ endObj; /* The class we inherit from. */
|
||||
int unit; /* unit number */
|
||||
char * pTxCluster; /* pointer to transmit cluster */
|
||||
int nRxFrames; /* number of recv frames */
|
||||
int rxFilter; /* current recv address filter bits */
|
||||
int port; /* base I/O port of this board */
|
||||
int ivec; /* interrupt vector */
|
||||
int intLevel; /* interrupt level */
|
||||
int attachment; /* connector to use (AUI,BNC,TPE) */
|
||||
int intMask; /* current board interrupt mask */
|
||||
ELT3C509_STAT elt3c509Stat; /* statistics */
|
||||
long flags; /* Our local flags. */
|
||||
UCHAR enetAddr [6]; /* ethernet address */
|
||||
CACHE_FUNCS cacheFuncs; /* cache function pointers */
|
||||
BOOL txBlocked; /* indicates netTask active/queued */
|
||||
CL_POOL_ID pClPoolId; /* cluster pool id */
|
||||
M_CL_CONFIG endClConfig; /* cluster config structure */
|
||||
CL_DESC endClDesc; /* cluster descriptor table */
|
||||
#ifdef ELT_TIMING
|
||||
int interruptTime; /* timer value at ISR, -1 if invalid */
|
||||
int maxRxLatency; /* max time to service receive buffer */
|
||||
#endif /* ELT_TIMING */
|
||||
} ELT3C509_DEVICE;
|
||||
|
||||
/* ELT register offsets, grouped by window number */
|
||||
|
||||
/* all windows */
|
||||
|
||||
#define ELT3C509_COMMAND 0x0e /* command register */
|
||||
#define ELT3C509_STATUS 0x0e /* status register */
|
||||
|
||||
/* window number symbols for selection command */
|
||||
|
||||
#define WIN_CONFIG 0x0000
|
||||
#define WIN_OPERATING 0x0001
|
||||
#define WIN_ADDRESS 0x0002
|
||||
#define WIN_FIFO 0x0003
|
||||
#define WIN_DIAGNOSTIC 0x0004
|
||||
#define WIN_RESULTS 0x0005
|
||||
#define WIN_STATISTICS 0x0006
|
||||
|
||||
/* window 0, configuration and EEPROM */
|
||||
|
||||
#define MANUF_ID 0x00 /* manufacturer ID */
|
||||
#define PRODUCT_ID 0x02 /* product ID/MCA adapter ID */
|
||||
#define CONFIG_CONTROL 0x04 /* configuration control */
|
||||
#define ADDRESS_CONFIG 0x06 /* address configuration */
|
||||
#define RESOURCE_CONFIG 0x08 /* resource configuration */
|
||||
#define EEPROM_CONTROL 0x0a /* EEPROM control */
|
||||
#define EEPROM_DATA 0x0c /* EEPROM data in/out */
|
||||
|
||||
/* window 1, operating set */
|
||||
|
||||
#define DATA_REGISTER 0x00 /* data (low word) in/out */
|
||||
#define DATA_HIGH 0x02 /* data (high word) in/out */
|
||||
#define RX_STATUS 0x08 /* received packet status */
|
||||
#define TIMER 0x0a /* (byte) interrupt latency timer */
|
||||
#define TX_STATUS 0x0b /* (byte) transmit status */
|
||||
#define TX_FREE_BYTES 0x0c /* free bytes available in tx FIFO */
|
||||
/* also appears in window 3 */
|
||||
|
||||
/* window 2, station address setup/read */
|
||||
|
||||
#define ADDRESS_0 0x00 /* (byte) station address 0 */
|
||||
#define ADDRESS_1 0x01 /* (byte) station address 1 */
|
||||
#define ADDRESS_2 0x02 /* (byte) station address 2 */
|
||||
#define ADDRESS_3 0x03 /* (byte) station address 3 */
|
||||
#define ADDRESS_4 0x04 /* (byte) station address 4 */
|
||||
#define ADDRESS_5 0x05 /* (byte) station address 5 */
|
||||
|
||||
/* window 3, FIFO management */
|
||||
|
||||
#define TX_RECLAIM 0x08 /* MCA tx reclaim threshold */
|
||||
#define RX_FREE_BYTES 0x0a /* free bytes available in rx FIFO */
|
||||
#define TX_FREE_BYTES_3 0x0c /* free bytes available in tx FIFO */
|
||||
/* also appears in window 1 */
|
||||
/* same offset so can use same macro */
|
||||
|
||||
/* window 4, diagnostics */
|
||||
|
||||
#define TX_DIAGNOSTIC 0x00 /* tx diagnostic */
|
||||
#define HOST_DIAGNOSTIC 0x02 /* host diagnostic */
|
||||
#define FIFO_DIAGNOSTIC 0x04 /* FIFO diagnostic */
|
||||
#define NET_DIAGNOSTIC 0x06 /* net diagnostic */
|
||||
#define ETHERNET_STATUS 0x08 /* ethernet controller status */
|
||||
#define MEDIA_STATUS 0x0a /* media type and status */
|
||||
|
||||
/* window 5, command results and internal state (read only) */
|
||||
|
||||
#define TX_START_THRESH 0x00 /* tx start threshold + 4 */
|
||||
#define TX_AVAIL_THRESH 0x02 /* tx available threshold */
|
||||
#define RX_EARLY_THRESH 0x06 /* rx early threshold */
|
||||
#define RX_FILTER 0x08 /* rx filter lower 4 bits */
|
||||
#define INTERRUPT_MASK 0x0a /* interrupt mask */
|
||||
#define READ_ZERO_MASK 0x0c /* read zero mask */
|
||||
|
||||
/* window 6, statistics registers (byte regs. MUST be read/written as bytes) */
|
||||
|
||||
#define CARRIER_LOSTS 0x00 /* (byte) carrier loss during tx */
|
||||
#define SQE_FAILURES 0x01 /* (byte) heartbeat loss during tx */
|
||||
#define MULT_COLLISIONS 0x02 /* (byte) tx with multiple collis. */
|
||||
#define ONE_COLLISIONS 0x03 /* (byte) tx with one collision */
|
||||
#define LATE_COLLISIONS 0x04 /* (byte) tx with late collision */
|
||||
#define RECV_OVERRUNS 0x05 /* (byte) receive overruns */
|
||||
#define GOOD_TRANSMITS 0x06 /* (byte) frames transmitted OK */
|
||||
#define GOOD_RECEIVES 0x07 /* (byte) frames received OK */
|
||||
#define TX_DEFERRALS 0x08 /* (byte) transmit deferrals */
|
||||
#define BYTES_RECEIVED 0x0a /* total bytes received OK */
|
||||
#define BYTES_TRANSMITTED 0x0c /* total bytes transmitted OK */
|
||||
|
||||
/* ISA ID sequence state machine commands */
|
||||
|
||||
#define ID_PORT 0x0100 /* I/O port to access ID sequence */
|
||||
/* could be 0x110..0x1f0 but this */
|
||||
/* is a highly unlikely address to */
|
||||
/* be used by anything else */
|
||||
#define ID_RESET 0x00 /* reset ID state machine */
|
||||
#define ID_EEPROM_READ 0x80 /* read EEPROM register addressed by */
|
||||
/* last 6 bits of this command */
|
||||
#define ID_EEPROM_MASK 0x3f /* these bits here */
|
||||
#define ID_SET_TAG 0xd0 /* set tag register to last 3 bits */
|
||||
#define ID_TAG_MASK 0x07 /* values 1..7 take tagged adapter */
|
||||
/* out of the contention process */
|
||||
#define ID_ACTIVATE 0xff /* activate adapter as pre-configured */
|
||||
|
||||
#define ID_SEQUENCE_INITIAL 0xff /* initial value in ID sequence */
|
||||
#define ID_SEQUENCE_LENGTH 255 /* iteration count */
|
||||
#define ID_CARRY_BIT 0x100 /* carry out of 8-bit ID value shift */
|
||||
#define ID_POLYNOMIAL 0xcf /* XOR this with ID value */
|
||||
#define ID_REGISTER_SIZE 16 /* bits in an EEPROM register */
|
||||
|
||||
/* important EEPROM addresses */
|
||||
|
||||
#define EE_A_PRODUCT_ID 0x03 /* 3C5xx product id */
|
||||
#define EE_A_MANUFACTURER 0x07 /* 3Com mfg. id == 0x6d50 */
|
||||
#define EE_A_ADDRESS 0x08 /* address configuration */
|
||||
#define EE_A_RESOURCE 0x09 /* resource configuration */
|
||||
#define EE_A_OEM_NODE_0 0x0a /* word 0 of OEM Ethernet address */
|
||||
#define EE_A_OEM_NODE_1 0x0b /* word 1 of OEM Ethernet address */
|
||||
#define EE_A_OEM_NODE_2 0x0c /* word 2 of OEM Ethernet address */
|
||||
|
||||
#define MANUFACTURER_ID 0x6d50 /* 3Com id code in EEPROM */
|
||||
|
||||
/* address configuration register fields and values */
|
||||
|
||||
#define AC_IO_BASE_MASK 0x001f /* I/O base address encoding */
|
||||
/* 0-30 select n * 0x10 + 0x200 */
|
||||
#define AC_IO_BASE_ZERO 0x0200 /* first encoded address */
|
||||
#define AC_IO_BASE_FACTOR 0x10 /* convert code to address range */
|
||||
#define AC_IO_BASE_EISA 0x001f /* EISA addressing indicator */
|
||||
#define AC_XCVR_MASK 0xc000 /* transciever selection field */
|
||||
#define AC_XCVR_TPE 0x0000 /* select twisted-pair (10BASE-T) */
|
||||
#define AC_XCVR_AUI 0x4000 /* select AUI (external transceiver) */
|
||||
#define AC_XCVR_BNC 0xc000 /* select BNC (10BASE-2); must also */
|
||||
/* activate with START_COAX command */
|
||||
|
||||
/* configuration control register bits */
|
||||
|
||||
#define CC_ENABLE 0x0001 /* set to enable IRQ driver */
|
||||
#define CC_RESET 0x0004 /* reset adapter to POR state */
|
||||
#define CC_POR_INTERNAL_ENDEC 0x0100 /* use internal encoder/decoder */
|
||||
#define CC_POR_10BASETAVAIL 0x0200
|
||||
/* on-board TPE transceiver available */
|
||||
#define CC_POR_TEST_MASK 0x0c00 /* test mode bits */
|
||||
#define CC_POR_TEST_RECEIVE 0x0400 /* receive test mode */
|
||||
#define CC_POR_TEST_TRANSMIT 0x0800 /* transmit test mode */
|
||||
#define CC_POR_TEST_NORMAL 0x0c00 /* normal operation mode */
|
||||
#define CC_POR_10BASE2_AVAIL 0x1000
|
||||
/* on-board coax transceiver available*/
|
||||
#define CC_POR_AUI_AVAIL 0x2000 /* on-board AUI connector evailable */
|
||||
|
||||
/* FIFO diagnostic register bits */
|
||||
|
||||
#define FD_TX_BC 0x0001 /* TX BIST is complete */
|
||||
#define FD_TX_BF 0x0002 /* TX BIST has failed */
|
||||
#define FD_TX_BFC 0x0004 /* sets TX BF to test for stuck-at */
|
||||
#define FD_TX_BIST 0x0008 /* enable BIST in TX FIFO RAM */
|
||||
#define FD_RX_BC 0x0010 /* TRX BIST is complete */
|
||||
#define FD_RX_BF 0x0020 /* RX BIST has failed */
|
||||
#define FD_RX_BFC 0x0040 /* sets RX BF to test for stuck-at */
|
||||
#define FD_RX_BIST 0x0080 /* enable BIST in RX FIFO RAM */
|
||||
#define FD_TX_OVERRUN 0x0400 /* host wrote too much data */
|
||||
#define FD_RX_OVERRUN 0x0800 /* RX overrun (not necessarily */
|
||||
/* packet overrun yet) */
|
||||
#define FD_RX_STATUS_OVERRUN 0x1000 /* already 8 packets in RX FIFO */
|
||||
#define FD_RX_UNDERRUN 0x2000 /* host read past end of packet */
|
||||
#define FD_RX_RECEIVING 0x8000 /* packet being received now */
|
||||
|
||||
/* media type and status bits */
|
||||
|
||||
#define MT_S_SQE_ENABLE 0x0008 /* enable SQE error detection */
|
||||
#define MT_S_COLLISION 0x0010 /* (?) collision in progress */
|
||||
#define MT_S_CARRIER 0x0020 /* (?) carrier sensed currently */
|
||||
#define MT_S_JABBER_ENABLE 0x0040 /* enable jabber and polarity detect */
|
||||
#define MT_S_LINK_BEAT_ENABLE 0x0080 /* enable TPE link beat */
|
||||
#define MT_S_UNSQUELCH 0x0100 /* unsquelch status */
|
||||
#define MT_S_JABBER 0x0200 /* jabber status */
|
||||
#define MT_S_POLARITY 0x0400 /* polarity swap status */
|
||||
#define MT_S_LINK_BEAT 0x0800 /* link beat correct status */
|
||||
#define MT_S_SQE 0x1000 /* SQE present status */
|
||||
#define MT_S_INTERNAL_ENDEC 0x2000 /* internal encoder/decoder in use */
|
||||
#define MT_S_BNC 0x4000 /* BNC transceiver in use */
|
||||
#define MT_S_AUI_DISABLE 0x8000 /* AUI interface disabled */
|
||||
|
||||
/* command opcodes (uppper 5 bits of command register) */
|
||||
|
||||
#define GLOBAL_RESET 0x0000 /* global reset (powerup equiv.) */
|
||||
#define SELECT_WINDOW 0x0800 /* select register window */
|
||||
#define START_COAX 0x1000 /* start coaxial transciever */
|
||||
#define RX_DISABLE 0x1800 /* disable ethernet receiver */
|
||||
#define RX_ENABLE 0x2000 /* enable ethernet receiver */
|
||||
#define RX_RESET 0x2800 /* reset ethernet receiver */
|
||||
#define RX_DISCARD 0x4000 /* discard remainder of top FIFO pkt */
|
||||
#define TX_ENABLE 0x4800 /* enable ethernet transmitter */
|
||||
#define TX_DISABLE 0x5000 /* disable ethernet transmitter */
|
||||
#define TX_RESET 0x5800 /* reset ethernet transmitter */
|
||||
#define REQ_INTERRUPT 0x6000 /* set interrupt requested bit */
|
||||
#define ACK_INTERRUPT 0x6800 /* acknowledge interrupt conditions */
|
||||
#define MASK_INTERRUPT 0x7000 /* set interrupt mask bits */
|
||||
#define MASK_STATUS 0x7800 /* set status mask bits */
|
||||
/* the "read zero mask" */
|
||||
#define SET_RX_FILTER 0x8000 /* set receive filter bits */
|
||||
#define SET_RX_THRESH 0x8800 /* set receive early threshold */
|
||||
#define SET_TX_AVAIL 0x9000 /* set transmit available threshold */
|
||||
#define SET_TX_START 0x9800 /* set transmit start threshold */
|
||||
#define STATS_ENABLE 0xa800 /* enable statistics collection */
|
||||
#define STATS_DISABLE 0xb000 /* disable statistics collection */
|
||||
#define STOP_COAX 0xb800 /* stop coaxial transciever */
|
||||
#define SET_TX_RECLAIM 0xc000 /* (MCA) set tx reclaim threshold */
|
||||
|
||||
/* receive filter command argument bits */
|
||||
|
||||
#define RX_F_STATION_IA 0x01 /* accept individual address */
|
||||
#define RX_F_MULTICAST 0x02 /* accept multicast (group) addresses */
|
||||
#define RX_F_BROADCAST 0x04 /* accept broadcast address */
|
||||
#define RX_F_PROMISCUOUS 0x08 /* accept all addresses */
|
||||
#define RX_F_NORMAL (RX_F_STATION_IA | RX_F_BROADCAST)
|
||||
|
||||
/* board status bits (also acknowledge and mask bits) */
|
||||
|
||||
#define INTERRUPT_LATCH 0x0001 /* raise interrupt to host */
|
||||
#define ADAPTER_FAILURE 0x0002 /* error unrecoverable by adapter */
|
||||
/* tx overrun, rx underrun, or */
|
||||
/* hypothetical hardware errors */
|
||||
#define TX_COMPLETE 0x0004 /* tx finished with error or */
|
||||
/* packet interrupt bit was set */
|
||||
#define TX_AVAILABLE 0x0008 /* tx available threshold exceeded */
|
||||
#define RX_COMPLETE 0x0010 /* a complete packet is available */
|
||||
#define RX_EARLY 0x0020 /* rx early threshold exceeded */
|
||||
#define INTERRUPT_REQ 0x0040 /* set by request interrupt command */
|
||||
#define UPDATE_STATS 0x0080 /* one or more statistics counters */
|
||||
/* needs to be flushed */
|
||||
#define STATUS_MASK 0x00ff /* pick status bits out of register */
|
||||
#define COMMAND_IN_PROGRESS 0x1000 /* last command still being processed */
|
||||
#define WINDOW_MASK 0xe000 /* current register window selection */
|
||||
|
||||
/* transmit status register bits */
|
||||
|
||||
#define TX_S_RECLAIM 0x02 /* tx reclaim (MCA only) */
|
||||
#define TX_S_OVERFLOW 0x04 /* tx status overflow (lost info) */
|
||||
#define TX_S_MAX_COLL 0x08 /* maximum collisions reached */
|
||||
#define TX_S_UNDERRUN 0x10 /* underrun, tx reset required */
|
||||
#define TX_S_JABBER 0x20 /* jabber error, tx reset required */
|
||||
#define TX_S_INTERRUPT 0x40 /* interrupt on successful xmit */
|
||||
#define TX_S_COMPLETE 0x80 /* transmission complete */
|
||||
/* This bit denotes a valid status */
|
||||
/* when set; valid status is popped */
|
||||
/* off the stack by a write cycle to */
|
||||
/* the transmit status register */
|
||||
|
||||
/* transmit free bytes constants */
|
||||
|
||||
#define TX_IDLE_COUNT 0x7f8 /* 2,040; supposed to be 2,044 */
|
||||
/* use a >= test to see if tx idle */
|
||||
|
||||
/* receive status register bits */
|
||||
|
||||
#define RX_S_CNT_MASK 0x07ff /* received byte count field */
|
||||
#define RX_S_CODE_MASK 0x3800 /* error code field */
|
||||
#define RX_S_OVERRUN 0x0000 /* overrun error */
|
||||
#define RX_S_RUNT 0x1800 /* runt packet error */
|
||||
#define RX_S_ALIGN 0x2000 /* alignment (framing) error */
|
||||
#define RX_S_CRC 0x2800 /* CRC error */
|
||||
#define RX_S_OVERSIZE 0x0800 /* oversize packet error (>1514) */
|
||||
#define RX_S_DRIBBLE 0x1000 /* dribble bit(s); this code is */
|
||||
/* valid when error bit is not set */
|
||||
#define RX_S_ERROR 0x4000 /* error in rx packet, code above */
|
||||
#define RX_S_INCOMPLETE 0x8000 /* packet is incomplete or FIFO empty */
|
||||
/* opposite of transmit status! */
|
||||
|
||||
/* transmit packet preamble bits and fields */
|
||||
|
||||
#define TX_F_LEN_MASK 0x07ff /* length field */
|
||||
#define TX_F_INTERRUPT 0x8000 /* interrupt on transmit complete */
|
||||
#define TX_F_DWORD_MASK 0xfffc /* mask to round lengths to dword */
|
||||
#define TX_F_PREAMBLE_SIZE 4 /* size of packet length "preamble" */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCelt3c509Endh */
|
||||
@@ -0,0 +1,752 @@
|
||||
/* emacEnd.h - END based IBM EMAC Ethernet header */
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
This source and object code has been made available to you by IBM on an
|
||||
AS-IS basis.
|
||||
|
||||
IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
|
||||
OF THIRD PARTY RIGHTS. IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
|
||||
FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES. IBMS OR ITS LICENSORS
|
||||
DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
|
||||
AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE. No license
|
||||
under IBM patents or patent applications is to be implied by the copyright
|
||||
license.
|
||||
|
||||
Any user of this software should understand that neither IBM nor its
|
||||
licensors will be responsible for any consequences resulting from the use
|
||||
of this software.
|
||||
|
||||
Any person who transfers this source code or any derivative work must
|
||||
include the IBM copyright notice, this paragraph, and the preceding two
|
||||
paragraphs in the transferred software.
|
||||
|
||||
Any person who transfers this object code or any derivative work must
|
||||
include the IBM copyright notice in the transferred software.
|
||||
|
||||
COPYRIGHT I B M CORPORATION 2000
|
||||
LICENSED MATERIAL - PROGRAM PROPERTY OF I B M"
|
||||
|
||||
********************************************************************************
|
||||
\NOMANUAL
|
||||
*/
|
||||
|
||||
/* Copyright 1984-2004, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
02b,29apr10,pad Moved extern C statement after include statements.
|
||||
02a,07apr06,mmi added EMAC_AMCC_440EP
|
||||
01z,16jul04,jln add TAH definition; add tahBase for TAH; 2 Byte offset
|
||||
01y,03sep04,mdo Documentation fixes for apigen
|
||||
01x,30jun04,jln add pRxMblkArray member; 10 byte offset
|
||||
01w,28may04,jln add EMAC_GIGABIT_CAPABLE_INTERFACE
|
||||
01v,19may04,jb3 change local flags for SPR 95025
|
||||
01u,26aug03,jln change malLib.h to ibmMalDma.h;
|
||||
define EMAC_RX_GROUP_POLL_ENABLE
|
||||
01t,18aug03,jln add emacBspInfo structure; add burstLength
|
||||
01s,24jul03,jln add pTxPollBufAdr member
|
||||
01r,16jul03,jln rename ibmEmacEnd.h to emacEnd.h; add PHY definition
|
||||
01q,24jun03,jln remove restart timer from EMAC_DRV_CTRL
|
||||
01p,13jun03,jln modified EMAC_DRV_CTRL structure
|
||||
01o,29may03,jln merge ibm440gx change for gigabit support; modify DRV_CTRL
|
||||
01n,28may03,jtp Merge IBM changes; add CICADA PHY errata processing to ignore
|
||||
Loss of Carrier Sense.
|
||||
01m,06nov01,alr fix (SPR 71487) ibmEmacEnd: driver may instruct MUX to block
|
||||
(EMAC_TX_BLOCKED/END_ERR_BLOCK) but never call muxTxRestart
|
||||
01l,18oct01,mcg Polled mode fixes, added OPB speed variables to main struct.
|
||||
01k,20aug01,kab Change ibmEmac to emac - max 4 letter boot dev in DHCP, other
|
||||
01j,25jul01,pmr added macro to control memory allocation for loaning buffers
|
||||
01i,10may01,mcg extensive changes to driver to remove data cache coherency
|
||||
code, add support for both TX channels, add full-duplex flow
|
||||
control support. 405 kernel must be used.
|
||||
01h,09may01,pmr changed ENET_HDR_REAL_SIZ to SIZEOF_ETHERHEADER.
|
||||
01g,29nov00,s_m changes from ibm
|
||||
01f,02nov00,mcg added semMutexRX to device structure
|
||||
01e,05jul00,mcg added phyAnlpr to device structure
|
||||
01d,15may00,mcg register name updates to match 405GP User Manual
|
||||
01c,03mar00 mcg Added bit fields. TX and RX descriptor queues to 64 entries
|
||||
01b,07dec99 mcg Increased default TX and RX descriptor queues to 128 entries
|
||||
01a,11oct99,mcg created.
|
||||
*/
|
||||
|
||||
#ifndef __INCibmEmacEndh
|
||||
#define __INCibmEmacEndh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include "end.h"
|
||||
#include "cacheLib.h"
|
||||
#include "drv/dma/ibmMalDma.h"
|
||||
#include "wdLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Defines for inputFlags in the ibmEmacEnd load string. If none of the flags
|
||||
* below are set in the input string, the driver will use one transmit
|
||||
* channel, will use cached buffer/clusters (and manage the data cache
|
||||
* coherency), and will do transmits without copying (zero copy). The flags
|
||||
* below can be used change the default behavior.
|
||||
*/
|
||||
|
||||
#define EMAC_INPUT_TX_COPY 0x01 /* Do transmits with copy */
|
||||
#define EMAC_INPUT_UNCACHED_BUF 0x02 /* Use uncached buffers */
|
||||
#define EMAC_INPUT_TX_2_CHANNEL 0x04 /* Use both TX channels */
|
||||
|
||||
#define EMAC_RXCHAN_GROUP_ENABLE 0x1000 /* group all RX channels */
|
||||
#define EMAC_RXCHAN_GROUP_POLL_ENABLE 0x2000 /* polling in grouping mode */
|
||||
|
||||
#define EMAC_GIGABIT_CAPABLE_INTERFACE 0x4000 /* flag for 440GX Gigabit port */
|
||||
#define EMAC_XSUM_OFFLOAD_SUPPORT 0x8000 /* flag for 440GX XSUM support */
|
||||
|
||||
/*
|
||||
* A common buffer descriptor structure is used for transmit and receive
|
||||
* operations. Only the status/control bits have different meaning for TX
|
||||
* and RX. Bits 0:5 are used to control the RX and TX behavior of MAL on a
|
||||
* per-packet basis. See malLib.h for the MAL buffer descriptor structure,
|
||||
* and the definitions of bits 0:5.
|
||||
*
|
||||
* Bits 6:15 are used to control the EMAC TX behavior, and to get status
|
||||
* about the TX and RX behavior of the EMAC on a per packet basis.
|
||||
*/
|
||||
|
||||
/* EMAC Transmit Control */
|
||||
#define EMAC_TX_CTRL_GFCS 0x0200 /* Generate FCS */
|
||||
#define EMAC_TX_CTRL_GP 0x0100 /* Generate padding */
|
||||
#define EMAC_TX_CTRL_ISA 0x0080 /* Insert source address */
|
||||
#define EMAC_TX_CTRL_RSA 0x0040 /* Replace source address */
|
||||
#define EMAC_TX_CTRL_IVT 0x0020 /* Insert VLAN tag */
|
||||
#define EMAC_TX_CTRL_RVT 0x0010 /* Replace VLAN tag */
|
||||
|
||||
#define EMAC_TX_CTRL_XM_SSR0 0x0002 /* TCP xsum and seg on SSR0 */
|
||||
#define EMAC_TX_CTRL_XM_SSR1 0x0004 /* TCP xsum and seg on SSR1 */
|
||||
#define EMAC_TX_CTRL_XM_SSR2 0x0006 /* TCP xsum and seg on SSR2 */
|
||||
#define EMAC_TX_CTRL_XM_SSR3 0x0008 /* TCP xsum and seg on SSR3 */
|
||||
#define EMAC_TX_CTRL_XM_SSR4 0x000a /* TCP xsum and seg on SSR4 */
|
||||
#define EMAC_TX_CTRL_XM_SSR5 0x000c /* TCP xsum and seg on SSR5 */
|
||||
#define EMAC_TX_CTRL_XM_ONLY 0x000e /* tcp xsum only */
|
||||
|
||||
/* EMAC Transmit Status */
|
||||
#define EMAC_TX_STAT_BFCS 0x0200 /* Bad FCS in packet */
|
||||
#define EMAC_TX_STAT_BPP 0x0100 /* Bad previous packet */
|
||||
#define EMAC_TX_STAT_LCS 0x0080 /* Loss of carrier sense */
|
||||
#define EMAC_TX_STAT_ED 0x0040 /* Excessive deferral */
|
||||
#define EMAC_TX_STAT_EC 0x0020 /* Excessive collisions */
|
||||
#define EMAC_TX_STAT_LC 0x0010 /* Late collision */
|
||||
#define EMAC_TX_STAT_MC 0x0008 /* Multiple collision */
|
||||
#define EMAC_TX_STAT_SC 0x0004 /* Single collision */
|
||||
#define EMAC_TX_STAT_UR 0x0002 /* Underrun */
|
||||
#define EMAC_TX_STAT_SQE 0x0001 /* Signal quality error (SQE) */
|
||||
#define EMAC_TX_STAT 0x03FF /* All TX STAT bits above */
|
||||
|
||||
/* All the TX status bits that are considered errors */
|
||||
#ifdef CICADA_PHY_RGMII_10MPS_12DUPLEX_ERRATA
|
||||
/* Ignore Loss of Carrier Sense Errors for Cicada PHY errata */
|
||||
#define EMAC_TX_ERRORS ( EMAC_TX_STAT_EC | \
|
||||
EMAC_TX_STAT_LC | EMAC_TX_STAT_UR | \
|
||||
EMAC_TX_STAT_SQE)
|
||||
#else
|
||||
#define EMAC_TX_ERRORS (EMAC_TX_STAT_LCS | EMAC_TX_STAT_EC | \
|
||||
EMAC_TX_STAT_LC | EMAC_TX_STAT_UR | \
|
||||
EMAC_TX_STAT_SQE)
|
||||
#endif
|
||||
|
||||
/* EMAC Receive Status */
|
||||
#define EMAC_RX_STAT_OE 0x0200 /* Overrun error */
|
||||
#define EMAC_RX_STAT_PP 0x0100 /* Pause packet received */
|
||||
#define EMAC_RX_STAT_BP 0x0080 /* Bad packet */
|
||||
#define EMAC_RX_STAT_RP 0x0040 /* Runt packet */
|
||||
#define EMAC_RX_STAT_SE 0x0020 /* Short event */
|
||||
#define EMAC_RX_STAT_AE 0x0010 /* Alignment error */
|
||||
#define EMAC_RX_STAT_BFCS 0x0008 /* Bad FCS */
|
||||
#define EMAC_RX_STAT_PTL 0x0004 /* Packet too long */
|
||||
#define EMAC_RX_STAT_ORE 0x0002 /* Out of range error */
|
||||
#define EMAC_RX_STAT_IRE 0x0001 /* In range error */
|
||||
#define EMAC_RX_STAT 0x03FF /* All RX STAT bits above */
|
||||
|
||||
/* Range error */
|
||||
|
||||
#define EMAC_RX_STAT_RE (EMAC_RX_STAT_IRE | EMAC_RX_STAT_ORE)
|
||||
|
||||
/* RX XSUM error */
|
||||
|
||||
#define EMAC_RX_STAT_RX_XSUM EMAC_RX_STAT_RE
|
||||
|
||||
/* All the RX status bits that are considered errors */
|
||||
#define EMAC_RX_ERRORS (EMAC_RX_STAT_OE | EMAC_RX_STAT_BP | \
|
||||
EMAC_RX_STAT_RP | EMAC_RX_STAT_SE | \
|
||||
EMAC_RX_STAT_AE | EMAC_RX_STAT_BFCS | \
|
||||
EMAC_RX_STAT_PTL | EMAC_RX_STAT_RE )
|
||||
|
||||
/*
|
||||
* Default descriptor initialization values.
|
||||
*/
|
||||
|
||||
#define EMAC_TX_DESC_INIT (EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP)
|
||||
|
||||
#define EMAC_RX_DESC_INIT (MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR)
|
||||
|
||||
/* Definitions for localFlags bits in the EMAC_DRV_CTRL structure */
|
||||
|
||||
#define EMAC_HANDLE_RX_RUNNING 0x01 /* HandleRcvInt job running */
|
||||
#define EMAC_POLLING_MODE 0x02 /* Currently in polling mode */
|
||||
#define EMAC_TX_CLEAN_RUNNING 0x04 /* TX clean in progress */
|
||||
#define EMAC_TX_BLOCKED 0x08 /* Ran out of TX descriptors */
|
||||
#define EMAC_TX_NOT_RESTARTED 0x10 /* netJob emacTxRestart running */
|
||||
|
||||
/*
|
||||
* EMAC_BUF_SIZE is 1500 + 14 + 18 = 1532 which is 4 less than an even number
|
||||
* of 32 byte cache lines. Add sizeof(long) cluster overhead and it is 1536.
|
||||
* The 18 bytes is padding.
|
||||
*/
|
||||
|
||||
#define EMAC_BUF_SIZE (ETHERMTU + SIZEOF_ETHERHEADER + 18)
|
||||
#define EMAC_MIN_FBUF 100 /* Minsize of first buffer in chain */
|
||||
#define EMAC_SPEED 10000000 /* 10Mbps */
|
||||
#define EMAC_RXD_MIN 8 /* minimum # of RX descriptors/MAL chn */
|
||||
#define EMAC_TXD_MIN 8 /* minimum # of TX descriptors/MAL chn */
|
||||
#define EMAC_RXD_DFT 64 /* default # of RX descriptors/MAL chn */
|
||||
#define EMAC_TXD_DFT 256 /* default # of TX descriptors/MAL chn */
|
||||
#define EMAC_RXD_MAX MAL_MAX_DESC /* max # of RX descriptors/MAL chn */
|
||||
#define EMAC_TXD_MAX MAL_MAX_DESC /* max # of TX descriptors/MAL chn */
|
||||
|
||||
#define EMAC_RXD_LOAN_X 4 /* multiply no. of RX desc. to allow */
|
||||
/* for buffer loaning */
|
||||
#define EMAC_RXBUF_OFFSET 0x2 /* force 2 byte offset */
|
||||
|
||||
#define EMAC_DEV_NAME "emac" /* Name of this device - max 4 char */
|
||||
#define EMAC_DEV_DESC "IBM EMAC End Driver" /* Description */
|
||||
|
||||
/*
|
||||
* Basic unit, maximum, minimum, and default memory sizes.
|
||||
* The sizeof(long) in EMAC_BSC_MEM_SIZE is for cluster overhead.
|
||||
*/
|
||||
#define EMAC_BSC_MEM_SIZE (EMAC_BUF_SIZE + sizeof(long))
|
||||
|
||||
#define EMAC_MAX_MEM_SIZE ((EMAC_RXD_MAX * EMAC_RXD_LOAN_X) * EMAC_BSC_MEM_SIZE)
|
||||
#define EMAC_MIN_MEM_SIZE ((EMAC_RXD_MIN * EMAC_RXD_LOAN_X) * EMAC_BSC_MEM_SIZE)
|
||||
#define EMAC_DFT_MEM_SIZE ((EMAC_RXD_DFT * EMAC_RXD_LOAN_X) * EMAC_BSC_MEM_SIZE)
|
||||
|
||||
/* Multiple Individual and Group Address Filter definitions */
|
||||
|
||||
#define EMAC_FILTER_CRC_POLY 0x04C11DB6
|
||||
#define EMAC_ADDR_BYTES 6
|
||||
#define EMAC_ADDR_BITS 8
|
||||
|
||||
/* EMAC type */
|
||||
|
||||
#define EMAC_IBM_405GP 2
|
||||
#define EMAC_IBM_440GP 3
|
||||
#define EMAC_IBM_440GX 4
|
||||
#define EMAC_AMCC_440EP 5
|
||||
|
||||
/* EMAC speed */
|
||||
|
||||
#define EMAC_SPEED_10Mbps 10
|
||||
#define EMAC_SPEED_100Mbps 100
|
||||
#define EMAC_SPEED_1000Mbps 1000
|
||||
|
||||
/* mode supported in EMAC */
|
||||
|
||||
#define PHY_MODE_DISABLED 0x00
|
||||
#define PHY_MODE_MII 0x01
|
||||
#define PHY_MODE_SMII 0x02
|
||||
#define PHY_MODE_RMII 0x03
|
||||
#define PHY_MODE_GMII 0x04
|
||||
#define PHY_MODE_RGMII 0x05
|
||||
#define PHY_MODE_TBI 0x06
|
||||
#define PHY_MODE_RTBI 0x07
|
||||
|
||||
#define PHY_TYPE_UNKNOWN 0xff
|
||||
|
||||
#define PHY_HALF_DUPLEX 22
|
||||
#define PHY_FULL_DUPLEX 44
|
||||
|
||||
/* PHY register offsets */
|
||||
|
||||
#define PHY_BMCR 0x00 /* Basic Mode Control Reg */
|
||||
#define PHY_BMSR 0x01 /* Basic Mode Status Reg */
|
||||
#define PHY_PHYIDR1 0x02 /* PHY identifier Reg 1 */
|
||||
#define PHY_PHYIDR2 0x03 /* PHY identifier Reg 2 */
|
||||
#define PHY_ANAR 0x04 /* Auto-neg Advertisement Reg */
|
||||
#define PHY_ANLPAR 0x05 /* Auto-neg Link Partner Ability Reg */
|
||||
#define PHY_ANER 0x06 /* Auto-neg Expansion Reg */
|
||||
#define PHY_ANNPTR 0x07 /* Auto-neg Next Page TX */
|
||||
#define PHY_PHYSTS 0x10 /* PHY Status Reg */
|
||||
#define PHY_MIPSCR 0x11
|
||||
#define PHY_MIPGSR 0x12
|
||||
#define PHY_DCR 0x13
|
||||
#define PHY_FCSCR 0x14
|
||||
#define PHY_RECR 0x15
|
||||
#define PHY_PCSR 0x16
|
||||
#define PHY_LBR 0x17
|
||||
#define PHY_10BTSCR 0x18
|
||||
#define PHY_PHYCTRL 0x19
|
||||
|
||||
/* PHY BMCR */
|
||||
|
||||
#define PHY_BMCR_RESET 0x8000
|
||||
#define PHY_BMCR_LOOP 0x4000
|
||||
#define PHY_BMCR_100MB 0x2000
|
||||
#define PHY_BMCR_AUTON 0x1000
|
||||
#define PHY_BMCR_POWD 0x0800
|
||||
#define PHY_BMCR_ISO 0x0400
|
||||
#define PHY_BMCR_RST_NEG 0x0200
|
||||
#define PHY_BMCR_DPLX 0x0100
|
||||
#define PHY_BMCR_COL_TST 0x0080
|
||||
|
||||
/* PHY BMSR */
|
||||
|
||||
#define PHY_BMSR_100T4 0x8000
|
||||
#define PHY_BMSR_100TXF 0x4000
|
||||
#define PHY_BMSR_100TXH 0x2000
|
||||
#define PHY_BMSR_10TF 0x1000
|
||||
#define PHY_BMSR_10TH 0x0800
|
||||
#define PHY_BMSR_PRE_SUP 0x0040
|
||||
#define PHY_BMSR_AUTN_COMP 0x0020
|
||||
#define PHY_BMSR_RF 0x0010
|
||||
#define PHY_BMSR_AUTN_ABLE 0x0008
|
||||
#define PHY_BMSR_LS 0x0004
|
||||
#define PHY_BMSR_JD 0x0002
|
||||
#define PHY_BMSR_EXT 0x0001
|
||||
|
||||
/*PHY ANLPAR */
|
||||
|
||||
#define PHY_ANLPAR_NP 0x8000
|
||||
#define PHY_ANLPAR_ACK 0x4000
|
||||
#define PHY_ANLPAR_RF 0x2000
|
||||
#define PHY_ANLPAR_T4 0x0200
|
||||
#define PHY_ANLPAR_TXFD 0x0100
|
||||
#define PHY_ANLPAR_TX 0x0080
|
||||
#define PHY_ANLPAR_10FD 0x0040
|
||||
#define PHY_ANLPAR_10 0x0020
|
||||
#define PHY_ANLPAR_100 0x0380
|
||||
|
||||
/* PHY 10BTSCR */
|
||||
|
||||
#define PHY_10BTSCR_HBDS 0x0080
|
||||
|
||||
/* Structure to keep track of resources to be freed by ibmEmacSendCleanup */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UCHAR * pFree; /* Cluster address, Mblk, etc. */
|
||||
int descNum; /* desc num used for this packet */
|
||||
int lastIndex; /* last index for this packet */
|
||||
int typeFree; /* padding */
|
||||
} EMAC_FREE;
|
||||
|
||||
/* Structure to keep track of TX descriptor queue information */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile MAL_BD * pTxDesc; /* First descriptor in the TX ring */
|
||||
volatile int indexTxD; /* Current TX descriptor index */
|
||||
volatile int indexTxDClean; /* Current TX cleanup descriptor index*/
|
||||
int txFreeDesc; /* free descriptor in this channel */
|
||||
int numTxD; /* Number of TX descriptors */
|
||||
int freeMblkNum; /* Number of Mblk needed to be free */
|
||||
UINT getNewPacketTX; /* Write to EMAC_TMR0 to kick off TX */
|
||||
UINT fifoAeTX; /* Tx Fifo Almost Empty value */
|
||||
EMAC_FREE txFree[EMAC_TXD_MAX]; /* array of info for TX free cleanup */
|
||||
} TX_INFO;
|
||||
|
||||
/* Flags used by the txFree arrays */
|
||||
|
||||
#define EMAC_TX_FREE_NONE 0
|
||||
#define EMAC_TX_FREE_CLUSTER 1
|
||||
#define EMAC_TX_FREE_MBLK 2
|
||||
#define EMAC_TX_FREE_MBLK_LAST 3
|
||||
|
||||
typedef struct emac_phy_info EMAC_PHY_INFO;
|
||||
|
||||
typedef struct emacBspInfo
|
||||
{
|
||||
UINT emacBaseAdr; /* EMAC base address */
|
||||
int malTxChn0; /* TX channel 0 No. */
|
||||
int malTxChn1; /* TX channel 1 No. */
|
||||
int malRxChn0; /* RX channel 0 No. */
|
||||
|
||||
int intVec; /* Interrupt vector */
|
||||
int intLvl; /* Interrupt Level */
|
||||
int cacheLineSz; /* Cache line size */
|
||||
|
||||
int emacType; /* type of EMAC (405/440GP/440GX) */
|
||||
int burstLength; /* burst length */
|
||||
int phyAdrs; /* PHY address */
|
||||
int opbSpeedMhz; /* OPB bus speed in MHz */
|
||||
MAL_DATA * pMalData; /* pointer to MAL struct*/
|
||||
EMAC_PHY_INFO * pEmacPhyInfo; /* pointer to PHY_INFO struct */
|
||||
|
||||
UINT extFlag1; /* reserved flag 1 */
|
||||
UINT extFlag2; /* reserved flag 2 */
|
||||
UINT tahBase; /* TAH base address for EMAC2/3 */
|
||||
int tahIntLvl; /* TAH interrupt level */
|
||||
UINT reserved3; /* reserved 3 */
|
||||
UINT reserved4; /* reserved 4 */
|
||||
|
||||
void * pExtBspInfo; /* reserved forward compatibility */
|
||||
} EMAC_BSP_INFO;
|
||||
|
||||
/*
|
||||
* The definition of the overall driver control structure. Each instance of
|
||||
* the driver creates its own copy of this structure.
|
||||
*/
|
||||
|
||||
typedef struct ibmEmacDevice
|
||||
{
|
||||
END_OBJ end; /* END_OBJ for this device */
|
||||
int unit; /* Unit number of this EMAC device */
|
||||
UINT baseAdrs; /* Base address of EMAC registers */
|
||||
UINT tahBase; /* Base address for TAH */
|
||||
UINT8 enetAddr[6]; /* Ethernet MAC address */
|
||||
int txChn0MalChannel; /* MAL channel # for EMAC TX channel 0*/
|
||||
int txChn1MalChannel; /* MAL channel # for EMAC TX channel 1*/
|
||||
int rxChn0MalChannel; /* MAL channel # for EMAC RX channel 0*/
|
||||
MAL_DATA * pMalData; /* ptr to MAL data for this EMAC */
|
||||
int numTxChannels; /* using 1 or 2 TX Channels */
|
||||
int txChannel; /* TX channel next for next transmit */
|
||||
TX_INFO txInfo[2]; /* Tx desc info */
|
||||
M_BLK_ID * pRxMblkArray; /* pointer to Mblk Array */
|
||||
volatile MAL_BD * pRxDesc; /* First descriptor in the RX ring */
|
||||
volatile int indexRxD; /* Current RX descriptor index */
|
||||
int maxRxCountPerInt; /* max Rx packets per ISR */
|
||||
int numRxD; /* Number of RX descriptors */
|
||||
int totalTxD; /* Number of TX descriptors */
|
||||
int ivec; /* Ethernet Interrupt vector */
|
||||
int ilevel; /* Ethernet Interrupt level */
|
||||
int phyAdrs; /* Address of PHY to be used */
|
||||
USHORT phyAnlpar; /* Results of auto-negotiation */
|
||||
char * memInputAdrs; /* Memory address from input string */
|
||||
char * memAdrsMalloc; /* Memory that was malloced */
|
||||
int memSizeMalloc; /* Size of memory that was malloced */
|
||||
char * memAdrs; /* Actual address to be used */
|
||||
int memInputSize; /* Memory size from input string */
|
||||
int memSize; /* Actual memory size to be used */
|
||||
UINT inputFlags; /* Flags passed in load string */
|
||||
volatile UINT localFlags; /* Local status flags */
|
||||
CACHE_FUNCS * pCacheFuncs; /* pointer to Cache function */
|
||||
CL_POOL_ID pClPoolId; /* Cluster pool Id */
|
||||
M_CL_CONFIG mClCfg; /* mBlk & cluster config structure */
|
||||
CL_DESC clDesc; /* Cluster descriptor table */
|
||||
END_ERR lastError; /* Last error sent to muxError */
|
||||
UINT errorEmac; /* saves last EMAC error */
|
||||
int intErrorTX; /* number of TX error interrupts */
|
||||
int intErrorRX; /* number of RX error interrupts */
|
||||
int cacheLineSize; /* size of the processor cache line */
|
||||
int opbSpeedMhz; /* OPB bus speed in MHz */
|
||||
UINT stacrOpbSpeed; /* used in STACR reg OPB speed field */
|
||||
volatile int txFreeDesc; /* number of free TX descriptor */
|
||||
int txIntDescCount; /* TX packets since last TX INT set */
|
||||
int wMarkLow; /* low water mark to set TX INT */
|
||||
int wMarkHigh; /* high water mark to cleanup TX desc */
|
||||
BOOL recount; /* flag to set TX interrupt */
|
||||
int lastIntPktCount; /* packet count since last TX INT set */
|
||||
UCHAR intNumTbl[64]; /* TX INT setup table */
|
||||
int txError; /* TX error counter */
|
||||
int txMacRestart; /* TX MAC restart counter */
|
||||
int txStallCount; /* TX stall counter */
|
||||
int txStallDescNum; /* required TX desc num to unblock */
|
||||
UINT32 txEoBIntCount; /* count of TX EOF interrrupt */
|
||||
int rxEoBIntCount; /* RX EOB interrupt count */
|
||||
int rxDescError; /* RX descriptor count */
|
||||
WDOG_ID monitorTimer; /* WD to monitor device */
|
||||
int monitorInterval; /* time to fire monitor timer in sec */
|
||||
int txPacketCount; /* statistic for TX packets */
|
||||
int rxPacketCount; /* statistic for RX packets */
|
||||
BOOL startFlag; /* device start flag */
|
||||
EMAC_PHY_INFO * phyInfo; /* PHY info structure */
|
||||
int emacType; /* EMAC type */
|
||||
int burstLength; /* burst length */
|
||||
EMAC_BSP_INFO *pEmacBspInfo; /* pointer to EMAC_BSP_INFO */
|
||||
STATUS linkStatus; /* link status */
|
||||
UINT phySpeed; /* PHY speed */
|
||||
UINT phyDuplex; /* PHY Duplex */
|
||||
UINT phyType; /* PHY type */
|
||||
char * pTxPollBufAdr; /* cache-safe buffer for TX polling */
|
||||
int initType; /* buffer initialization typr */
|
||||
int tahIntLvl; /* TAH interrupt */
|
||||
BOOL xsumUsrflag; /* IP/TCP/UDP XSUM flag */
|
||||
BOOL tahEnableFlag; /* TAH enabled in BSP */
|
||||
END_CAPABILITIES hwCaps; /* interface capability structure */
|
||||
} EMAC_DRV_CTRL;
|
||||
|
||||
/* Struct for PHY information */
|
||||
|
||||
struct emac_phy_info
|
||||
{
|
||||
STATUS (* phyPreInit)(EMAC_DRV_CTRL *); /* PHY/MAC interface setup func */
|
||||
void (* phyPreConfig)(EMAC_DRV_CTRL *); /* Pre autoNegotiation func */
|
||||
STATUS (* phyConfigStart)(EMAC_DRV_CTRL *, UINT); /* start auto negotiation func */
|
||||
void (* phyPostConfig)(EMAC_DRV_CTRL *); /* Post autoNegotiation func */
|
||||
UINT (* phySpeedGet)(EMAC_DRV_CTRL *); /* phySpeedGet func pointer */
|
||||
UINT (* phyDuplexGet)(EMAC_DRV_CTRL *); /* phyDuplexGet func pointer */
|
||||
UINT (* phyTypeGet)(EMAC_DRV_CTRL *); /* phyTypeGet func pointer */
|
||||
UINT reserved1; /* reserved 1 */
|
||||
UINT reserved2; /* reserved 2 */
|
||||
UINT reserved3; /* reserved 3 */
|
||||
UINT reserved4; /* reserved 4 */
|
||||
};
|
||||
|
||||
/*
|
||||
* TAH register and BIT definitions
|
||||
* The base address of TAH0/TAH1 is passed by loadstring
|
||||
*/
|
||||
|
||||
#define TAH_REVID 0x50 /* Revision ID */
|
||||
#define TAH_MR 0x60 /* Mode */
|
||||
#define TAH_SSR0 0x64 /* Segment size 0 */
|
||||
#define TAH_SSR1 0x68 /* Segment size 1 */
|
||||
#define TAH_SSR2 0x6c /* Segment size 2 */
|
||||
#define TAH_SSR3 0x70 /* Segment size 3 */
|
||||
#define TAH_SSR4 0x74 /* Segment size 4 */
|
||||
#define TAH_SSR5 0x78 /* Segment size 5 */
|
||||
#define TAH_TSR 0x7c /* Transmit status (RO) */
|
||||
|
||||
/* TAH REVID register bits */
|
||||
|
||||
#define TAH_REVID_RN 0x000fff00 /* REVID_RN */
|
||||
#define TAH_REVID_BRN 0x000000FF /* REVID_BRN */
|
||||
|
||||
/* TAH Mode register bits */
|
||||
|
||||
#define TAH_MR_CVR 0x80000000 /* XSUM verify on RX */
|
||||
#define TAH_MR_SR 0x40000000 /* reset */
|
||||
#define TAH_MR_ST 0x3f000000 /* send threshod */
|
||||
#define TAH_MR_TFS 0x00e00000 /* TX FIFO size */
|
||||
#define TAH_MR_DTFP 0x00100000 /* parity protection */
|
||||
#define TAH_MR_DIG 0x00010000 /* TAH interrupt */
|
||||
|
||||
#define TAH_MR_ST_256 0x01000000 /* 256B Send Threshold */
|
||||
#define TAH_MR_ST_512 0x02000000 /* 512B Send Threshold */
|
||||
#define TAH_MR_ST_1024 0x04000000 /* 1024B Send Threshold */
|
||||
#define TAH_MR_ST_1536 0x06000000 /* 1536B Send Threshold */
|
||||
|
||||
#define TAH_MR_TFS_2K 0x00200000 /* 2K for TFS */
|
||||
#define TAH_MR_TFS_4K 0x00400000 /* 4K for TFS */
|
||||
#define TAH_MR_TFS_6K 0x00600000 /* 6K for TFS */
|
||||
#define TAH_MR_TFS_8K 0x00800000 /* 8K for TFS */
|
||||
#define TAH_MR_TFS_10K 0x00A00000 /* 10K for TFS */
|
||||
#define TAH_MR_TFS_16K 0x00000000 /* 16K for TFS */
|
||||
|
||||
/* TAH Segment Size Registers(0 - 5) bits */
|
||||
|
||||
#define TAH_SSR_SS 0x3ffe0000 /* Segment Size */
|
||||
|
||||
/* TAH transmit status register bits */
|
||||
|
||||
#define TAH_TSR_TFTS 0x80000000 /* TX FIFO too small */
|
||||
#define TAH_TSR_UH 0x40000000 /* Unrecognized header */
|
||||
#define TAH_TSR_NIPF 0x20000000 /* Not IP V4 */
|
||||
#define TAH_TSR_IPOP 0x10000000 /* IP Option present */
|
||||
#define TAH_TSR_NISF 0x08000000 /* No IEEE SNAP Format */
|
||||
#define TAH_TSR_ILTS 0x04000000 /* ip length too short */
|
||||
#define TAH_TSR_IPFP 0x02000000 /* ip fragment present */
|
||||
#define TAH_TSR_UP 0x01000000 /* Upsupported Protocal */
|
||||
#define TAH_TSR_TFP 0x00800000 /* some TCP flag present */
|
||||
#define TAH_TSR_SUDP 0x00400000 /* Segmentation for UDP */
|
||||
#define TAH_TSR_DLM 0x00200000 /* Data length mismatch */
|
||||
#define TAH_TSR_SIEEE 0x00100000 /* segmentation for IEEE */
|
||||
#define TAH_TSR_TFPE 0x00080000 /* TX Fifo parity error */
|
||||
#define TAH_TSR_SSTS 0x00040000 /* Segment size too small */
|
||||
|
||||
/*
|
||||
* Ethernet Register and Register Bit Definitions
|
||||
* The base address of the EMAC is one of the load string parameters.
|
||||
*/
|
||||
|
||||
#define EMAC_MR0 0x00 /* Mode Reg 0 */
|
||||
#define EMAC_MR1 0x04 /* Mode Reg 1 */
|
||||
#define EMAC_TMR0 0x08 /* Transmit Mode 0 */
|
||||
#define EMAC_TMR1 0x0C /* Transmit Mode 1 */
|
||||
#define EMAC_RMR 0x10 /* Receive Mode */
|
||||
#define EMAC_ISR 0x14 /* Interrupt Status */
|
||||
#define EMAC_ISER 0x18 /* Interrupt Status Enable */
|
||||
#define EMAC_IAHR 0x1C /* Individual Adrs High */
|
||||
#define EMAC_IALR 0x20 /* Individual Adrs Low */
|
||||
#define EMAC_VTPID 0x24 /* VLAN TPID Reg */
|
||||
#define EMAC_VTCI 0x28 /* VLAN TCI Reg */
|
||||
#define EMAC_PTR 0x2C /* Pause Timer */
|
||||
#define EMAC_IAHT1 0x30 /* Ind Adrs Hash Table 1 */
|
||||
#define EMAC_IAHT2 0x34 /* Ind Adrs Hash Table 2 */
|
||||
#define EMAC_IAHT3 0x38 /* Ind Adrs Hash Table 3 */
|
||||
#define EMAC_IAHT4 0x3C /* Ind Adrs Hash Table 4 */
|
||||
#define EMAC_GAHT1 0x40 /* Group Adrs Hash Table 1 */
|
||||
#define EMAC_GAHT2 0x44 /* Group Adrs Hash Table 2 */
|
||||
#define EMAC_GAHT3 0x48 /* Group Adrs Hash Table 3 */
|
||||
#define EMAC_GAHT4 0x4C /* Group Adrs Hash Table 4 */
|
||||
#define EMAC_LSAH 0x50 /* Last Source Adrs High */
|
||||
#define EMAC_LSAL 0x54 /* Last Source Adrs Low */
|
||||
#define EMAC_IPGVR 0x58 /* Inter-Frame Gap Value */
|
||||
#define EMAC_STACR 0x5C /* STA Control */
|
||||
#define EMAC_TRTR 0x60 /* TX Request Threshold */
|
||||
#define EMAC_RWMR 0x64 /* RX High/Low Water Mark */
|
||||
#define EMAC_OCTX 0x68 /* MIB Octets transmitted */
|
||||
#define EMAC_OCRX 0x6C /* MIB Octets received */
|
||||
|
||||
/*
|
||||
* EMAC Mode Reg 0 bit definitions
|
||||
*/
|
||||
#define EMAC_MR0_RXI 0x80000000 /* RX MAC idle */
|
||||
#define EMAC_MR0_TXI 0x40000000 /* TX MAC idle */
|
||||
#define EMAC_MR0_SRST 0x20000000 /* Soft reset */
|
||||
#define EMAC_MR0_TXE 0x10000000 /* TX MAC enable */
|
||||
#define EMAC_MR0_RXE 0x08000000 /* RX MAC enable */
|
||||
#define EMAC_MR0_WKE 0x04000000 /* Wake up enable */
|
||||
|
||||
#define EMAC_MR0_BOTH_IDLE (EMAC_MR0_RXI | EMAC_MR0_TXI)
|
||||
|
||||
/*
|
||||
* EMAC Mode Reg 1 bit definitions
|
||||
*/
|
||||
#define EMAC_MR1_FDE 0x80000000 /* Full Duplex enable */
|
||||
#define EMAC_MR1_ILE 0x40000000 /* Internal loopback */
|
||||
#define EMAC_MR1_VLE 0x20000000 /* VLAN enable */
|
||||
#define EMAC_MR1_EIFC 0x10000000 /* Enable Int. Flow Control */
|
||||
#define EMAC_MR1_APP 0x08000000 /* Allow pause packet */
|
||||
#define EMAC_MR1_IST 0x01000000 /* Ignore SQE test */
|
||||
|
||||
#define EMAC_MR1_MF_10MBPS 0x00000000 /* Medium frequency = 10Mbps */
|
||||
#define EMAC_MR1_MF_100MBPS 0x00400000 /* Medium frequency = 100Mbps */
|
||||
#define EMAC_MR1_MF_1GBPS 0x00800000 /* Medium frequency = 1000Mbps*/
|
||||
#define EMAC_MR1_MF_1GBPS_GPCS 0x00C00000 /* 1000Mbps using GPCS */
|
||||
#define EMAC_MR1_RFS_512 0x00000000 /* Receive FIF0 = 512B */
|
||||
#define EMAC_MR1_RFS_1K 0x00080000 /* Receive FIF0 = 1KB */
|
||||
#define EMAC_MR1_RFS_2K 0x00100000 /* Receive FIF0 = 2KB */
|
||||
#define EMAC_MR1_RFS_4K 0x00180000 /* Receive FIF0 = 4KB */
|
||||
#define EMAC_MR1_RFS_8K 0x00200000 /* Receive FIF0 = 8KB */
|
||||
#define EMAC_MR1_RFS_16K 0x00280000 /* Receive FIF0 = 16KB */
|
||||
#define EMAC_MR1_TFS_512 0x00000000 /* Transmit FIFO = 512B */
|
||||
#define EMAC_MR1_TFS_1K 0x00010000 /* Transmit FIFO = 1KB */
|
||||
#define EMAC_MR1_TFS_2K 0x00020000 /* Transmit FIFO = 2KB */
|
||||
#define EMAC_MR1_TFS_4K 0x00030000 /* Transmit FIFO = 4KB */
|
||||
#define EMAC_MR1_TFS_8K 0x00040000 /* Transmit FIFO = 8KB */
|
||||
#define EMAC_MR1_TFS_16K 0x00050000 /* Transmit FIFO = 16KB */
|
||||
|
||||
/* walnut/ebony only */
|
||||
#define EMAC_MR1_TR0_SINGLE 0x00000000 /* TX 0 single packet mode */
|
||||
#define EMAC_MR1_TR0_DEPEND 0x00010000 /* TX 0 multi packet mode */
|
||||
#define EMAC_MR1_TR0_MULTI 0x00008000 /* TX 0 dependent mode */
|
||||
#define EMAC_MR1_TR1_SINGLE 0x00000000 /* TX 1 single packet mode */
|
||||
#define EMAC_MR1_TR1_DEPEND 0x00004000 /* TX 1 multi packet mode */
|
||||
#define EMAC_MR1_TR1_MULTI 0x00002000 /* TX 1 dependent mode */
|
||||
|
||||
#define EMAC_MR1_TR 0x00008000 /* Transmit request */
|
||||
#define EMAC_MR1_MWSW 0x00007000 /* Max wait status words */
|
||||
#define EMAC_MR1_MWSW_VAL 0x00001000 /* Max wait status words val */
|
||||
#define EMAC_MR1_JPSM 0x00000800 /* Jumbo packet support mode */
|
||||
#define EMAC_MR1_IPPA 0x000007C0 /* Internal PCS PHY address */
|
||||
#define EMAC_MR1_IPPA_ENCODE(n) ((((unsigned long)(n))&0x1F)<<6)
|
||||
#define EMAC_MR1_OBCI 0x00000038 /* OPB bus clock indication */
|
||||
#define EMAC_MR1_OBCI_50MHZ 0x00000000 /* OPB bus clock freq 50MHz */
|
||||
#define EMAC_MR1_OBCI_66MHZ 0x00000008 /* OPB bus clock freq 66MHz */
|
||||
#define EMAC_MR1_OBCI_83MHZ 0x00000010 /* OPB bus clock freq 83MHz */
|
||||
#define EMAC_MR1_OBCI_100MHZ 0x00000018 /* OPB bus clock freq 100MHz */
|
||||
#define EMAC_MR1_OBCI_G100MHZ 0x00000020 /* OPB bus clock freq 100MHz */
|
||||
|
||||
/*
|
||||
* EMAC Transmit Mode Register 0 bit definitions
|
||||
*/
|
||||
#define EMAC_TMR0_GNP0 0x80000000 /* TX 0 get new packet */
|
||||
#define EMAC_TMR0_GNP1 0x40000000 /* TX 1 get new packet */
|
||||
|
||||
/* walnut / ebony only */
|
||||
#define EMAC_TMR0_GNPD 0x20000000 /* TX dependent get new packet */
|
||||
#define EMAC_TMR0_FC 0x10000000 /* First channel */
|
||||
|
||||
#define EMAC_TMR0_TFAE 0x00000007 /* TX fifo almost empty */
|
||||
#define EMAC_TMR0_TFAE_DIS 0x00000007 /* '111'b disables */
|
||||
|
||||
/*
|
||||
* EMAC Receive Mode Register bit definitions
|
||||
*/
|
||||
#define EMAC_RMR_SP 0x80000000 /* Strip padding */
|
||||
#define EMAC_RMR_SFCS 0x40000000 /* Strip FCS */
|
||||
#define EMAC_RMR_RRP 0x20000000 /* RX runt packets */
|
||||
#define EMAC_RMR_RFP 0x10000000 /* RX packets with FCS error */
|
||||
#define EMAC_RMR_ROP 0x08000000 /* RX oversize packets */
|
||||
#define EMAC_RMR_RPIR 0x04000000 /* RX packets w/ inrange error */
|
||||
#define EMAC_RMR_PPP 0x02000000 /* Propagate pause packets */
|
||||
#define EMAC_RMR_PME 0x01000000 /* Promiscuous mode enable */
|
||||
#define EMAC_RMR_PMME 0x00800000 /* Promiscuous multicast mode */
|
||||
#define EMAC_RMR_IAE 0x00400000 /* Individual address enable */
|
||||
#define EMAC_RMR_MIAE 0x00200000 /* Multiple individual address */
|
||||
#define EMAC_RMR_BAE 0x00100000 /* Broadcast address enable */
|
||||
#define EMAC_RMR_MAE 0x00080000 /* Multicast address enable */
|
||||
#define EMAC_RMR_RFAF 0x00000007 /* Rx Fifo Almost Full */
|
||||
#define EMAC_RMR_RFAF_DIS 0x00000007 /* '111'b disables */
|
||||
|
||||
/*
|
||||
* EMAC Interrupt Status & Enable registers bit definitions
|
||||
*/
|
||||
/* RX bits */
|
||||
#define EMAC_ISR_OVR 0x02000000 /* Overrun error */
|
||||
#define EMAC_ISR_PP 0x01000000 /* Pause packet received */
|
||||
#define EMAC_ISR_BP 0x00800000 /* Bad packet */
|
||||
#define EMAC_ISR_RP 0x00400000 /* Runt packet */
|
||||
#define EMAC_ISR_SE 0x00200000 /* Short event */
|
||||
#define EMAC_ISR_SYE 0x00100000 /* Symbol error */
|
||||
#define EMAC_ISR_BFCS 0x00080000 /* Bad FCS */
|
||||
#define EMAC_ISR_PTLE 0x00040000 /* Packet too long */
|
||||
#define EMAC_ISR_ORE 0x00020000 /* Out of range error */
|
||||
#define EMAC_ISR_IRE 0x00010000 /* In range error */
|
||||
/* TX bits */
|
||||
#define EMAC_ISR_DBDM 0x00000200 /* Dead bit TX dependent mode */
|
||||
#define EMAC_ISR_DB0 0x00000100 /* Dead bit TX channel 0 */
|
||||
#define EMAC_ISR_SE0 0x00000080 /* SQE error TX channel 0 */
|
||||
#define EMAC_ISR_TE0 0x00000040 /* TX error channel 0 */
|
||||
#define EMAC_ISR_DB1 0x00000020 /* Dead bit TX channel 1 */
|
||||
#define EMAC_ISR_SE1 0x00000010 /* SQE error TX channel 1 */
|
||||
#define EMAC_ISR_TE1 0x00000008 /* TX error channel 1 */
|
||||
#define EMAC_ISR_MOS 0x00000002 /* MMA operation succeeded */
|
||||
#define EMAC_ISR_MOF 0x00000001 /* MMA operation failed */
|
||||
#define EMAC_ISR_NO_INTS 0x00000000 /* No interrupts */
|
||||
|
||||
/* The set of bits above we want to cause an Ethernet interrupt for RX error */
|
||||
|
||||
#define EMAC_ISR_RX_INTS 0
|
||||
|
||||
/* The set of bits above we want to cause an Ethernet interrupt for TX error */
|
||||
|
||||
#define EMAC_ISR_TX_INTS 0
|
||||
|
||||
/*
|
||||
* EMAC MII station management unit (STA Control) register bit definitions
|
||||
*/
|
||||
#define EMAC_STACR_OC 0x00008000 /* Operation complete */
|
||||
#define EMAC_STACR_PHYE 0x00004000 /* PHY error */
|
||||
#define EMAC_STACR_WRITE 0x00002000 /* STA command WRITE */
|
||||
#define EMAC_STACR_READ 0x00001000 /* STA command READ */
|
||||
|
||||
/* Walnut / Ebony only */
|
||||
#define EMAC_STACR_CLK_50MHZ 0x00000000 /* OPB bus clock freq 50MHz */
|
||||
#define EMAC_STACR_CLK_83MHZ 0x00000800 /* OPB bus clock freq 83MHz */
|
||||
#define EMAC_STACR_CLK_66MHZ 0x00000400 /* OPB bus clock freq 66MHz */
|
||||
#define EMAC_STACR_CLK_100MHZ 0x00000C00 /* OPB bus clock freq 100MHz */
|
||||
|
||||
/*
|
||||
* EMAC Transmit Request Threshold Register bit definitions
|
||||
*/
|
||||
#define EMAC_TRTR_64 0x00000000
|
||||
#define EMAC_TRTR_128 0x01000000
|
||||
#define EMAC_TRTR_192 0x02000000
|
||||
#define EMAC_TRTR_256 0x03000000
|
||||
#define EMAC_TRTR_1024 0x0F000000
|
||||
#define EMAC_TRTR_1536 0x17000000
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
#else
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCibmEmacEndh */
|
||||
@@ -0,0 +1,745 @@
|
||||
/* fei82557End.h - Intel 82557 network interface header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997-2001, 2003-2005, 2007 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01s,19jul07,d_l change N_MCAST from 12 to 24.(WIND00093549)
|
||||
01r,16feb05,pmr macrotized the 32-byte alignment used by device.
|
||||
01q,26jan05,pmr SPR 102537: make CFD_SIZE a multiple of cache line size.
|
||||
01p,17may04,mdo Add include file to fix compilation error when included in
|
||||
the wrSbc405gp BSP
|
||||
01o,26mar04,dlk Fix incorrect usage of 'volatile' keyword.
|
||||
01n,28jan04,wap Add checksum offload support
|
||||
01m,24feb03,rcs added added definition of RFD_DESC_SIZE SPR#86352
|
||||
01l,23jan03,rcs Added RBD_TAG struct
|
||||
01k,20sep01,dat Removing ANSI errors for diab compiler
|
||||
01j,28sep00,jgn remove physical to virtual translations (SPR 34891)
|
||||
01i,13sep00,jkf T3 SPR#33822 (aka T2 SPR's 33792, 33795, and 33796)
|
||||
01i,11jun00,ham removed reference to etherLib.
|
||||
01h,06nov99,dat Merge from tor3_x.bsp_drv_facility branch
|
||||
01g,12nov99,mas added typecasting to non-PPC FEI_XXXX_RD macros (SPR 24474)
|
||||
01f,21mar99,jkf Added PPC access routines needed for Yellowknife.
|
||||
01e,21jul98,cn Moved here some redefineable macros
|
||||
01d,01apr98,cn added vendor and device id definitions
|
||||
01c,11mar98,cn checked-in
|
||||
01b,05mar98,cn code clean-up after code review
|
||||
01a,07nov97,cn created from ../netif/if_fei.h, version 01c
|
||||
*/
|
||||
|
||||
#ifndef __INCfei82557Endh
|
||||
#define __INCfei82557Endh
|
||||
|
||||
/* includes */
|
||||
#include "netBufLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if ((CPU_FAMILY==I960) && (defined __GNUC__))
|
||||
#pragma align 1 /* tell gcc960 not to optimize alignments */
|
||||
#endif /* CPU_FAMILY==I960 */
|
||||
|
||||
/* defines */
|
||||
|
||||
/*
|
||||
* redefine the macro below in the bsp if you need to access the device
|
||||
* registers/descriptors in a more suitable way.
|
||||
*/
|
||||
|
||||
|
||||
#if (CPU_FAMILY == PPC)
|
||||
|
||||
#ifndef FEI_LONG_WR
|
||||
#define FEI_LONG_WR(addr, value) (sysOutLong ((ULONG) addr, (ULONG) value))
|
||||
#endif
|
||||
|
||||
#ifndef FEI_WORD_WR
|
||||
#define FEI_WORD_WR(addr, value) (sysOutWord ((ULONG) addr, (USHORT) value))
|
||||
#endif
|
||||
|
||||
#ifndef FEI_BYTE_WR
|
||||
#define FEI_BYTE_WR(addr, value) (sysOutByte ((ULONG) addr, (UCHAR) value))
|
||||
#endif
|
||||
|
||||
#ifndef FEI_LONG_RD
|
||||
#define FEI_LONG_RD(addr, value) (value = sysInLong ((ULONG) addr))
|
||||
#endif
|
||||
|
||||
#ifndef FEI_WORD_RD
|
||||
#define FEI_WORD_RD(addr, value) (value = sysInWord ((ULONG) addr))
|
||||
#endif
|
||||
|
||||
#ifndef FEI_BYTE_RD
|
||||
#define FEI_BYTE_RD(addr, value) (value = sysInByte ((ULONG) addr))
|
||||
#endif
|
||||
|
||||
#endif /* CPU_FAMILY == PPC */
|
||||
|
||||
#ifndef FEI_LONG_WR
|
||||
#define FEI_LONG_WR(addr, value) \
|
||||
(* (volatile UINT32 *) (addr) = ((UINT32) FEI_SWAP_LONG (value) ))
|
||||
#endif /* FEI_LONG_WR */
|
||||
|
||||
#ifndef FEI_WORD_WR
|
||||
#define FEI_WORD_WR(addr, value) \
|
||||
(* (volatile UINT16 *) (addr) = ((UINT16) FEI_SWAP_WORD (value) ))
|
||||
#endif /* FEI_WORD_WR */
|
||||
|
||||
#ifndef FEI_BYTE_WR
|
||||
#define FEI_BYTE_WR(addr, value) \
|
||||
(* (volatile UINT8 *) (addr) = (UINT8) (value) )
|
||||
#endif /* FEI_BYTE_WR */
|
||||
|
||||
#ifndef FEI_LONG_RD
|
||||
#define FEI_LONG_RD(addr, value) \
|
||||
do { \
|
||||
UINT32 _temp_ = *(volatile UINT32 *)(addr); \
|
||||
(value) = (UINT32) FEI_SWAP_LONG (_temp_); \
|
||||
} while (0)
|
||||
#endif /* FEI_LONG_RD */
|
||||
|
||||
#ifndef FEI_WORD_RD
|
||||
#define FEI_WORD_RD(addr, value) \
|
||||
do { \
|
||||
UINT16 _temp_ = *(volatile UINT16 *)(addr); \
|
||||
(value) = (UINT16) FEI_SWAP_WORD (_temp_); \
|
||||
} while (0)
|
||||
#endif /* FEI_WORD_RD */
|
||||
|
||||
#ifndef FEI_BYTE_RD
|
||||
#define FEI_BYTE_RD(addr, value) \
|
||||
do { \
|
||||
(value) = (UINT8) (*(volatile UINT8 *)(addr)); \
|
||||
} while (0)
|
||||
#endif /* FEI_BYTE_RD */
|
||||
|
||||
/*
|
||||
* Default macro definitions for BSP interface.
|
||||
* These macros can be redefined in a wrapper file, to generate
|
||||
* a new module with an optimized interface.
|
||||
*/
|
||||
|
||||
#ifndef SYS_INT_CONNECT
|
||||
#define SYS_INT_CONNECT(pDrvCtrl, pFunc, arg, pRet) \
|
||||
{ \
|
||||
/* SPR 33796/33822 - init SYS_INT_CONNECT's return value" to ERROR */ \
|
||||
*pRet = ERROR; \
|
||||
\
|
||||
/* SPR 33792 - remove FEI_VECTOR checking from SYS_INT_CONNECT */ \
|
||||
/* SPR 33795 - add feiEndIntConnect NULL checking in SYS_INT_CONNECT */ \
|
||||
if (feiEndIntConnect != NULL) \
|
||||
{ \
|
||||
*pRet = (feiEndIntConnect) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEI_VECTOR (pDrvCtrl)), \
|
||||
(pFunc), (int) (arg)); \
|
||||
} \
|
||||
}
|
||||
#endif /* SYS_INT_CONNECT */
|
||||
|
||||
#ifndef SYS_INT_DISCONNECT
|
||||
#define SYS_INT_DISCONNECT(pDrvCtrl, pFunc, arg, pRet) \
|
||||
{ \
|
||||
/* SPR 33796 - initialize SYS_INT_DISCONNECT's return value to ERROR */ \
|
||||
*pRet = ERROR; \
|
||||
\
|
||||
/* SPR 33792 - remove FEI_VECTOR checking from SYS_INT_DISCONNECT */ \
|
||||
if (feiEndIntDisconnect != NULL) \
|
||||
{ \
|
||||
*pRet = feiEndIntDisconnect ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEI_VECTOR (pDrvCtrl)), \
|
||||
(pFunc)); \
|
||||
} \
|
||||
}
|
||||
#endif /* SYS_INT_DISCONNECT */
|
||||
|
||||
#ifndef SYS_INT_ENABLE
|
||||
#define SYS_INT_ENABLE(pDrvCtrl) \
|
||||
if (FEI_INT_ENABLE (pDrvCtrl)) \
|
||||
((*(FUNCPTR) (FEI_INT_ENABLE (pDrvCtrl))) (pDrvCtrl->unit))
|
||||
#endif /*SYS_INT_ENABLE*/
|
||||
|
||||
#ifndef SYS_INT_DISABLE
|
||||
#define SYS_INT_DISABLE(pDrvCtrl) \
|
||||
if (FEI_INT_DISABLE (pDrvCtrl)) \
|
||||
((*(FUNCPTR) (FEI_INT_DISABLE (pDrvCtrl))) (pDrvCtrl->unit))
|
||||
#endif /*SYS_INT_DISABLE*/
|
||||
|
||||
#ifndef SYS_INT_ACK
|
||||
#define SYS_INT_ACK(pDrvCtrl) \
|
||||
if (FEI_INT_ACK (pDrvCtrl)) \
|
||||
((*(FUNCPTR) (FEI_INT_ACK (pDrvCtrl))) (pDrvCtrl->unit))
|
||||
#endif /*SYS_INT_ACK*/
|
||||
|
||||
#ifndef LOCAL_TO_SYS_ADDR
|
||||
#define LOCAL_TO_SYS_ADDR(unit,localAddr) \
|
||||
((int) pDrvCtrl->board.sysLocalToBus ? \
|
||||
(*pDrvCtrl->board.sysLocalToBus) (unit, localAddr) : localAddr)
|
||||
#endif /* LOCAL_TO_SYS_ADDR */
|
||||
|
||||
#ifndef SYS_TO_LOCAL_ADDR
|
||||
#define SYS_TO_LOCAL_ADDR(unit,sysAddr) \
|
||||
((int) pDrvCtrl->board.sysBusToLocal ? \
|
||||
(*pDrvCtrl->board.sysBusToLocal)(unit, sysAddr) : sysAddr)
|
||||
#endif /* SYS_TO_LOCAL_ADDR */
|
||||
|
||||
/* Intel PRO-100B PCI specific definitions */
|
||||
|
||||
#define PRO100B_PCI_VENDOR_ID 0x8086 /* PCI vendor ID */
|
||||
#define PRO100B_PCI_DEVICE_ID 0x1229 /* PCI device ID */
|
||||
|
||||
#define FEI82557_DEVICE_ID 0x1229 /* 82557 device ID */
|
||||
#define FEI82550_DEVICE_ID 0x9999 /* 82550 pseudo device ID */
|
||||
|
||||
#define MC_FEI MC_EI /* temp */
|
||||
|
||||
#define DEV_NAME "fei"
|
||||
#define DEV_NAME_LEN 4
|
||||
#define DEF_NUM_CFDS 64 /* default number of CFDs */
|
||||
#define DEF_NUM_RFDS 128 /* default number of RFDs */
|
||||
#define FEI_100MBS 100000000 /* bits per sec */
|
||||
#define FEI_10MBS 10000000 /* bits per sec */
|
||||
#define EADDR_LEN 6 /* ethernet address length */
|
||||
#define FEI_ADDR_LEN EADDR_LEN /* ethernet address length */
|
||||
|
||||
#define FEI_ACTION_TMO 0x01 /* action command timeout in seconds */
|
||||
#define FEI_SCB_TMO 0x01 /* SCB command timeout in seconds */
|
||||
#define FEI_INIT_TMO 0x01 /* 557 init timeout in seconds */
|
||||
#define FEI_TX_RESTART_TMO 0x01 /* tx restart watchdog timeout */
|
||||
#define FEI_TCB_TX_THRESH 0x10 /* Tx threshold value */
|
||||
|
||||
/* Cluster Size */
|
||||
#define CLUSTER_SIZE 1536
|
||||
|
||||
/* RFD and CFD size */
|
||||
#define DESC_ALIGN 32
|
||||
#define RFD_SIZE_HDR 16
|
||||
|
||||
/* The RFD wants to be 32 byte aligned so is rounded up to 32 */
|
||||
#define RFD_SIZE_HDR 16
|
||||
#define RFD_SIZE_EXTHDR 16
|
||||
#define RFD_SIZE_PKT (EH_SIZE + ETHERMTU + 2)
|
||||
#define RFD_SIZE_TRAIL RFD_SIZE_PREV + RFD_SIZE_SW_NEXT
|
||||
#define RFD_SIZE_PREV 4
|
||||
#define RFD_SIZE_SW_NEXT 4
|
||||
|
||||
#define RFD_SIZE ROUND_UP ((RFD_SIZE_HDR + \
|
||||
RFD_SIZE_EXTHDR + \
|
||||
RFD_SIZE_PKT + \
|
||||
RFD_SIZE_TRAIL), 4)
|
||||
|
||||
#define RFD_DESC_SIZE DESC_ALIGN
|
||||
|
||||
#define RFD_STATUS_NONE 0x00
|
||||
#define RFD_STATUS_START 0x01
|
||||
#define RFD_STATUS_EL 0x02
|
||||
|
||||
#define FIRST_RFD 0x00
|
||||
#define LAST_RFD 0xff
|
||||
#define MID_RFD 0x12
|
||||
|
||||
|
||||
/* The actual RBD size is 16 bytes but wants to be 32 byte aligned */
|
||||
|
||||
#define RBD_SIZE DESC_ALIGN
|
||||
|
||||
#define RBD_STATUS_FREE 0x00
|
||||
#define RBD_STATUS_DMA 0x01
|
||||
#define RBD_STATUS_MISSED 0x03
|
||||
#define RBD_STATUS_EL_SEEN 0x55
|
||||
#define RBD_STATUS_BAD 0xff
|
||||
#define RBD_FORCE_REQUEUE 0xff
|
||||
|
||||
#define RBD_TAG_FREE 0x00
|
||||
#define RBD_TAG_DMA 0x01
|
||||
#define RBD_TAG_RING 0x02
|
||||
#define RBD_TAG_BAD 0xff
|
||||
|
||||
#define CFD_SIZE_HDR 8
|
||||
#define CFD_SIZE_DUMP 4
|
||||
#define CFD_SIZE_MULTIC (2 + (6 * N_MCAST))
|
||||
#define CFD_SIZE_IA 8
|
||||
#define CFD_SIZE_NOP 0
|
||||
#define CFD_SIZE_PKT (EH_SIZE + ETHERMTU + 2)
|
||||
#define CFD_SIZE_TCB (8 + CFD_SIZE_PKT)
|
||||
#define CFD_SIZE_PREV 4
|
||||
#define CFD_SIZE_SW_NEXT 4
|
||||
#define CFD_SIZE_ACTION 1
|
||||
#define CFD_SIZE_TRAIL (CFD_SIZE_PREV + \
|
||||
CFD_SIZE_SW_NEXT + \
|
||||
CFD_SIZE_ACTION)
|
||||
#define CFD_SIZE_CORE CFD_SIZE_TCB
|
||||
|
||||
/* The CFD wants to be 32 byte aligned so is rounded up to 32 */
|
||||
|
||||
#define CFD_SIZE ROUND_UP ((CFD_SIZE_HDR + \
|
||||
CFD_SIZE_CORE + \
|
||||
CFD_SIZE_TRAIL), DESC_ALIGN)
|
||||
|
||||
/* frame descriptors definitions */
|
||||
|
||||
#define CFD_STAT_OFFSET 0x00 /* status word */
|
||||
#define CFD_COMM_OFFSET 0x02 /* command word */
|
||||
#define CFD_NEXT_OFFSET 0x04 /* next frame */
|
||||
#define CFD_PREV_OFFSET (CFD_SIZE - 4) /* previous frame */
|
||||
#define CFD_TBD_ADDR_OFFSET 0x08 /* buffer descriptor*/
|
||||
#define CFD_COUNT_OFFSET 0x0c /* count field */
|
||||
#define CFD_NUM_OFFSET 0x0f /* buffer num field */
|
||||
#define CFD_THRESH_OFFSET 0x0e /* threshold field */
|
||||
|
||||
/*
|
||||
* Extended CFD offsets (present in 82550 and 82551 only). These
|
||||
* are used when we issue an IPCB transmit command, which gives us
|
||||
* extra fields that allow the use of TX checksum offload.
|
||||
*/
|
||||
#define CFD_SCHEDLO_OFFSET 0x10 /* 16 bits */
|
||||
#define CFD_IPSCHED_OFFSET 0x12 /* 8 bits */
|
||||
#define CFD_IPACTIVATEHI_OFFSET 0x13 /* 8 bits */
|
||||
#define CFD_VLAN_OFFSET 0x14 /* 16 bits */
|
||||
#define CFD_IPHDROFF_OFFSET 0x16 /* 8 bits */
|
||||
#define CFD_TCPUDPHDROFF_OFFSET 0x17 /* 8 bits */
|
||||
#define CFD_TBDZEROPTR_OFFSET 0x18 /* 32 bits */
|
||||
#define CFD_TBDZEROSIZE_OFFSET 0x1C /* 16 bits */
|
||||
#define CFD_TOTALTCPLEN_OFFSET 0x1E /* 16 bits */
|
||||
|
||||
#define CFD_ACTION_OFFSET (CFD_SIZE - 9) /* action/transmit */
|
||||
#define CFD_SW_NEXT_OFFSET (CFD_SIZE - 8) /* s/w next link */
|
||||
#define CFD_PKT_OFFSET (CFD_SIZE_HDR + 8) /* packet data */
|
||||
#define CFD_IA_OFFSET CFD_SIZE_HDR /* individual address */
|
||||
#define CFD_MCOUNT_OFFSET CFD_SIZE_HDR /* mcount field */
|
||||
#define CFD_MC_OFFSET (CFD_SIZE_HDR + 2) /* mcast list */
|
||||
|
||||
#define RFD_STAT_OFFSET 0x00 /* status word */
|
||||
#define RFD_COMM_OFFSET 0x02 /* command word */
|
||||
#define RFD_NEXT_OFFSET 0x04 /* next frame field */
|
||||
#define RFD_PREV_OFFSET (RFD_SIZE - 4) /* previous frame */
|
||||
#define RFD_SW_NEXT_OFFSET (RFD_SIZE - 8) /* s/w next frame */
|
||||
#define RFD_RBD_OFFSET 0x08 /* buffer descriptor */
|
||||
#define RFD_COUNT_OFFSET 0x0c /* count field */
|
||||
#define RFD_SIZE_OFFSET 0x0e /* data size */
|
||||
|
||||
/* Extended RFD offsets (present in 82550 and 82551 only) */
|
||||
#define RFD_VLANID_OFFSET 0x10 /* VLAN ID (16 bits) */
|
||||
#define RFD_RXPARSESTS_OFFSET 0x12 /* 8 bits */
|
||||
#define RFD_RSVD0_OFFSET 0x13 /* 8 bits */
|
||||
#define RFD_SECURITYSTS_OFFSET 0x14 /* 16 bits */
|
||||
#define RFD_CSUMSTS_OFFSET 0x16 /* 8 bits */
|
||||
#define RFD_ZEROCOPYSTS_OFFSET 0x17 /* 8 bits */
|
||||
#define RFD_PAD_OFFSET 0x18 /* 64 bits */
|
||||
|
||||
#define RFD_PKT_OFFSET (RFD_SIZE_HDR) /* packet data*/
|
||||
|
||||
#define RBD_STAT_OFFSET 0x00 /* Count & F flag */
|
||||
#define RBD_EOF_OFFSET 0x02 /* End of Frame */
|
||||
#define RBD_NEXT_OFFSET 0x04 /* Next RBD in list */
|
||||
#define RBD_BUFFER_OFFSET 0x08 /* cluster pointer */
|
||||
#define RBD_CFG_OFFSET 0x0c /* EL & size fields */
|
||||
|
||||
#define RBD_C_EL 0x8000
|
||||
|
||||
#define RBD_EL_MASK 0x8000
|
||||
#define RBD_SIZE_MASK 0x7fff
|
||||
#define RBD_COUNT_MASK 0x3fff
|
||||
|
||||
#define TBD_NOT_USED 0xffffffff /* use semplified mode */
|
||||
#define RBD_NULL_ADDR 0xffffffff /* use flexible mode */
|
||||
|
||||
/* TX-specific constants */
|
||||
|
||||
/* Number of TX frags allowed per transmission. */
|
||||
#define TBD_MAX_FRAGS 32
|
||||
|
||||
/*
|
||||
* We place the transmit buffer array immediately after
|
||||
* the CFD structure, when doing scatter/gather TX DMA.
|
||||
*/
|
||||
#define CFD_TBD_OFFSET 0x10
|
||||
#define CFD_TBD_OFFSET_TxCB 0x20
|
||||
#define CFD_TBD_OFFSET_IPCB 0x20
|
||||
#define CFD_FRAG1_OFFSET CFD_TBD_OFFSET
|
||||
#define CFD_FRAG1_OFFSET_TxCB CFD_TBD_OFFSET
|
||||
#define CFD_FRAG1_OFFSET_IPCB 0x18
|
||||
|
||||
/* A fragment address/length pair is 8 bytes long (two 32-bit words). */
|
||||
#define TBD_SIZE 8
|
||||
|
||||
/*
|
||||
* A fragment addrees/length pair contains a 32-bit physical address
|
||||
* pointer, followed by a 32-bit length field.
|
||||
*/
|
||||
#define TBD_ADDR_OFFSET 0x00
|
||||
#define TBD_LEN_OFFSET 0x04
|
||||
|
||||
/* IPCB flags */
|
||||
|
||||
#define IPCB_IP_CHECKSUM_ENABLE 0x10
|
||||
#define IPCB_TCPUDP_CHECKSUM_ENABLE 0x20
|
||||
#define IPCB_TCP_PACKET 0x40
|
||||
#define IPCB_LARGESEND_ENABLE 0x80
|
||||
#define IPCB_HARDWAREPARSING_ENABLE 0x01
|
||||
#define IPCB_INSERTVLAN_ENABLE 0x02
|
||||
#define IPCB_IP_ACTIVATION_DEFAULT IPCB_HARDWAREPARSING_ENABLE
|
||||
|
||||
#define IPCB_DEFAULT (/*IPCB_TCPUDP_CHECKSUM_ENABLE*/0 | \
|
||||
IPCB_IP_CHECKSUM_ENABLE | \
|
||||
(IPCB_HARDWAREPARSING_ENABLE << 8))
|
||||
|
||||
/*
|
||||
* We also need to save a pointer to the mBlk so we
|
||||
* can reap it later. We can place it after the TFD array.
|
||||
*/
|
||||
#define CFD_MBLK_OFFSET CFD_TBD_OFFSET + (TBD_SIZE * (TBD_MAX_FRAGS + 2))
|
||||
|
||||
|
||||
/*
|
||||
* This bit, if set in the FragLen field, indicates that this
|
||||
* is the last fragment that needs to be processed in this TBD.
|
||||
*/
|
||||
#define TBD_LASTFRAG 0x00008000
|
||||
|
||||
/* TX-specific bits in the status/command fields */
|
||||
|
||||
#define TBD_CTL_SF 0x0008 /* simple/flex mode */
|
||||
#define TBD_CTL_NO_CRC 0x0010 /* no TX CRC */
|
||||
|
||||
#define TBD_STS_DMA_COMPLETE 0x8000 /* TX DMA done for this txcb */
|
||||
#define TBD_STS_TX_OK 0x2000 /* TX done with no error */
|
||||
#define TBD_STS_URUN 0x1000 /* TX underrun */
|
||||
|
||||
/* board specific infomation */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 vector; /* interrupt vector number */
|
||||
UINT32 baseAddr; /* memory base address for CSR */
|
||||
UCHAR enetAddr[6]; /* ethernet address */
|
||||
int (*intEnable)(int unit); /* board specific interrupt enable routine */
|
||||
int (*intDisable)(int unit); /* board specific interrupt disable routine */
|
||||
int (*intAck) (int unit); /* interrupt ack */
|
||||
UINT32 (*sysLocalToBus)(int unit,UINT32 localAdr);
|
||||
UINT32 (*sysBusToLocal)(int unit,UINT32 sysAdr);
|
||||
|
||||
/* configuration parameters, user can override in the BSP */
|
||||
UINT8 phyAddr; /* PHY device address, valid addresses: 0-32 */
|
||||
UINT8 phySpeed;
|
||||
UINT8 phyDpx;
|
||||
UINT8 fill0;
|
||||
|
||||
UINT16 tcbTxThresh;
|
||||
|
||||
UINT16 others; /* allow you write all bits to Mode Control Register in the
|
||||
PHY device, don't touch it unless you know what you're doing. */
|
||||
|
||||
UINT32 spare1;
|
||||
UINT32 spare2;
|
||||
UINT32 spare3;
|
||||
UINT32 spare4;
|
||||
} FEI_BOARD_INFO;
|
||||
|
||||
typedef UINT32 * RFD_ID;
|
||||
typedef UINT32 * RBD_ID;
|
||||
typedef UINT32 * RBD_TAG_ID;
|
||||
|
||||
/*
|
||||
* The read discriptor structure is a place holdes for the actual RFD
|
||||
* used by the device. The driver does not actuall access this area
|
||||
* the structure but uses the macros and offsets provided.
|
||||
*/
|
||||
typedef struct read_disc
|
||||
{
|
||||
UINT32 long1;
|
||||
UINT32 long2;
|
||||
UINT32 long3;
|
||||
UINT32 long4;
|
||||
} RD_DESC;
|
||||
|
||||
/*
|
||||
* The RFD_TAG makes use of the additional 16 bytes of space allocated
|
||||
* for each RFD beyond the 16 bytes used by the device. This space is used
|
||||
* to store information not provided by the device but useful for managing
|
||||
* the flexible mode configuration.
|
||||
*/
|
||||
|
||||
typedef struct rfd_tag
|
||||
{
|
||||
RD_DESC rfd; /* DON'T ACCESS this field */
|
||||
UINT16 index;
|
||||
UINT16 nextIndex;
|
||||
UINT16 spareWord;
|
||||
UINT16 status;
|
||||
RBD_ID pRFD; /* pointer to own pRFD */
|
||||
UINT32 spareLong;
|
||||
} RFD_TAG;
|
||||
|
||||
/*
|
||||
* The RBD_TAG makes use of the additional 16 bytes of space allocated
|
||||
* for each RBD beyond the 16 bytes used by the device. This space is used
|
||||
* to store information not provided by the device but useful for managing
|
||||
* the flexible mode configuration.
|
||||
*/
|
||||
typedef struct rbd_tag
|
||||
{
|
||||
RD_DESC rbd; /* DON'T ACCESS this field */
|
||||
UINT16 index;
|
||||
UINT16 next;
|
||||
M_BLK_ID pMblk;
|
||||
RFD_ID pRFD; /* pointer to self */
|
||||
RBD_ID pRBD; /* pointer to own RBD */
|
||||
} RBD_TAG;
|
||||
|
||||
/* constants needed within this file */
|
||||
|
||||
#define FEI_MAX_UNITS 4 /* max units supported */
|
||||
#define FEI_CFD_DEF 32 /* default number of CFDs */
|
||||
#define FEI_RFD_DEF 32 /* default number of RFDs */
|
||||
#define FEI_RFD_LOAN 8 /* number RFDs that can be loaned */
|
||||
#define EH_SIZE 14 /* avoid structure padding issues */
|
||||
#define N_MCAST 24
|
||||
|
||||
/* SCB registers offset definitions @@@ */
|
||||
#define SCB_STATUS 0x00 /* SCB status byte */
|
||||
#define SCB_CMD 0x02 /* SCB command byte */
|
||||
#define SCB_POINTER 0x04 /* SCB pointer */
|
||||
#define SCB_PORT 0x08 /* SCB port register */
|
||||
#define SCB_FLASH 0x0c /* SCB flash control register */
|
||||
#define SCB_EEPROM 0x0e /* SCB eeprom control register */
|
||||
#define SCB_MDI 0x10 /* SCB mdi control register */
|
||||
#define SCB_EARLYRX 0x14 /* SCB early receive */
|
||||
|
||||
/* SCB Status Word byte mask definitions */
|
||||
|
||||
#define SCB_S_RUMASK 0x3c /* RU status mask */
|
||||
#define SCB_S_RUIDLE 0x00 /* RU is idle */
|
||||
#define SCB_S_RUSUSP 0x04 /* RU is suspended */
|
||||
#define SCB_S_RUNORSR 0x08 /* RU no more resources */
|
||||
#define SCB_S_RURDY 0x10 /* RU is ready */
|
||||
#define SCB_S_RUSUSPNR 0x24 /* RU is suspended/no more resources */
|
||||
#define SCB_S_RUNORSRBD 0x28 /* RU no more resources/no more RBD's */
|
||||
#define SCB_S_RURDYBD 0x30 /* RU is ready/no more RBD's */
|
||||
#define SCB_S_CUMASK 0xc0 /* CU status mask */
|
||||
#define SCB_S_CUIDLE 0x00 /* CU is idle */
|
||||
#define SCB_S_CUSUSP 0x40 /* CU is suspended */
|
||||
#define SCB_S_CUACTIVE 0x80 /* CU is active */
|
||||
#define SCB_S_MASK 0xff
|
||||
|
||||
/* SCB STAT/ACK byte bit mask definitions */
|
||||
|
||||
#define SCB_S_STATMASK 0xfc00 /* stat mask */
|
||||
#define SCB_S_SWI 0x0400 /* software generated interrupt */
|
||||
#define SCB_S_MDI 0x0800 /* An MDI read or write cycle is done */
|
||||
#define SCB_S_RNR 0x1000 /* RU left the ready state */
|
||||
#define SCB_S_CNA 0x2000 /* CU left the active state */
|
||||
#define SCB_S_CI 0x2000 /* CU entered the idle state */
|
||||
#define SCB_S_FR 0x4000 /* RU finished receiveing a frame */
|
||||
#define SCB_S_CX 0x8000 /* CU finished a cmd with I bit set */
|
||||
#define SCB_S_TNO 0x8000 /* Tx command ended with not OK */
|
||||
|
||||
/* SCB Command byte bit mask definitions */
|
||||
|
||||
#define SCB_C_RUMASK 0x07 /* RU Command mask */
|
||||
#define SCB_C_RUNOP 0x00 /* NOP */
|
||||
#define SCB_C_RUSTART 0x01 /* RU start reception of frames */
|
||||
#define SCB_C_RURESUME 0x02 /* RU resume reception of frames */
|
||||
#define SCB_C_RUABORT 0x04 /* RU abort receiver immediately */
|
||||
#define SCB_C_RULDHDS 0x05 /* RU load header data size */
|
||||
#define SCB_C_RULDBASE 0x06 /* load RU base address */
|
||||
#define SCB_C_RURBDRSM 0x07 /* RBD resume */
|
||||
#define SCB_C_CUMASK 0x70 /* CU Command mask */
|
||||
#define SCB_C_CUNOP 0x00 /* NOP */
|
||||
#define SCB_C_CUSTART 0x10 /* CU start execution */
|
||||
#define SCB_C_CURESUME 0x20 /* CU resume execution */
|
||||
#define SCB_C_CULDDUMP 0x40 /* load dump counters address */
|
||||
#define SCB_C_CUDUMP 0x50 /* dump stat counters */
|
||||
#define SCB_C_CULDBASE 0x60 /* load CU base address */
|
||||
#define SCB_C_CUDUMPRST 0x70 /* dump and reset stat counters */
|
||||
#define SCB_CR_MASK 0xff
|
||||
|
||||
/* SCB Interrupt Control byte bit mask definitions */
|
||||
|
||||
#define SCB_C_M 0x01 /* interrupt mask */
|
||||
#define SCB_C_SI 0x02 /* software generated interrupt */
|
||||
#define SCB_C_RNR 0x10 /* RU ran out of resources */
|
||||
#define SCB_C_CNA 0x20 /* CU left active state (transmit) */
|
||||
#define SCB_C_FR 0x40 /* frame receive */
|
||||
|
||||
/* PORT commands */
|
||||
|
||||
#define FEI_PORT_RESET 0x0 /* PORT reset command */
|
||||
#define FEI_PORT_SELFTEST 0x1 /* PORT selftest command */
|
||||
#define FEI_PORT_SELRESET 0x2 /* PORT selective reset command */
|
||||
#define FEI_PORT_DUMP 0x3 /* PORT dump command */
|
||||
|
||||
/* Action Command Descriptions */
|
||||
|
||||
/* special TCB-specific command block bit mask definitions */
|
||||
|
||||
#define CFD_S_TX_DMA_U 0x1000 /* DMA underrun */
|
||||
#define TCB_CNT_EOF 0x8000 /* all data kept in TFD */
|
||||
#define CFD_C_TX_FLEX 0x0008 /* use flexible mode */
|
||||
|
||||
|
||||
/* special Diag-specific command block bit mask definitions */
|
||||
|
||||
#define CFD_S_DIAG_F 0x0800 /* diag failed */
|
||||
|
||||
/* Command Frame Description and defines */
|
||||
|
||||
/* Action Status Word bit mask definitions */
|
||||
|
||||
#define CFD_S_OK 0x2000 /* Command completed successfully */
|
||||
#define CFD_S_B 0x4000 /* CU starts access this CFD */
|
||||
#define CFD_S_COMPLETE 0x8000 /* Command complete */
|
||||
|
||||
/* Action Command Word bit mask definitions */
|
||||
|
||||
#define CFD_C_NOP 0x0000 /* No Operation */
|
||||
#define CFD_C_IASETUP 0x0001 /* Individual Address Setup */
|
||||
#define CFD_C_CONFIG 0x0002 /* Configure Chip */
|
||||
#define CFD_C_MASETUP 0x0003 /* Multicast Setup */
|
||||
#define CFD_C_XMIT 0x0004 /* Transmit (see below too ...) */
|
||||
#define CFD_C_DUMP 0x0006 /* Dump Registers */
|
||||
#define CFD_C_DIAG 0x0007 /* Diagnose */
|
||||
#define CFD_C_LOADFILT 0x0008
|
||||
#define CFD_C_IPCBXMIT 0x0009 /* hardware offload transmit */
|
||||
#define CFD_C_CID 0x1F00 /* Delay CNA interrupt */
|
||||
#define CFD_C_INT 0x2000 /* 557 interrupts CPU after execution */
|
||||
#define CFD_C_SUSP 0x4000 /* CU should suspend after execution */
|
||||
#define CFD_C_EL 0x8000 /* End of command list */
|
||||
|
||||
/* 82557 Receive Frame Descriptors */
|
||||
|
||||
/* RFD bit mask definitions */
|
||||
|
||||
#define RFD_S_COLL 0x0001 /* collision during reception */
|
||||
#define RFD_S_IA 0x0002 /* individual address match */
|
||||
#define RFD_S_NOAMATCH 0x0004 /* doesn't match anything */
|
||||
#define RFD_S_HWPARSE 0x0008 /* hardware parsed frame */
|
||||
#define RFD_S_RXER 0x0010 /* receive error */
|
||||
#define RFD_S_LEN 0x0020 /* type/len field designator */
|
||||
#define RFD_S_SHORT 0x0080 /* frame too short */
|
||||
#define RFD_S_DMA 0x0100 /* DMA Overrun failure to get bus */
|
||||
#define RFD_S_RSRC 0x0200 /* received, but ran out of buffers */
|
||||
#define RFD_S_ALGN 0x0400 /* received misaligned with CRC error */
|
||||
#define RFD_S_CRC 0x0800 /* received with CRC error */
|
||||
#define RFD_S_OK 0x2000 /* frame received successfully */
|
||||
#define RFD_S_B 0x4000 /* RU begins accessing this RFD */
|
||||
#define RFD_S_COMPLETE 0x8000 /* frame reception complete */
|
||||
|
||||
#define RFD_C_FLEX 0x0008 /* flexible mode */
|
||||
#define RFD_C_HEADER 0x10 /* frame is a header */
|
||||
#define RFD_C_SUSP 0x4000 /* suspend RU after receiving frame */
|
||||
#define RFD_C_EL 0x8000 /* end of RFD list */
|
||||
|
||||
#define RFD_CNT_F 0x4000 /* actual count updated */
|
||||
#define RFD_CNT_EOF 0x80 /* end of frame */
|
||||
|
||||
/*
|
||||
* Extended RFD definitions relating to TCP/IP checksum offload
|
||||
* (82550/82551 only)
|
||||
*/
|
||||
|
||||
/* Bits in the 'csum' byte */
|
||||
#define RFD_CS_TCPUDP_CHECKSUM_BIT_VALID 0x10
|
||||
#define RFD_CS_TCPUDP_CHECKSUM_VALID 0x20
|
||||
#define RFD_CS_IP_CHECKSUM_BIT_VALID 0x01
|
||||
#define RFD_CS_IP_CHECKSUM_VALID 0x02
|
||||
|
||||
/* Bits in the 'packet parser' byte */
|
||||
#define RFD_P_PARSE_BIT 0x08
|
||||
#define RFD_P_CHECKSUM_PROTOCOL_MASK 0x03
|
||||
#define RFD_P_TCP_PACKET 0x00
|
||||
#define RFD_P_UDP_PACKET 0x01
|
||||
#define RFD_P_IP_PACKET 0x03
|
||||
|
||||
typedef volatile UINT32 * FD_ID;
|
||||
typedef volatile UINT32 * CSR_ID;
|
||||
typedef FD_ID CFD_ID;
|
||||
|
||||
/* Configuration definitions */
|
||||
|
||||
#define FEI_BYTE_COUNT 0x16 /* the number of Command Block bytes */
|
||||
#define FEI_RX_FIFO 0x08 /* Receive FIFO limit */
|
||||
#define FEI_TX_FIFO 0x00 /* Transmit FIFO limit */
|
||||
#define FEI_ADAPT_IFS 0x00 /* Adaptive IFS */
|
||||
#define FEI_MWI_ENABLE 0x01 /* Enable MWI */
|
||||
#define FEI_RD_ALIGN 0x02 /* Read alignment Enabled */
|
||||
#define FEI_RX_MAX_DMA 0x00 /* RX DMA Max Byte Count(not enabled) */
|
||||
#define FEI_TX_MAX_DMA 0x00 /* TX DMA Max Byte Count(not enabled) */
|
||||
#define FEI_MAX_DMA_EN 0x00 /* Enable DMA Max Byte Counts */
|
||||
|
||||
|
||||
|
||||
|
||||
/* EEPROM bit definitions */
|
||||
|
||||
#define FEI_EESK 0x01 /* EEPROM shift clock */
|
||||
#define FEI_EECS 0x02 /* EEPROM chip select */
|
||||
#define FEI_EEDI 0x04 /* EEPROM data in */
|
||||
#define FEI_EEDO 0x08 /* EEPROM data out */
|
||||
|
||||
|
||||
/* Following defines should be in another header file */
|
||||
|
||||
/* MDI definitions */
|
||||
|
||||
#define MDI_READ 0x2
|
||||
#define MDI_WRITE 0x1
|
||||
#define MDI_CTRL_REG 0x0
|
||||
#define MDI_STATUS_REG 0x1
|
||||
|
||||
/* MDI control register bit */
|
||||
#define MDI_CR_COLL_TEST 0x80
|
||||
#define MDI_CR_FDX 0x100 /* FDX =1, half duplex =0 */
|
||||
#define MDI_CR_RESTART 0x200 /* restart auto negotiation */
|
||||
#define MDI_CR_ISOLATE 0x400 /* isolate PHY from MII */
|
||||
#define MDI_CR_POWER_DOWN 0x800 /* power down */
|
||||
#define MDI_CR_SELECT 0x1000 /* auto speed select */
|
||||
#define MDI_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
|
||||
#define MDI_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MDI_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
|
||||
/* MDI Status register bit definitions */
|
||||
#define MDI_SR_LINK_STATUS 0x4 /* link Status -- 1 = link */
|
||||
#define MDI_SR_AUTO_SELECT 0x8 /* auto speed select capable */
|
||||
#define MDI_SR_REMOTE_FAULT 0x10 /* Remote fault detect */
|
||||
#define MDI_SR_AUTO_NEG 0x20 /* auto negotiation complete */
|
||||
#define MDI_SR_10T_HALF_DPX 0x800 /* 10BaseT half duplex capable */
|
||||
#define MDI_SR_10T_FULL_DPX 0x1000 /* 10BaseT full duplex capable */
|
||||
#define MDI_SR_TX_HALF_DPX 0x2000 /* TX half duplex capable */
|
||||
#define MDI_SR_TX_FULL_DPX 0x4000 /* TX full duplex capable */
|
||||
#define MDI_SR_T4 0x8000 /* T4 capable */
|
||||
|
||||
#define PHY_100MBS 1
|
||||
#define PHY_10MBS 0
|
||||
#define PHY_AUTO_SPEED 2
|
||||
|
||||
#define PHY_FULL_DPX 1
|
||||
#define PHY_HALF_DPX 0
|
||||
#define PHY_AUTO_DPX 2
|
||||
|
||||
#define PHY_LINK_ERROR 0x10
|
||||
#define PHY_AUTO_FAIL 0x20
|
||||
|
||||
/* PRO/100B definitions */
|
||||
|
||||
#define EP100B_PCI_VENDOR_ID 0x8086 /* Intel vendor ID */
|
||||
#define EP100B_PCI_DEVICE_ID 0x1229 /* PRO/100B device ID */
|
||||
|
||||
#if ((CPU_FAMILY==I960) && (defined __GNUC__))
|
||||
#pragma align 0 /* turn off alignment requirement */
|
||||
#endif /* CPU_FAMILY==I960 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCfei82557Endh */
|
||||
|
||||
@@ -0,0 +1,873 @@
|
||||
/* gei82543End.h - Intel 8254x network interface header */
|
||||
|
||||
/* Copyright 1990-2002, 2013 Wind River Systems, Inc. */
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
13dec13,xms Support 82545 network card. (WIND00446795)
|
||||
01l,11aug05,dlk Add support for IPv6 checksum offload.
|
||||
01k,04jun04,jln add new flags: GEI_END_FORCE_FLUSH_CACHE and
|
||||
GEI_END_FORCE_INVALIDATE_CACHE
|
||||
01j,08may04,dlk Remove txType field from TX_DESCTL.
|
||||
Remove DEFAULT_MBLK_NUM_FACTOR, must be same as
|
||||
DEFAULT_LOAN_RXBUF_FACTOR for linkBuf/netTupleGet use.
|
||||
01i,02feb04,wap Add checksum offload support
|
||||
01h,19dec02,jln add PHY BSP call hook for 82543-copper (SPR 84779)
|
||||
01g,28may02,jln add TX_RESTART_TRUE and TX_RESTART_NONE
|
||||
01f,20apr02,jln support 82540/5/6 spr # 76739
|
||||
01e,31jan02,jln change len of device name (spr#73010)
|
||||
01d,05dec01,jln add definitions for TBI compatibility workaround
|
||||
01c,01oct01,jln move device ID definition to sysGei82543End.c
|
||||
01b,01apr01,jln clean up after code review (partial spr#65326)
|
||||
01a,08Jan01,jln written
|
||||
*/
|
||||
|
||||
#ifndef __INCGEI82543Endh
|
||||
#define __INCGEI82543Endh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include "etherLib.h"
|
||||
#include "miiLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if ((CPU_FAMILY==I960) && (defined __GNUC__))
|
||||
#pragma align 1 /* tell gcc960 not to optimize alignments */
|
||||
#endif /* CPU_FAMILY==I960 */
|
||||
|
||||
/* define */
|
||||
|
||||
#define UNKNOWN -1
|
||||
|
||||
#ifndef PHYS_TO_BUS_ADDR
|
||||
#define PHYS_TO_BUS_ADDR(unit,physAddr) \
|
||||
((int) pDrvCtrl->adaptor.sysLocalToBus ? \
|
||||
(*pDrvCtrl->adaptor.sysLocalToBus) (unit, physAddr) : physAddr)
|
||||
#endif /* PHYS_TO_BUS_ADDR */
|
||||
|
||||
#ifndef BUS_TO_PHYS_ADDR
|
||||
#define BUS_TO_PHYS_ADDR(unit,busAddr) \
|
||||
((int) pDrvCtrl->adaptor.sysBusToLocal ? \
|
||||
(*pDrvCtrl->adaptor.sysBusToLocal)(unit, busAddr) : busAddr)
|
||||
#endif /* BUS_TO_PHYS_ADDR */
|
||||
|
||||
#define TX_DESC_TYPE_CLEAN 0 /* TX descriptor type */
|
||||
#define TX_DESC_TYPE_COPY 1 /* -- copy/chain/EOP */
|
||||
#define TX_DESC_TYPE_CHAIN 2
|
||||
#define TX_DESC_TYPE_EOP 3
|
||||
|
||||
/* TX descriptors structure */
|
||||
|
||||
#define TXDESC_BUFADRLOW_OFFSET 0 /* buf mem low offset */
|
||||
#define TXDESC_BUFADRHIGH_OFFSET 4 /* buf mem high offset */
|
||||
#define TXDESC_LENGTH_OFFSET 8 /* buf length offset */
|
||||
#define TXDESC_CSO_OFFSET 10 /* checksum offset */
|
||||
#define TXDESC_CMD_OFFSET 11 /* command offset */
|
||||
#define TXDESC_STATUS_OFFSET 12 /* status offset */
|
||||
#define TXDESC_CSS_OFFSET 13 /* cksum start */
|
||||
#define TXDESC_SPECIAL_OFFSET 14 /* special field */
|
||||
#define TXDESC_SIZE 16 /* descriptor size */
|
||||
|
||||
#ifdef notdef
|
||||
#define TXDESC_CTX_IPCSS_OFFSET 0 /* CXT descriptor IPCSS */
|
||||
#define TXDESC_CTX_TUCSS_OFFSET 4 /* CXT descriptor TUCSS */
|
||||
#endif
|
||||
/*
|
||||
* Extended TCP/IP Context TX descriptor structure.
|
||||
* Identified by DEXT bit = 1 in TUCMD field, and DTYP = 0000b
|
||||
*/
|
||||
|
||||
#define TXDESC_CTX_IPCSS_OFFSET 0 /* IP checksum start offset */
|
||||
#define TXDESC_CTX_IPCSO_OFFSET 1 /* IP checksum offset offset */
|
||||
#define TXDESC_CTX_IPCSE_OFFSET 2 /* IP checksum end offset */
|
||||
#define TXDESC_CTX_TUCSS_OFFSET 4 /* TCP/UDP checksum start offset */
|
||||
#define TXDESC_CTX_TUCSO_OFFSET 5 /* TCP/UDP cksum. offset offset */
|
||||
#define TXDESC_CTX_TUCSE_OFFSET 6 /* TCP/UDP checksum end offset */
|
||||
/*
|
||||
* The PKTLEN field is 20 bits, and DTYP is 4 bits. DTYP appears in the
|
||||
* High-order 4 bits of the byte at offset 10.
|
||||
*/
|
||||
#define TXDESC_CTX_PKTLEN_OFFSET 8 /* Packet len for segmentation */
|
||||
#define TXDESC_CTX_DTYP_OFFSET 10 /* Descriptor type == 0000b */
|
||||
#define TXDESC_CTX_TUCMD_OFFSET 11 /* context command byte offset */
|
||||
#define TXDESC_CTX_STATUS_OFFSET 12 /* Status nybble byte offset */
|
||||
#define TXDESC_CTX_HDRLEN_OFFSET 13 /* Header length offset (seg) */
|
||||
#define TXDESC_CTX_MSS_OFFSET 14 /* MSS offset (segmentation) */
|
||||
|
||||
/* RX descriptor structure */
|
||||
|
||||
#define RXDESC_BUFADRLOW_OFFSET 0 /* buf mem low offset */
|
||||
#define RXDESC_BUFADRHIGH_OFFSET 4 /* buf mem high offset */
|
||||
#define RXDESC_LENGTH_OFFSET 8 /* length offset */
|
||||
#define RXDESC_CHKSUM_OFFSET 10 /* cksum offset */
|
||||
#define RXDESC_STATUS_OFFSET 12 /* status offset */
|
||||
#define RXDESC_ERROR_OFFSET 13 /* error offset */
|
||||
#define RXDESC_SPECIAL_OFFSET 14 /* special offset */
|
||||
#define RXDESC_SIZE 16 /* descriptor size */
|
||||
|
||||
#define TX_ETHER_PHY_SIZE (EH_SIZE + ETHERMTU + 2)
|
||||
|
||||
#define PRO1000_PCI_VENDOR_ID 0x8086 /* Intel vendor ID */
|
||||
#define PRO1000_PCI_DEVICE_ID 0x1001 /* device ID */
|
||||
#define PRO1000F_PCI_SUBSYSTEM_ID 0x1003 /* device subsystem ID */
|
||||
#define PRO1000T_PCI_SUBSYSTEM_ID 0x1004
|
||||
#define PRO1000T_PCI_DEVICE_ID 0x1004 /* bizard case */
|
||||
#define PRO1000F_BOARD 0x1003 /* backward compatible */
|
||||
#define PRO1000T_BOARD 0x1003 /* backward compatible */
|
||||
#define INTEL_PCI_VENDOR_ID 0x8086
|
||||
|
||||
#define PRO1000_546_BOARD 0x100e /* 82540/82545/82546 MAC */
|
||||
#define PRO1000_544_BOARD 0x1008 /* 82544 MAC */
|
||||
#define PRO1000_543_BOARD 0x1003 /* 82543 MAC */
|
||||
#define PRO1000_545_BOARD 0x1026 /* 82545 GM MAC */
|
||||
|
||||
#define GEI_COPPER_MEDIA 1
|
||||
#define GEI_FIBER_MEDIA 2
|
||||
|
||||
#define GEI_PHY_GMII_TYPE 1
|
||||
|
||||
#define DEFAULT_RXRES_PROCESS_FACTOR 2
|
||||
#define DEFAULT_TIMER_INTERVAL 2 /* 2 seconds */
|
||||
#define DEFAULT_DRV_FLAGS 0
|
||||
#define DEFAULT_LOAN_RXBUF_FACTOR 4
|
||||
#define DEFAULT_MBUF_COPY_SIZE 256
|
||||
#define DEFAULT_NUM_TXDES 24
|
||||
#define DEFAULT_NUM_RXDES 24
|
||||
#define DEFAULT_RXINT_DELAY 0
|
||||
#define DEFAULT_MULTI_FILTER_TYPE MULTI_FILTER_TYPE_47_36
|
||||
#define DEFAULT_FLOW_CONTRL FLOW_CONTRL_HW
|
||||
#define DEFAULT_TX_REPORT TX_REPORT_RS
|
||||
#define DEFAULT_TIPG_IPGT_F 6
|
||||
#define DEFAULT_TIPG_IPGT_T 8
|
||||
#define DEFAULT_TIPG_IPGR1 8
|
||||
#define DEFAULT_TIPG_IPGR2 6
|
||||
|
||||
#define GEI543_MAX_DEV_UNIT 4
|
||||
|
||||
/* flags available to config system */
|
||||
|
||||
#define GEI_END_SET_TIMER 0x0001 /* use a watchdog timer */
|
||||
#define GEI_END_SET_RX_PRIORITY 0x0002 /* RX has higher priority (543 only) */
|
||||
#define GEI_END_FREE_RESOURCE_DELAY 0x0004 /* allow delay to free loaned TX cluster */
|
||||
#define GEI_END_JUMBO_FRAME_SUPPORT 0x0008 /* Jumbo Frame allowed */
|
||||
#define GEI_END_RX_IP_XSUM 0x0010 /* RX IP XSUM allowed, not supported */
|
||||
#define GEI_END_RX_TCPUDP_XSUM 0x0020 /* RX TCP XSUM allowed, not supported */
|
||||
#define GEI_END_TX_IP_XSUM 0x0040 /* TX IP XSUM allowed, not supported */
|
||||
#define GEI_END_TX_TCPUDP_XSUM 0x0080 /* TX TCP XSUM allowed, not supported */
|
||||
#define GEI_END_TX_TCP_SEGMENTATION 0x0100 /* TX TCP segmentation, not supported */
|
||||
#define GEI_END_TBI_COMPATIBILITY 0x0200 /* TBI compatibility workaround (543 only) */
|
||||
#define GEI_END_USER_MEM_FOR_DESC_ONLY 0x0400 /* cacheable user mem for RX descriptors only */
|
||||
#define GEI_END_FORCE_FLUSH_CACHE 0x1000 /* force flush data cache */
|
||||
#define GEI_END_FORCE_INVALIDATE_CACHE 0x2000 /* force flush data cache */
|
||||
|
||||
#define GEI_END_CSUM (GEI_END_RX_IP_XSUM | GEI_END_TX_IP_XSUM |\
|
||||
GEI_END_RX_TCPUDP_XSUM | GEI_END_TX_TCPUDP_XSUM)
|
||||
|
||||
|
||||
#define GEI_DEFAULT_RXDES_NUM 0x40
|
||||
#define GEI_DEFAULT_TXDES_NUM 0x80
|
||||
#define GEI_DEFAULT_USR_FLAG (GEI_END_SET_TIMER | \
|
||||
GEI_END_SET_RX_PRIORITY | \
|
||||
GEI_END_FREE_RESOURCE_DELAY)
|
||||
|
||||
#define GEI_DEFAULT_ETHERHEADER (SIZEOF_ETHERHEADER)
|
||||
#define GEI_MAX_FRAME_SIZE 16288 /* based on default RX/TX
|
||||
buffer configuration */
|
||||
|
||||
#define GEI_MAX_JUMBO_MTU_SIZE (GEI_MAX_FRAME_SIZE - \
|
||||
GEI_DEFAULT_ETHERHEADER - \
|
||||
ETHER_CRC_LENGTH)
|
||||
|
||||
#define GEI_DEFAULT_JUMBO_MTU_SIZE 9000 /* 9000 bytes */
|
||||
|
||||
#define AVAIL_TX_INT (INT_TXDW_BIT)
|
||||
#define AVAIL_RX_INT (INT_RXO_BIT | INT_RXTO_BIT)
|
||||
#define AVAIL_RX_TX_INT (AVAIL_TX_INT | AVAIL_RX_INT)
|
||||
#define AVAIL_LINK_INT (INT_LSC_BIT)
|
||||
#define INT_LINK_CHECK (AVAIL_LINK_INT | INT_RXCFG_BIT)
|
||||
#define INTEL_82543GC_VALID_INT (AVAIL_RX_TX_INT | INT_LINK_CHECK | INT_TXDLOW_BIT)
|
||||
|
||||
#define MAX_TXINT_DELAY 65536
|
||||
#define MAX_RXINT_DELAY 65536
|
||||
#define MIN_TXINT_DELAY 1
|
||||
#define TXINT_DELAY_LESS 5
|
||||
#define TXINT_DELAY_MORE 512
|
||||
|
||||
#define ETHER_CRC_LENGTH 4
|
||||
#define RX_CRC_LEN ETHER_CRC_LENGTH
|
||||
#define MAX_ETHER_PACKET_SIZE 1514
|
||||
#define MIN_ETHER_PACKET_SIZE 60
|
||||
#define ETHER_ADDRESS_SIZE 6
|
||||
|
||||
#define CARRIER_EXTENSION_BYTE 0x0f
|
||||
|
||||
#define INTEL_82543GC_MTA_NUM 128
|
||||
|
||||
#define INTEL_82543GC_MULTIPLE_DES 8
|
||||
|
||||
#define TX_COLLISION_THRESHOLD 16
|
||||
#define FDX_COLLISION_DISTANCE 64
|
||||
#define HDX_COLLISION_DISTANCE 64
|
||||
#define BIG_HDX_COLLISION_DISTANCE 512
|
||||
|
||||
#define NUM_RAR 16
|
||||
#define NUM_MTA 128
|
||||
#define NUM_VLAN 128
|
||||
#define MAX_NUM_MULTI (NUM_RAR + NUM_MTA - 1)
|
||||
|
||||
#define MULTI_FILTER_TYPE_47_36 0
|
||||
#define MULTI_FILTER_TYPE_46_35 1
|
||||
#define MULTI_FILTER_TYPE_45_34 2
|
||||
#define MULTI_FILTER_TYPE_43_32 3
|
||||
|
||||
#define FLOW_CONTRL_NONE 0
|
||||
#define FLOW_CONTRL_TRANSMIT 1
|
||||
#define FLOW_CONTRL_RECEIVE 2
|
||||
#define FLOW_CONTRL_ALL 3
|
||||
#define FLOW_CONTRL_HW 0xf
|
||||
|
||||
#define TX_REPORT_RS 1
|
||||
#define TX_REPORT_RPS 2
|
||||
|
||||
#define DMA_RX_PRIORITY 1
|
||||
#define DMA_FAIR_RX_TX 2
|
||||
|
||||
#define FULL_DUPLEX_MODE 1
|
||||
#define HALF_DUPLEX_MODE 2
|
||||
#define DUPLEX_HW 3
|
||||
#define DEFAULT_DUPLEX_MODE FULL_DUPLEX_MODE
|
||||
|
||||
#define END_SPEED_10M 10000000 /* 10Mbs */
|
||||
#define END_SPEED_100M 100000000 /* 100Mbs */
|
||||
#define END_SPEED_1000M 1000000000 /* 1000Mbs */
|
||||
#define END_SPEED END_SPEED_1000M
|
||||
|
||||
#define DEVICE_NAME "gei"
|
||||
#define DEVICE_NAME_LENGTH 4
|
||||
|
||||
#define TYPE_PRO1000F_PCI 1
|
||||
#define TYPE_PRO1000T_PCI 2
|
||||
#define GEI82543_HW_AUTO 0x1
|
||||
#define GEI82543_FORCE_LINK 0x2
|
||||
|
||||
/* general flags */
|
||||
|
||||
#define FLAG_POLLING_MODE 0x0001
|
||||
#define FLAG_PROMISC_MODE 0x0002
|
||||
#define FLAG_ALLMULTI_MODE 0x0004
|
||||
#define FLAG_MULTICAST_MODE 0x0008
|
||||
#define FLAG_BROADCAST_MODE 0x0010
|
||||
|
||||
/* misc */
|
||||
|
||||
#define TX_RESTART_NONE 0x4000 /* muxTxRestart not scheduled */
|
||||
#define TX_RESTART_TRUE 0x8000 /* muxTxRestart is scheduled */
|
||||
#define LINK_STATUS_OK 0
|
||||
#define LINK_STATUS_ERROR 1
|
||||
#define LINK_STATUS_UNKNOWN 2
|
||||
#define FREE_ALL_AUTO 1
|
||||
#define FREE_ALL_FORCE 2
|
||||
#define TX_LOAN_TRANSMIT 1
|
||||
#define TX_COPY_TRANSMIT 2
|
||||
#define LINK_TIMEOUT_IN_QUAR_SEC 12 /* 3s */
|
||||
|
||||
#define GEI_MII_PHY_CAP_FLAGS (MII_PHY_10 | MII_PHY_100 | \
|
||||
MII_PHY_FD | MII_PHY_HD | \
|
||||
MII_PHY_1000T_FD)
|
||||
|
||||
/* Offsets of checksum fields within protocol headers */
|
||||
|
||||
#define IP_HDR_CKSUM_OFFSET 10 /* Offset within IP header */
|
||||
#define TCP_HDR_CKSUM_OFFSET 16 /* Offset within TCP header */
|
||||
#define UDP_HDR_CKSUM_OFFSET 6 /* Offset within UDP header */
|
||||
|
||||
/* register area */
|
||||
|
||||
/* TX registers */
|
||||
|
||||
#define INTEL_82543GC_TDBAL 0x3800 /* Tx Descriptor Base Low */
|
||||
#define INTEL_82543GC_TDBAH 0x3804 /* Tx Descriptor Base High */
|
||||
#define INTEL_82543GC_TDLEN 0x3808 /* Tx Descriptor Length */
|
||||
#define INTEL_82543GC_TDH 0x3810 /* Tx Descriptor Head */
|
||||
#define INTEL_82543GC_TDT 0x3818 /* Tx Descriptor Tail */
|
||||
|
||||
/* RX registers */
|
||||
|
||||
#define INTEL_82543GC_RDBAL 0x2800 /* Rx Descriptor Base Low */
|
||||
#define INTEL_82543GC_RDBAH 0x2804 /* Rx Descriptor Base High */
|
||||
#define INTEL_82543GC_RDLEN 0x2808 /* Rx Descriptor Length */
|
||||
#define INTEL_82543GC_RDH 0x2810 /* Rx Descriptor Head */
|
||||
#define INTEL_82543GC_RDT 0x2818 /* Rx Descriptor Tail */
|
||||
|
||||
/* Interrupt registers */
|
||||
|
||||
#define INTEL_82543GC_ICR 0xc0 /* Interrupt Cause Read */
|
||||
#define INTEL_82543GC_ICS 0xc8 /* Interrupt Cause Set */
|
||||
#define INTEL_82543GC_IMS 0xd0 /* Interrupt Mask Set/Read */
|
||||
#define INTEL_82543GC_IMC 0xD8 /* Interrupt Mask Clear */
|
||||
|
||||
#define INTEL_82543GC_CTRL 0x0 /* Device Control */
|
||||
#define INTEL_82543GC_STATUS 0x8 /* Device Status */
|
||||
#define INTEL_82543GC_EECD 0x10 /* EEPROM/Flash Data */
|
||||
#define INTEL_82543GC_CTRL_EXT 0x18 /* Extended Device Control */
|
||||
#define INTEL_82543GC_MDI 0x20 /* MDI Control */
|
||||
#define INTEL_82543GC_FCAL 0x28 /* Flow Control Adr Low */
|
||||
#define INTEL_82543GC_FCAH 0x2c /* Flow Control Adr High */
|
||||
#define INTEL_82543GC_FCT 0x30 /* Flow Control Type */
|
||||
#define INTEL_82543GC_VET 0x38 /* VLAN EtherType */
|
||||
#define INTEL_82546EB_ITR 0xc4 /* register for 82540/5/6 MAC only,
|
||||
interrupt throttle register */
|
||||
#define INTEL_82543GC_RCTL 0x100 /* Receive Control */
|
||||
#define INTEL_82543GC_FCTTV 0x170 /* Flow Ctrl TX Timer Value */
|
||||
#define INTEL_82543GC_TXCW 0x178 /* TX Configuration Word */
|
||||
#define INTEL_82543GC_RXCW 0x180 /* RX Configuration Word */
|
||||
#define INTEL_82543GC_TCTL 0x400 /* TX control */
|
||||
#define INTEL_82543GC_TIPG 0x410 /* Transmit IPG */
|
||||
#define INTEL_82543GC_PBA 0x1000 /* Packet Buffer Allocation */
|
||||
#define INTEL_82543GC_FCRTL 0x2160 /* Flow ctrl RX Threshold Lo*/
|
||||
#define INTEL_82543GC_FCRTH 0x2168 /* Flow ctrl RX Threshold hi*/
|
||||
#define INTEL_82543GC_RDTR 0x2820 /* Rx Delay Timer Ring */
|
||||
#define INTEL_82546EB_RADV 0x282C /* register for 82540/5/6 MAC only,
|
||||
absolute Rx Delay Timer register */
|
||||
#define INTEL_82543GC_TIDV 0x3820 /* Tx Interrupt Delay Value */
|
||||
#define INTEL_82543GC_TXDCTL 0x3828 /* Transmit descriptor control */
|
||||
#define INTEL_82546EB_TADV 0x382C /* register for 82540/5/6 MAC only,
|
||||
absolute Tx Interrupt Delay register */
|
||||
#define INTEL_82543GC_RXCSUM 0x5000 /* Receive Checksum control */
|
||||
#define INTEL_82543GC_MTA 0x5200 /* Multicast Table Array */
|
||||
#define INTEL_82543GC_RAL 0x5400 /* Rx Adr Low */
|
||||
#define INTEL_82543GC_RAH 0x5404 /* Rx Adr High */
|
||||
#define INTEL_82543GC_VLAN 0x5600 /* VLAN Filter Table Array */
|
||||
|
||||
/* Statistic Registers */
|
||||
|
||||
#define INTEL_82543GC_CRCERRS 0x4000
|
||||
#define INTEL_82543GC_ALGNERRC 0x4004
|
||||
#define INTEL_82543GC_SYMERRS 0x4008
|
||||
#define INTEL_82543GC_RXERRC 0x400c
|
||||
#define INTEL_82543GC_MPC 0x4010
|
||||
#define INTEL_82543GC_SCC 0x4014
|
||||
#define INTEL_82543GC_ECOL 0x4018
|
||||
#define INTEL_82543GC_MCC 0x401c
|
||||
#define INTEL_82543GC_LATECOL 0x4020
|
||||
#define INTEL_82543GC_COLC 0x4028
|
||||
#define INTEL_82543GC_TUC 0x402c
|
||||
#define INTEL_82543GC_DC 0x4030
|
||||
#define INTEL_82543GC_TNCRS 0x4034
|
||||
#define INTEL_82543GC_SEC 0x4038
|
||||
#define INTEL_82543GC_CEXTEER 0x403c
|
||||
#define INTEL_82543GC_RLEC 0x4040
|
||||
#define INTEL_82543GC_XONRXC 0x4048
|
||||
#define INTEL_82543GC_XONTXC 0x404c
|
||||
#define INTEL_82543GC_XOFFRXC 0x4050
|
||||
#define INTEL_82543GC_XOFFTXC 0x4054
|
||||
#define INTEL_82543GC_FCRUC 0x4058
|
||||
#define INTEL_82543GC_PRC64 0x405c
|
||||
#define INTEL_82543GC_PRC127 0x4060
|
||||
#define INTEL_82543GC_PRC255 0x4064
|
||||
#define INTEL_82543GC_PRC511 0x4068
|
||||
#define INTEL_82543GC_PRC1023 0x406c
|
||||
#define INTEL_82543GC_PRC1522 0x4070
|
||||
#define INTEL_82543GC_GPRC 0x4074
|
||||
#define INTEL_82543GC_BPRC 0x4078
|
||||
#define INTEL_82543GC_MPRC 0x407c
|
||||
#define INTEL_82543GC_GPTC 0x4080
|
||||
#define INTEL_82543GC_GORL 0x4088
|
||||
#define INTEL_82543GC_GORH 0x408c
|
||||
#define INTEL_82543GC_GOTL 0x4090
|
||||
#define INTEL_82543GC_GOTH 0x4094
|
||||
#define INTEL_82543GC_RNBC 0x40a0
|
||||
#define INTEL_82543GC_RUC 0x40a4
|
||||
#define INTEL_82543GC_RFC 0x40a8
|
||||
#define INTEL_82543GC_ROC 0x40ac
|
||||
#define INTEL_82543GC_RJC 0x40b0
|
||||
#define INTEL_82543GC_TORL 0x40c0
|
||||
#define INTEL_82543GC_TORH 0x40c4
|
||||
#define INTEL_82543GC_TOTL 0x40c8
|
||||
#define INTEL_82543GC_TOTH 0x40cc
|
||||
#define INTEL_82543GC_TPR 0x40d0
|
||||
#define INTEL_82543GC_TPT 0x40d4
|
||||
#define INTEL_82543GC_PTC64 0x40d8
|
||||
#define INTEL_82543GC_PTC127 0x40dc
|
||||
#define INTEL_82543GC_PTC255 0x40e0
|
||||
#define INTEL_82543GC_PTC511 0x40e4
|
||||
#define INTEL_82543GC_PTC1023 0x40e8
|
||||
#define INTEL_82543GC_PTC1522 0x40ec
|
||||
#define INTEL_82543GC_MPTC 0x40f0
|
||||
#define INTEL_82543GC_BPTC 0x40f4
|
||||
#define INTEL_82543GC_TSCTC 0x40f8
|
||||
#define INTEL_82543GC_TSCTFC 0x40fc
|
||||
#define INTEL_82543GC_RDFH 0x2410
|
||||
#define INTEL_82543GC_RDFT 0x2418
|
||||
#define INTEL_82543GC_RDFHS 0x2420
|
||||
#define INTEL_82543GC_RDFTS 0x2428
|
||||
#define INTEL_82543GC_RDFPC 0x2430
|
||||
#define INTEL_82543GC_TDFH 0x3410
|
||||
#define INTEL_82543GC_TDFT 0x3418
|
||||
#define INTEL_82543GC_TDFHS 0x3420
|
||||
#define INTEL_82543GC_TDFTS 0x3428
|
||||
#define INTEL_82543GC_TDFPC 0x3430
|
||||
|
||||
/* Rx Configuration Word Field */
|
||||
|
||||
#define RXCW_C_BIT 0x20000000
|
||||
|
||||
/* EEPROM Structure */
|
||||
|
||||
#define EEPROM_WORD_SIZE 0x40 /* 0-0x3f */
|
||||
#define EEPROM_SUM 0xBABA
|
||||
#define EEPROM_INDEX_SIZE 0x40
|
||||
#define EEPROM_INDEX_BITS 6
|
||||
#define EEPROM_CMD_BITS 3
|
||||
#define EEPROM_DATA_BITS 16
|
||||
#define EEPROM_READ_OPCODE 0x6
|
||||
#define EEPROM_WRITE_OPCODE 0x5
|
||||
#define EEPROM_ERASE_OPCODE 0x7
|
||||
|
||||
#define EEPROM_IA_ADDRESS 0x0
|
||||
#define EEPROM_ICW1 0xa
|
||||
#define EEPROM_ICW1_SWDPIO_BITS 0x1e0
|
||||
#define EEPROM_ICW1_SWDPIO_SHIFT 5
|
||||
#define EEPROM_ICW1_ILOS_BIT 0x10
|
||||
#define EEPROM_ICW1_FRCSPD_BIT 0x800
|
||||
#define EEPROM_ICW1_ILOS_SHIFT 4
|
||||
|
||||
#define EEPROM_ICW2 0xf
|
||||
#define EEPROM_ICW2_PAUSE_BITS 0x3000
|
||||
#define EEPROM_ICW2_ASM_DIR 0x2000
|
||||
#define EEPROM_ICW2_SWDPIO_EXE_BITS 0xf0
|
||||
#define EEPROM_ICW2_SWDPIO_EXE_SHIFT 4
|
||||
|
||||
#define BAR0_64_BIT 0x04
|
||||
|
||||
/* TX Descriptor Command Fields */
|
||||
|
||||
#define TXD_CMD_EOP 0x01
|
||||
#define TXD_CMD_IFCS 0x02
|
||||
#define TXD_CMD_IC 0x04
|
||||
#define TXD_CMD_RS 0x08
|
||||
#define TXD_CMD_RPS 0x10
|
||||
#define TXD_CMD_DEXT 0x20
|
||||
#define TXD_CMD_VLE 0x40
|
||||
#define TXD_CMD_IDE 0x80
|
||||
|
||||
/* for TX context descriptor only */
|
||||
|
||||
#define TXD_CMD_CTX_TCP 0x01 /* 1 == TCP, 0 == UDP */
|
||||
#define TXD_CMD_CTX_IP 0x02
|
||||
#define TXD_CMD_CTX_TSE 0x04
|
||||
#define TXD_CMD_CTX_RS 0x08
|
||||
#define TXD_CMD_CTX_DEXT 0x20
|
||||
#define TXD_CMD_CTX_IDE 0x80
|
||||
|
||||
/* TX Descriptor Status Fields */
|
||||
|
||||
#define TXD_STAT_DD 0x01
|
||||
#define TXD_STAT_EC 0x02
|
||||
#define TXD_STAT_LC 0x04
|
||||
#define TXD_STAT_TU 0x08
|
||||
|
||||
/* TX Data Descriptor POPTS fields */
|
||||
|
||||
#define TXD_DATA_POPTS_IXSM_BIT 0x01
|
||||
#define TXD_DATA_POPTS_TXSM_BIT 0x02
|
||||
|
||||
/* TX Data Descriptor DTYP Fileld */
|
||||
#define TXD_DTYP_BIT 0x01
|
||||
|
||||
/* RX Descriptor Status Field */
|
||||
|
||||
#define RXD_STAT_DD 0x01
|
||||
#define RXD_STAT_EOP 0x02
|
||||
#define RXD_STAT_IXSM 0x04
|
||||
#define RXD_STAT_VP 0x08
|
||||
#define RXD_STAT_RSV 0x10
|
||||
#define RXD_STAT_TCPCS 0x20
|
||||
#define RXD_STAT_IPCS 0x40
|
||||
#define RXD_STAT_PIF 0x80
|
||||
|
||||
/* RX Descriptor Error Field */
|
||||
|
||||
#define RXD_ERROR_CE 0x01 /* CRC or Align error */
|
||||
#define RXD_ERROR_SE 0x02 /* Symbol error */
|
||||
#define RXD_ERROR_SEQ 0x04 /* Sequence error */
|
||||
#define RXD_ERROR_RSV 0x08 /* reserved */
|
||||
#define RXD_ERROR_CXE 0x10 /* Carrier ext error */
|
||||
#define RXD_ERROR_TCPE 0x20 /* TCP/UDP CKSUM error */
|
||||
#define RXD_ERROR_IPE 0x40 /* IP CKSUM error */
|
||||
#define RXD_ERROR_RXE 0x80 /* RX data error */
|
||||
|
||||
/* Interrupt Register Fields */
|
||||
|
||||
#define INT_TXDW_BIT 0x01 /* TX descriptor write-back */
|
||||
#define INT_TXQE_BIT 0x02 /* TX ring empty */
|
||||
#define INT_LSC_BIT 0x04 /* link change interrupt */
|
||||
#define INT_RXSEQ_BIT 0x08 /* RX sequence error */
|
||||
#define INT_RXDMT0_BIT 0x10 /* RX descriptor Mini Threshold */
|
||||
#define INT_RXO_BIT 0x40 /* RX FIFO overrun */
|
||||
#define INT_RXTO_BIT 0x80 /* RX timer interrupt */
|
||||
#define INT_MDAC_BIT 0x200 /* MDIO complete interrupt */
|
||||
#define INT_RXCFG_BIT 0x400 /* Receiving /C/ ordered set */
|
||||
#define INT_GPI0_BIT 0x800 /* GPIO 0 interrupt (543 MAC) */
|
||||
#define INT_GPI1_BIT 0x1000 /* PHY (544 MAC) or GPIO1 (543) interrupt */
|
||||
#define INT_GPI2_BIT 0x2000 /* GPIO2 interrupt */
|
||||
#define INT_GPI3_BIT 0x4000 /* GPIO3 interrupt */
|
||||
#define INT_TXDLOW_BIT 0x8000 /* TX descriptor low threshold hit */
|
||||
|
||||
/* IMS register */
|
||||
|
||||
#define IMS_TXDW_BIT 0x01
|
||||
#define IMS_TXQE_BIT 0x02
|
||||
#define IMS_LSC_BIT 0x04
|
||||
#define IMS_RXSEQ_BIT 0x08
|
||||
#define IMS_RXDMT0_BIT 0x10
|
||||
#define IMS_RXO_BIT 0x40
|
||||
#define IMS_RXTO_BIT 0x80
|
||||
#define IMS_MDAC_BIT 0x200
|
||||
#define IMS_RXCFG_BIT 0x400
|
||||
#define IMS_TXDLOW_BIT 0x8000
|
||||
|
||||
/* IMC register */
|
||||
|
||||
#define IMC_ALL_BITS 0xffffffff
|
||||
#define IMC_TXDW_BIT 0x01
|
||||
#define IMC_TXQE_BIT 0x02
|
||||
#define IMC_LSC_BIT 0x04
|
||||
#define IMC_RXSEQ_BIT 0x08
|
||||
#define IMC_RXDMT0_BIT 0x10
|
||||
#define IMC_RXO_BIT 0x40
|
||||
#define IMC_RXTO_BIT 0x80
|
||||
#define IMC_MDAC_BIT 0x200
|
||||
#define IMC_RXCFG_BIT 0x400
|
||||
#define IMC_TXDLOW_BIT 0x8000
|
||||
|
||||
/* ICR register */
|
||||
|
||||
#define ICR_TXDW_BIT 0x01
|
||||
#define ICR_TXQE_BIT 0x02
|
||||
#define ICR_LSC_BIT 0x04
|
||||
#define ICR_RXSEQ_BIT 0x08
|
||||
#define ICR_RXDMT0_BIT 0x10
|
||||
#define ICR_RXO_BIT 0x40
|
||||
#define ICR_RXTO_BIT 0x80
|
||||
#define ICR_MDAC_BIT 0x200
|
||||
#define ICR_RXCFG_BIT 0x400
|
||||
#define ICR_TXDLOW_BIT 0x8000
|
||||
|
||||
/* EEPROM Register Fields */
|
||||
|
||||
#define EECD_SK_BIT 0x1
|
||||
#define EECD_CS_BIT 0x2
|
||||
#define EECD_DI_BIT 0x4
|
||||
#define EECD_DO_BIT 0x8
|
||||
#define EECD_REQ_BIT 0x40
|
||||
#define EECD_GNT_BIT 0x80
|
||||
#define EECD_PRES_BIT 0x100
|
||||
#define EECD_SIZE_BIT 0x200
|
||||
|
||||
/* RAT field */
|
||||
|
||||
#define RAH_AV_BIT 0x80000000
|
||||
|
||||
/* Control Register Field */
|
||||
|
||||
#define CTRL_FD_BIT 0x1
|
||||
#define CTRL_PRIOR_BIT 0x4
|
||||
#define CTRL_ASDE_BIT 0x20
|
||||
#define CTRL_SLU_BIT 0x40
|
||||
#define CTRL_ILOS_BIT 0x80
|
||||
#define CTRL_SPD_100_BIT 0x100
|
||||
#define CTRL_SPD_1000_BIT 0x200
|
||||
#define CTRL_FRCSPD_BIT 0x800
|
||||
#define CTRL_FRCDPX_BIT 0x1000
|
||||
#define CTRL_SWDPIN0_BIT 0x40000
|
||||
#define CTRL_SWDPIN1_BIT 0x80000
|
||||
#define CTRL_SWDPIN2_BIT 0x100000
|
||||
#define CTRL_SWDPIN3_BIT 0x200000
|
||||
#define CTRL_SWDPIO0_BIT 0x400000
|
||||
#define CTRL_SWDPIO1_BIT 0x800000
|
||||
#define CTRL_SWDPIO2_BIT 0x1000000
|
||||
#define CTRL_SWDPIO3_BIT 0x2000000
|
||||
#define CTRL_RST_BIT 0x4000000
|
||||
#define CTRL_RFCE_BIT 0x8000000
|
||||
#define CTRL_TFCE_BIT 0x10000000
|
||||
#define CTRL_PHY_RST_BIT 0x80000000
|
||||
#define CTRL_MDC_BIT CTRL_SWDPIN3_BIT
|
||||
#define CTRL_MDIO_BIT CTRL_SWDPIN2_BIT
|
||||
#define CTRL_MDC_DIR_BIT CTRL_SWDPIO3_BIT
|
||||
#define CTRL_MDIO_DIR_BIT CTRL_SWDPIO2_BIT
|
||||
#define CTRL_SPEED_MASK 0x300
|
||||
#define CTRL_SWDPIOLO_SHIFT 22
|
||||
#define CTRL_ILOS_SHIFT 7
|
||||
|
||||
/* Receive Control Register Fields */
|
||||
|
||||
#define RCTL_MO_SHIFT 12
|
||||
#define RCTL_BSIZE_2048 0
|
||||
#define RCTL_BSIZE_4096 0x00030000
|
||||
#define RCTL_BSIZE_8192 0x00020000
|
||||
#define RCTL_BSIZE_16384 0x00010000
|
||||
#define RCTL_EN_BIT 0x00000002
|
||||
#define RCTL_SBP_BIT 0x00000004
|
||||
#define RCTL_UPE_BIT 0x00000008
|
||||
#define RCTL_MPE_BIT 0x00000010
|
||||
#define RCTL_LPE_BIT 0x00000020
|
||||
#define RCTL_BAM_BIT 0x00008000
|
||||
#define RCTL_BSEX_BIT 0x02000000
|
||||
#define RCTL_SECRC_BIT 0x04000000
|
||||
|
||||
/* MDI register fields */
|
||||
|
||||
#define MDI_WRITE_BIT 0x4000000
|
||||
#define MDI_READ_BIT 0x8000000
|
||||
#define MDI_READY_BIT 0x10000000
|
||||
#define MDI_ERR_BIT 0x40000000
|
||||
#define MDI_REG_SHIFT 16
|
||||
#define MDI_PHY_SHIFT 21
|
||||
|
||||
/* Flow Control Field and Initial value */
|
||||
|
||||
#define FCRTL_XONE_BIT 0x80000000
|
||||
#define FLOW_CONTROL_LOW_ADR 0x00c28001
|
||||
#define FLOW_CONTROL_HIGH_ADR 0x00000100
|
||||
#define FLOW_CONTROL_TYPE 0x8808
|
||||
#define FLOW_CONTROL_TIMER_VALUE 0x100
|
||||
#define FLOW_CONTROL_LOW_THRESH 0x4000
|
||||
#define FLOW_CONTROL_HIGH_THRESH 0x8000
|
||||
|
||||
/* Extended Control Register Fields */
|
||||
|
||||
#define CTRL_EXT_SWDPIN4_BIT 0x10
|
||||
#define CTRL_EXT_SWDPIN5_BIT 0x20
|
||||
#define CTRL_EXT_SWDPIN6_BIT 0x40
|
||||
#define CTRL_EXT_SWDPIN7_BIT 0x80
|
||||
#define CTRL_EXT_SWDPIO4_BIT 0x100
|
||||
#define CTRL_EXT_SWDPIO5_BIT 0x200
|
||||
#define CTRL_EXT_SWDPIO6_BIT 0x400
|
||||
#define CTRL_EXT_SWDPIO7_BIT 0x800
|
||||
#define CTRL_EXT_SWDPIOHI_SHIFT 8
|
||||
|
||||
#define CTRL_PHY_RESET_DIR4_BIT CTRL_EXT_SWDPIO4_BIT
|
||||
#define CTRL_PHY_RESET4_BIT CTRL_EXT_SWDPIN4_BIT
|
||||
|
||||
/* Status Register Fields */
|
||||
|
||||
#define STATUS_FD_BIT 0x1
|
||||
#define STATUS_LU_BIT 0x2
|
||||
#define STATUS_TBIMODE_BIT 0x20
|
||||
#define STATUS_SPEED_100_BIT 0x40
|
||||
#define STATUS_SPEED_1000_BIT 0x80
|
||||
|
||||
/* TX control Regsiter Fields */
|
||||
|
||||
#define TCTL_EN_BIT 0x2
|
||||
#define TCTL_PSP_BIT 0x8
|
||||
#define TCTL_PBE_BIT 0x800000
|
||||
#define TCTL_COLD_BIT 0x3ff000
|
||||
#define TCTL_COLD_SHIFT 12
|
||||
#define TCLT_CT_SHIFT 4
|
||||
|
||||
/* TIPG Register Fields */
|
||||
|
||||
#define TIPG_IPGR1_SHIFT 10
|
||||
#define TIPG_IPGR2_SHIFT 20
|
||||
|
||||
/* RDTR Register Field */
|
||||
|
||||
#define RDTR_FPD_BIT 0x80000000
|
||||
|
||||
/* TX Configuration Word fields */
|
||||
|
||||
#define TXCW_ANE_BIT 0x80000000
|
||||
#define TXCW_FD_BIT 0x20
|
||||
#define TXCW_ASM_DIR 0x100
|
||||
#define TXCW_PAUSE_BITS 0x180
|
||||
|
||||
/* RXCSUM register field */
|
||||
|
||||
#define RXCSUM_IPOFL_BIT 0x0100
|
||||
#define RXCSUM_TUOFL_BIT 0x0200
|
||||
#define RXCSUM_IPV6OFL_BIT 0x0400
|
||||
|
||||
/* PHY's Registers And Initial Value*/
|
||||
|
||||
#define PHY_PREAMBLE 0xFFFFFFFF
|
||||
#define PHY_PREAMBLE_SIZE 32
|
||||
#define PHY_WR_OP 0x01
|
||||
#define PHY_RD_OP 0x02
|
||||
#define PHY_TURNAR 0x02
|
||||
#define PHY_MARK 0x01
|
||||
|
||||
#define CL_OVERHEAD 4
|
||||
|
||||
/* Type define */
|
||||
|
||||
typedef struct txDescManager TX_DESCTL;
|
||||
|
||||
typedef TX_DESCTL * P_TX_DESCTL;
|
||||
|
||||
struct txDescManager
|
||||
{
|
||||
M_BLK_ID mBlk; /* location for mBlk */
|
||||
};
|
||||
|
||||
typedef struct devDrv_stat
|
||||
{
|
||||
UINT32 rxtxHandlerNum; /* num of rxtx handle routine was called per sec */
|
||||
UINT32 rxIntCount; /* num of rx interrupt per sec */
|
||||
UINT32 txIntCount; /* num of tx interrupt per sec */
|
||||
UINT32 rxORunIntCount; /* num of rx overrun interrupt per sec */
|
||||
UINT32 rxPacketNum; /* num of rx packet per sec */
|
||||
UINT32 txPacketNum; /* num of tx packet per sec */
|
||||
UINT32 rxPacketDrvErr; /* num of pkt rx error on driver per sec */
|
||||
} DEVDRV_STAT;
|
||||
|
||||
typedef struct dev_Timer
|
||||
{
|
||||
UINT32 rdtrVal; /* RDTR, unit of 1.024ns */
|
||||
UINT32 radvVal; /* RADV, unit of 1.024us */
|
||||
UINT32 itrVal; /* ITR, unit of 256 ns */
|
||||
UINT32 tidvVal; /* TIDV, unit of 1.024us */
|
||||
UINT32 tadvVal; /* TADV, unit of 1.024us */
|
||||
UINT32 watchDogIntVal; /* interval of watchdog, unit of second */
|
||||
} DEV_TIMER;
|
||||
|
||||
struct adapter_info
|
||||
{
|
||||
int vector; /* interrupt vector */
|
||||
UINT32 regBaseLow; /* register PCI base address - low */
|
||||
UINT32 regBaseHigh; /* register PCI base address - high */
|
||||
UINT32 flashBase; /* flash PCI base address */
|
||||
|
||||
BOOL adr64; /* indictor of 64 bit address */
|
||||
UINT32 boardType; /* board type */
|
||||
UINT32 phyType; /* PHY type (MII/GMII) */
|
||||
|
||||
UINT32 delayUnit; /* delay unit(in ns) for the delay function */
|
||||
FUNCPTR delayFunc; /* BSP specified delay function */
|
||||
|
||||
STATUS (*intEnable)(int); /* board specific interrupt enable routine */
|
||||
STATUS (*intDisable)(int); /* board specific interrupt disable routine */
|
||||
STATUS (*intAck) (int); /* interrupt ack */
|
||||
|
||||
void (*phySpecInit)(PHY_INFO *, UINT8); /* vendor specified PHY's init */
|
||||
UINT32 (*sysLocalToBus)(int,UINT32);
|
||||
UINT32 (*sysBusToLocal)(int,UINT32);
|
||||
|
||||
FUNCPTR intConnect; /* interrupt connect function */
|
||||
FUNCPTR intDisConnect; /* interrupt disconnect function */
|
||||
|
||||
UINT16 eeprom_icw1; /* ICW1 in EEPROM */
|
||||
UINT16 eeprom_icw2; /* ICW2 in EEPROM */
|
||||
|
||||
UCHAR enetAddr[6]; /* Ether address for this adaptor */
|
||||
UCHAR reserved1[2]; /* reserved */
|
||||
|
||||
FUNCPTR phyDelayRtn; /* phy delay function */
|
||||
UINT32 phyMaxDelay; /* max phy detection retry */
|
||||
UINT32 phyDelayParm; /* delay parameter for phy delay function */
|
||||
UINT32 phyAddr; /* phy Addr */
|
||||
|
||||
BOOL (*sysGeiDynaTimerSetup)(struct adapter_info *); /* adjust device's timer dynamically */
|
||||
BOOL (*sysGeiInitTimerSetup)(struct adapter_info *); /* set the device's timer initially */
|
||||
|
||||
DEVDRV_STAT devDrvStat; /* statistic data for devices */
|
||||
DEV_TIMER devTimerUpdate; /* timer register value for update */
|
||||
|
||||
void (*phyBspPreInit)(PHY_INFO *, UINT8); /* BSP specific PHY init for 82543-copper */
|
||||
};
|
||||
|
||||
typedef struct adapter_info ADAPTOR_INFO;
|
||||
|
||||
/* structure for Statistic registers */
|
||||
|
||||
typedef struct sta_reg
|
||||
{
|
||||
UINT32 crcerrs; /* CRC error count */
|
||||
UINT32 algnerrc; /* alignment err count */
|
||||
UINT32 symerrs; /* symbol err count */
|
||||
UINT32 rxerrc; /* rx err count */
|
||||
UINT32 mpc; /* missed packet count */
|
||||
UINT32 scc; /* single collision count */
|
||||
UINT32 ecol; /* excessive collision count */
|
||||
UINT32 mcc; /* multi collision count */
|
||||
UINT32 latecol; /* later collision count */
|
||||
UINT32 colc; /* collision count */
|
||||
UINT32 tuc; /* tx underun count */
|
||||
UINT32 dc; /* defer count */
|
||||
UINT32 tncrs; /* tx - no crs count */
|
||||
UINT32 sec; /* sequence err count */
|
||||
UINT32 cexteer; /* carrier extension count */
|
||||
UINT32 rlec; /* rx length error count */
|
||||
UINT32 xonrxc; /* XON receive count */
|
||||
UINT32 xontxc; /* XON transmit count */
|
||||
UINT32 xoffrxc; /* XOFF receive count */
|
||||
UINT32 xofftxc; /* XFF transmit count */
|
||||
UINT32 fcruc; /* FC received unsupported count */
|
||||
UINT32 prc64; /* packet rx (64 byte) count */
|
||||
UINT32 prc127; /* packet rx (65 - 127 byte) count */
|
||||
UINT32 prc255; /* packet rx (128 - 255 byte) count */
|
||||
UINT32 prc511; /* packet rx (256 - 511 byte) count */
|
||||
UINT32 prc1023; /* packet rx (512 - 1023 byte) count */
|
||||
UINT32 prc1522; /* packet rx (1024 - 1522 byte) count */
|
||||
UINT32 gprc; /* good packet received count */
|
||||
UINT32 bprc; /* broadcast packet received count */
|
||||
UINT32 mprc; /* Multicast packet received count */
|
||||
UINT32 gptc; /* good packet transmit count */
|
||||
UINT32 gorl; /* good octets receive count (low) */
|
||||
UINT32 gorh; /* good octets received count (high) */
|
||||
UINT32 gotl; /* good octets transmit count (lo) */
|
||||
UINT32 goth; /* good octets transmit count (hi) */
|
||||
UINT32 rnbc; /* receive no buffer count */
|
||||
UINT32 ruc; /* receive undersize count */
|
||||
UINT32 rfc; /* receive fragment count */
|
||||
UINT32 roc; /* receive oversize count */
|
||||
UINT32 rjc; /* receive Jabber count */
|
||||
UINT32 torl; /* total octets received (lo) */
|
||||
UINT32 torh; /* total octets received (hi) */
|
||||
UINT32 totl; /* total octets transmit (lo) */
|
||||
UINT32 toth; /* total octets transmit (hi) */
|
||||
UINT32 tpr; /* total packet received */
|
||||
UINT32 tpt; /* total packet transmit */
|
||||
UINT32 ptc64; /* packet transmit (64 byte) count */
|
||||
UINT32 ptc127; /* packet transmit (65-127 byte) count */
|
||||
UINT32 ptc255; /* packet transmit (128-255 byte) count */
|
||||
UINT32 ptc511; /* packet transmit (256-511 byte) count */
|
||||
UINT32 ptc1023; /* packet transmit (512-1023 byte) count */
|
||||
UINT32 ptc1522; /* packet transmit (1024-1522 byte) count */
|
||||
UINT32 mptc; /* Multicast packet transmit count */
|
||||
UINT32 bptc; /* Broadcast packet transmit count */
|
||||
UINT32 tsctc; /* TCP segmentation context tx count */
|
||||
UINT32 tsctfc; /* TCP segmentation context tx fail count */
|
||||
UINT32 rdfh; /* rx data FIFO head */
|
||||
UINT32 rdft; /* rx data FIFO tail */
|
||||
UINT32 rdfhs; /* rx data FIFO head saved register */
|
||||
UINT32 rdfts; /* rx data FIFO tail saved register */
|
||||
UINT32 rdfpc; /* rx data FIFO packet count */
|
||||
UINT32 tdfh; /* tx data FIFO head */
|
||||
UINT32 tdft; /* tx data FIFO tail */
|
||||
UINT32 tdfhs; /* tx data FIFO head saved register */
|
||||
UINT32 tdfts; /* tx data FIFO tail saved register */
|
||||
UINT32 tdfpc; /* tx data FIFO packet count */
|
||||
} STA_REG;
|
||||
|
||||
#if ((CPU_FAMILY==I960) && (defined __GNUC__))
|
||||
#pragma align 0 /* turn off alignment requirement */
|
||||
#endif /* CPU_FAMILY==I960 */
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
IMPORT END_OBJ * gei82543EndLoad (char * initString);
|
||||
#else
|
||||
IMPORT END_OBJ * gei82543EndLoad ();
|
||||
#endif /* defined(__STDC__) || defined(__cplusplus) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCGEI82543Endh */
|
||||
|
||||
|
||||
@@ -0,0 +1,616 @@
|
||||
/* iOlicomEnd.h - END-style Intel Olicom PCMCIA Ethernet interface header */
|
||||
|
||||
/* Copyright 1997-2001, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,29apr10,pad Moved extern C statement after include statements.
|
||||
01g,20sep01,dat Removing ANSI errors for diab compiler
|
||||
01f,03aug00,jpd corrected length of drive name string (SPR #32276).
|
||||
01e,11jun00,ham removed reference to etherLib.
|
||||
01d,02sep98,jpd renamed struct type name to prevent conflict. Improved
|
||||
data copying macros efficiency. Add big-endian support.
|
||||
01c,02apr98,jpd made conditionally-compilable version for Brutus and PID.
|
||||
01b,16feb98.jpd modified to work on Brutus, but not yet on both Brutus and PID.
|
||||
01a,16dec97,rlp copied from if_oli.h
|
||||
*/
|
||||
|
||||
#ifndef __INCiOlicomEndh
|
||||
#define __INCiOlicomEndh
|
||||
|
||||
#include "end.h"
|
||||
#include "netBufLib.h"
|
||||
#include "netinet/if_ether.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Define Constants */
|
||||
|
||||
#define PC_SOCKET_A 0x00
|
||||
#define PC_SOCKET_B 0x40
|
||||
|
||||
#define ATTRIBUTE_MEMORY_SLOT 0x01000
|
||||
|
||||
#ifndef TARGET_HAS_NO_VADEM
|
||||
#define PC_INDEX ((volatile char *)(ctrlBase + 0x00))
|
||||
#define PC_DATA_READ ((volatile int *) (ctrlBase + 0x01))
|
||||
#define PC_DATA_WRITE ((volatile char *)(ctrlBase + 0x01))
|
||||
|
||||
#define MAPPED_MEMORY_BASE 0x10000 /* 64K */
|
||||
|
||||
#define ATTRIB_MEMORY_A MAPPED_MEMORY_BASE
|
||||
#define ATTRIB_MEMORY_B ATTRIB_MEMORY_A + ATTRIBUTE_MEMORY_SLOT
|
||||
#endif /* TARGET_HAS_NO_VADEM */
|
||||
|
||||
/*
|
||||
* Define to have complete control over the PCMCIA system.
|
||||
* These definitions are Access macro, I/O Registers, Control Registers,
|
||||
* PCMCIA Structures and Constants.
|
||||
*/
|
||||
|
||||
/* Macro definition for PCMCIA Access */
|
||||
|
||||
#ifndef I82595_REGS_CONTIGUOUS
|
||||
#define PCMCIA_CALC_ADDR(x) (((((UINT)(x)) & ~0x01) << 1) | \
|
||||
(((UINT)(x)) & 0x01))
|
||||
|
||||
#define PCMCIA_READ_RAW(x, y) (*(volatile UINT *) (PCMCIA_CALC_ADDR(x) | (y)))
|
||||
|
||||
#define PCMCIA_WRITE_RAW(x, y, z) (*(volatile UINT8 *) \
|
||||
(PCMCIA_CALC_ADDR(x) | (y)) = (z))
|
||||
|
||||
#define PCMCIA_IO_WRITE(x, y) ((*(volatile UINT8 *)(x)) = (y))
|
||||
|
||||
#define PCMCIA_IO_READ(x) (((((UINT)(x)) & 0x01) == 0) ? \
|
||||
(*(volatile UINT *)(x)) & OCT_MSK: \
|
||||
(*(volatile UINT *)(x)) >> 24)
|
||||
|
||||
#define PCMCIA_ATTR_READ(x) (((((UINT)(x)) & ODD_MSK) == 0) ? \
|
||||
PCMCIA_READ_RAW(x, (int)pDrvCtrl->pcmcia.memBaseA) & OCT_MSK :\
|
||||
PCMCIA_READ_RAW(x, (int)pDrvCtrl->pcmcia.memBaseA) >> 24)
|
||||
|
||||
#define PCMCIA_ATTR_WRITE(x, y) PCMCIA_WRITE_RAW((x), (int) \
|
||||
pDrvCtrl->pcmcia.memBaseA, (y))
|
||||
/* On PID, two apparently consecutive registers cannot be read at once */
|
||||
|
||||
#define READ_R14_R15(val) \
|
||||
{ \
|
||||
val = PCMCIA_IO_READ (pDrvCtrl->pcmcia.oliAddr + I595_R14); \
|
||||
val |= (PCMCIA_IO_READ (pDrvCtrl->pcmcia.oliAddr + I595_R15) << 8); \
|
||||
}
|
||||
#if (_BYTE_ORDER == _BIG_ENDIAN)
|
||||
#define READ_PTR_R14_R15(ptr, pR14) \
|
||||
{ \
|
||||
*(ptr)++ = (0xFF & *((volatile UINT32 *)(pR14))); \
|
||||
*(ptr)++ = (*((UINT32 *)((pR14) + 1)) >> 24); \
|
||||
}
|
||||
#else /* (_BYTE_ORDER == _BIG_ENDIAN) */
|
||||
#define READ_PTR_R14_R15(ptr, pR14) \
|
||||
{ \
|
||||
*(ptr)++ = *((volatile UINT8 *)(pR14)); \
|
||||
*(ptr)++ = (*((UINT32 *)((pR14) + 1)) >> 24); \
|
||||
}
|
||||
#endif /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
#define WRITE_R14_R15(val) \
|
||||
{ \
|
||||
PCMCIA_IO_WRITE (pDrvCtrl->pcmcia.oliAddr + I595_R14, (val)); \
|
||||
PCMCIA_IO_WRITE (pDrvCtrl->pcmcia.oliAddr + I595_R15, ((val) >> 8)); \
|
||||
}
|
||||
#define WRITE_PTR_R14_R15(ptr, pR14) \
|
||||
{ \
|
||||
*(pR14) = *(ptr)++; \
|
||||
*((pR14) + 1) = *(ptr)++; \
|
||||
}
|
||||
#else /* I82595_REGS_CONTIGUOUS */
|
||||
#define PCMCIA_CALC_ADDR(x) (x)
|
||||
#define PCMCIA_IO_WRITE(x, y) ((*(volatile UINT8 *) (x)) = (y))
|
||||
#define PCMCIA_IO_WRITE16(x, y) ((*(volatile UINT16 *)(x)) = (y))
|
||||
#define PCMCIA_IO_READ(x) (* (volatile UINT8 *) (x))
|
||||
#define PCMCIA_IO_READ16(x) (* (volatile UINT16 *)(x))
|
||||
#define PCMCIA_ATTR_READ(x) (* (volatile UINT8 *) (x))
|
||||
#define PCMCIA_ATTR_WRITE(x, y) ((*(volatile UINT8 *) (x)) = (y))
|
||||
|
||||
/* On Brutus, R14 and R15 can be read with one 16 bit operation */
|
||||
|
||||
#define READ_R14_R15(val) \
|
||||
{ \
|
||||
val = (PCMCIA_IO_READ16 (pDrvCtrl->pcmcia.oliAddr + I595_R14)); \
|
||||
}
|
||||
#define READ_PTR_R14_R15(ptr, pR14) \
|
||||
{ \
|
||||
*((UINT16 *)(ptr))++ = *((volatile UINT16 *)(pR14));\
|
||||
}
|
||||
#define WRITE_R14_R15(val) \
|
||||
PCMCIA_IO_WRITE16 (pDrvCtrl->pcmcia.oliAddr + I595_R14, (val));
|
||||
|
||||
#define WRITE_PTR_R14_R15(ptr, pr14) \
|
||||
*(volatile UINT16 *)(pR14) = *((UINT16 *)(ptr))++;
|
||||
#endif /* !I82595_REGS_CONTIGUOUS */
|
||||
|
||||
/* General Setup Registers */
|
||||
|
||||
#define PCIDREV 0x00 /* Identification & Revision */
|
||||
#define PCIFSTATUS 0x01 /* Interface Status */
|
||||
#define PCPWRRSTCTL 0x02 /* Power and RESETDRV Control */
|
||||
#define PCCSTATCHNG 0x04 /* Card Status Change */
|
||||
#define PCADDWINEN 0x06 /* Address Window Enable */
|
||||
#define PCCDGCR 0x16 /* Card Detect and General Control Register */
|
||||
#define PCGLBCTL 0x1E /* Global Control Register */
|
||||
|
||||
#define PCINTGCTL 0x03 /* Interrupt & General Control */
|
||||
#define PCSTATCHNGINT 0x05 /* Card Status Change Interrupt Configuration */
|
||||
|
||||
/* Definitions for fields in general setup registers */
|
||||
|
||||
/* Interface Status Register */
|
||||
|
||||
#define GSR_CD 0x0C /* Card detect - Complement of CD[2:1] pins */
|
||||
#define GSR_RDY 0x20 /* Card is ready */
|
||||
|
||||
/* Power and RESETDRV control register */
|
||||
|
||||
#define GSR_CPE 0x10 /* PC card power enable */
|
||||
#define GSR_PSE 0x20 /* Auto power switch enable */
|
||||
#define GSR_OE 0x80 /* Output enable */
|
||||
|
||||
/* Interrupt & general control register */
|
||||
|
||||
#define GSR_DRT 0x40 /* Deactivates reset signal to the PC card */
|
||||
|
||||
/* Card Status Change Register */
|
||||
|
||||
#define GSR_CDC 0x08 /* Card detect change */
|
||||
|
||||
/* Card status change interrupt configuration register */
|
||||
|
||||
#define GSR_IRQ4 0x40 /* IRQ4 enable */
|
||||
#define GSR_IRQ3 0x30 /* IRQ3 enable */
|
||||
#define GSR_CDE 0x08 /* Card detect enable */
|
||||
|
||||
/* Address window enable register */
|
||||
|
||||
#define GSR_WD0 0x01 /* Enable window 0 */
|
||||
|
||||
/* I/O Registers */
|
||||
|
||||
#define PCIOCTL 0x7 /* I/O Control */
|
||||
#define PCIOA0STARTL 0x08 /* I/O Addr 0 Start Low */
|
||||
#define PCIOA0STARTH 0x09 /* I/O Addr 0 Start High */
|
||||
#define PCIOA0STOPL 0x0A /* I/O Addr 0 Stop Low */
|
||||
#define PCIOA0STOPH 0x0B /* I/O Addr 0 Stop High */
|
||||
#define PCIOA1STARTL 0x0C /* I/O Addr 1 Start Low */
|
||||
#define PCIOA1STARTH 0x0D /* I/O Addr 1 Start High */
|
||||
#define PCIOA1STOPL 0x0E /* I/O Addr 1 Stop Low */
|
||||
#define PCIOA1STOPH 0x0F /* I/O Addr 1 Stop High */
|
||||
|
||||
#define PCSYSA0MSTARTL 0x10 /* System Memory Addr 0 Mapping Start Low */
|
||||
#define PCSYSA0MSTARTH 0x11 /* System Memory Addr 0 Mapping Start High */
|
||||
#define PCSYSA0MSTOPL 0x12 /* System Memory Addr 0 Mapping Stop Low */
|
||||
#define PCSYSA0MSTOPH 0x13 /* System Memory Addr 0 Mapping Stop High */
|
||||
#define PCCMEMA0OFFL 0x14 /* Card Memory Offset Addr 0 Low */
|
||||
#define PCCMEMA0OFFH 0x15 /* Card Memory Offset Addr 0 High */
|
||||
|
||||
#define PCSYSA1MSTARTL 0x18 /* System Memory Addr 1 Mapping Start Low */
|
||||
#define PCSYSA1MSTARTH 0x19 /* System Memory Addr 1 Mapping Start High */
|
||||
#define PCSYSA1MSTOPL 0x1A /* System Memory Addr 1 Mapping Stop Low */
|
||||
#define PCSYSA1MSTOPH 0x1B /* System Memory Addr 1 Mapping Stop High */
|
||||
#define PCCMEMA1OFFL 0x1C /* Card Memory Offset Addr 1 Low */
|
||||
#define PCCMEMA1OFFH 0x1D /* Card Memory Offset Addr 1 High */
|
||||
|
||||
#define PCSYSA2MSTARTL 0x20 /* System Memory Addr 2 Mapping Start Low */
|
||||
#define PCSYSA2MSTARTH 0x21 /* System Memory Addr 2 Mapping Start High */
|
||||
#define PCSYSA2MSTOPL 0x22 /* System Memory Addr 2 Mapping Stop Low */
|
||||
#define PCSYSA2MSTOPH 0x23 /* System Memory Addr 2 Mapping Stop High */
|
||||
#define PCCMEMA2OFFL 0x24 /* Card Memory Offset Addr 2 Low */
|
||||
#define PCCMEMA2OFFH 0x25 /* Card Memory Offset Addr 2 High */
|
||||
|
||||
#define PCSYSA3MSTARTL 0x28 /* System Memory Addr 3 Mapping Start Low */
|
||||
#define PCSYSA3MSTARTH 0x29 /* System Memory Addr 3 Mapping Start High */
|
||||
#define PCSYSA3MSTOPL 0x2A /* System Memory Addr 3 Mapping Stop Low */
|
||||
#define PCSYSA3MSTOPH 0x2B /* System Memory Addr 3 Mapping Stop High */
|
||||
#define PCCMEMA3OFFL 0x2C /* Card Memory Offset Addr 3 Low */
|
||||
#define PCCMEMA3OFFH 0x2D /* Card Memory Offset Addr 3 High */
|
||||
|
||||
#define PCSYSA4MSTARTL 0x30 /* System Memory Addr 4 Mapping Start Low */
|
||||
#define PCSYSA4MSTARTH 0x31 /* System Memory Addr 4 Mapping Start High */
|
||||
#define PCSYSA4MSTOPL 0x32 /* System Memory Addr 4 Mapping Stop Low */
|
||||
#define PCSYSA4MSTOPH 0x33 /* System Memory Addr 4 Mapping Stop High */
|
||||
#define PCCMEMA4OFFL 0x34 /* Card Memory Offset Addr 4 Low */
|
||||
#define PCCMEMA4OFFH 0x35 /* Card Memory Offset Addr 4 High */
|
||||
|
||||
/* Unique Registers */
|
||||
|
||||
#define PCCONTROL 0x38 /* Control */
|
||||
#define PCACTTIM 0x39 /* Activity Timer */
|
||||
#define PCMISC 0x3A /* Miscellaneous */
|
||||
#define PCGPIOCON 0x3B /* GPIO Configuration */
|
||||
#define PCPROGCS 0x3D /* Programmable Chip Select */
|
||||
#define PCPROGCSCON 0x3E /* Programmable Chip Select
|
||||
* Configuration Register */
|
||||
#define PCATA 0x3F /* ATA */
|
||||
|
||||
/* Define PCMCIA structures */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
COMMON, /* Common memory */
|
||||
ATTRIBUTE /* Attribute memory */
|
||||
}
|
||||
MEMTYPE;
|
||||
|
||||
typedef struct PCMCIASocket
|
||||
{
|
||||
UINT pcs_attrbase;
|
||||
UINT pcs_attrrange;
|
||||
UINT pcs_iobase;
|
||||
UINT pcs_iorange;
|
||||
} PCMCIASOCKET;
|
||||
|
||||
/* PCMCIA Control Structure */
|
||||
|
||||
typedef struct pcmcia_ctrl
|
||||
{
|
||||
char * ioBaseA; /* I/O space base address for Card A */
|
||||
char * attrBaseA; /* Attribute space base address Card A*/
|
||||
char * memBaseA; /* Memory space base address Card A */
|
||||
char * ioBaseB; /* I/O space base address for Card B */
|
||||
char * attrBaseB; /* Attribute space base address Card B*/
|
||||
char * memBaseB; /* Memory space base address Card B */
|
||||
char * ctrlBase; /* Base of Vadem PCMCIA controller */
|
||||
char * oliAddr; /* address of board */
|
||||
char * oliAttribMem; /* Address of attribute memory */
|
||||
int intLevelA; /* Interrupt level for Card A */
|
||||
int intVectA; /* Interrupt vector for Card A */
|
||||
int intLevelB; /* Interrupt level for Card B */
|
||||
int intVectB; /* Interrupt vector for Card B */
|
||||
BOOL cardPresent; /* TRUE if a card is in the slot */
|
||||
UINT socket; /* Socket holding card, A or B */
|
||||
PCMCIASOCKET theSocket; /* PCMCIA Socket descriptor */
|
||||
} OLI_PCMCIA_CTRL;
|
||||
|
||||
/* Trasmit Buffer Descriptor */
|
||||
|
||||
typedef struct tx_bd
|
||||
{
|
||||
UINT16 statusMode; /* status and control */
|
||||
UINT16 dataLength; /* length of data buffer in bytes */
|
||||
char * dataPointer; /* points to memory data buffer */
|
||||
} TX_BD;
|
||||
|
||||
/* Receive Buffer Descriptor */
|
||||
|
||||
typedef struct rx_bd
|
||||
{
|
||||
UINT16 statusMode; /* status and control */
|
||||
UINT16 dataLength; /* length of data buffer in bytes */
|
||||
char * dataPointer; /* points to memory data buffer */
|
||||
} RX_BD;
|
||||
|
||||
/* Olicom Card Configuration registers */
|
||||
|
||||
#define CARDCONFREG0 0x3F8
|
||||
#define CARDCONFREG1 0x3FA
|
||||
|
||||
/* Definitions for fields in Olicom card configuration registers */
|
||||
|
||||
/* Register 1 */
|
||||
|
||||
#define CREG1_INT_IO 0x02 /* I/O Interrupt */
|
||||
|
||||
/* There are four tuples that we need to read from the card */
|
||||
|
||||
#define CARD_FUNCID 0x21 /* Should identify the card as
|
||||
an Network Adaptor */
|
||||
#define CARD_FUNCE 0x22 /* Function extension tuple detailing
|
||||
the Ethernet hardware address */
|
||||
#define CARD_CONFIG 0x1A /* Describes card configuration registers */
|
||||
#define CARD_CFT_ENTRY 0x1B /* There are several different copies of
|
||||
this one tuple, which describe the
|
||||
different I/O addresses accepted by the
|
||||
Intel 82595 Controller */
|
||||
|
||||
/*
|
||||
* Register layout of the Intel 82595TX chip
|
||||
*
|
||||
* Those ever imaginative people at Intel have no other
|
||||
* names for the registers on their chip than r1, r2
|
||||
* etc..
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef I82595_REGS_CONTIGUOUS
|
||||
/*
|
||||
* To try and optimise I/O to the chip, this structure represents
|
||||
* the *real* appearance of the chip in the PID7T NISA I/O space;
|
||||
* the weird wiring arrangement described in pid.h means that,
|
||||
* although the chip has a sequential collection of registers, they
|
||||
* appear to be grouped as two-register pairs, aligned on a word
|
||||
* boundary
|
||||
*/
|
||||
#define I595_R0 0x00
|
||||
#define I595_R1 0x01
|
||||
#define I595_R2 0x04
|
||||
#define I595_R3 0x05
|
||||
#define I595_R4 0x08
|
||||
#define I595_R5 0x09
|
||||
#define I595_R6 0x0C
|
||||
#define I595_R7 0x0D
|
||||
#define I595_R8 0x10
|
||||
#define I595_R9 0x11
|
||||
#define I595_R10 0x14
|
||||
#define I595_R11 0x15
|
||||
#define I595_R12 0x18
|
||||
#define I595_R13 0x19
|
||||
#define I595_R14 0x1C
|
||||
#define I595_R15 0x1D
|
||||
#else
|
||||
/* Normal layout */
|
||||
#define I595_R0 0x00
|
||||
#define I595_R1 0x01
|
||||
#define I595_R2 0x02
|
||||
#define I595_R3 0x03
|
||||
#define I595_R4 0x04
|
||||
#define I595_R5 0x05
|
||||
#define I595_R6 0x06
|
||||
#define I595_R7 0x07
|
||||
#define I595_R8 0x08
|
||||
#define I595_R9 0x09
|
||||
#define I595_R10 0x0A
|
||||
#define I595_R11 0x0B
|
||||
#define I595_R12 0x0C
|
||||
#define I595_R13 0x0D
|
||||
#define I595_R14 0x0E
|
||||
#define I595_R15 0x0F
|
||||
#endif /* !I82595_REGS_CONTIGUOUS */
|
||||
|
||||
/*
|
||||
* Register 0 is special, as it's the same in all banks
|
||||
* Access Macro to Register 0.
|
||||
*/
|
||||
|
||||
#define SELECTBANK(c, b)(PCMCIA_IO_WRITE((c) + I595_R0, (b) << 6))
|
||||
#define RUNCMD(c, o) (PCMCIA_IO_WRITE((c) + I595_R0, \
|
||||
((o) & OPCODE_MASK)))
|
||||
#define ABORTCMD(c) (PCMCIA_IO_WRITE((c) + I595_R0, (1 << 5)))
|
||||
|
||||
/* 82595TX Command Set for register 0 */
|
||||
|
||||
#define CMD_MC_SETUP 0x03
|
||||
#define CMD_TRANSMIT 0x04
|
||||
#define CMD_TDR 0x05
|
||||
#define CMD_DUMP 0x06
|
||||
#define CMD_DIAGNOSE 0x07
|
||||
#define CMD_RCV_ENABLE 0x08
|
||||
#define CMD_RCV_DISABLE 0x0A
|
||||
#define CMD_RCV_STOP 0x0B
|
||||
#define CMD_ABORT 0x0D
|
||||
#define CMD_RESET 0x0E
|
||||
#define CMD_XMIT_RAW 0x14
|
||||
#define CMD_CONT_XMIT_LIST 0x15
|
||||
#define CMD_SET_TRISTATE 0x16
|
||||
#define CMD_RESET_TRISTATE 0x17
|
||||
#define CMD_POWER_DOWN 0x18
|
||||
#define CMD_RESUME_XMIT_LIST 0x1C
|
||||
#define CMD_SEL_RESET 0x1E
|
||||
|
||||
#define OPCODE_MASK 0x1F
|
||||
|
||||
/* 82595TX result codes for register 0 */
|
||||
|
||||
#define RESULT_INIT_DONE 0x0E
|
||||
|
||||
/* Definitions for fields and bits in the OLI_DEVICE */
|
||||
|
||||
/* I/O Bank 0 */
|
||||
|
||||
/* Reg 1 Interrupt/Status Register */
|
||||
|
||||
#define BNK0_RX_SIT 0x01 /* RX stop interrupt */
|
||||
#define BNK0_RX_IT 0x02 /* RX interrupt */
|
||||
#define BNK0_TX_IT 0x04 /* TX interrupt */
|
||||
#define BNK0_EXE_IT 0x08 /* Execution interrupt */
|
||||
#define BNK0_EXE_IDL 0x00 /* Execution state idle */
|
||||
#define BNK0_EXE_BSY 0x20 /* Execution state busy */
|
||||
#define BNK0_EXE_ART 0x30 /* Execution state aborting */
|
||||
#define BNK0_RCV_DIS 0x00 /* Receive state disable */
|
||||
#define BNK0_RCV_RDY 0x40 /* Receive state ready */
|
||||
#define BNK0_RCV_ACT 0x80 /* Receive state active */
|
||||
#define BNK0_RCV_STP 0xC0 /* Receive state stopping */
|
||||
|
||||
#define BNK0_ITS_MSK 0x0F /* All interrupts mask */
|
||||
#define BNK0_EXE_MSK 0x30 /* Execution state mask */
|
||||
#define BNK0_RCV_MSK 0xC0 /* Receive state mask */
|
||||
|
||||
#define BNK0_EXE_STE(r) ((r) & BNK0_EXE_MSK)
|
||||
#define BNK0_RCV_STE(r) ((r) & BNK0_RCV_MSK)
|
||||
|
||||
/* Reg 3 Interrupt Mask Register */
|
||||
|
||||
#define BNK0_RX_SMK 0x01 /* RX stop interrupt mask */
|
||||
#define BNK0_RX_MK 0x02 /* RX interrupt mask */
|
||||
#define BNK0_TX_MK 0x04 /* TX interrupt mask */
|
||||
#define BNK0_EXE_MK 0x08 /* Execution interrupt mask */
|
||||
#define BNK0_HAR_SLT 0x10 /* 32Bit IO port/host address select */
|
||||
#define BNK0_CBR_SLT 0x20 /* Current/Base register select */
|
||||
|
||||
/* I/O Bank 1 */
|
||||
|
||||
/* Reg 1 Config ISA Register/Tri-state irq lines */
|
||||
|
||||
#define BNK1_ISA_HBW 0x02 /* Host bus width (ISA only) */
|
||||
#define BNK1_ISA_ART 0x40 /* Alternate ready timing (ISA only) */
|
||||
#define BNK1_TST_EN 0x80 /* Tri-state interrupt lines */
|
||||
|
||||
/* I/O Bank 2 */
|
||||
|
||||
/* Reg 1 Control the program features of the 82595TX */
|
||||
|
||||
#define BNK2_TCP_DIS 0x01 /* Transmit concurrent processing disable */
|
||||
#define BNK2_PCM_ISA 0x10 /* PCMCIA/ISA Select */
|
||||
#define BNK2_TCH_END 0x20 /* Transmit chaining int mode */
|
||||
#define BNK2_TCH_ERR 0x40 /* Transmit chaining error stop */
|
||||
#define BNK2_BAD_DSC 0x80 /* Discard bad frames */
|
||||
|
||||
/* Reg 2 Control the program features of the 82595TX */
|
||||
|
||||
#define BNK2_PCS_EN 0x01 /* Promiscous mode enable */
|
||||
#define BNK2_BRO_DIS 0x02 /* Disable broadcast */
|
||||
#define BNK2_RX_CRC 0x04 /* RX CRC in memory */
|
||||
#define BNK2_LEN_DIS 0x08 /* Length disable */
|
||||
#define BNK2_SAI_EN 0x10 /* enable source address insertion */
|
||||
#define BNK2_MIA_EN 0x20 /* Multi individual address enable */
|
||||
#define BNK2_LP_DIS 0x00 /* Loopback disable */
|
||||
#define BNK2_LP_INT 0x40 /* Internal loopback */
|
||||
#define BNK2_LP_EXT 0x80 /* External loopback */
|
||||
|
||||
/* Reg 3 Control the program features of the 82595TX */
|
||||
|
||||
#define BNK2_LI_DIS 0x01 /* Link integrity disable */
|
||||
#define BNK2_PC_DIS 0x02 /* disable polarity correction */
|
||||
#define BNK2_TPE_AUI 0x04 /* TPE/AUI */
|
||||
#define BNK2_JB_DIS 0x08 /* Jabber disable */
|
||||
#define BNK2_AP_EN 0x10 /* APORT */
|
||||
#define BNK2_BNC_TPE 0x20 /* BNC/TPE */
|
||||
#define BNK2_TST_EN 0xC0 /* Production testing mode */
|
||||
|
||||
/* RCV status field*/
|
||||
|
||||
#define RCV_EOF 0x08 /* Reception of frame completed */
|
||||
#define RCV_BOF 0x10 /* Begining of frame bit */
|
||||
#define RCV_RXCPY 0x20 /* RCV copy threshold */
|
||||
#define RCV_RECLM 0x40 /* RCV-DMA reclaimes location */
|
||||
#define RCV_UNDRN 0x80 /* RCV data underrun */
|
||||
|
||||
#define RCV_COL_DCT 0x0001 /* Collision detected */
|
||||
#define RCV_IA_MCH 0x0002 /* Individual address match */
|
||||
#define RCV_SRT_FRM 0x0080 /* Received frame shorter than 64Bytes */
|
||||
#define RCV_OVR_RUN 0x0100 /* OVERRUN */
|
||||
#define RCV_ALG_ERR 0x0400 /* Alignment error */
|
||||
#define RCV_CRC_ERR 0x0800 /* CRC error */
|
||||
#define RCV_LEN_ERR 0x1000 /* Length error */
|
||||
#define RCV_OK 0x2000 /* Frame received OK */
|
||||
#define RCV_TYP_LEN 0x8000 /* Type field */
|
||||
|
||||
/* XMT status field*/
|
||||
|
||||
#define XMT_COL_MAX 0x0020 /* Failed due to max collisions */
|
||||
#define XMT_HRT_BET 0x0040 /* Collision detect test passed after prev Tx */
|
||||
#define XMT_LN_DEF 0x0080 /* Tx deferred due to link activity */
|
||||
#define XMT_UND_RUN 0x0100 /* Underrun */
|
||||
#define XMT_LST_CRS 0x0400 /* Carrier sense lost */
|
||||
#define XMT_LT_COL 0x0800 /* Later collision */
|
||||
#define XMT_OK 0x2000 /* Transmit OK */
|
||||
#define XMT_COLL 0x8000 /* Collision on the last transmit */
|
||||
|
||||
#define XMT_COL_MSK 0x000F /* number collisions mask */
|
||||
#define XMT_CHAIN 0x8000 /* Flag indicates a XMT chaining (16Bit) */
|
||||
#define XMT_CHAIN_OCT 0x80 /* Flag indicates a XMT chaining (8Bit) */
|
||||
|
||||
#define TOTAL_RAM_SIZE (64 * 1024)
|
||||
#define RAM_TX_BASE (0)
|
||||
#define RAM_TX_SIZE (32 * 1024)
|
||||
#define RAM_TX_LIMIT (RAM_TX_BASE + (RAM_TX_SIZE - 1))
|
||||
|
||||
#define RAM_RX_SIZE (TOTAL_RAM_SIZE - RAM_TX_SIZE)
|
||||
#define RAM_RX_BASE (RAM_TX_SIZE)
|
||||
#define RAM_RX_LIMIT (RAM_RX_BASE + (RAM_RX_SIZE - 1))
|
||||
|
||||
/*
|
||||
* Macro for converting from packet byte count to length in Tx ring
|
||||
* buffer which needs to include 8 bytes of header and half-word
|
||||
* alignment
|
||||
*/
|
||||
|
||||
#define COUNT_TO_LEN(x) ((x) + ((((x) & 0x01) == 0) ? 8 : 9))
|
||||
|
||||
/* Define Ethernet Network Driver parameters */
|
||||
|
||||
#define MAX_UNITS 1 /* max Olicom units */
|
||||
#define DRV_NAME "oli"
|
||||
#define DRV_NAME_LEN 4 /* including null terminator */
|
||||
#define EADDR_LEN 6
|
||||
#define OLI_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + EADDR_LEN)
|
||||
#define OLI_SPEED 10000000
|
||||
|
||||
#define TX_BD_MIN 2 /* minimum number of Tx buffer descriptors */
|
||||
#define TX_BD_MAX 0x14 /* maximum number of Tx buffer descriptors */
|
||||
#define RX_BD_MIN 2 /* minimum number of Rx buffer descriptors */
|
||||
#define TX_BD_DEFAULT 0x10 /* default number of Tx buffer descriptors */
|
||||
#define RX_BD_DEFAULT 0x10 /* default number of Rx buffer descriptors */
|
||||
#define OLI_MIN_FBUF 9 /* min. size of the first buffer in a frame */
|
||||
#define OLI_MAX_XMT 0x600 /* max. size of the XMT block mem. structure */
|
||||
#define NUM_LOAN 0x10 /* number of Rx loaner buffers in pool */
|
||||
|
||||
/* Define control structures */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef struct free_buf
|
||||
{
|
||||
void * pClBuf; /* pointer cluster buffer */
|
||||
} FREE_BUF;
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct end_device
|
||||
{
|
||||
END_OBJ endObj; /* The class we inherit from. */
|
||||
int unit; /* unit number */
|
||||
long flags; /* Our local flags. */
|
||||
|
||||
OLI_PCMCIA_CTRL pcmcia; /* PCMCIA control structure */
|
||||
int ivec; /* interrupt vector */
|
||||
int ilevel; /* interrupt level */
|
||||
|
||||
int txBdNum; /* number of transmit BD */
|
||||
TX_BD * txBdBase; /* transmit BD base address */
|
||||
int txBdNext; /* next transmit BD to fill */
|
||||
int txBdIndexC; /* current transmit BD index */
|
||||
|
||||
int rxBdNum; /* number of receive BD */
|
||||
RX_BD * rxBdBase; /* receive BD base address */
|
||||
int rxBdNext; /* next receive BD to read */
|
||||
|
||||
char * pShMem; /* real ptr to shared memory */
|
||||
ULONG shMemSize; /* shared memory size */
|
||||
|
||||
UINT8 enetAddr[EADDR_LEN]; /* ethernet address */
|
||||
int offset;
|
||||
|
||||
CACHE_FUNCS cacheFuncs; /* cache function pointers */
|
||||
FREE_BUF freeBuf[128]; /* Array of free routines. */
|
||||
CL_POOL_ID clPoolId;
|
||||
} END_DEVICE;
|
||||
|
||||
#define FLTR_FRM_SIZE 0x180 /* filter frm size 64 Multicast address */
|
||||
|
||||
/* Definitions for the flags field */
|
||||
|
||||
#define OLI_RCV_HANDLING 0x0001
|
||||
#define OLI_POLLING 0x0002 /* Poll mode */
|
||||
#define OLI_TX_CLEANING 0x0004
|
||||
#define OLI_TX_STOP 0x0008
|
||||
|
||||
#define OLI_MEMOWN 0x8000 /* memory allocated by driver */
|
||||
|
||||
/* state of transmit BD */
|
||||
|
||||
#define TX_BD_READY 0x80
|
||||
|
||||
/* state of receive BD */
|
||||
|
||||
#define RX_BD_EMPTY 0x01
|
||||
|
||||
/* definitions of several mask */
|
||||
|
||||
#define OCT_MSK 0xFF /* 8-bit mask */
|
||||
#define ODD_MSK 0x01 /* Odd mask */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCiOlicomEndh */
|
||||
@@ -0,0 +1,491 @@
|
||||
/* ln97xEnd.h - END style AMD Am79C97X PCnet-PCI Ethernet driver header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998-2002, 2004, 2010, 2013 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
/* Copyright 1998 CETIA Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,21mar13,fao Increase LN_BUFSIZ for maximum ethernet payload.(WIND00408872)
|
||||
01j,29apr10,pad Moved extern C statement after include statements.
|
||||
01i,26sep05,wap Add TX underflow error indication flag (SPR #111881)
|
||||
01h,02nov04,wap Fixed SPR# 102962 and SPR# 103409
|
||||
01g,08aug04,sru Added fields to support fast phys-to-virt translation.
|
||||
01f,30may02,sru Added REG_SWAP and LS_MODE_NOSWAP_MASTER definitions.
|
||||
01e,12nov01,pai Added definitions for CSR5 and CSR8-CSR11 fields. Setup
|
||||
PCI_SWAP definition in one place. Doubled the number of
|
||||
receive and transmit descriptors the device will use.
|
||||
Removed obsolete <errorStat> member from DRV_CTRL.
|
||||
Removed superfluous "arch-specific" (CPU_FAMILY==I80X86)
|
||||
macros.
|
||||
01d,27mar01,tlc Add definitions for interrupt level and PCI bus endianess.
|
||||
Revised how PCI_SWAP is defined. It is now conditionally
|
||||
defined based on the ln97xEndianess parameter set in
|
||||
ln97xParamInit().
|
||||
01c,11jun00,ham removed reference to etherLib.
|
||||
01b,19may00,pai Implemented accumulated driver bug fixes (SPR #31349).
|
||||
01a,07dec98,snk added support 7997x[012] across architectures.
|
||||
written from 01b of lnPciEnd.h
|
||||
*/
|
||||
|
||||
#ifndef __INCln97xEndh
|
||||
#define __INCln97xEndh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include "end.h"
|
||||
#include "cacheLib.h"
|
||||
#include "netinet/if_ether.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* define the various levels of debugging if the DRV_DEBUG is defined */
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
# include "logLib.h"
|
||||
# define DRV_DEBUG_OFF 0x0000
|
||||
# define DRV_DEBUG_RX 0x0001
|
||||
# define DRV_DEBUG_TX 0x0002
|
||||
# define DRV_DEBUG_INT 0x0004
|
||||
# define DRV_DEBUG_POLL (DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
|
||||
# define DRV_DEBUG_POLL_RX 0x0008
|
||||
# define DRV_DEBUG_POLL_TX 0x0010
|
||||
# define DRV_DEBUG_LOAD 0x0020
|
||||
# define DRV_DEBUG_LOAD2 0x0040
|
||||
# define DRV_DEBUG_IOCTL 0x0080
|
||||
# define DRV_DEBUG_RESET 0x0100
|
||||
# define DRV_DEBUG_MCAST 0x0200
|
||||
# define DRV_DEBUG_CSR 0x0400
|
||||
# define DRV_DEBUG_RX_PKT 0x0800
|
||||
# define DRV_DEBUG_POLL_REDIR 0x10000
|
||||
# define DRV_DEBUG_LOG_NVRAM 0x20000
|
||||
# define DRV_DEBUG_ALL 0xfffff
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
/* board level/bus specific and architecture specific macros */
|
||||
|
||||
#if _BYTE_ORDER==_BIG_ENDIAN
|
||||
# define PCI_SWAP(x) ((ln97xBusEndianess) ? (int)(x) : LONGSWAP((int)(x)))
|
||||
#else
|
||||
# define PCI_SWAP(x) (x)
|
||||
#endif
|
||||
|
||||
#if _BYTE_ORDER==_BIG_ENDIAN
|
||||
# define REG_SWAP(d,x) (((d)->flags & LS_MODE_NOSWAP_MASTER) ? \
|
||||
(int)(x) : LONGSWAP((int)(x)))
|
||||
#else
|
||||
# define REG_SWAP(d,x) (x)
|
||||
#endif
|
||||
|
||||
/* device IO or memory mapped access and data registers */
|
||||
|
||||
#define LN_97X_RDP ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x10))
|
||||
#define LN_97X_RAP ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x14))
|
||||
#define LN_97X_RST ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x18))
|
||||
#define LN_97X_BDP ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x1C))
|
||||
|
||||
/* csr and bcr addresses */
|
||||
|
||||
#define CSR(x) (x)
|
||||
#define BCR(x) (x)
|
||||
|
||||
/* Definitions for fields and bits in the device */
|
||||
|
||||
#define CSR0_RESRVD 0xffff0000 /* resvd: written 0, read undefined */
|
||||
#define CSR0_ERR 0x8000 /* (RO) err flg (BABL|CERR|MISS|MERR) */
|
||||
#define CSR0_BABL 0x4000 /* (RC) babble transmitter timeout */
|
||||
#define CSR0_CERR 0x2000 /* (RC) collision error */
|
||||
#define CSR0_MISS 0x1000 /* (RC) missed packet */
|
||||
#define CSR0_MERR 0x0800 /* (RC) memory error */
|
||||
#define CSR0_RINT 0x0400 /* (RC) receiver interrupt */
|
||||
#define CSR0_TINT 0x0200 /* (RC) transmitter interrupt */
|
||||
#define CSR0_IDON 0x0100 /* (RC) initialization done */
|
||||
#define CSR0_INTR 0x0080 /* (RO) interrupt flag */
|
||||
#define CSR0_INEA 0x0040 /* (RW) interrupt enable */
|
||||
#define CSR0_RXON 0x0020 /* (RO) receiver on */
|
||||
#define CSR0_TXON 0x0010 /* (RO) transmitter on */
|
||||
#define CSR0_TDMD 0x0008 /* (WOO)transmit demand */
|
||||
#define CSR0_STOP 0x0004 /* (WOO)stop (& reset) chip */
|
||||
#define CSR0_STRT 0x0002 /* (RW) start chip */
|
||||
#define CSR0_INIT 0x0001 /* (RW) initialize (acces init block) */
|
||||
|
||||
#define CSR0_INTMASK (CSR0_BABL | CSR0_CERR | CSR0_MISS | \
|
||||
CSR0_MERR | CSR0_RINT | CSR0_TINT | \
|
||||
CSR0_IDON | CSR0_INEA)
|
||||
|
||||
#define CSR3_DXSUFLO 0x0040 /* disable transmit stop on UFLO */
|
||||
#define CSR3_BSWP 0x0004 /* Byte Swap */
|
||||
|
||||
/* CSR 4 test and features control */
|
||||
|
||||
#define CSR4_EN124 0x8000 /* enable CSR124 access */
|
||||
#define CSR4_DMAPLUS 0x4000 /* disable DMA burst xfer counter */
|
||||
#define CSR4_TIMER 0x2000 /* enable bus activity timer */
|
||||
#define CSR4_DPOLL 0x1000 /* disable transmit polling */
|
||||
#define CSR4_APAD_XMIT 0x0800 /* enable auto pad transmit */
|
||||
#define CSR4_ASTRP_RCV 0x0400 /* enable auto pad stripping */
|
||||
#define CSR4_MFCO 0x0200 /* missed frame counter overflow */
|
||||
#define CSR4_MFCOM 0x0100 /* missed frame counter mask */
|
||||
#define CSR4_UINTCMD 0x0080 /* user interrupt command */
|
||||
#define CSR4_UINT 0x0040 /* user interrupt issued */
|
||||
#define CSR4_RCVCC0 0x0020 /* receive collision cntr overflow */
|
||||
#define CSR4_RCVCCOM 0x0010 /* receive collision cntr mask */
|
||||
#define CSR4_TXSTRT 0x0008 /* transmit start status */
|
||||
#define CSR4_TXSTRTM 0x0004 /* transmit start mask */
|
||||
#define CSR4_JAB 0x0002 /* jabber error indicated */
|
||||
#define CSR4_JABM 0x0001 /* jabber error mask */
|
||||
|
||||
#define CSR4_TFC_MASK (CSR4_MFCOM | CSR4_RCVCCOM | \
|
||||
CSR4_TXSTRTM | CSR4_JABM)
|
||||
|
||||
/* CSR 5 extended control and interrupt */
|
||||
|
||||
#define CSR5_RESRVD_B 0xffff0000 /* resvd: written 0, read undefined */
|
||||
#define CSR5_TOKINTD 0x00008000 /* transmit OK interrupt disable */
|
||||
#define CSR5_LTINTEN 0x00004000 /* last transmit interrupt enable */
|
||||
#define CSR5_RESRVD_A 0x00003000 /* resvd: written 0, read undefined */
|
||||
#define CSR5_SINT 0x00000800 /* system interrupt asserted */
|
||||
#define CSR5_SINTE 0x00000400 /* system interrupt enable */
|
||||
#define CSR5_SLPINT 0x00000200 /* sleep interrupt asserted */
|
||||
#define CSR5_SLPINTE 0x00000100 /* sleep interrupt enable */
|
||||
#define CSR5_EXDINT 0x00000080 /* excessive deferral asserted */
|
||||
#define CSR5_EXDINTE 0x00000040 /* excessive deferral int. enable */
|
||||
#define CSR5_MPPLBA 0x00000020 /* magic packet broadcast accept */
|
||||
#define CSR5_MPINT 0x00000010 /* magic packet int. asserted */
|
||||
#define CSR5_MPINTE 0x00000008 /* magic packet int. enable */
|
||||
#define CSR5_MPEN 0x00000004 /* magic packet mode enable */
|
||||
#define CSR5_MPMODE 0x00000002 /* set magic packet mode */
|
||||
#define CSR5_SPND 0x00000001 /* set suspend mode */
|
||||
|
||||
#define CSR5_RESRVD_MASK (~(CSR5_RESRVD_B | CSR5_RESRVD_A))
|
||||
|
||||
/* CSR 8 logical address filter 0 */
|
||||
|
||||
#define CSR8_RESRVD 0xffff0000 /* reserved locations, write as 0 */
|
||||
#define CSR8_LADRF0 0x0000ffff /* logical address filter [15:0] */
|
||||
|
||||
/* CSR 9 logical address filter 1 */
|
||||
|
||||
#define CSR9_RESRVD 0xffff0000 /* reserved locations, write as 0 */
|
||||
#define CSR9_LADRF1 0x0000ffff /* logical address filter [31:16] */
|
||||
|
||||
/* CSR 10 logical address filter 2 */
|
||||
|
||||
#define CSR10_RESRVD 0xffff0000 /* reserved locations, write as 0 */
|
||||
#define CSR10_LADRF2 0x0000ffff /* logical address filter [47:32] */
|
||||
|
||||
/* CSR 11 logical address filter 3 */
|
||||
|
||||
#define CSR11_RESRVD 0xffff0000 /* reserved locations, write as 0 */
|
||||
#define CSR11_LADRF3 0x0000ffff /* logical address filter [63:48] */
|
||||
|
||||
/* CSR 15 mode register - loaded from initialization block */
|
||||
|
||||
#define CSR15_PROM 0x00008000 /* set promiscuous mode */
|
||||
#define CSR15_DTX 0x00000002 /* disable transmitter section */
|
||||
#define CSR15_DRX 0x00000001 /* disable receiver section */
|
||||
|
||||
/* CSR 80 RX and TX FIFO threshold register */
|
||||
|
||||
#define CSR80_TXTHR0 0x0400 /* TX threshold low bit */
|
||||
#define CSR80_TXTHR1 0x0800 /* TX threshold hi bit */
|
||||
#define CSR80_DEFAULT 0x1410 /* chip default value */
|
||||
|
||||
/* CSR 88 and CSR 89 chip ID registers */
|
||||
|
||||
#define CSR88_LN970_PARTID 0x00001003 /* Am79c970 part ID lower value */
|
||||
#define CSR88_LN971_PARTID 0x00003003 /* Am79c971 part ID lower value */
|
||||
#define CSR88_LN972_PARTID 0x00004003 /* Am79c972 part ID lower value */
|
||||
#define CSR88_LN973_PARTID 0x00005003 /* Am79c973 part ID lower value */
|
||||
#define CSR88_LN975_PARTID 0x00007003 /* Am79c975 part ID lower value */
|
||||
|
||||
#define CSR89_LN97X_PARTID 0x00000262 /* Am79c97x part ID upper value */
|
||||
|
||||
/* chip ID values are formed as follows:
|
||||
*
|
||||
* chipId = (CSR(88) | (CSR(89) << 16))
|
||||
* chipId = (chipId >> 12) & 0xffff
|
||||
*/
|
||||
|
||||
#define CHIP_ID_AM79C970A (0x2621) /* PCnet-PCI II Am79C970A */
|
||||
#define CHIP_ID_AM79C971 (0x2623) /* PCnet-FAST Am79C971 */
|
||||
#define CHIP_ID_AM79C972 (0x2624) /* PCnet-FAST + Am79C972 */
|
||||
#define CHIP_ID_AM79C973 (0x2625) /* PCnet-FAST III Am79C973 */
|
||||
#define CHIP_ID_AM79C975 (0x2627) /* PCnet Fast III Am79C975 */
|
||||
|
||||
/* BCR 2 */
|
||||
|
||||
#define BCR2_LEDPE 0x1000 /* LED program enable */
|
||||
#define BCR2_AUTO_SELECT 0x0002 /* auto select port type 10BT/AUI */
|
||||
#define BCR2_ACTIVE_HIGH 0x80 /* select active high interrupt pin */
|
||||
#define BCR2_ACTIVE_LOW 0x00 /* select active low interrupt pin */
|
||||
|
||||
/* BCR 18 burst size and bus control register */
|
||||
|
||||
#define BCR18_ROMTMG 0x9000 /* expansion ROM timing (default) */
|
||||
#define BCR18_NOUFLO 0x0800 /* TX store and forward mode */
|
||||
#define BCR18_MEMCMD 0x0200 /* enable PCI memory read multiple */
|
||||
#define BCR18_BREADE 0x0040 /* burst read enable (SWSTYLE=3) */
|
||||
#define BCR18_BWRITE 0x0020 /* burst write enable (SWSTYLE=3) */
|
||||
#define BCR18_RESRVD 0x0001 /* reserved location (default) */
|
||||
|
||||
#define BCR18_BSBC_MASK (BCR18_ROMTMG | BCR18_RESRVD | \
|
||||
BCR18_BREADE | BCR18_BWRITE)
|
||||
|
||||
/* BCR 20 software style register */
|
||||
|
||||
#define BCR20_SSIZE32 0x0100
|
||||
#define BCR20_SWSTYLE_LANCE 0x0000
|
||||
#define BCR20_SWSTYLE_ILACC 0x0001
|
||||
#define BCR20_SWSTYLE_PCNET 0x0002
|
||||
#define BCR20_SWSTYLE_PCNET_II 0x0003
|
||||
|
||||
/* Control block definitions for AMD PCnet (Ethernet) chip. */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
ULONG rdp; /* register data Port */
|
||||
ULONG rap; /* Register Address Port */
|
||||
ULONG rst; /* Reset Register */
|
||||
ULONG bdp; /* Bus Configuration Register Data Port */
|
||||
} LN_DEVICE;
|
||||
|
||||
/* Initialization Block */
|
||||
|
||||
typedef struct lnIB
|
||||
{
|
||||
ULONG lnIBMode; /* mode register */
|
||||
UCHAR lnIBPadr [8]; /* PADR: bswapd ethnt phys address */
|
||||
UCHAR lnIBLadrf [8]; /* logical address filter */
|
||||
ULONG lnIBRdra; /* RDRA: read ring address, long word */
|
||||
ULONG lnIBTdra; /* TDRA: transmit ring address long word */
|
||||
} LN_IB;
|
||||
|
||||
/* Receive Message Descriptor Entry.*/
|
||||
|
||||
typedef struct lnRMD
|
||||
{
|
||||
/* element order changed to accomodate burst mode operation */
|
||||
ULONG lnRMD2; /* message byte count */
|
||||
ULONG lnRMD1; /* status & buffer byte count (negative) */
|
||||
ULONG lnRMD0; /* bits 31:00 of receive buffer address */
|
||||
ULONG lnRMD3; /* reserved */
|
||||
} LN_RMD;
|
||||
|
||||
/* Transmit Message Descriptor Entry. */
|
||||
|
||||
typedef struct lnTMD
|
||||
{
|
||||
/* element order changed to accomodate burst mode operation */
|
||||
ULONG lnTMD2; /* errors */
|
||||
ULONG lnTMD1; /* message byte count */
|
||||
ULONG lnTMD0; /* bits 31:00 of transmit buffer address */
|
||||
ULONG lnTMD3; /* reserved */
|
||||
} LN_TMD;
|
||||
|
||||
typedef union addrFilter /* logical address filter layout */
|
||||
{
|
||||
UINT8 lafBytes [8]; /* (8) bytes */
|
||||
UINT16 lafWords [4]; /* (4) 16-bit words */
|
||||
UINT32 lafDwords [2]; /* (2) 32-bit dwords */
|
||||
} ADDR_FILTER;
|
||||
|
||||
typedef enum filterModCmd /* addrFilterMod() commands */
|
||||
{
|
||||
LN_LADRF_ADD, /* add a logical address */
|
||||
LN_LADRF_DEL, /* delete a logical address */
|
||||
LN_LADRF_ADD_ALL, /* add all logical addresses */
|
||||
LN_LADRF_DEL_ALL /* delete all logical addresses */
|
||||
} FILTER_MOD_CMD;
|
||||
|
||||
/* initialization block */
|
||||
|
||||
#define IB_MODE_TLEN_MSK 0xf0000000
|
||||
#define IB_MODE_RLEN_MSK 0x00f00000
|
||||
|
||||
/* receive descriptor */
|
||||
|
||||
#define RMD1_OWN 0x80000000 /* Own */
|
||||
#define RMD1_ERR 0x40000000 /* Error */
|
||||
#define RMD1_FRAM 0x20000000 /* Framming Error */
|
||||
#define RMD1_OFLO 0x10000000 /* Overflow */
|
||||
#define RMD1_CRC 0x08000000 /* CRC */
|
||||
#define RMD1_BUFF 0x04000000 /* Buffer Error */
|
||||
#define RMD1_STP 0x02000000 /* Start of Packet */
|
||||
#define RMD1_ENP 0x01000000 /* End of Packet */
|
||||
#define RMD1_RES 0x00ff0000 /* reserved */
|
||||
#define RMD1_CNST 0x0000f000 /* rmd1 constant value */
|
||||
|
||||
#define RMD1_BCNT_MSK 0x00000fff /* buffer cnt mask */
|
||||
#define RMD2_MCNT_MSK 0x00000fff /* message buffer cnt mask */
|
||||
|
||||
/* transmit descriptor */
|
||||
|
||||
#define TMD1_OWN 0x80000000 /* Own */
|
||||
#define TMD1_ERR 0x40000000 /* Error */
|
||||
#define TMD1_MORE 0x10000000 /* More than One Retry */
|
||||
#define TMD1_ONE 0x08000000 /* One Retry */
|
||||
#define TMD1_DEF 0x04000000 /* Deferred */
|
||||
#define TMD1_STP 0x02000000 /* Start of Packet */
|
||||
#define TMD1_ENP 0x01000000 /* End of Packet */
|
||||
#define TMD1_BPE 0x00800000 /* Bus Parity Error */
|
||||
#define TMD1_RES 0x007F0000 /* Reserved locations */
|
||||
#define TMD1_CNST 0x0000f000 /* tmd1 constant value */
|
||||
|
||||
#define TMD2_BUFF 0x80000000 /* Buffer Error */
|
||||
#define TMD2_UFLO 0x40000000 /* Underflow Error */
|
||||
#define TMD2_LCOL 0x10000000 /* Late Collision */
|
||||
#define TMD2_LCAR 0x08000000 /* Lost Carrier */
|
||||
#define TMD2_RTRY 0x04000000 /* Retry Error */
|
||||
#define TMD2_TDR 0x03FF0000 /* Time Domain Reflectometry */
|
||||
|
||||
#define TMD1_BCNT_MSK 0x00000fff /* buffer cnt mask */
|
||||
|
||||
/* CRC for logical address filter */
|
||||
|
||||
#define LN_CRC_POLYNOMIAL (0xedb88320) /* Ethernet CRC polynomial */
|
||||
#define LN_CRC_TO_LAF_IX(crc) ((crc) >> 26) /* get 6 MSBits */
|
||||
#define LN_LAF_LEN (8) /* logical addr filter length */
|
||||
#define LN_LA_LEN (6) /* logical address length */
|
||||
#define BITS_PER_LA (8 * LN_LA_LEN) /* logical addr length bits */
|
||||
|
||||
/* Definitions for the drvCtrl specific flags field */
|
||||
|
||||
#define LS_PROMISCUOUS_FLAG 0x1 /* set the promiscuous mode */
|
||||
#define LS_MEM_ALLOC_FLAG 0x2 /* allocating memory flag */
|
||||
#define LS_PAD_USED_FLAG 0x4 /* padding used flag */
|
||||
#define LS_RCV_HANDLING_FLAG 0x8 /* handling recv packet */
|
||||
#define LS_START_OUTPUT_FLAG 0x10 /* trigger output flag */
|
||||
#define LS_POLLING 0x20 /* polling flag */
|
||||
#define LS_MODE_MEM_IO_MAP 0x100 /* device registers memory mapped */
|
||||
#define LS_MODE_DWIO 0x200 /* device in 32 bit mode */
|
||||
#define LS_MODE_NOSWAP_MASTER 0x400 /* don't swap PCI master I/O ops */
|
||||
#define LS_TX_UFLO 0x800 /* TX underflow occured */
|
||||
|
||||
/* descriptor size */
|
||||
|
||||
#define RMD_SIZ sizeof(LN_RMD)
|
||||
#define TMD_SIZ sizeof(LN_TMD)
|
||||
#define IB_SIZ sizeof(LN_IB)
|
||||
|
||||
/* How much work we're allowed to do in the RX handler (# of pkts processed) */
|
||||
|
||||
#define LN_RX_LIMIT 16
|
||||
|
||||
/* How many descriptors we want to use up in a single gather-write transmit */
|
||||
|
||||
#define LN_MAX_FRAGS 16
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct ln97xDevice
|
||||
{
|
||||
END_OBJ endObj; /* The class we inherit from */
|
||||
|
||||
int unit; /* unit number of the device */
|
||||
volatile LN_IB * ib; /* ptr to Initialization Block */
|
||||
|
||||
int rmdIndex; /* current RMD send index */
|
||||
int rringSize; /* RMD ring size */
|
||||
int rringLen; /* RMD ring length (bytes) */
|
||||
volatile LN_RMD * pRring; /* RMD ring start */
|
||||
|
||||
int tmdIndex; /* current TMD transmit index */
|
||||
int tmdIndexC; /* current TMD cleaning index */
|
||||
int tringSize; /* TMD ring size */
|
||||
int tringLen; /* TMD ring length (bytes) */
|
||||
volatile LN_TMD * pTring; /* TMD ring start */
|
||||
|
||||
int inum; /* interrupt number */
|
||||
int ilevel; /* interrupt level */
|
||||
|
||||
volatile UINT32 * pRdp; /* device register CSR */
|
||||
volatile UINT32 * pRap; /* device register RAP */
|
||||
volatile UINT32 * pReset; /* device register Reset */
|
||||
volatile UINT32 * pBdp; /* device register BCR */
|
||||
|
||||
volatile char * pShMem; /* real ptr to shared memory */
|
||||
volatile char * pShMemEnd; /* real ptr to shared memory end */
|
||||
volatile char * memBase; /* PCnet memory pool base */
|
||||
volatile char * memAdrs; /* PCnet memory pool base */
|
||||
|
||||
UINT32 shMemPtoVOffset; /* bias to convert pShMem P->V */
|
||||
|
||||
UINT32 devAdrs; /* device structure address */
|
||||
UINT16 csr3B; /* csr3 value board specific */
|
||||
UINT32 chipId; /* (csr88|csr89) chip ID value */
|
||||
int memSize; /* PCnet memory pool size */
|
||||
int memWidth; /* width of data port */
|
||||
int offset; /* offset of data in the buffer */
|
||||
volatile UINT32 flags; /* Our local flags */
|
||||
UINT32 pciMemBase; /* memory base as seen from PCI*/
|
||||
UINT8 enetAddr[6]; /* ethernet address */
|
||||
CACHE_FUNCS cacheFuncs; /* cache function pointers */
|
||||
|
||||
volatile BOOL txBlocked; /* transmit flow control */
|
||||
volatile BOOL txCleaning; /* transmit descriptor cleaning */
|
||||
|
||||
CL_POOL_ID pClPoolId; /* cluster pool Id */
|
||||
M_CL_CONFIG mClCfg; /* mBlk & cluster config structure */
|
||||
CL_DESC clDesc; /* cluster descriptor table */
|
||||
|
||||
END_ERR lastError; /* Last error passed to muxError */
|
||||
volatile BOOL errorHandling; /* task level error handling */
|
||||
|
||||
M_BLK_ID * mBlks; /* saved mBlk pointers */
|
||||
|
||||
} LN_97X_DRV_CTRL;
|
||||
|
||||
/* Configuration items */
|
||||
|
||||
#define LN_MIN_FBUF (100) /* Min sizeof first buffer in chain */
|
||||
#define LN_BUFSIZ (1536)
|
||||
#define LN_SPEED (10000000)
|
||||
#define LN_RMD_RLEN (7) /* ring size as a ^ 2 => 128 RMD's */
|
||||
#define LN_TMD_TLEN (7) /* ring size as a ^ 2 => 128 TMD's */
|
||||
#define LN_RMD_MIN (2) /* min descriptors 4 */
|
||||
#define LN_TMD_MIN (2) /* min descriptors 4 */
|
||||
#define LN_RMD_MAX (9) /* max descriptors 512 */
|
||||
#define LN_TMD_MAX (9) /* max descriptors 512 */
|
||||
#define LN_97X_DEV_NAME "lnPci" /* name of the device */
|
||||
#define LN_97X_DEV_NAME_LEN (6) /* length of the name string */
|
||||
#define LN_97X_APROM_SIZE (32) /* hardware Address PROM size bytes */
|
||||
#define LN_LITTLE_ENDIAN (0) /* little endian PCI bus */
|
||||
#define LN_BIG_ENDIAN (1) /* big endian PCI bus */
|
||||
#define LN_ACTIVE_LOW (0) /* active-low interrupt line */
|
||||
#define LN_ACTIVE_HI (1) /* active-high interrupt line */
|
||||
|
||||
#define LN_RMD_OWNED(rmd) (PCI_SWAP ((rmd)->lnRMD1) & RMD1_OWN)
|
||||
#define LN_TMD_OWNED(tmd) (PCI_SWAP ((tmd)->lnTMD1) & TMD1_OWN)
|
||||
|
||||
#define LN_PKT_LEN_GET(rmd) (PCI_SWAP ((rmd)->lnRMD2) - 4)
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
|
||||
IMPORT STATUS ln97xInitParse (LN_97X_DRV_CTRL * pDrvCtrl, char * initString);
|
||||
IMPORT END_OBJ * ln97xEndLoad (char * initString);
|
||||
|
||||
#else
|
||||
|
||||
IMPORT STATUS ln97xInitParse ();
|
||||
IMPORT END_OBJ * ln97xEndLoad ();
|
||||
|
||||
#endif /* __STDC__ */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCln97xEndh */
|
||||
|
||||
@@ -0,0 +1,780 @@
|
||||
/* m5200FecEnd.h - Motorola MPC5200 Ethernet network interface header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998, 2003-2005, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify, or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,05feb10,c_t m5200FecEnd auto neg may fail with high sysClkRate
|
||||
01h,04jan10,c_t correct individual & group register offset
|
||||
01g,17feb05,j_b add undocumented XFIFO Control Register bit to set with Rev.B
|
||||
01f,10jan05,k_p replaced sysEnetAddrGet() with sysFecEnetAddrGet() as a part
|
||||
of 'M' command modification and cleanups.
|
||||
01e,17jun04,bjn RFIFO_ERROR - changes to fecStop/fecStart.
|
||||
01d,25may04,bjn resolve various issues, see change log details (SPR97198)
|
||||
01c,15mar04,bjn Support for Bestcomm 2.0
|
||||
01b,18Jul03,pkr adopted from motFecEnd
|
||||
01a,09nov98,cn written.
|
||||
*/
|
||||
|
||||
/*
|
||||
change log details
|
||||
------------------
|
||||
01e * Added stoppingTx for handling of RFIFO_ERROR/XFIFO_ERROR
|
||||
01d * Increase FEC_END_BD_LOAN_NUM from 32 to 64. This creates more
|
||||
network cluster buffers for the system to use and is necessary
|
||||
to allow ping buffer sizes of 65500 bytes to be returned.
|
||||
This results in m5200FecInitMem() allocating much more memory,
|
||||
so this parameter is best trimmed to suit the application.
|
||||
* Added BUF_TYPE_LOCAL, txBuffAvailable and pTxBuffLocal, requied
|
||||
to ensure that TX packets get sent to the wire when NET_BUF_ALLOC()
|
||||
returns NULL.
|
||||
*/
|
||||
|
||||
#ifndef __INCm5200FecEndh
|
||||
#define __INCm5200FecEndh
|
||||
|
||||
/* includes */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/* revision D.3 and greater processors require special FEC initialization */
|
||||
|
||||
#define REV_D_4 0x0502
|
||||
#define REV_D_3 0x0501
|
||||
|
||||
/*
|
||||
* redefine the macro below in the bsp if you need to access the device
|
||||
* registers/descriptors in a more suitable way.
|
||||
*/
|
||||
|
||||
#ifndef FEC_END_LONG_WR
|
||||
#define FEC_END_LONG_WR(addr, value) \
|
||||
(* (addr) = ((UINT32) (value)))
|
||||
#endif /* FEC_END_LONG_WR */
|
||||
|
||||
#ifndef FEC_END_WORD_WR
|
||||
#define FEC_END_WORD_WR(addr, value) \
|
||||
(* (addr) = ((UINT16) (value)))
|
||||
#endif /* FEC_END_WORD_WR */
|
||||
|
||||
#ifndef FEC_END_BYTE_WR
|
||||
#define FEC_END_BYTE_WR(addr, value) \
|
||||
(* (addr) = ((UINT8) (value)))
|
||||
#endif /* FEC_END_BYTE_WR */
|
||||
|
||||
#ifndef FEC_END_LONG_RD
|
||||
#define FEC_END_LONG_RD(addr, value) \
|
||||
((value) = (* (UINT32 *) (addr)))
|
||||
#endif /* FEC_END_LONG_RD */
|
||||
|
||||
#ifndef FEC_END_WORD_RD
|
||||
#define FEC_END_WORD_RD(addr, value) \
|
||||
((value) = (* (UINT16 *) (addr)))
|
||||
#endif /* FEC_END_WORD_RD */
|
||||
|
||||
#ifndef FEC_END_BYTE_RD
|
||||
#define FEC_END_BYTE_RD(addr, value) \
|
||||
((value) = (* (UINT8 *) (addr)))
|
||||
#endif /* FEC_END_BYTE_RD */
|
||||
|
||||
/*
|
||||
* Default macro definitions for BSP interface.
|
||||
* These macros can be redefined in a wrapper file, to generate
|
||||
* a new module with an optimized interface.
|
||||
*/
|
||||
|
||||
#ifndef SYS_FEC_INT_CONNECT
|
||||
#define SYS_FEC_INT_CONNECT(pDrvCtrl, pFuncFEC, pFuncRDMA, pFuncWDMA, arg, ret) \
|
||||
{ \
|
||||
IMPORT STATUS intConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int); \
|
||||
ret = OK; \
|
||||
if (!pDrvCtrl->intrConnect) \
|
||||
{ \
|
||||
if (FEC_END_FEC_VECTOR (pDrvCtrl)) \
|
||||
{ \
|
||||
ret = (intConnect) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEC_END_FEC_VECTOR (pDrvCtrl)), \
|
||||
(pFuncFEC), (int) (arg)); \
|
||||
} \
|
||||
\
|
||||
if (FEC_END_RDMA_VECTOR (pDrvCtrl)) \
|
||||
{ \
|
||||
ret = (intConnect) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEC_END_RDMA_VECTOR (pDrvCtrl)),\
|
||||
(pFuncRDMA), (int) (arg)); \
|
||||
} \
|
||||
\
|
||||
if (FEC_END_WDMA_VECTOR (pDrvCtrl)) \
|
||||
{ \
|
||||
ret = (intConnect) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEC_END_WDMA_VECTOR (pDrvCtrl)), \
|
||||
(pFuncWDMA), (int) (arg)); \
|
||||
} \
|
||||
pDrvCtrl->intrConnect = TRUE; \
|
||||
} \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_CONNECT */
|
||||
|
||||
|
||||
|
||||
#ifndef SYS_FEC_INT_DISCONNECT
|
||||
|
||||
#define SYS_FEC_INT_DISCONNECT(pDrvCtrl, pFuncFEC, pFuncRDMA, pFuncWDMA, arg, ret) \
|
||||
{ \
|
||||
ret = OK; \
|
||||
if ( m5200FecIntDisc != NULL) \
|
||||
{ \
|
||||
if (FEC_END_FEC_VECTOR (pDrvCtrl)) \
|
||||
{ \
|
||||
ret = (*m5200FecIntDisc) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEC_END_FEC_VECTOR (pDrvCtrl)), \
|
||||
(pFuncFEC)); \
|
||||
} \
|
||||
\
|
||||
if (FEC_END_RDMA_VECTOR (pDrvCtrl)) \
|
||||
{ \
|
||||
ret = (*m5200FecIntDisc) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEC_END_RDMA_VECTOR (pDrvCtrl)), \
|
||||
(pFuncRDMA)); \
|
||||
} \
|
||||
\
|
||||
if (FEC_END_WDMA_VECTOR (pDrvCtrl)) \
|
||||
{ \
|
||||
ret = (*m5200FecIntDisc) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (FEC_END_WDMA_VECTOR (pDrvCtrl)), \
|
||||
(pFuncWDMA)); \
|
||||
} \
|
||||
pDrvCtrl->intrConnect = FALSE; \
|
||||
} \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_DISCONNECT */
|
||||
|
||||
|
||||
#ifndef SYS_FEC_INT_ENABLE
|
||||
#define SYS_FEC_INT_ENABLE(pDrvCtrl, ret) \
|
||||
{ \
|
||||
IMPORT int intEnable (int); \
|
||||
ret = OK; \
|
||||
if (FEC_END_FEC_VECTOR (pDrvCtrl)) \
|
||||
ret = intEnable ((int) (FEC_END_FEC_VECTOR (pDrvCtrl))); \
|
||||
if (FEC_END_RDMA_VECTOR (pDrvCtrl)) \
|
||||
ret = intEnable ((int) (FEC_END_RDMA_VECTOR (pDrvCtrl))); \
|
||||
if (FEC_END_WDMA_VECTOR (pDrvCtrl)) \
|
||||
ret = intEnable ((int) (FEC_END_WDMA_VECTOR (pDrvCtrl))); \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_ENABLE */
|
||||
|
||||
|
||||
#ifndef SYS_FEC_INT_DISABLE
|
||||
|
||||
#define SYS_FEC_INT_DISABLE(pDrvCtrl, ret) \
|
||||
{ \
|
||||
IMPORT int intDisable (int); \
|
||||
ret = OK; \
|
||||
if (FEC_END_FEC_VECTOR (pDrvCtrl)) \
|
||||
ret = intDisable ((int) (FEC_END_FEC_VECTOR (pDrvCtrl))); \
|
||||
if (FEC_END_RDMA_VECTOR (pDrvCtrl)) \
|
||||
ret = intDisable ((int) (FEC_END_RDMA_VECTOR (pDrvCtrl))); \
|
||||
if (FEC_END_WDMA_VECTOR (pDrvCtrl)) \
|
||||
ret = intDisable ((int) (FEC_END_WDMA_VECTOR (pDrvCtrl))); \
|
||||
}
|
||||
|
||||
#endif /* SYS_FEC_INT_DISABLE */
|
||||
|
||||
#define SYS_FEC_ENET_ADDR_GET(address) \
|
||||
if (sysFecEnetAddrGet != NULL) \
|
||||
if (sysFecEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR) \
|
||||
{ \
|
||||
errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS); \
|
||||
return (NULL); \
|
||||
}
|
||||
|
||||
#define SYS_FEC_ENET_ENABLE \
|
||||
if (sysFecEnetEnable != NULL) \
|
||||
if (sysFecEnetEnable (pDrvCtrl->fecBaseAddr) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#define SYS_FEC_ENET_DISABLE \
|
||||
if (sysFecEnetDisable != NULL) \
|
||||
if (sysFecEnetDisable (pDrvCtrl->fecBaseAddr) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#define FEC_END_DEV_NAME "fec"
|
||||
#define FEC_END_DEV_NAME_LEN 4
|
||||
#define FEC_END_TBD_DEF_NUM 64 /* default number of TBDs */
|
||||
#define FEC_END_RBD_DEF_NUM 48 /* default number of RBDs */
|
||||
#define FEC_END_TX_CL_NUM 6 /* number of tx clusters */
|
||||
#define FEC_END_BD_LOAN_NUM 64 /* loaned BDs */
|
||||
#define FEC_END_TBD_MAX 128 /* max number of TBDs */
|
||||
#define FEC_END_RBD_MAX 128 /* max number of TBDs */
|
||||
#define FEC_END_WAIT_MAX 0xf0000000 /* max delay after sending */
|
||||
|
||||
#define FEC_END_ADDR_LEN 6 /* ethernet address length */
|
||||
|
||||
/* Control/Status Registers (CSR) definitions */
|
||||
|
||||
#define FEC_END_EVENT_OFF 0x0004 /* interrupt event register */
|
||||
#define FEC_END_MASK_OFF 0x0008 /* interrupt mask register */
|
||||
#define FEC_END_iaddr1_OFF 0x0118 /* Individual Address 1*/
|
||||
#define FEC_END_iaddr2_OFF 0x011C /* Individual Address 2*/
|
||||
#define FEC_END_CTRL_OFF 0x0024 /* FEC control register */
|
||||
#define FEC_END_MII_DATA_OFF 0x0040 /* MII data register */
|
||||
#define FEC_END_MII_SPEED_OFF 0x0044 /* MII speed register */
|
||||
#define FEC_END_RX_CTRL_OFF 0x0084 /* rx control register */
|
||||
#define FEC_END_TX_CTRL_OFF 0x00c4 /* tx control register */
|
||||
#define FEC_END_ADDR_L_OFF 0x00e4 /* lower 32-bits of MAC address */
|
||||
#define FEC_END_ADDR_H_OFF 0x00e8 /* upper 16-bits of MAC address */
|
||||
#define FEC_END_OP_PAUSE_OFF 0x00EC
|
||||
#define FEC_END_HASH_H_OFF 0x0120 /* upper 32-bits of group address */
|
||||
#define FEC_END_HASH_L_OFF 0x0124 /* lower 32-bits of group address */
|
||||
|
||||
#define FEC_END_fifo_id_OFF 0x140
|
||||
#define FEC_END_x_wmrk_OFF 0x144
|
||||
#define FEC_END_fcntrl_OFF 0x148
|
||||
#define FEC_END_r_bound_OFF 0x14C
|
||||
#define FEC_END_r_fstart_OFF 0x150
|
||||
#define FEC_END_r_count_OFF 0x154
|
||||
#define FEC_END_r_lag_OFF 0x158
|
||||
#define FEC_END_r_read_OFF 0x15C
|
||||
#define FEC_END_r_write_OFF 0x160
|
||||
#define FEC_END_x_count_OFF 0x164
|
||||
#define FEC_END_x_lag_OFF 0x168
|
||||
#define FEC_END_x_retry_OFF 0x16C
|
||||
#define FEC_END_x_write_OFF 0x170
|
||||
#define FEC_END_x_read_OFF 0x174
|
||||
#define FEC_END_fm_cntrl_OFF 0x180
|
||||
#define FEC_END_rfifo_data_OFF 0x184
|
||||
#define FEC_END_rfifo_status_OFF 0x188
|
||||
#define FEC_END_rfifo_cntrl_OFF 0x18C
|
||||
#define FEC_END_rfifo_lrf_ptr_OFF 0x190
|
||||
#define FEC_END_rfifo_lwf_ptr_OFF 0x194
|
||||
#define FEC_END_rfifo_alarm_OFF 0x198
|
||||
#define FEC_END_rfifo_rdptr_OFF 0x19C
|
||||
#define FEC_END_rfifo_wrptr_OFF 0x1A0
|
||||
#define FEC_END_tfifo_data_OFF 0x1A4
|
||||
#define FEC_END_tfifo_status_OFF 0x1A8
|
||||
#define FEC_END_tfifo_cntrl_OFF 0x1AC
|
||||
#define FEC_END_tfifo_lrf_ptr_OFF 0x1B0
|
||||
#define FEC_END_tfifo_lwf_ptr_OFF 0x1B4
|
||||
#define FEC_END_tfifo_alarm_OFF 0x1B8
|
||||
#define FEC_END_tfifo_rdptr_OFF 0x1BC
|
||||
#define FEC_END_tfifo_wrptr_OFF 0x1C0
|
||||
#define FEC_END_reset_cntrl_OFF 0x1C4
|
||||
#define FEC_END_xmit_fsm_OFF 0x1C8
|
||||
|
||||
#define FEC_FIFO_STAT_ERROR 0x400000
|
||||
#define FEC_FIFO_STAT_UF 0x200000
|
||||
#define FEC_FIFO_STAT_OF 0x100000
|
||||
#define FEC_FIFO_STAT_ALARM 0x020000
|
||||
|
||||
/* Control/Status Registers (CSR) bit definitions */
|
||||
|
||||
#define FEC_END_RX_START_MSK 0xfffffffc /* quad-word alignment */
|
||||
/* required for rx BDs */
|
||||
|
||||
#define FEC_END_TX_START_MSK 0xfffffffc /* quad-word alignment */
|
||||
/* required for tx BDs */
|
||||
/* Ethernet CSR bit definitions */
|
||||
|
||||
#define FEC_END_ETH_EN 0x00000002 /* enable Ethernet operation */
|
||||
#define FEC_END_ETH_DIS 0x00000000 /* disable Ethernet operation*/
|
||||
#define FEC_END_ETH_RES 0x00000001 /* reset the FEC */
|
||||
#define FEC_END_CTRL_MASK 0x00000003 /* FEC control register mask */
|
||||
|
||||
/*
|
||||
* interrupt bits definitions: these are common to both the
|
||||
* mask and the event register.
|
||||
*/
|
||||
|
||||
#define FEC_END_EVENT_HB 0x80000000 /* heartbeat error */
|
||||
#define FEC_END_EVENT_BABR 0x40000000 /* babbling rx error */
|
||||
#define FEC_END_EVENT_BABT 0x20000000 /* babbling tx error */
|
||||
#define FEC_END_EVENT_GRA 0x10000000 /* graceful stop complete */
|
||||
#define FEC_END_EVENT_TXF 0x08000000 /* tx frame */
|
||||
#define FEC_END_EVENT_MII 0x00800000 /* MII transfer */
|
||||
#define FEC_END_EVENT_BERR 0x00400000 /* U-bus access error */
|
||||
#define FEC_END_EVENT_LCOL 0x00200000 /* Late collision */
|
||||
#define FEC_END_EVENT_COL_RL 0x00100000 /* Collision retry limit */
|
||||
#define FEC_END_EVENT_XFIFO_UN 0x00080000 /* Transmit fifo underrun */
|
||||
#define FEC_END_EVENT_FIFO_ERR 0x00040000 /* Transmit fifo error */
|
||||
#define FEC_END_EVENT_RFIFO_ERR 0x00020000 /* Receive fifo error */
|
||||
#define FEC_END_EVENT_MSK 0xfffe0000 /* clear all interrupts */
|
||||
#define FEC_END_MASK_ALL FEC_END_EVENT_MSK /* mask all interrupts */
|
||||
|
||||
|
||||
/* bit masks for the interrupt level/vector CSR */
|
||||
|
||||
#define FEC_END_LVL_MSK 0xe0000000 /* intr level */
|
||||
#define FEC_END_TYPE_MSK 0x0000000c /* highest pending intr */
|
||||
#define FEC_END_VEC_MSK 0xe000000c /* this register mask */
|
||||
#define FEC_END_RES_MSK 0x1ffffff3 /* reserved bits */
|
||||
#define FEC_END_LVL_SHIFT 0x1d /* intr level bits location */
|
||||
|
||||
/* transmit and receive active registers definitions */
|
||||
|
||||
#define FEC_END_TX_ACT 0x01000000 /* tx active bit */
|
||||
#define FEC_END_RX_ACT 0x01000000 /* rx active bit */
|
||||
|
||||
/* MII management frame CSRs */
|
||||
|
||||
#define FEC_END_MII_ST 0x40000000 /* start of frame delimiter */
|
||||
#define FEC_END_MII_OP_RD 0x20000000 /* perform a read operation */
|
||||
#define FEC_END_MII_OP_WR 0x10000000 /* perform a write operation */
|
||||
#define FEC_END_MII_ADDR_MSK 0x0f800000 /* PHY address field mask */
|
||||
#define FEC_END_MII_REG_MSK 0x007c0000 /* PHY register field mask */
|
||||
#define FEC_END_MII_TA 0x00020000 /* turnaround */
|
||||
#define FEC_END_MII_DATA_MSK 0x0000ffff /* PHY data field */
|
||||
#define FEC_END_MII_RA_SHIFT 0x12 /* mii reg address bits */
|
||||
#define FEC_END_MII_PA_SHIFT 0x17 /* mii PHY address bits */
|
||||
|
||||
#define FEC_END_MII_PRE_DIS 0x00000080 /* desable preamble */
|
||||
#define FEC_END_MII_SPEED_25 0x00000005 /* recommended for 25Mhz CPU */
|
||||
#define FEC_END_MII_SPEED_33 0x00000007 /* recommended for 33Mhz CPU */
|
||||
#define FEC_END_MII_SPEED_40 0x00000008 /* recommended for 40Mhz CPU */
|
||||
#define FEC_END_MII_SPEED_50 0x0000000a /* recommended for 50Mhz CPU */
|
||||
#define FEC_END_MII_SPEED_SHIFT 1 /* MII_SPEED bits location */
|
||||
#define FEC_END_MII_CLOCK_MAX 2500000 /* max freq of MII clock (Hz)*/
|
||||
#define FEC_END_MII_MAN_DIS 0x00000000 /* disable the MII management*/
|
||||
/* interface */
|
||||
#define FEC_END_MII_SPEED_MSK 0xffffff81 /* speed field mask */
|
||||
|
||||
/* FIFO transmit and receive CSRs definitions */
|
||||
|
||||
#define FEC_END_FIFO_MSK 0x000003ff /* FIFO rx/tx/bound mask */
|
||||
|
||||
/* SDMA function code CSR */
|
||||
|
||||
#define FEC_END_SDMA_DATA_BE 0x60000000 /* big-endian byte-ordering */
|
||||
/* for SDMA data transfer */
|
||||
|
||||
#define FEC_END_SDMA_DATA_PPC 0x20000000 /* PPC byte-ordering */
|
||||
/* for SDMA data transfer */
|
||||
|
||||
#define FEC_END_SDMA_DATA_RES 0x00000000 /* reserved value */
|
||||
|
||||
#define FEC_END_SDMA_BD_BE 0x18000000 /* big-endian byte-ordering */
|
||||
/* for SDMA BDs transfer */
|
||||
|
||||
#define FEC_END_SDMA_BD_PPC 0x08000000 /* PPC byte-ordering */
|
||||
/* for SDMA BDs transfer */
|
||||
|
||||
|
||||
#define FEC_END_SDMA_BD_RES 0x00000000 /* reserved value */
|
||||
#define FEC_END_SDMA_FUNC_0 0x00000000 /* no function code */
|
||||
|
||||
/* receive control/hash registers bit definitions */
|
||||
|
||||
#define FEC_END_RX_CTRL_PROM 0x00000008 /* promiscous mode */
|
||||
#define FEC_END_RX_CTRL_MII 0x00000004 /* select MII interface */
|
||||
#define FEC_END_RX_CTRL_DRT 0x00000002 /* disable rx on transmit */
|
||||
#define FEC_END_RX_CTRL_LOOP 0x00000001 /* loopback mode */
|
||||
#define FEC_END_RX_FR_MSK 0x000007ff /* rx frame length mask */
|
||||
|
||||
|
||||
/* transmit control register bit definitions */
|
||||
|
||||
#define FEC_END_TX_CTRL_FD 0x00000004 /* enable full duplex mode */
|
||||
#define FEC_END_TX_CTRL_HBC 0x00000002 /* HB check is performed */
|
||||
#define FEC_END_TX_CTRL_GRA 0x00000001 /* issue a graceful tx stop */
|
||||
|
||||
/* rx/tx buffer descriptors definitions */
|
||||
|
||||
#define FEC_END_RBD_SZ 8 /* RBD size in byte */
|
||||
#define FEC_END_TBD_SZ 8 /* TBD size in byte */
|
||||
#define FEC_END_TBD_MIN 6 /* min number of TBDs */
|
||||
#define FEC_END_RBD_MIN 4 /* min number of RBDs */
|
||||
#define FEC_END_TBD_POLL_NUM 1 /* one TBD for poll operation */
|
||||
#define CL_OVERHEAD 4 /* prepended cluster overhead */
|
||||
#define CL_ALIGNMENT 4 /* cluster required alignment */
|
||||
#define MBLK_ALIGNMENT 4 /* mBlks required alignment */
|
||||
#define FEC_END_BD_ALIGN 0x20 /* required alignment for RBDs */
|
||||
#define FEC_END_MAX_PCK_SZ (ETHERMTU + SIZEOF_ETHERHEADER \
|
||||
+ ETHER_CRC_LEN)
|
||||
|
||||
#define FEC_END_BD_STAT_OFF 0 /* offset of the status word */
|
||||
#define FEC_END_BD_LEN_OFF 2 /* offset of the data length word */
|
||||
#define FEC_END_BD_ADDR_OFF 4 /* offset of the data pointer word */
|
||||
|
||||
#define BESTCOMM_API 11
|
||||
|
||||
#ifndef BESTCOMM_API
|
||||
/* TBD bits definitions */
|
||||
|
||||
#define FEC_END_TBD_RDY 0x8000 /* ready for transmission */
|
||||
#define FEC_END_TBD_WRAP 0x2000 /* look at CSR5 for next bd */
|
||||
#define FEC_END_TBD_INT 0x1000 /* Interrupt */
|
||||
#define FEC_END_TBD_LAST 0x0800 /* last bd in this frame */
|
||||
#define FEC_END_TBD_CRC 0x0400 /* transmit the CRC sequence */
|
||||
#define FEC_END_TBD_DEF 0x0200 /* Append bad CRC */
|
||||
#define FEC_END_TBD_HB 0x0100 /* heartbeat error */
|
||||
#define FEC_END_TBD_LC 0x0080 /* late collision */
|
||||
#define FEC_END_TBD_RL 0x0040 /* retransmission limit */
|
||||
#define FEC_END_TBD_UN 0x0002 /* underrun error */
|
||||
#define FEC_END_TBD_CSL 0x0001 /* carrier sense lost */
|
||||
#define FEC_END_TBD_RC_MASK 0x003c /* retransmission count mask */
|
||||
|
||||
/* RBD bits definitions */
|
||||
|
||||
#define FEC_END_RBD_EMPTY 0x8000 /* ready for reception */
|
||||
#define FEC_END_RBD_WRAP 0x2000 /* look at CSR4 for next bd */
|
||||
#define FEC_END_RBD_INT 0x1000 /* BD int bit in status */
|
||||
#define FEC_END_RBD_LAST 0x0800 /* last bd in this frame */
|
||||
#define FEC_END_RBD_MISS 0x0100 /* address recognition miss */
|
||||
#define FEC_END_RBD_BC 0x0080 /* broadcast frame */
|
||||
#define FEC_END_RBD_MC 0x0040 /* multicast frame */
|
||||
#define FEC_END_RBD_LG 0x0020 /* frame length violation */
|
||||
#define FEC_END_RBD_NO 0x0010 /* nonoctet aligned frame */
|
||||
#define FEC_END_RBD_SH 0x0008 /* short frame error */
|
||||
/* not supported by the 860T */
|
||||
#define FEC_END_RBD_CRC 0x0004 /* CRC error */
|
||||
#define FEC_END_RBD_OV 0x0002 /* overrun error */
|
||||
#define FEC_END_RBD_TR 0x0001 /* truncated frame (>2KB) */
|
||||
|
||||
#define FEC_END_RBD_ERR (FEC_END_RBD_LG | \
|
||||
FEC_END_RBD_NO | \
|
||||
FEC_END_RBD_CRC | \
|
||||
FEC_END_RBD_OV | \
|
||||
FEC_END_RBD_TR)
|
||||
#else
|
||||
#define FEC_END_RBD_EMPTY (SDMA_BD_MASK_READY>>16) /* ready for RX */
|
||||
#define FEC_END_TBD_RDY (SDMA_BD_MASK_READY>>16) /* ready for TX */
|
||||
#define FEC_END_TBD_LAST (TASK_BD_TFD>>16) /* ready for TX */
|
||||
#define FEC_END_TBD_INT (TASK_BD_INT>>16) /* BD int bit in status */
|
||||
#define FEC_END_TBD_CRC 0
|
||||
|
||||
/* if RBD contains RxFIO Status at the end */
|
||||
#define FEC_END_RBD_FEMPTY 0x0001 /* FIFO run empty */
|
||||
#define FEC_END_RBD_ALARM 0x0002 /* FIFO alarm */
|
||||
#define FEC_END_RBD_FULL 0x0004 /* FIFO is full */
|
||||
#define FEC_END_RBD_FR 0x0008 /* frame data ready */
|
||||
#define FEC_END_RBD_OV 0x0010 /* FIFO overflow */
|
||||
#define FEC_END_RBD_UF 0x0020 /* FIFO underflow */
|
||||
|
||||
#define FEC_END_RBD_ERR (FEC_END_RBD_FEMPTY | \
|
||||
FEC_END_RBD_ALARM | \
|
||||
FEC_END_RBD_FULL | \
|
||||
FEC_END_RBD_OV | \
|
||||
FEC_END_RBD_UF)
|
||||
#endif
|
||||
|
||||
#define FEC_END_CRC_POLY 0x04c11db7 /* CRC polynomium: */
|
||||
/* x^32 + x^26 + x^23 + */
|
||||
/* x^22 + x^16 + x^12 + */
|
||||
/* x^11 + x^10 + x^8 + */
|
||||
/* x^7 + x^5 + x^4 + */
|
||||
/* x^2 + x^1 + x^0 + */
|
||||
|
||||
#define FEC_END_HASH_MASK 0x7c000000 /* bits 27-31 */
|
||||
#define FEC_END_HASH_SHIFT 0x1a /* to get the index */
|
||||
|
||||
/* defines related to the PHY device */
|
||||
|
||||
#define FEC_END_PHY_PRE_INIT 0x0001 /* PHY info initialized */
|
||||
#define FEC_END_PHY_AUTO 0x0010 /* enable auto-negotiation */
|
||||
#define FEC_END_PHY_TBL 0x0020 /* use negotiation table */
|
||||
#define FEC_END_PHY_100 0x0040 /* PHY may use 100Mbit speed */
|
||||
#define FEC_END_PHY_10 0x0080 /* PHY may use 10Mbit speed */
|
||||
#define FEC_END_PHY_FD 0x0100 /* PHY may use full duplex */
|
||||
#define FEC_END_PHY_HD 0x0200 /* PHY may use half duplex */
|
||||
#define FEC_END_PHY_MAX_WAIT 0x100 /* max delay before */
|
||||
#define FEC_END_PHY_MAX_SEC 0x04 /* max delay in seconds */
|
||||
#define FEC_END_PHY_NULL 0xff /* PHY is not present */
|
||||
#define FEC_END_PHY_DEF 0x0 /* PHY's logical address */
|
||||
|
||||
/* allowed PHY's speeds */
|
||||
|
||||
#define FEC_END_100MBS 100000000 /* bits per sec */
|
||||
#define FEC_END_10MBS 10000000 /* bits per sec */
|
||||
|
||||
/*
|
||||
* user flags: full duplex mode, loopback mode, serial interface etc.
|
||||
* the user may configure some of this options according to his needs
|
||||
* by setting the related bits in the <userFlags> field of the load string.
|
||||
*/
|
||||
|
||||
#define FEC_END_USR_PHY_NO_AN 0x00000001 /* do not auto-negotiate */
|
||||
#define FEC_END_USR_PHY_TBL 0x00000002 /* use negotiation table */
|
||||
#define FEC_END_USR_PHY_NO_FD 0x00000004 /* do not use full duplex */
|
||||
#define FEC_END_USR_PHY_NO_100 0x00000008 /* do not use 100Mbit speed */
|
||||
#define FEC_END_USR_PHY_NO_HD 0x00000010 /* do not use half duplex */
|
||||
#define FEC_END_USR_PHY_NO_10 0x00000020 /* do not use 10Mbit speed */
|
||||
#define FEC_END_USR_PHY_ISO 0x00000100 /* isolate a PHY */
|
||||
#define FEC_END_USR_SER 0x00000200 /* 7-wire serial interface */
|
||||
#define FEC_END_USR_LOOP 0x00000400 /* loopback mode */
|
||||
/* only use it for testing */
|
||||
#define FEC_END_USR_HBC 0x00000080 /* perform heartbeat control */
|
||||
|
||||
#define FEC_END_TBD_OK 0x1 /* the TBD is a good one */
|
||||
#define FEC_END_TBD_BUSY 0x2 /* the TBD has not been used */
|
||||
#define FEC_END_TBD_ERROR 0x4 /* the TBD is errored */
|
||||
|
||||
#define PKT_TYPE_MULTI 0x1 /* packet with a multicast address */
|
||||
#define PKT_TYPE_UNI 0x2 /* packet with a unicast address */
|
||||
#define PKT_TYPE_NONE 0x4 /* address type is not meaningful */
|
||||
|
||||
#define BUF_TYPE_CL 0x1 /* this's a cluster pointer */
|
||||
#define BUF_TYPE_MBLK 0x2 /* this's a mblk pointer */
|
||||
#define BUF_TYPE_LOCAL 0x4 /* local TX buffer (not from
|
||||
netBufLib) */
|
||||
|
||||
/* frame descriptors definitions */
|
||||
|
||||
typedef char * FEC_END_BD_ID;
|
||||
typedef FEC_END_BD_ID FEC_END_TBD_ID;
|
||||
typedef FEC_END_BD_ID FEC_END_RBD_ID;
|
||||
|
||||
/* MII definitions */
|
||||
|
||||
#define MII_MAX_PHY_NUM 0x20 /* max number of attached PHYs */
|
||||
|
||||
#define MII_CTRL_REG 0x0 /* Control Register */
|
||||
#define MII_STAT_REG 0x1 /* Status Register */
|
||||
#define MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
|
||||
#define MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
|
||||
#define MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
|
||||
/* Advertisement Register */
|
||||
#define MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
|
||||
/* partner ability Register */
|
||||
#define MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
|
||||
/* Expansion Register */
|
||||
#define MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
|
||||
/* next-page transmit Register */
|
||||
|
||||
/* MII control register bit */
|
||||
|
||||
#define MII_CR_COLL_TEST 0x0080 /* collision test */
|
||||
#define MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
|
||||
#define MII_CR_RESTART 0x0200 /* restart auto negotiation */
|
||||
#define MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
|
||||
#define MII_CR_POWER_DOWN 0x0800 /* power down */
|
||||
#define MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
|
||||
#define MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
|
||||
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
#define MII_CR_NORM_EN 0x0000 /* just enable the PHY */
|
||||
|
||||
/* MII Status register bit definitions */
|
||||
|
||||
#define MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
|
||||
#define MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
|
||||
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
|
||||
#define MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
|
||||
#define MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
|
||||
#define MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
|
||||
#define MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
|
||||
#define MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
|
||||
#define MII_SR_T4 0x8000 /* T4 capable */
|
||||
|
||||
/* MII Link Code word bit definitions */
|
||||
|
||||
#define MII_BP_FAULT 0x2000 /* remote fault */
|
||||
#define MII_BP_ACK 0x4000 /* acknowledge */
|
||||
#define MII_BP_NP 0x8000 /* nexp page is supported */
|
||||
|
||||
/* MII Next Page bit definitions */
|
||||
|
||||
#define MII_NP_TOGGLE 0x0800 /* toggle bit */
|
||||
#define MII_NP_ACK2 0x1000 /* acknowledge two */
|
||||
#define MII_NP_MSG 0x2000 /* message page */
|
||||
#define MII_NP_ACK1 0x4000 /* acknowledge one */
|
||||
#define MII_NP_NP 0x8000 /* nexp page will follow */
|
||||
|
||||
/* MII Expansion Register bit definitions */
|
||||
|
||||
#define MII_EXP_FAULT 0x0010 /* parallel detection fault */
|
||||
#define MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
|
||||
#define MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
|
||||
#define MII_EXP_PR 0x0002 /* full page received */
|
||||
#define MII_EXP_PRT_AN 0x0001 /* link partner auto negotiation able*/
|
||||
|
||||
/* technology ability field bit definitions */
|
||||
|
||||
#define MII_TECH_10BASE_T 0x0020 /* 10Base-T */
|
||||
#define MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
|
||||
#define MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
|
||||
#define MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
|
||||
#define MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
|
||||
#define MII_TECH_MASK 0x1fe0 /* technology abilities mask */
|
||||
|
||||
#define MII_AN_FAIL 0x10 /* auto-negotiation fail */
|
||||
#define MII_STAT_FAIL 0x20 /* errors in the status register */
|
||||
#define FEC_END_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
|
||||
|
||||
/* FEC_Lite FIFO Transmit Watermark Register(X_WMRK) definitions */
|
||||
|
||||
#define FEC_XFIFO_WMRK_64 0x00000000 /* TX FIFO watermark(64 bytes) */
|
||||
#define FEC_XFIFO_WMRK_128 0x00000001 /* TX FIFO watermark(128 bytes) */
|
||||
#define FEC_XFIFO_WMRK_192 0x00000002 /* TX FIFO watermark(192 bytes) */
|
||||
#define FEC_XFIFO_WMRK_256 0x00000003 /* TX FIFO watermark(256 bytes) */
|
||||
|
||||
/* FEC_Lite Opcode/Pause Duration Register(OP_PAUSE) definitions */
|
||||
|
||||
#define FEC_OP_PAUSE_OPCODE 0x00010000 /* Opcode field used in PAUSE
|
||||
frames */
|
||||
|
||||
/* settings */
|
||||
|
||||
/* FEC-Lite RFIFO Control Register (RFIFO_CNTRL) definitions */
|
||||
|
||||
#define FEC_RFIFO_CNTRL_FRAME 0x08000000 /* Frame mode enable */
|
||||
|
||||
#ifdef BESTCOMM_API
|
||||
#define FEC_RFIFO_CNTRL_GR 0x07000000 /* Default Granularity value = 7*/
|
||||
#else
|
||||
#define FEC_RFIFO_CNTRL_GR 0x04000000 /* Default Granularity value = 4*/
|
||||
#endif
|
||||
|
||||
/* FEC-Lite RFIFO Alarm Register (RFIFO_ALARM) definitions */
|
||||
#define FEC_RFIFO_ALARM 0x0000030C /* Default value is 520 bytes */
|
||||
|
||||
/* FEC-Lite XFIFO Control Register(XFIFO_CNTRL) definitions */
|
||||
|
||||
#define FEC_XFIFO_CNTRL_FRAME 0x08000000 /* Frame mode enable */
|
||||
|
||||
#ifdef BESTCOMM_API
|
||||
#define FEC_XFIFO_CNTRL_GR 0x07000000 /* Default Granularity value = 7*/
|
||||
#else
|
||||
#define FEC_XFIFO_CNTRL_GR 0x04000000 /* Default Granularity value = 4*/
|
||||
#endif
|
||||
|
||||
#define FEC_XFIFO_CNTRL_TXW_MASK 0x00040000 /* Undocumented bit to set w/Rev.B */
|
||||
|
||||
#define FEC_PAUSE_DURATION 0x0020 /* Pause transmission for the
|
||||
duration */
|
||||
|
||||
/*
|
||||
* this table may be customized by the user in configNet.h
|
||||
*/
|
||||
|
||||
IMPORT INT16 m5200FecPhyAnOrderTbl [];
|
||||
|
||||
|
||||
typedef struct mii_regs
|
||||
{
|
||||
UINT16 phyStatus; /* PHY's status register */
|
||||
UINT16 phyCtrl; /* PHY's control register */
|
||||
UINT16 phyId1; /* PHY's identifier field 1 */
|
||||
UINT16 phyId2; /* PHY's identifier field 2 */
|
||||
UINT16 phyAds; /* PHY's advertisement register */
|
||||
UINT16 phyPrtn; /* PHY's partner register */
|
||||
UINT16 phyExp; /* PHY's expansion register */
|
||||
UINT16 phyNext; /* PHY's next paget transmit register */
|
||||
} MII_REGS;
|
||||
|
||||
typedef struct phy_info
|
||||
{
|
||||
MII_REGS miiRegs; /* PHY registers */
|
||||
UINT8 phyAddr; /* address of the PHY to be used */
|
||||
UINT8 isoPhyAddr; /* address of a PHY to isolate */
|
||||
UINT32 phyFlags; /* some flags */
|
||||
UINT32 phySpeed; /* 10/100 Mbit/sec */
|
||||
UINT32 phyMode; /* half/full duplex mode */
|
||||
UINT32 phyDefMode; /* default operating mode */
|
||||
} PHY_INFO;
|
||||
|
||||
typedef struct mot_fec_tbd_list
|
||||
{
|
||||
UINT16 fragNum;
|
||||
UINT16 pktType;
|
||||
UCHAR * pBuf;
|
||||
UINT16 bufType;
|
||||
struct mot_fec_tbd_list * pNext;
|
||||
FEC_END_TBD_ID pTbd;
|
||||
} FEC_END_TBD_LIST;
|
||||
|
||||
typedef FEC_END_TBD_LIST * FEC_END_TBD_LIST_ID;
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct drv_ctrl
|
||||
{
|
||||
END_OBJ endObj; /* base class */
|
||||
int unit; /* unit number */
|
||||
UINT32 fecBaseAddr; /* internal RAM base address */
|
||||
VOIDFUNCPTR * ivecFEC; /* interrupt vector number FEC */
|
||||
VOIDFUNCPTR * ivecRDMA; /* interrupt vector number RDMA */
|
||||
VOIDFUNCPTR * ivecWDMA; /* interrupt vector number WDMA */
|
||||
UINT32 fifoTxBase; /* address of Tx FIFO in internal RAM*/
|
||||
UINT32 fifoRxBase; /* address of Rx FIFO in internal RAM*/
|
||||
char * pBufBase; /* FEC memory pool base */
|
||||
ULONG bufSize; /* FEC memory pool size */
|
||||
UINT16 rbdNum; /* number of RBDs */
|
||||
#ifndef BESTCOMM_API
|
||||
FEC_END_RBD_ID rbdBase; /* RBD ring */
|
||||
#else
|
||||
int recvTaskNo; /* Bestcomm Task for Receive */
|
||||
int rxPollTID;
|
||||
#endif
|
||||
UINT16 rbdIndex; /* RBD index */
|
||||
UINT16 tbdNum; /* number of TBDs */
|
||||
FEC_END_TBD_ID tbdBase; /* TBD ring */
|
||||
#ifdef BESTCOMM_API
|
||||
int xmitTaskNo; /* Bestcomm Task for Transmit */
|
||||
#endif
|
||||
UINT16 tbdIndex; /* TBD index */
|
||||
UINT16 usedTbdIndex; /* used TBD index */
|
||||
volatile UINT16 cleanTbdNum; /* number of clean TBDs */
|
||||
BOOL txStall; /* tx handler stalled - no Tbd */
|
||||
FEC_END_TBD_LIST * pTbdList [FEC_END_TBD_MAX];
|
||||
/* list of TBDs */
|
||||
ULONG userFlags; /* some user flags */
|
||||
INT8 flags; /* driver state */
|
||||
BOOL loaded; /* interface has been loaded */
|
||||
BOOL intrConnect; /* interrupt has been connected */
|
||||
UINT32 intMask; /* interrupt mask register */
|
||||
UCHAR * pTxPollBuf; /* cluster pointer for poll mode */
|
||||
UCHAR * rxBuf[FEC_END_RBD_MAX];
|
||||
/* array of pointers to clusters */
|
||||
SEM_ID miiSem; /* synch semaphore for mii frames */
|
||||
SEM_ID graSem; /* synch semaphore for graceful */
|
||||
/* transmit command */
|
||||
char * pClBlkArea; /* cluster block pointer */
|
||||
UINT32 clBlkSize; /* clusters block memory size */
|
||||
char * pMBlkArea; /* mBlock area pointer */
|
||||
UINT32 mBlkSize; /* mBlocks area memory size */
|
||||
CACHE_FUNCS bdCacheFuncs; /* cache descriptor */
|
||||
CACHE_FUNCS bufCacheFuncs; /* cache descriptor */
|
||||
CL_POOL_ID pClPoolId; /* cluster pool identifier */
|
||||
PHY_INFO *phyInfo; /* info on a MII-compliant PHY */
|
||||
UINT32 clockSpeed; /* clock speed (Hz) for MII_SPEED */
|
||||
UINT8 txBuffAvailable; /* Flag for use with pTxBuffLocal */
|
||||
char * pTxBuffLocal; /* Local buffer for sending data */
|
||||
UINT32 stoppingTx; /* Flag to stop sending frames after */
|
||||
/* fecStop has been scheduled */
|
||||
} DRV_CTRL;
|
||||
|
||||
/*
|
||||
* this cache functions descriptors is used to flush/invalidate
|
||||
* the FEC's data buffers. They are set to the system's cache
|
||||
* flush and invalidate routine. This will allow proper operation
|
||||
* of the driver if data cache are turned on.
|
||||
*/
|
||||
|
||||
IMPORT STATUS cacheArchInvalidate (CACHE_TYPE, void *, size_t);
|
||||
|
||||
IMPORT STATUS cacheArchFlush (CACHE_TYPE, void *, size_t);
|
||||
|
||||
IMPORT STATUS sysFecEnetAddrGet (UINT32 motCmpAddr, UCHAR * address);
|
||||
IMPORT STATUS sysEnetAddrSet (UINT32 motCmpAddr, UCHAR * address);
|
||||
IMPORT STATUS sysFecEnetEnable (UINT32 motCmpAddr);
|
||||
IMPORT STATUS sysFecEnetDisable (UINT32 motCmpAddr);
|
||||
IMPORT FUNCPTR _func_m5200FecPhyInit;
|
||||
IMPORT FUNCPTR _func_m5200FecHbFail;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCm5200FecEndh */
|
||||
|
||||
@@ -0,0 +1,310 @@
|
||||
/* m8260Fcc.h - Motorola MPC8260 Fast Communications Controller header file */
|
||||
|
||||
/* Copyright 1984-1999 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,12sep99,ms_ created from m8260Cpm.h, 01d.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains constants for the Fast Communications Controllers
|
||||
* (fCCs) in the Motorola MPC8260 PowerQUICC II integrated Communications
|
||||
* Processor
|
||||
*/
|
||||
|
||||
#ifndef __INCm8260Fcch
|
||||
#define __INCm8260Fcch
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef M8260ABBREVIATIONS
|
||||
#define M8260ABBREVIATIONS
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
#define CAST(x)
|
||||
#else /* _ASMLANGUAGE */
|
||||
typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
|
||||
typedef volatile INT32 VINT32; /* volatile unsigned word */
|
||||
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
|
||||
typedef volatile INT8 VINT8; /* volatile unsigned byte */
|
||||
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
|
||||
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
|
||||
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
|
||||
#define CAST(x) (x)
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* M8260ABBREVIATIONS */
|
||||
|
||||
/*
|
||||
* MPC8260 internal register/memory map (section 17 of prelim. spec)
|
||||
* note that these are offsets from the value stored in the IMMR
|
||||
* register. Also note that in the MPC8260, the IMMR is not a special
|
||||
* purpose register, but it is memory mapped.
|
||||
*/
|
||||
|
||||
/* CPM mux FCC clock route register */
|
||||
|
||||
#define M8260_CMXFCR(base) (CAST(VUINT32 *)((base) + 0x11B04))
|
||||
|
||||
/* FCC 1 register set */
|
||||
|
||||
#define M8260_FGMR1(base) (CAST(VUINT32 *)((base) + 0x11300)) /* Gen Mode */
|
||||
#define M8260_FPSMR1(base) (CAST(VUINT32 *)((base) + 0x11304)) /* Prot Spec */
|
||||
#define M8260_FTODR1(base) (CAST(VUINT32 *)((base) + 0x11308)) /* transmit */
|
||||
/* on demand */
|
||||
#define M8260_FDSR1(base) (CAST(VUINT32 *)((base) + 0x1130C)) /* data sync */
|
||||
#define M8260_FCCER1(base) (CAST(VUINT32 *)((base) + 0x11310)) /* event */
|
||||
#define M8260_FCCMR1(base) (CAST(VUINT32 *)((base) + 0x11304)) /* mask */
|
||||
#define M8260_FCCSR1(base) (CAST(VUINT32 *)((base) + 0x11308)) /* status */
|
||||
|
||||
/* FCC1 transmit internal rate registers for PHY 0-3 */
|
||||
|
||||
#define M8260_FTIRR1_PHY0(base) (CAST(VUINT32 *)((base) + 0x1131C))
|
||||
#define M8260_FTIRR1_PHY1(base) (CAST(VUINT32 *)((base) + 0x1131D))
|
||||
#define M8260_FTIRR1_PHY2(base) (CAST(VUINT32 *)((base) + 0x1131E))
|
||||
#define M8260_FTIRR1_PHY3(base) (CAST(VUINT32 *)((base) + 0x1131F))
|
||||
|
||||
/* offsets in internal RAM of FCC registers */
|
||||
|
||||
#define M8260_FCC_IRAM_GAP 0x20 /* gap between FCCs */
|
||||
/* in Internal RAM */
|
||||
#define M8260_FCC_GFMR_OFF 0x0 /* GFMR offset */
|
||||
#define M8260_FCC_FPSMR_OFF 0x4 /* FPSMR offset */
|
||||
#define M8260_FCC_FTODR_OFF 0x8 /* FTODR offset */
|
||||
#define M8260_FCC_FDSR_OFF 0xC /* FDSR offset */
|
||||
#define M8260_FCC_FCCER_OFF 0x10 /* FCCER offset */
|
||||
#define M8260_FCC_FCCMR_OFF 0x14 /* FCCMR offset */
|
||||
#define M8260_FCC_FCCSR_OFF 0x18 /* FCCSR offset */
|
||||
|
||||
/* FCC Dual-Ported RAM definitions */
|
||||
|
||||
#define M8260_FCC1_BASE(base) (CAST(VUINT32 *)((base) + 0x8400)) /* FCC1 */
|
||||
#define M8260_FCC2_BASE(base) (CAST(VUINT32 *)((base) + 0x8500)) /* FCC2 */
|
||||
#define M8260_FCC3_BASE(base) (CAST(VUINT32 *)((base) + 0x8600)) /* FCC3 */
|
||||
#define M8260_FCC_DPRAM_GAP 0x100 /* gap between FCCs */
|
||||
/* parameter RAM in DPRAM */
|
||||
#define M8260_FCC_RIPTR_OFF 0x0 /* rx FIFO pointer offset */
|
||||
#define M8260_FCC_TIPTR_OFF 0x2 /* tx FIFO pointer offset */
|
||||
#define M8260_FCC_RES1_OFF 0x4 /* reserved */
|
||||
#define M8260_FCC_MRBLR_OFF 0x6 /* max rx buffer length */
|
||||
#define M8260_FCC_RSTATE_OFF 0x8 /* rx internal state */
|
||||
#define M8260_FCC_RBASE_OFF 0xC /* RBD base address */
|
||||
#define M8260_FCC_RBDSTAT_OFF 0x10 /* RBD status/control */
|
||||
#define M8260_FCC_RBDLEN_OFF 0x12 /* RBD data length */
|
||||
#define M8260_FCC_RDPTR_OFF 0x14 /* RBD data pointer */
|
||||
#define M8260_FCC_TSTATE_OFF 0x18 /* tx internal state */
|
||||
#define M8260_FCC_TBASE_OFF 0x1C /* TBD base address */
|
||||
#define M8260_FCC_TBDSTAT_OFF 0x20 /* TBD status/control */
|
||||
#define M8260_FCC_TBDLEN_OFF 0x22 /* TBD data length */
|
||||
#define M8260_FCC_TDPTR_OFF 0x24 /* TBD data pointer */
|
||||
#define M8260_FCC_RBPTR_OFF 0x28 /* RBD pointer */
|
||||
#define M8260_FCC_TBPTR_OFF 0x2C /* TBD pointer */
|
||||
#define M8260_FCC_RCRC_OFF 0x30 /* temp rx CRC */
|
||||
#define M8260_FCC_TCRC_OFF 0x34 /* temp tx CRC */
|
||||
|
||||
#define M8260_FCC_STATBUF_OFF 0x3C /* internal buffer */
|
||||
#define M8260_FCC_CAM_PTR_OFF 0x40 /* CAM address */
|
||||
#define M8260_FCC_C_MASK_OFF 0x44 /* MASK for CRC */
|
||||
#define M8260_FCC_C_PRES_OFF 0x48 /* preset CRC */
|
||||
#define M8260_FCC_CRCEC_OFF 0x4C /* CRC error counter */
|
||||
#define M8260_FCC_ALEC_OFF 0x50 /* alignment error counter */
|
||||
#define M8260_FCC_DISFC_OFF 0x54 /* discard frame counter */
|
||||
#define M8260_FCC_RET_LIM_OFF 0x58 /* retry limit */
|
||||
#define M8260_FCC_RET_CNT_OFF 0x5A /* retry limit counter */
|
||||
#define M8260_FCC_P_PER_OFF 0x5C /* persistence */
|
||||
#define M8260_FCC_BOFF_CNT_OFF 0x5E /* backoff counter */
|
||||
#define M8260_FCC_GADDR_H_OFF 0x60 /* group address filter high */
|
||||
#define M8260_FCC_GADDR_L_OFF 0x64 /* group address filter low */
|
||||
#define M8260_FCC_TFCSTAT_OFF 0x68 /* out-of-sequence TBD stat */
|
||||
#define M8260_FCC_TFCLEN_OFF 0x6A /* out-of-sequence TBD length */
|
||||
#define M8260_FCC_TFCPTR_OFF 0x6C /* out-of-sequence TBD pointer*/
|
||||
#define M8260_FCC_MFLR_OFF 0x70 /* max receive frame length */
|
||||
#define M8260_FCC_PADDR_H_OFF 0x72 /* individual address high */
|
||||
#define M8260_FCC_PADDR_M_OFF 0x74 /* individual address medium */
|
||||
#define M8260_FCC_PADDR_L_OFF 0x76 /* individual address low */
|
||||
#define M8260_FCC_IBD_CNT_OFF 0x78 /* internal BD counter */
|
||||
#define M8260_FCC_IBD_START_OFF 0x7A /* internal BD start pointer */
|
||||
#define M8260_FCC_IBD_END_OFF 0x7C /* internal BD end pointer */
|
||||
#define M8260_FCC_TX_LEN_OFF 0x7E /* tx frame length counter */
|
||||
#define M8260_FCC_IBD_BASE_OFF 0x80 /* internal BD base */
|
||||
#define M8260_FCC_IADDR_H_OFF 0xA0 /* individual addr filter high*/
|
||||
#define M8260_FCC_IADDR_L_OFF 0xA4 /* individual addr filter low */
|
||||
#define M8260_FCC_MINFLR_OFF 0xA8 /* min frame lenght */
|
||||
#define M8260_FCC_TADDR_H_OFF 0xAA /* set hash table addr high */
|
||||
#define M8260_FCC_TADDR_M_OFF 0xAC /* set hash table addr medium */
|
||||
#define M8260_FCC_TADDR_L_OFF 0xAE /* set hash table addr low */
|
||||
#define M8260_FCC_PAD_PTR_OFF 0xB0 /* internal PAD pointer */
|
||||
#define M8260_FCC_RES2_OFF 0xB2 /* reserved */
|
||||
#define M8260_FCC_CF_RANGE_OFF 0xB4 /* control frame range */
|
||||
#define M8260_FCC_MAX_B_OFF 0xB6 /* max BD byte counter */
|
||||
#define M8260_FCC_MAXD1_OFF 0xB8 /* max DMA1 lenght */
|
||||
#define M8260_FCC_MAXD2_OFF 0xBA /* max DMA2 lenght */
|
||||
#define M8260_FCC_MAXD_OFF 0xBC /* rx max DMA lenght */
|
||||
#define M8260_FCC_DMA_CNT_OFF 0xBE /* rx DMA counter */
|
||||
#define M8260_FCC_OCTC_OFF 0xC0 /* data octets number */
|
||||
#define M8260_FCC_COLC_OFF 0xC4 /* collision estimate */
|
||||
#define M8260_FCC_BROC_OFF 0xC8 /* received broadast packets */
|
||||
#define M8260_FCC_MULC_OFF 0xCC /* received multicast packets */
|
||||
#define M8260_FCC_USPC_OFF 0xD0 /* good packets shorter than */
|
||||
/* 64 bytes */
|
||||
#define M8260_FCC_FRGC_OFF 0xD4 /* bad packets shorter than */
|
||||
/* 64 bytes */
|
||||
#define M8260_FCC_OSPC_OFF 0xD8 /* good packets longer than */
|
||||
/* 1518 bytes */
|
||||
#define M8260_FCC_JBRC_OFF 0xDC /* bad packets longer than */
|
||||
/* 1518 bytes */
|
||||
#define M8260_FCC_P64C_OFF 0xE0 /* packets 64-byte long */
|
||||
#define M8260_FCC_P65C_OFF 0xE4 /* packets < 128 bytes and */
|
||||
/* > 64 bytes */
|
||||
#define M8260_FCC_P128C_OFF 0xE8 /* packets < 256 bytes and */
|
||||
/* > 127 bytes */
|
||||
#define M8260_FCC_P256C_OFF 0xEC /* packets < 512 bytes and */
|
||||
/* > 255 bytes */
|
||||
#define M8260_FCC_P512C_OFF 0xF0 /* packets < 1024 bytes and */
|
||||
/* > 511 bytes */
|
||||
#define M8260_FCC_P1024C_OFF 0xF4 /* packets < 1519 bytes and */
|
||||
/* > 1023 bytes */
|
||||
#define M8260_FCC_CAM_BUF_OFF 0xF8 /* internal buffer */
|
||||
#define M8260_FCC_RES3_OFF 0xFC /* reserved */
|
||||
|
||||
/* General FCC Mode Register definitions */
|
||||
|
||||
#define M8260_GFMR_HDLC 0x00000000 /* HDLC mode */
|
||||
#define M8260_GFMR_RES1 0x00000001 /* reserved mode */
|
||||
#define M8260_GFMR_RES2 0x00000002 /* reserved mode */
|
||||
#define M8260_GFMR_RES3 0x00000003 /* reserved mode */
|
||||
#define M8260_GFMR_RES4 0x00000004 /* reserved mode */
|
||||
#define M8260_GFMR_RES5 0x00000005 /* reserved mode */
|
||||
#define M8260_GFMR_RES6 0x00000006 /* reserved mode */
|
||||
#define M8260_GFMR_RES7 0x00000007 /* reserved mode */
|
||||
#define M8260_GFMR_RES8 0x00000008 /* reserved mode */
|
||||
#define M8260_GFMR_RES9 0x00000009 /* reserved mode */
|
||||
#define M8260_GFMR_ATM 0x0000000a /* ATM mode */
|
||||
#define M8260_GFMR_RES10 0x0000000b /* reserved mode */
|
||||
#define M8260_GFMR_ETHERNET 0x0000000c /* ethernet mode */
|
||||
#define M8260_GFMR_RES11 0x0000000d /* reserved mode */
|
||||
#define M8260_GFMR_RES12 0x0000000e /* reserved mode */
|
||||
#define M8260_GFMR_RES13 0x0000000f /* reserved mode */
|
||||
#define M8260_GFMR_NORM 0x00000000 /* normal mode */
|
||||
#define M8260_GFMR_LOOP 0x40000000 /* local loopback */
|
||||
#define M8260_GFMR_ECHO 0x80000000 /* automatic echo */
|
||||
#define M8260_GFMR_LOOP_ECHO 0xc0000000 /* loop & echo */
|
||||
#define M8260_GFMR_TCI 0x20000000 /* tx clock invert */
|
||||
#define M8260_GFMR_TRX 0x10000000 /* transparent receiver */
|
||||
#define M8260_GFMR_TTX 0x08000000 /* transparent transmitter */
|
||||
#define M8260_GFMR_CDP 0x04000000 /* CD* pulse */
|
||||
#define M8260_GFMR_CTSP 0x02000000 /* CTS* pulse */
|
||||
#define M8260_GFMR_CDS 0x01000000 /* CD* sampling */
|
||||
#define M8260_GFMR_CTSS 0x00800000 /* CTS* sampling */
|
||||
#define M8260_GFMR_SYN_EXT 0x00000000 /* external sync */
|
||||
#define M8260_GFMR_SYN_AUTO 0x00004000 /* automatic sync */
|
||||
#define M8260_GFMR_SYN_8 0x00008000 /* 8-bit sync pattern */
|
||||
#define M8260_GFMR_SYN_16 0x0000c000 /* 16-bit sync pattern */
|
||||
#define M8260_GFMR_RTSM 0x00002000 /* RTS* mode */
|
||||
#define M8260_GFMR_RENC_RES 0x00001000 /* receiver encoding reserved */
|
||||
#define M8260_GFMR_RENC_NRZI 0x00000800 /* receiver encoding NRZI */
|
||||
#define M8260_GFMR_RENC_NRZ 0x00000000 /* receiver encoding NRZ */
|
||||
#define M8260_GFMR_REVD 0x00000400 /* reverse data */
|
||||
#define M8260_GFMR_TENC_RES 0x00000200 /* transmitter encoding res */
|
||||
#define M8260_GFMR_TENC_NRZI 0x00000100 /* transmitter encoding NRZI */
|
||||
#define M8260_GFMR_TENC_NRZ 0x00000000 /* transmitter encoding NRZ */
|
||||
#define M8260_GFMR_TCRC_RES 0x00000040 /* transparent CRC reserved */
|
||||
#define M8260_GFMR_TCRC_16 0x00000000 /* 16-bit transparent CRC */
|
||||
#define M8260_GFMR_TCRC_32 0x00000080 /* 32-bit transparent CRC */
|
||||
#define M8260_GFMR_ENT 0x00000010 /* enable transmitter */
|
||||
#define M8260_GFMR_ENR 0x00000020 /* enable receiver */
|
||||
|
||||
/* FCC Data Synchronization Register definitions */
|
||||
|
||||
#define M8260_FDSR_SYN1_MASK 0x00ff /* sync pattern mask 1 */
|
||||
#define M8260_FDSR_SYN2_MASK 0xff00 /* sync pattern mask 2 */
|
||||
#define M8260_FDSR_ETH_SYN1 0x55 /* Ethernet sync pattern 1 */
|
||||
#define M8260_FDSR_ETH_SYN2 0xd5 /* Ethernet sync pattern 2 */
|
||||
|
||||
/* FCC Transmit on Demand Register definitions */
|
||||
|
||||
#define M8260_FTODR_TOD 0x8000 /* transmit on demand */
|
||||
|
||||
/* FCC Function Code Register definitions */
|
||||
|
||||
#define M8260_FCR_GBL 0x20 /* global mem operation */
|
||||
/* enable snooping */
|
||||
#define M8260_FCR_BO_BE 0x10 /* big-endian ordering */
|
||||
#define M8260_FCR_BO_LE 0x08 /* little-endian ordering */
|
||||
#define M8260_FCR_TC2 0x04 /* transfer code for TC[2] */
|
||||
#define M8260_FCR_DTB 0x02 /* data is in the local bus */
|
||||
#define M8260_FCR_BDB 0x01 /* BDs are in the local bus */
|
||||
#define M8260_FCR_SHIFT 24 /* get to fcr bits in xstate */
|
||||
|
||||
/* FCC Ethernet Protocol Specific Mode Register definitions */
|
||||
|
||||
#define M8260_FPSMR_ETH_HBC 0x80000000 /* heartbeat checking */
|
||||
#define M8260_FPSMR_ETH_FC 0x40000000 /* force collision */
|
||||
#define M8260_FPSMR_ETH_SBT 0x20000000 /* stop backoff timer */
|
||||
#define M8260_FPSMR_ETH_LPB 0x10000000 /* loopback operation */
|
||||
#define M8260_FPSMR_ETH_LCW 0x08000000 /* late collision window */
|
||||
#define M8260_FPSMR_ETH_FDE 0x04000000 /* full duplex enable */
|
||||
#define M8260_FPSMR_ETH_MON 0x02000000 /* enable RMON mode */
|
||||
#define M8260_FPSMR_ETH_PRO 0x00400000 /* enable promiscous mode */
|
||||
#define M8260_FPSMR_ETH_FCE 0x00200000 /* flow control enable */
|
||||
#define M8260_FPSMR_ETH_RSH 0x00100000 /* receive short frame */
|
||||
#define M8260_FPSMR_ETH_CAM 0x00000400 /* CAM address matching */
|
||||
#define M8260_FPSMR_ETH_BRO 0x00000200 /* broadcast enable */
|
||||
#define M8260_FPSMR_ETH_CRC_32 0x00000080 /* use 32-bit CCITT CRC */
|
||||
#define M8260_FPSMR_ETH_CRC_MASK 0x000000c0 /* CRC mask field */
|
||||
|
||||
/* FCC Ethernet Event and Mask Register definitions */
|
||||
|
||||
#define M8260_FEM_ETH_RES 0xff00 /* reserved mask */
|
||||
#define M8260_FEM_ETH_EVENT 0x00ff /* event mask */
|
||||
#define M8260_FEM_ETH_GRA 0x0080 /* graceful stop event */
|
||||
#define M8260_FEM_ETH_RXC 0x0040 /* rx control frame event */
|
||||
#define M8260_FEM_ETH_TXC 0x0020 /* tx control frame event */
|
||||
#define M8260_FEM_ETH_TXE 0x0010 /* transmission error event */
|
||||
#define M8260_FEM_ETH_RXF 0x0008 /* frame received event */
|
||||
#define M8260_FEM_ETH_BSY 0x0004 /* busy condition */
|
||||
#define M8260_FEM_ETH_TXB 0x0002 /* buffer transmitted event */
|
||||
#define M8260_FEM_ETH_RXB 0x0001 /* buffer received event */
|
||||
|
||||
/* FCC Ethernet Receive Buffer Descriptor definitions */
|
||||
|
||||
#define M8260_FETH_RBD_E 0x8000 /* buffer is empty */
|
||||
#define M8260_FETH_RBD_W 0x2000 /* last BD in ring */
|
||||
#define M8260_FETH_RBD_I 0x1000 /* interrupt on receive */
|
||||
#define M8260_FETH_RBD_L 0x0800 /* buffer is last in frame */
|
||||
#define M8260_FETH_RBD_F 0x0400 /* buffer is first in frame */
|
||||
#define M8260_FETH_RBD_M 0x0100 /* miss bit for prom mode */
|
||||
#define M8260_FETH_RBD_BC 0x0080 /* broadcast address frame */
|
||||
#define M8260_FETH_RBD_MC 0x0040 /* multicast address frame */
|
||||
#define M8260_FETH_RBD_LG 0x0020 /* frame length violation */
|
||||
#define M8260_FETH_RBD_NO 0x0010 /* nonoctet aligned frame */
|
||||
#define M8260_FETH_RBD_SH 0x0008 /* short frame received */
|
||||
#define M8260_FETH_RBD_CR 0x0004 /* Rx CRC error */
|
||||
#define M8260_FETH_RBD_OV 0x0002 /* overrun condition */
|
||||
#define M8260_FETH_RBD_CL 0x0001 /* collision condition */
|
||||
|
||||
/* FCC Ethernet Transmit Buffer Descriptor definitions */
|
||||
|
||||
#define M8260_FETH_TBD_R 0x8000 /* buffer is ready */
|
||||
#define M8260_FETH_TBD_PAD 0x4000 /* auto pad short frames */
|
||||
#define M8260_FETH_TBD_W 0x2000 /* last BD in ring */
|
||||
#define M8260_FETH_TBD_I 0x1000 /* interrupt on transmit */
|
||||
#define M8260_FETH_TBD_L 0x0800 /* buffer is last in frame */
|
||||
#define M8260_FETH_TBD_TC 0x0400 /* auto transmit CRC */
|
||||
#define M8260_FETH_TBD_DEF 0x0200 /* defer indication */
|
||||
#define M8260_FETH_TBD_HB 0x0100 /* heartbeat */
|
||||
#define M8260_FETH_TBD_LC 0x0080 /* late collision */
|
||||
#define M8260_FETH_TBD_RL 0x0040 /* retransmission limit */
|
||||
#define M8260_FETH_TBD_RC 0x003c /* retry count */
|
||||
#define M8260_FETH_TBD_UN 0x0002 /* underrun */
|
||||
#define M8260_FETH_TBD_CSL 0x0001 /* carrier sense lost */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCm8260Fcch */
|
||||
@@ -0,0 +1,517 @@
|
||||
/* m8260SccEnd.h - Motorola MPC8260 Serial Communication Controllers (SCC) Ethernet interface header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996-2009 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,28jan09,wap Complete driver rewrite (WIND00146685)
|
||||
01d,16jan03,gjc SPR#85071 and SPR#85093 :Added define to support DUPLEX.
|
||||
01c,17may02,gjc #SPR 75922, undef SCC_BUF if prev defined.
|
||||
01b,09may02,gjc Fixing SPR #75046 by setting SCC to Full Duplex Mode.
|
||||
01a,10may01,g_h adapted from sbcM8260CpmEnd.h (ver. 01b).
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INCm8260SccEndh
|
||||
#define __INCm8260SccEndh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ETHER_ADDR_LEN 6
|
||||
#define ETHER_CRC_LEN 4
|
||||
|
||||
typedef struct endNetPool
|
||||
{
|
||||
NET_POOL pool;
|
||||
void * pMblkMemArea;
|
||||
void * pClMemArea;
|
||||
} END_NET_POOL;
|
||||
|
||||
#define sccEndPoolTupleFree(x) netMblkClChainFree(x)
|
||||
#define sccEndPoolTupleGet(x) \
|
||||
netTupleGet((x), (x)->clTbl[0]->clSize, M_DONTWAIT, MT_DATA, 0)
|
||||
|
||||
|
||||
#define SCC_GSMR_L 0x00 /* SCC General Mode */
|
||||
#define SCC_GSMR_H 0x04 /* SCC General Mode */
|
||||
#define SCC_PSMR 0x08 /* SCC Proto. Spec */
|
||||
#define SCC_TODR 0x0C /* SCC Tx On Demand */
|
||||
#define SCC_DSR 0x0E /* SCC Data Sync */
|
||||
#define SCC_SCCER 0x10 /* SCC Event Reg */
|
||||
#define SCC_SCCMR 0x14 /* SCC Mask Reg */
|
||||
#define SCC_SCCSR 0x17 /* SCC Status Reg */
|
||||
|
||||
|
||||
#define SCC_GSMRL_HDLC 0x00000000 /* HDLC mode */
|
||||
#define SCC_GSMRL_APPLETALK 0x00000002 /* AppleTalk mode (LocalTalk) */
|
||||
#define SCC_GSMRL_SS7 0x00000003 /* SS7 mode (microcode) */
|
||||
#define SCC_GSMRL_UART 0x00000004 /* UART mode */
|
||||
#define SCC_GSMRL_PROFI_BUS 0x00000005 /* Profi-Bus mode (microcode) */
|
||||
#define SCC_GSMRL_ASYNC_HDLC 0x00000006 /* async HDLC mode (microcode)*/
|
||||
#define SCC_GSMRL_V14 0x00000007 /* V.14 mode */
|
||||
#define SCC_GSMRL_BISYNC 0x00000008 /* BISYNC mode */
|
||||
#define SCC_GSMRL_DDCMP 0x00000009 /* DDCMP mode (microcode) */
|
||||
#define SCC_GSMRL_ETHERNET 0x0000000c /* ethernet mode (SCC1 only) */
|
||||
#define SCC_GSMRL_ENT 0x00000010 /* enable transmitter */
|
||||
#define SCC_GSMRL_ENR 0x00000020 /* enable receiver */
|
||||
#define SCC_GSMRL_LOOPBACK 0x00000040 /* local loopback mode */
|
||||
#define SCC_GSMRL_ECHO 0x00000080 /* automatic echo mode */
|
||||
#define SCC_GSMRL_TENC 0x00000700 /* transmitter encoding method*/
|
||||
#define SCC_GSMRL_RENC 0x00003800 /* receiver encoding method */
|
||||
#define SCC_GSMRL_RDCR_X8 0x00004000 /* receive DPLL clock x8 */
|
||||
#define SCC_GSMRL_RDCR_X16 0x00008000 /* receive DPLL clock x16 */
|
||||
#define SCC_GSMRL_RDCR_X32 0x0000c000 /* receive DPLL clock x32 */
|
||||
#define SCC_GSMRL_TDCR_X8 0x00010000 /* transmit DPLL clock x8 */
|
||||
#define SCC_GSMRL_TDCR_X16 0x00020000 /* transmit DPLL clock x16 */
|
||||
#define SCC_GSMRL_TDCR_X32 0x00030000 /* transmit DPLL clock x32 */
|
||||
#define SCC_GSMRL_TEND 0x00040000 /* transmitter frame ending */
|
||||
#define SCC_GSMRL_TPP_00 0x00180000 /* Tx preamble pattern = 00 */
|
||||
#define SCC_GSMRL_TPP_10 0x00080000 /* Tx preamble pattern = 10 */
|
||||
#define SCC_GSMRL_TPP_01 0x00100000 /* Tx preamble pattern = 01 */
|
||||
#define SCC_GSMRL_TPP_11 0x00180000 /* Tx preamble pattern = 11 */
|
||||
#define SCC_GSMRL_TPL_NONE 0x00000000 /* no Tx preamble (default) */
|
||||
#define SCC_GSMRL_TPL_8 0x00200000 /* Tx preamble = 1 byte */
|
||||
#define SCC_GSMRL_TPL_16 0x00400000 /* Tx preamble = 2 bytes */
|
||||
#define SCC_GSMRL_TPL_32 0x00600000 /* Tx preamble = 4 bytes */
|
||||
#define SCC_GSMRL_TPL_48 0x00800000 /* Tx preamble = 6 bytes */
|
||||
#define SCC_GSMRL_TPL_64 0x00a00000 /* Tx preamble = 8 bytes */
|
||||
#define SCC_GSMRL_TPL_128 0x00c00000 /* Tx preamble = 16 bytes */
|
||||
#define SCC_GSMRL_TINV 0x01000000 /* DPLL transmit input invert */
|
||||
#define SCC_GSMRL_RINV 0x02000000 /* DPLL receive input invert */
|
||||
#define SCC_GSMRL_TSNC 0x0c000000 /* transmit sense */
|
||||
#define SCC_GSMRL_TCI 0x10000000 /* transmit clock invert */
|
||||
#define SCC_GSMRL_EDGE 0x60000000 /* adjustment edge +/- */
|
||||
|
||||
#define SCC_GSMRH_RSYN 0x00000001 /* receive sync timing*/
|
||||
#define SCC_GSMRH_RTSM 0x00000002 /* RTS* mode */
|
||||
#define SCC_GSMRH_SYNL 0x0000000c /* sync length */
|
||||
#define SCC_GSMRH_TXSY 0x00000010 /* transmitter/receiver sync */
|
||||
#define SCC_GSMRH_RFW 0x00000020 /* Rx FIFO width */
|
||||
#define SCC_GSMRH_TFL 0x00000040 /* transmit FIFO length */
|
||||
#define SCC_GSMRH_CTSS 0x00000080 /* CTS* sampling */
|
||||
#define SCC_GSMRH_CDS 0x00000100 /* CD* sampling */
|
||||
#define SCC_GSMRH_CTSP 0x00000200 /* CTS* pulse */
|
||||
#define SCC_GSMRH_CDP 0x00000400 /* CD* pulse */
|
||||
#define SCC_GSMRH_TTX 0x00000800 /* transparent transmitter */
|
||||
#define SCC_GSMRH_TRX 0x00001000 /* transparent receiver */
|
||||
#define SCC_GSMRH_REVD 0x00002000 /* reverse data */
|
||||
#define SCC_GSMRH_TCRC 0x0000c000 /* transparent CRC */
|
||||
#define SCC_GSMRH_GDE 0x00010000 /* glitch detect enable */
|
||||
|
||||
/* CPM - Communication Processor Module */
|
||||
|
||||
/* SCC Ethernet Protocol Specific Mode Register definitions */
|
||||
|
||||
#define SCC_ETHER_PSMR_FDE 0x0001
|
||||
#define SCC_ETHER_PSMR_NIB_13 0x0000 /* SFD 13 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_14 0x0002 /* SFD 14 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_15 0x0004 /* SFD 15 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_16 0x0006 /* SFD 16 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_21 0x0008 /* SFD 21 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_22 0x000a /* SFD 22 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_23 0x000c /* SFD 23 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_24 0x000e /* SFD 24 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_LCW 0x0010 /* late collision window */
|
||||
#define SCC_ETHER_PSMR_SIP 0x0200 /* sample input pins */
|
||||
#define SCC_ETHER_PSMR_LPB 0x0040 /* loopback operation */
|
||||
#define SCC_ETHER_PSMR_SBT 0x0080 /* stop backoff timer */
|
||||
#define SCC_ETHER_PSMR_BRO 0x0100 /* broadcast address */
|
||||
#define SCC_ETHER_PSMR_PRO 0x0200 /* promiscuous mode */
|
||||
#define SCC_ETHER_PSMR_CRC 0x0800 /* CRC selection */
|
||||
#define SCC_ETHER_PSMR_IAM 0x1000 /* individual address mode */
|
||||
#define SCC_ETHER_PSMR_RSH 0x2000 /* receive short frame */
|
||||
#define SCC_ETHER_PSMR_FC 0x4000 /* force collision */
|
||||
#define SCC_ETHER_PSMR_HBC 0x8000 /* heartbeat checking*/
|
||||
|
||||
/* SCC Ethernet Event and Mask Register definitions */
|
||||
|
||||
#define SCC_ETHER_SCCX_RXB 0x0001 /* buffer received event */
|
||||
#define SCC_ETHER_SCCX_TXB 0x0002 /* buffer transmitted event */
|
||||
#define SCC_ETHER_SCCX_BSY 0x0004 /* busy condition */
|
||||
#define SCC_ETHER_SCCX_RXF 0x0008 /* frame received event */
|
||||
#define SCC_ETHER_SCCX_TXE 0x0010 /* transmission error event */
|
||||
#define SCC_ETHER_SCCX_GRA 0x0080 /* graceful stop event */
|
||||
|
||||
/* SCC Ethernet Receive Buffer Descriptor definitions */
|
||||
|
||||
#define SCC_ETHER_RX_BD_CL 0x0001 /* collision condition */
|
||||
#define SCC_ETHER_RX_BD_OV 0x0002 /* overrun condition */
|
||||
#define SCC_ETHER_RX_BD_CR 0x0004 /* Rx CRC error */
|
||||
#define SCC_ETHER_RX_BD_SH 0x0008 /* short frame received */
|
||||
#define SCC_ETHER_RX_BD_NO 0x0010 /* Rx nonoctet aligned frame */
|
||||
#define SCC_ETHER_RX_BD_LG 0x0020 /* Rx frame length violation */
|
||||
#define SCC_ETHER_RX_BD_M 0x0100 /* miss bit for prom mode */
|
||||
#define SCC_ETHER_RX_BD_F 0x0400 /* buffer is first in frame */
|
||||
#define SCC_ETHER_RX_BD_L 0x0800 /* buffer is last in frame */
|
||||
#define SCC_ETHER_RX_BD_I 0x1000 /* interrupt on receive */
|
||||
#define SCC_ETHER_RX_BD_W 0x2000 /* last BD in ring */
|
||||
#define SCC_ETHER_RX_BD_E 0x8000 /* buffer is empty */
|
||||
|
||||
/* SCC Ethernet Transmit Buffer Descriptor definitions */
|
||||
|
||||
#define SCC_ETHER_TX_BD_CSL 0x0001 /* carrier sense lost */
|
||||
#define SCC_ETHER_TX_BD_UN 0x0002 /* underrun */
|
||||
#define SCC_ETHER_TX_BD_RC 0x003c /* retry count */
|
||||
#define SCC_ETHER_TX_BD_RL 0x0040 /* retransmission limit */
|
||||
#define SCC_ETHER_TX_BD_LC 0x0080 /* late collision */
|
||||
#define SCC_ETHER_TX_BD_HB 0x0100 /* heartbeat */
|
||||
#define SCC_ETHER_TX_BD_DEF 0x0200 /* defer indication */
|
||||
#define SCC_ETHER_TX_BD_TC 0x0400 /* auto transmit CRC */
|
||||
#define SCC_ETHER_TX_BD_L 0x0800 /* buffer is last in frame */
|
||||
#define SCC_ETHER_TX_BD_I 0x1000 /* interrupt on transmit */
|
||||
#define SCC_ETHER_TX_BD_W 0x2000 /* last BD in ring */
|
||||
#define SCC_ETHER_TX_BD_PAD 0x4000 /* auto pad short frames */
|
||||
#define SCC_ETHER_TX_BD_R 0x8000 /* buffer is ready */
|
||||
|
||||
/* SCC Parameter RAM registers in ethernet mode */
|
||||
|
||||
#define SCC_RBASE 0x00
|
||||
#define SCC_TBASE 0x02
|
||||
#define SCC_RFCR 0x04
|
||||
#define SCC_TFCR 0x05
|
||||
#define SCC_MRBLR 0x06
|
||||
#define SCC_RSTATE 0x08
|
||||
#define SCC_RIP 0x0C
|
||||
#define SCC_RBPTR 0x10
|
||||
#define SCC_RCOUNT 0x12
|
||||
#define SCC_RTEMP 0x14
|
||||
#define SCC_TSTATE 0x18
|
||||
#define SCC_TIP 0x1C
|
||||
#define SCC_TBPTR 0x20
|
||||
#define SCC_TCOUNT 0x22
|
||||
#define SCC_TTEMP 0x24
|
||||
#define SCC_RCRC 0x28
|
||||
#define SCC_TCRC 0x2C
|
||||
#define SCC_C_PRES 0x30
|
||||
#define SCC_C_MASK 0x34
|
||||
#define SCC_CRCEC 0x38
|
||||
#define SCC_ALEC 0x3C
|
||||
#define SCC_DISFC 0x40
|
||||
#define SCC_PADS 0x44
|
||||
#define SCC_RET_LIM 0x46
|
||||
#define SCC_RET_CNT 0x48
|
||||
#define SCC_MFLR 0x4A
|
||||
#define SCC_MINFLR 0x4C
|
||||
#define SCC_MAXD1 0x4E
|
||||
#define SCC_MAXD2 0x50
|
||||
#define SCC_MAXD 0x52
|
||||
#define SCC_DMA_CNT 0x54
|
||||
#define SCC_MAX_B 0x56
|
||||
#define SCC_GADDR1 0x58
|
||||
#define SCC_GADDR2 0x5A
|
||||
#define SCC_GADDR3 0x5C
|
||||
#define SCC_GADDR4 0x5E
|
||||
#define SCC_TBUF0_DATA0 0x60
|
||||
#define SCC_TBUF0_DATA1 0x64
|
||||
#define SCC_TBUF0_RBA0 0x68
|
||||
#define SCC_TBUF0_CRC 0x6C
|
||||
#define SCC_TBUF0_BCNT 0x80
|
||||
#define SCC_PADDR_H 0x72
|
||||
#define SCC_PADDR_M 0x74
|
||||
#define SCC_PADDR_L 0x7C
|
||||
#define SCC_P_PER 0x78
|
||||
#define SCC_RFBD_PTR 0x7A
|
||||
#define SCC_TFBD_PTR 0x7C
|
||||
#define SCC_TLBD_PTR 0x7E
|
||||
#define SCC_TBUF1_DATA0 0x80
|
||||
#define SCC_TBUF1_DATA1 0x84
|
||||
#define SCC_TBUF1_RBA0 0x88
|
||||
#define SCC_TBUF1_CRC 0x8C
|
||||
#define SCC_TBUF1_BCNT 0x90
|
||||
#define SCC_TX_LEN 0x92
|
||||
#define SCC_IADDR1 0x94
|
||||
#define SCC_IADDR2 0x96
|
||||
#define SCC_IADDR3 0x98
|
||||
#define SCC_IADDR4 0x9A
|
||||
#define SCC_BOFF_CNT 0x9C
|
||||
#define SCC_TADDR_H 0x9E
|
||||
#define SCC_TADDR_M 0xA0
|
||||
#define SCC_TADDR_L 0xA2
|
||||
|
||||
|
||||
/* RFCR and TFCR registers */
|
||||
|
||||
#define FCR_DTB 0x02
|
||||
#define FCR_TC2 0x04
|
||||
#define FCR_BO_LE 0x08
|
||||
#define FCR_BO_BE 0x10
|
||||
#define FCR_GBL 0x20
|
||||
|
||||
#define SCC_NAME "motscc"
|
||||
#define SCC_TIMEOUT 10000
|
||||
#define SCC_INTRS \
|
||||
(SCC_ETHER_SCCX_RXB|SCC_ETHER_SCCX_BSY|SCC_ETHER_SCCX_RXF| \
|
||||
SCC_ETHER_SCCX_TXB|SCC_ETHER_SCCX_TXE)
|
||||
|
||||
#define SCC_RXINTRS \
|
||||
(SCC_ETHER_SCCX_RXB|SCC_ETHER_SCCX_BSY|SCC_ETHER_SCCX_RXF)
|
||||
|
||||
#define SCC_TXINTRS \
|
||||
(SCC_ETHER_SCCX_TXB|SCC_ETHER_SCCX_TXE)
|
||||
|
||||
#define SCC_LINKINTRS 0
|
||||
|
||||
#define SCC_RBD_ALIGN 16
|
||||
|
||||
#define SCC_ALIGN(x) (char *)(((UINT32)(x) + (15 * 2)) & ~15)
|
||||
|
||||
#define SCC_ADJ(x) \
|
||||
(x)->m_data = SCC_ALIGN((x)->m_data)
|
||||
|
||||
#define SCC_CLSIZE 1600
|
||||
|
||||
#define SCC_INC_DESC(x, y) (x) = ((x + 1) & (y - 1))
|
||||
#define SCC_MAXFRAG 16
|
||||
#define SCC_MAX_RX 16
|
||||
|
||||
/*
|
||||
* We deliberately specify a large number of DMA descriptors here,
|
||||
* in order to avoid losing any frames on receive. The number of
|
||||
* buffers (SCC_BUF_CNT) should be at least twice the number of
|
||||
* RX descriptors (SCC_RX_DESC_CNT), plus the number of TX descriptors
|
||||
* (SCC_TX_DESC_CNT).
|
||||
*
|
||||
* Note that unlike the FEC and FCC interfaces, the DMA descriptor
|
||||
* rings for the CPM/SCC must reside in DPRAM. Normally, the range
|
||||
* from 0x2000 to 0x21FF is used, howeve this is very small and only
|
||||
* allows for 32 descriptors for RX and TX. The MPC860/MPC850 has
|
||||
* additional DPRAM located at 0x3000 through 0x3BFF. We use this
|
||||
* region instead, so that we can have a fairly large RX ring.
|
||||
*/
|
||||
|
||||
#define SCC_BUF_CNT (256)
|
||||
#define SCC_RX_DESC_CNT 32
|
||||
#define SCC_TX_DESC_CNT 32
|
||||
|
||||
#define SCC_RX_DPRAM 0x3000
|
||||
#define SCC_TX_DPRAM 0x3400
|
||||
|
||||
/*
|
||||
#define SCC_BUF_CNT 768
|
||||
#define SCC_RX_DESC_CNT 256
|
||||
#define SCC_TX_DESC_CNT 128
|
||||
|
||||
#define SCC_RX_DPRAM 0x3000
|
||||
#define SCC_TX_DPRAM 0x3800
|
||||
*/
|
||||
|
||||
typedef struct scc_desc
|
||||
{
|
||||
volatile UINT16 bdSts;
|
||||
volatile UINT16 bdLen;
|
||||
volatile UINT32 bdAddr;
|
||||
} SCC_DESC;
|
||||
|
||||
/*
|
||||
* Private adapter context structure.
|
||||
*/
|
||||
|
||||
typedef struct scc_drv_ctrl
|
||||
{
|
||||
END_OBJ sccEndObj;
|
||||
void * sccPram;
|
||||
void * sccIram;
|
||||
int sccUnit;
|
||||
int sccIvec;
|
||||
int sccIlevel;
|
||||
|
||||
volatile BOOL sccIntPending;
|
||||
|
||||
volatile BOOL sccRxPending;
|
||||
|
||||
volatile BOOL sccTxPending;
|
||||
UINT8 sccTxCur;
|
||||
UINT8 sccTxLast;
|
||||
volatile BOOL sccTxStall;
|
||||
UINT16 sccTxThresh;
|
||||
|
||||
BOOL sccPolling;
|
||||
M_BLK_ID sccPollBuf;
|
||||
UINT16 sccIntMask;
|
||||
|
||||
UINT8 sccAddr[ETHER_ADDR_LEN + 2];
|
||||
|
||||
SCC_DESC *sccRxDescMem;
|
||||
|
||||
SCC_DESC *sccTxDescMem;
|
||||
|
||||
M_BLK_ID sccRxMblk[SCC_RX_DESC_CNT];
|
||||
M_BLK_ID sccTxMblk[SCC_TX_DESC_CNT];
|
||||
|
||||
UINT32 sccTxProd;
|
||||
UINT32 sccTxCons;
|
||||
UINT32 sccTxFree;
|
||||
UINT32 sccRxIdx;
|
||||
|
||||
int sccNum;
|
||||
|
||||
END_ERR sccLastError;
|
||||
} SCC_DRV_CTRL;
|
||||
|
||||
|
||||
#ifndef BSP_VERSION
|
||||
|
||||
LOCAL UINT32 csr_read_4 (SCC_DRV_CTRL *, UINT32, int);
|
||||
LOCAL void csr_write_4 (SCC_DRV_CTRL *, UINT32, int, UINT32);
|
||||
LOCAL UINT16 csr_read_2 (SCC_DRV_CTRL *, UINT16, int);
|
||||
LOCAL void csr_write_2 (SCC_DRV_CTRL *, UINT16, int, UINT16);
|
||||
#ifdef notused
|
||||
LOCAL UINT8 csr_read_1 (SCC_DRV_CTRL *, UINT8, int);
|
||||
#endif
|
||||
LOCAL void csr_write_1 (SCC_DRV_CTRL *, UINT8, int, UINT8);
|
||||
|
||||
#define SCC_PRAM 0
|
||||
#define SCC_IRAM 1
|
||||
|
||||
LOCAL UINT32 csr_read_4
|
||||
(
|
||||
SCC_DRV_CTRL * pDrv,
|
||||
UINT32 addr,
|
||||
int ix
|
||||
)
|
||||
{
|
||||
UINT32 data;
|
||||
if (ix == SCC_PRAM)
|
||||
data = *(UINT32 *)((UINT8 *)pDrv->sccPram + addr);
|
||||
else
|
||||
data = *(UINT32 *)((UINT8 *)pDrv->sccIram + addr);
|
||||
return (data);
|
||||
}
|
||||
|
||||
LOCAL void csr_write_4
|
||||
(
|
||||
SCC_DRV_CTRL * pDrv,
|
||||
UINT32 addr,
|
||||
int ix,
|
||||
UINT32 data
|
||||
)
|
||||
{
|
||||
UINT32 * reg;
|
||||
|
||||
if (ix == SCC_PRAM)
|
||||
reg = (UINT32 *)((UINT8 *)pDrv->sccPram + addr);
|
||||
else
|
||||
reg = (UINT32 *)((UINT8 *)pDrv->sccIram + addr);
|
||||
*reg = data;
|
||||
return;
|
||||
}
|
||||
|
||||
LOCAL UINT16 csr_read_2
|
||||
(
|
||||
SCC_DRV_CTRL * pDrv,
|
||||
UINT16 addr,
|
||||
int ix
|
||||
)
|
||||
{
|
||||
UINT16 data;
|
||||
if (ix == SCC_PRAM)
|
||||
data = *(UINT16 *)((UINT8 *)pDrv->sccPram + addr);
|
||||
else
|
||||
data = *(UINT16 *)((UINT8 *)pDrv->sccIram + addr);
|
||||
return (data);
|
||||
}
|
||||
|
||||
LOCAL void csr_write_2
|
||||
(
|
||||
SCC_DRV_CTRL * pDrv,
|
||||
UINT16 addr,
|
||||
int ix,
|
||||
UINT16 data
|
||||
)
|
||||
{
|
||||
UINT16 * reg;
|
||||
|
||||
if (ix == SCC_PRAM)
|
||||
reg = (UINT16 *)((UINT8 *)pDrv->sccPram + addr);
|
||||
else
|
||||
reg = (UINT16 *)((UINT8 *)pDrv->sccIram + addr);
|
||||
*reg = data;
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef notused
|
||||
LOCAL UINT8 csr_read_1
|
||||
(
|
||||
SCC_DRV_CTRL * pDrv,
|
||||
UINT8 addr,
|
||||
int ix
|
||||
)
|
||||
{
|
||||
UINT16 data;
|
||||
if (ix == SCC_PRAM)
|
||||
data = *(UINT8 *)((UINT8 *)pDrv->sccPram + addr);
|
||||
else
|
||||
data = *(UINT8 *)((UINT8 *)pDrv->sccIram + addr);
|
||||
return (data);
|
||||
}
|
||||
#endif
|
||||
|
||||
LOCAL void csr_write_1
|
||||
(
|
||||
SCC_DRV_CTRL * pDrv,
|
||||
UINT8 addr,
|
||||
int ix,
|
||||
UINT8 data
|
||||
)
|
||||
{
|
||||
UINT8 * reg;
|
||||
|
||||
if (ix == SCC_PRAM)
|
||||
reg = (UINT8 *)((UINT8 *)pDrv->sccPram + addr);
|
||||
else
|
||||
reg = (UINT8 *)((UINT8 *)pDrv->sccIram + addr);
|
||||
*reg = data;
|
||||
return;
|
||||
}
|
||||
|
||||
#define CSR_READ_4 csr_read_4
|
||||
#define CSR_READ_2 csr_read_2
|
||||
#define CSR_READ_1 csr_read_1
|
||||
#define CSR_WRITE_4 csr_write_4
|
||||
#define CSR_WRITE_2 csr_write_2
|
||||
#define CSR_WRITE_1 csr_write_1
|
||||
|
||||
#define CSR_SETBIT_1(pDev, offset, ix, val) \
|
||||
CSR_WRITE_1(pDev, offset, ix, CSR_READ_1(pDev, offset, ix) | (val))
|
||||
|
||||
#define CSR_CLRBIT_1(pDev, offset, ix, val) \
|
||||
CSR_WRITE_1(pDev, offset, CSR_READ_1(pDev, offset, ix) & ~(val))
|
||||
|
||||
#define CSR_SETBIT_2(pDev, offset, ix, val) \
|
||||
CSR_WRITE_2(pDev, offset, ix, CSR_READ_2(pDev, offset, ix) | (val))
|
||||
|
||||
#define CSR_CLRBIT_2(pDev, offset, ix, val) \
|
||||
CSR_WRITE_2(pDev, offset, ix, CSR_READ_2(pDev, offset, ix) & ~(val))
|
||||
|
||||
#define CSR_SETBIT_4(pDev, offset, ix, val) \
|
||||
CSR_WRITE_4(pDev, offset, ix, CSR_READ_4(pDev, offset, ix) | (val))
|
||||
|
||||
#define CSR_CLRBIT_4(pDev, offset, ix, val) \
|
||||
CSR_WRITE_4(pDev, offset, ix, CSR_READ_4(pDev, offset, ix) & ~(val))
|
||||
|
||||
#endif /* BSP_VERSION */
|
||||
|
||||
/*
|
||||
* Note: these have no meaning for this driver. They're provided only
|
||||
* for backwards compatibility with some BSPs, which expect these flags
|
||||
* to be defined.
|
||||
*/
|
||||
|
||||
#define SCC_USR_RUNNING_FROM_ROM 0x00000001 /* inhibit zcopy mode */
|
||||
#define SCC_USR_DUPLEX_HALF 0x00000000 /* Half duplex */
|
||||
#define SCC_USR_DUPLEX_FULL 0x00000002 /* Full duplex */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCm8260SccEndh */
|
||||
@@ -0,0 +1,343 @@
|
||||
/* motCpmEnd.h - Motorola CPM core Ethernet interface header */
|
||||
|
||||
/* Copyright 1996 - 2002, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01i,29apr10,pad Moved extern C statement after include statements.
|
||||
01h,12nov04,dtr Use PPC32 and CPU32 types instead of PPC860.
|
||||
01g,24jan02,rcs removed #include "drv/netif/if_cpm.h"
|
||||
01f,24jan02,rcs moved General SCC Mode Register definitions,
|
||||
SCC Ethernet Protocol Specific Mode Register definitions,
|
||||
SCC Ethernet Event and Mask Register definitions,
|
||||
SCC Ethernet Receive Buffer Descriptor definitions,
|
||||
SCC Ethernet Transmit Buffer Descriptor definitions,
|
||||
SCC Serial Comunications Controller,
|
||||
SCC device descriptor, and
|
||||
#include "drv/multi/ppc860Cpm.h" from h/drv/netif/if_cpm.h
|
||||
01e,08jan02,mil Backed out last update "Remove compilation warning".
|
||||
01d,22dec01,g_h Remove compilation warning
|
||||
01c,28aug98,dat changed all motCmp names to motCpm.
|
||||
01b,29jun98,cn fixed compiler errors for CPUs other than CPU32 or PPC860.
|
||||
01a,22jun98,cn created.
|
||||
*/
|
||||
|
||||
/*
|
||||
This file contains definitions to support the end-style Network Driver
|
||||
for the Motorola CPM core Ethernet controller used in the M68EN360 and
|
||||
PPC800-series communications controllers. These definitions are compiler
|
||||
dependant, meaning that their values are based on the particular cpu
|
||||
being used.
|
||||
*/
|
||||
|
||||
#ifndef __INCmotCpmEndh
|
||||
#define __INCmotCpmEndh
|
||||
|
||||
#if ((CPU == PPC32) || (CPU == PPC860))
|
||||
#include "drv/multi/ppc860Cpm.h"
|
||||
#include "drv/multi/ppc860Siu.h"
|
||||
#else
|
||||
#include "drv/multi/m68360.h" /* default: use CPU32 include file */
|
||||
#endif /* CPU == PPC32 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/*
|
||||
* the following may be redefined in the bsp to account for the actual
|
||||
* number of SCC devices in the system.
|
||||
*/
|
||||
|
||||
#ifndef MAX_SCC_CHANNELS
|
||||
#define MAX_SCC_CHANNELS 4 /* max SCC number for Ethernet channels */
|
||||
#endif /* MAX_SCC_CHANNELS */
|
||||
|
||||
#if ((CPU == PPC32) || (CPU == PPC860))
|
||||
|
||||
#define CPM_DPR_SCC1(baseAddr) MPC860_DPR_SCC1 (baseAddr)
|
||||
#define CPM_GSMR_L1(baseAddr) GSMR_L1 (baseAddr)
|
||||
#define CPM_CIMR_SCC4 CIMR_SCC4
|
||||
#define CPM_CIMR(baseAddr) CIMR (baseAddr)
|
||||
#define CPM_CISR(baseAddr) CISR (baseAddr)
|
||||
#define CPM_CPCR(baseAddr) CPCR (baseAddr)
|
||||
#define END_OBJ_STRING "MPC860 Power-QUICC Enhanced Network Driver"
|
||||
#define MOT_DEV_NAME "cpm"
|
||||
#define MOT_DEV_NAME_LEN 4
|
||||
|
||||
/* General SCC Mode Register definitions */
|
||||
|
||||
#define SCC_GSMRL_HDLC 0x00000000 /* HDLC mode */
|
||||
#define SCC_GSMRL_APPLETALK 0x00000002 /* AppleTalk mode (LocalTalk) */
|
||||
#define SCC_GSMRL_SS7 0x00000003 /* SS7 mode (microcode) */
|
||||
#define SCC_GSMRL_UART 0x00000004 /* UART mode */
|
||||
#define SCC_GSMRL_PROFI_BUS 0x00000005 /* Profi-Bus mode (microcode) */
|
||||
#define SCC_GSMRL_ASYNC_HDLC 0x00000006 /* async HDLC mode (microcode)*/
|
||||
#define SCC_GSMRL_V14 0x00000007 /* V.14 mode */
|
||||
#define SCC_GSMRL_BISYNC 0x00000008 /* BISYNC mode */
|
||||
#define SCC_GSMRL_DDCMP 0x00000009 /* DDCMP mode (microcode) */
|
||||
#define SCC_GSMRL_ETHERNET 0x0000000c /* ethernet mode (SCC1 only) */
|
||||
#define SCC_GSMRL_ENT 0x00000010 /* enable transmitter */
|
||||
#define SCC_GSMRL_ENR 0x00000020 /* enable receiver */
|
||||
#define SCC_GSMRL_LOOPBACK 0x00000040 /* local loopback mode */
|
||||
#define SCC_GSMRL_ECHO 0x00000080 /* automatic echo mode */
|
||||
#define SCC_GSMRL_TENC 0x00000700 /* transmitter encoding method*/
|
||||
#define SCC_GSMRL_RENC 0x00003800 /* receiver encoding method */
|
||||
#define SCC_GSMRL_RDCR_X8 0x00004000 /* receive DPLL clock x8 */
|
||||
#define SCC_GSMRL_RDCR_X16 0x00008000 /* receive DPLL clock x16 */
|
||||
#define SCC_GSMRL_RDCR_X32 0x0000c000 /* receive DPLL clock x32 */
|
||||
#define SCC_GSMRL_TDCR_X8 0x00010000 /* transmit DPLL clock x8 */
|
||||
#define SCC_GSMRL_TDCR_X16 0x00020000 /* transmit DPLL clock x16 */
|
||||
#define SCC_GSMRL_TDCR_X32 0x00030000 /* transmit DPLL clock x32 */
|
||||
#define SCC_GSMRL_TEND 0x00040000 /* transmitter frame ending */
|
||||
#define SCC_GSMRL_TPP_00 0x00180000 /* Tx preamble pattern = 00 */
|
||||
#define SCC_GSMRL_TPP_10 0x00080000 /* Tx preamble pattern = 10 */
|
||||
#define SCC_GSMRL_TPP_01 0x00100000 /* Tx preamble pattern = 01 */
|
||||
#define SCC_GSMRL_TPP_11 0x00180000 /* Tx preamble pattern = 11 */
|
||||
#define SCC_GSMRL_TPL_NONE 0x00000000 /* no Tx preamble (default) */
|
||||
#define SCC_GSMRL_TPL_8 0x00200000 /* Tx preamble = 1 byte */
|
||||
#define SCC_GSMRL_TPL_16 0x00400000 /* Tx preamble = 2 bytes */
|
||||
#define SCC_GSMRL_TPL_32 0x00600000 /* Tx preamble = 4 bytes */
|
||||
#define SCC_GSMRL_TPL_48 0x00800000 /* Tx preamble = 6 bytes */
|
||||
#define SCC_GSMRL_TPL_64 0x00a00000 /* Tx preamble = 8 bytes */
|
||||
#define SCC_GSMRL_TPL_128 0x00c00000 /* Tx preamble = 16 bytes */
|
||||
#define SCC_GSMRL_TINV 0x01000000 /* DPLL transmit input invert */
|
||||
#define SCC_GSMRL_RINV 0x02000000 /* DPLL receive input invert */
|
||||
#define SCC_GSMRL_TSNC 0x0c000000 /* transmit sense */
|
||||
#define SCC_GSMRL_TCI 0x10000000 /* transmit clock invert */
|
||||
#define SCC_GSMRL_EDGE 0x60000000 /* adjustment edge +/- */
|
||||
|
||||
#define SCC_GSMRH_RSYN 0x00000001 /* receive sync timing*/
|
||||
#define SCC_GSMRH_RTSM 0x00000002 /* RTS* mode */
|
||||
#define SCC_GSMRH_SYNL 0x0000000c /* sync length */
|
||||
#define SCC_GSMRH_TXSY 0x00000010 /* transmitter/receiver sync */
|
||||
#define SCC_GSMRH_RFW 0x00000020 /* Rx FIFO width */
|
||||
#define SCC_GSMRH_TFL 0x00000040 /* transmit FIFO length */
|
||||
#define SCC_GSMRH_CTSS 0x00000080 /* CTS* sampling */
|
||||
#define SCC_GSMRH_CDS 0x00000100 /* CD* sampling */
|
||||
#define SCC_GSMRH_CTSP 0x00000200 /* CTS* pulse */
|
||||
#define SCC_GSMRH_CDP 0x00000400 /* CD* pulse */
|
||||
#define SCC_GSMRH_TTX 0x00000800 /* transparent transmitter */
|
||||
#define SCC_GSMRH_TRX 0x00001000 /* transparent receiver */
|
||||
#define SCC_GSMRH_REVD 0x00002000 /* reverse data */
|
||||
#define SCC_GSMRH_TCRC 0x0000c000 /* transparent CRC */
|
||||
#define SCC_GSMRH_GDE 0x00010000 /* glitch detect enable */
|
||||
|
||||
/* CPM - Communication Processor Module */
|
||||
|
||||
/* SCC Ethernet Protocol Specific Mode Register definitions */
|
||||
|
||||
#define SCC_ETHER_PSMR_NIB_13 0x0000 /* SFD 13 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_14 0x0002 /* SFD 14 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_15 0x0004 /* SFD 15 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_16 0x0006 /* SFD 16 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_21 0x0008 /* SFD 21 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_22 0x000a /* SFD 22 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_23 0x000c /* SFD 23 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_NIB_24 0x000e /* SFD 24 bits after TENA */
|
||||
#define SCC_ETHER_PSMR_LCW 0x0100 /* late collision window */
|
||||
#define SCC_ETHER_PSMR_SIP 0x0200 /* sample input pins */
|
||||
#define SCC_ETHER_PSMR_LPB 0x0400 /* loopback operation */
|
||||
#define SCC_ETHER_PSMR_SBT 0x0800 /* stop backoff timer */
|
||||
#define SCC_ETHER_PSMR_BRO 0x0100 /* broadcast address */
|
||||
#define SCC_ETHER_PSMR_PRO 0x0200 /* promiscuous mode */
|
||||
#define SCC_ETHER_PSMR_CRC 0x0800 /* CRC selection */
|
||||
#define SCC_ETHER_PSMR_IAM 0x1000 /* individual address mode */
|
||||
#define SCC_ETHER_PSMR_RSH 0x2000 /* receive short frame */
|
||||
#define SCC_ETHER_PSMR_FC 0x4000 /* force collision */
|
||||
#define SCC_ETHER_PSMR_HBC 0x8000 /* heartbeat checking*/
|
||||
|
||||
/* SCC Ethernet Event and Mask Register definitions */
|
||||
|
||||
#define SCC_ETHER_SCCX_RXB 0x0001 /* buffer received event */
|
||||
#define SCC_ETHER_SCCX_TXB 0x0002 /* buffer transmitted event */
|
||||
#define SCC_ETHER_SCCX_BSY 0x0004 /* busy condition */
|
||||
#define SCC_ETHER_SCCX_RXF 0x0008 /* frame received event */
|
||||
#define SCC_ETHER_SCCX_TXE 0x0010 /* transmission error event */
|
||||
#define SCC_ETHER_SCCX_GRA 0x0080 /* graceful stop event */
|
||||
|
||||
/* SCC Ethernet Receive Buffer Descriptor definitions */
|
||||
|
||||
#define SCC_ETHER_RX_BD_CL 0x0001 /* collision condition */
|
||||
#define SCC_ETHER_RX_BD_OV 0x0002 /* overrun condition */
|
||||
#define SCC_ETHER_RX_BD_CR 0x0004 /* Rx CRC error */
|
||||
#define SCC_ETHER_RX_BD_SH 0x0008 /* short frame received */
|
||||
#define SCC_ETHER_RX_BD_NO 0x0010 /* Rx nonoctet aligned frame */
|
||||
#define SCC_ETHER_RX_BD_LG 0x0020 /* Rx frame length violation */
|
||||
#define SCC_ETHER_RX_BD_M 0x0100 /* miss bit for prom mode */
|
||||
#define SCC_ETHER_RX_BD_F 0x0400 /* buffer is first in frame */
|
||||
#define SCC_ETHER_RX_BD_L 0x0800 /* buffer is last in frame */
|
||||
#define SCC_ETHER_RX_BD_I 0x1000 /* interrupt on receive */
|
||||
#define SCC_ETHER_RX_BD_W 0x2000 /* last BD in ring */
|
||||
#define SCC_ETHER_RX_BD_E 0x8000 /* buffer is empty */
|
||||
|
||||
/* SCC Ethernet Transmit Buffer Descriptor definitions */
|
||||
|
||||
#define SCC_ETHER_TX_BD_CSL 0x0001 /* carrier sense lost */
|
||||
#define SCC_ETHER_TX_BD_UN 0x0002 /* underrun */
|
||||
#define SCC_ETHER_TX_BD_RC 0x003c /* retry count */
|
||||
#define SCC_ETHER_TX_BD_RL 0x0040 /* retransmission limit */
|
||||
#define SCC_ETHER_TX_BD_LC 0x0080 /* late collision */
|
||||
#define SCC_ETHER_TX_BD_HB 0x0100 /* heartbeat */
|
||||
#define SCC_ETHER_TX_BD_DEF 0x0200 /* defer indication */
|
||||
#define SCC_ETHER_TX_BD_TC 0x0400 /* auto transmit CRC */
|
||||
#define SCC_ETHER_TX_BD_L 0x0800 /* buffer is last in frame */
|
||||
#define SCC_ETHER_TX_BD_I 0x1000 /* interrupt on transmit */
|
||||
#define SCC_ETHER_TX_BD_W 0x2000 /* last BD in ring */
|
||||
#define SCC_ETHER_TX_BD_PAD 0x4000 /* auto pad short frames */
|
||||
#define SCC_ETHER_TX_BD_R 0x8000 /* buffer is ready */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
/* SCC - Serial Comunications Controller */
|
||||
|
||||
typedef struct /* SCC_ETHER_PROTO */
|
||||
{
|
||||
UINT32 c_pres; /* preset CRC */
|
||||
UINT32 c_mask; /* constant mask for CRC */
|
||||
volatile UINT32 crcec; /* CRC error counter */
|
||||
volatile UINT32 alec; /* alignment error counter */
|
||||
volatile UINT32 disfc; /* discard frame counter */
|
||||
UINT16 pads; /* short frame pad value */
|
||||
UINT16 ret_lim; /* retry limit threshold */
|
||||
volatile UINT16 ret_cnt; /* retry limit counter */
|
||||
UINT16 mflr; /* maximum frame length register */
|
||||
UINT16 minflr; /* minimum frame length register */
|
||||
UINT16 maxd1; /* max DMA1 length register */
|
||||
UINT16 maxd2; /* max DMA2 length register */
|
||||
volatile UINT16 maxd; /* Rx max DMA */
|
||||
volatile UINT16 dma_cnt; /* Rx DMA counter */
|
||||
volatile UINT16 max_b; /* max BD byte count */
|
||||
UINT16 gaddr1; /* group address filter 1 */
|
||||
UINT16 gaddr2; /* group address filter 2 */
|
||||
UINT16 gaddr3; /* group address filter 3 */
|
||||
UINT16 gaddr4; /* group address filter 4 */
|
||||
volatile UINT32 tbuf0_data0; /* save area 0 - current frame */
|
||||
volatile UINT32 tbuf0_data1; /* save area 1 - current frame */
|
||||
volatile UINT32 tbuf0_rba0; /* ? */
|
||||
volatile UINT32 tbuf0_crc; /* ? */
|
||||
volatile UINT16 tbuf0_bcnt; /* ? */
|
||||
UINT16 paddr1_h; /* physical address 1 (MSB) */
|
||||
UINT16 paddr1_m; /* physical address 1 */
|
||||
UINT16 paddr1_l; /* physical address 1 (LSB) */
|
||||
UINT16 p_per; /* persistence */
|
||||
volatile UINT16 rfbd_ptr; /* Rx first BD pointer */
|
||||
volatile UINT16 tfbd_ptr; /* Tx first BD pointer */
|
||||
volatile UINT16 tlbd_ptr; /* Tx last BD pointer */
|
||||
volatile UINT32 tbuf1_data0; /* save area 0 - next frame */
|
||||
volatile UINT32 tbuf1_data1; /* ? */
|
||||
volatile UINT32 tbuf1_rba0; /* ? */
|
||||
volatile UINT32 tbuf1_crc; /* ? */
|
||||
volatile UINT16 tbuf1_bcnt; /* ? */
|
||||
volatile UINT16 tx_len; /* Tx frame length counter */
|
||||
UINT16 iaddr1; /* individual address filter 1 */
|
||||
UINT16 iaddr2; /* individual address filter 2 */
|
||||
UINT16 iaddr3; /* individual address filter 3 */
|
||||
UINT16 iaddr4; /* individual address filter 4 */
|
||||
volatile UINT16 boff_cnt; /* backoff counter */
|
||||
UINT16 taddr_h; /* temp address (MSB) */
|
||||
UINT16 taddr_m; /* temp address */
|
||||
UINT16 taddr_l; /* temp address (LSB) */
|
||||
} SCC_ETHER_PROTO;
|
||||
|
||||
/* SCC device descriptor */
|
||||
|
||||
typedef struct /* SCC_ETHER_DEV */
|
||||
{
|
||||
int sccNum; /* number of SCC device */
|
||||
int txBdNum; /* number of transmit buf descriptors */
|
||||
int rxBdNum; /* number of receive buf descriptors */
|
||||
SCC_BUF * txBdBase; /* transmit BD base address */
|
||||
SCC_BUF * rxBdBase; /* receive BD base address */
|
||||
u_char * txBufBase; /* transmit buffer base address */
|
||||
u_char * rxBufBase; /* receive buffer base address */
|
||||
UINT32 txBufSize; /* transmit buffer size */
|
||||
UINT32 rxBufSize; /* receive buffer size */
|
||||
int txBdNext; /* next transmit BD to fill */
|
||||
int rxBdNext; /* next receive BD to read */
|
||||
volatile SCC * pScc; /* SCC parameter RAM */
|
||||
volatile SCC_REG * pSccReg; /* SCC registers */
|
||||
UINT32 intMask; /* interrupt acknowledge mask */
|
||||
} SCC_ETHER_DEV;
|
||||
|
||||
#else /* default: use CPU32 definitions */
|
||||
|
||||
#define SCC_ETHER_DEV SCC_DEV
|
||||
#define CPM_DPR_SCC1(baseAddr) M360_DPR_SCC1 (baseAddr)
|
||||
#define CPM_GSMR_L1(baseAddr) M360_CPM_GSMR_L1 (baseAddr)
|
||||
#define CPM_CIMR_SCC4 CPIC_CIXR_SCC4
|
||||
#define CPM_CIMR(baseAddr) M360_CPM_CIMR (baseAddr)
|
||||
#define CPM_CISR(baseAddr) M360_CPM_CISR (baseAddr)
|
||||
#define CPM_CPCR(baseAddr) M360_CPM_CR (baseAddr)
|
||||
#define END_OBJ_STRING "MC68EN360 QUICC Enhanced Network Driver"
|
||||
#define MOT_DEV_NAME "qu"
|
||||
#define MOT_DEV_NAME_LEN 3
|
||||
|
||||
#endif /* CPU == PPC32 || PPC860 */
|
||||
|
||||
/* bsp-specific routine to include */
|
||||
|
||||
#if ((CPU == PPC32)|| (CPU == PPC860))
|
||||
|
||||
#define SYS_ENET_ADDR_GET(address) \
|
||||
if (sysCpmEnetAddrGet != NULL) \
|
||||
if (sysCpmEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR) \
|
||||
{ \
|
||||
errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS); \
|
||||
return (NULL); \
|
||||
}
|
||||
|
||||
#define SYS_ENET_ENABLE \
|
||||
if (sysCpmEnetEnable != NULL) \
|
||||
if (sysCpmEnetEnable (pDrvCtrl->unit) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#define SYS_ENET_DISABLE \
|
||||
if (sysCpmEnetDisable != NULL) \
|
||||
sysCpmEnetDisable (pDrvCtrl->unit);
|
||||
|
||||
#else /* default: use CPU32 definitions */
|
||||
|
||||
#define SYS_ENET_ADDR_GET(address) \
|
||||
if (sys360EnetAddrGet != NULL) \
|
||||
if (sys360EnetAddrGet (pDrvCtrl->unit, (address)) == ERROR) \
|
||||
{ \
|
||||
errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS); \
|
||||
return (NULL); \
|
||||
}
|
||||
|
||||
#define SYS_ENET_ENABLE \
|
||||
if (sys360EnetEnable != NULL) \
|
||||
if (sys360EnetEnable (pDrvCtrl->unit, pDrvCtrl->regBase) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#define SYS_ENET_DISABLE \
|
||||
if (sys360EnetDisable != NULL) \
|
||||
sys360EnetDisable (pDrvCtrl->unit, pDrvCtrl->regBase);
|
||||
|
||||
#endif /* CPU == PPC32 | PPC860*/
|
||||
|
||||
/* globals */
|
||||
|
||||
#if ((CPU == PPC32) || (CPU == PPC860))
|
||||
|
||||
IMPORT STATUS sysCpmEnetEnable (int unit); /* enable ctrl */
|
||||
IMPORT void sysCpmEnetDisable (int unit); /* disable ctrl */
|
||||
IMPORT STATUS sysCpmEnetAddrGet (int unit, u_char * addr); /* get enet addr */
|
||||
|
||||
#else /* default: use CPU32 prototypes */
|
||||
|
||||
IMPORT STATUS sys360EnetEnable (int unit, UINT32 regBase); /* enable ctrl */
|
||||
IMPORT void sys360EnetDisable (int unit, UINT32 regBase); /* disable ctrl */
|
||||
IMPORT STATUS sys360EnetAddrGet (int unit, u_char * addr); /* get enet addr */
|
||||
|
||||
#endif /* CPU == PPC32 || PPC860 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmotCpmEndh */
|
||||
@@ -0,0 +1,533 @@
|
||||
/* motFcc2End.h - Second Generation Motorola FCC Ethernet network interface.*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003-2009 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,02feb09,wap Complete driver rewrite (legacy maintenance)
|
||||
01j,19mar05,dlk Enhancements. Combine buffer descriptor status and length
|
||||
fields.
|
||||
01j,19aug04,mdo Clean up unused variables.
|
||||
01h,23jul04,mdo Base 6 Enhancements
|
||||
01g,15jun04,mdo Fix compiler warning with gnu compiler.
|
||||
01f,04jun04,mil Changed cacheArchXXX funcs to cacheXXX funcs.
|
||||
01e,30mar04,mdo SPR's 81336, 93209, 94561, 94562 and general cleanup.
|
||||
01d,12jan04,dat lint removal
|
||||
01c,05dec03,rcs fixed warnings for base6
|
||||
01b,13aug03,gjc Fixed SPRs #89689,#89649,#87812,#87749,90135,#86434
|
||||
01a,16jan03,gjc SPR#85164 :Second Generation Motorola FCC END header.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INCmotFccEnd2h
|
||||
#define __INCmotFccEnd2h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
IMPORT STATUS sysFccEnetAddrGet (int, UINT8 *);
|
||||
IMPORT STATUS sysFccEnetEnable (UINT32, UINT8);
|
||||
IMPORT STATUS sysFccEnetDisable (UINT32, UINT8);
|
||||
|
||||
#define MOT_FCC_INUM(pDrvCtrl) \
|
||||
(pDrvCtrl)->fccIvec
|
||||
|
||||
#define MOT_FCC_IVEC(pDrvCtrl) \
|
||||
INUM_TO_IVEC ((pDrvCtrl)->fccIvec)
|
||||
|
||||
#ifndef SYS_FCC_INT_CONNECT
|
||||
#define SYS_FCC_INT_CONNECT(pDrvCtrl, pFunc, arg, ret) \
|
||||
intConnect ((VOIDFUNCPTR*) MOT_FCC_IVEC (pDrvCtrl), \
|
||||
(pFunc), (int) (arg));
|
||||
#endif /* SYS_FCC_INT_CONNECT */
|
||||
|
||||
#ifndef SYS_FCC_INT_DISCONNECT
|
||||
#define SYS_FCC_INT_DISCONNECT(pDrvCtrl, pFunc, arg, ret)
|
||||
#endif /* SYS_FCC_INT_DISCONNECT */
|
||||
|
||||
#ifndef SYS_FCC_INT_ENABLE
|
||||
#define SYS_FCC_INT_ENABLE(pDrvCtrl, ret) \
|
||||
intEnable ((int) (MOT_FCC_INUM (pDrvCtrl)));
|
||||
#endif /* SYS_FCC_INT_ENABLE */
|
||||
|
||||
#ifndef SYS_FCC_INT_DISABLE
|
||||
#define SYS_FCC_INT_DISABLE(pDrvCtrl, ret) \
|
||||
intDisable ((int) (MOT_FCC_INUM (pDrvCtrl)));
|
||||
#endif /* SYS_FCC_INT_DISABLE */
|
||||
|
||||
/*
|
||||
* For compatibility with older driver. The FCC_END_FUNCS
|
||||
* structure and the old user flags are not used by the
|
||||
* new driver.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is the bsp boot information structure for the Mii/Phy, Dpram
|
||||
* and misc functions. It contains bsp specific call backs for the driver.
|
||||
* A pointer to the structure is passed in the load string.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
FUNCPTR miiPhyInit; /* bsp MiiPhy init function */
|
||||
FUNCPTR miiPhyInt; /* Driver function for BSP to call */
|
||||
FUNCPTR miiPhyBitRead; /* Bit Read function */
|
||||
FUNCPTR miiPhyBitWrite; /* Bit Write function */
|
||||
FUNCPTR miiPhyDuplex; /* duplex status call back */
|
||||
FUNCPTR miiPhySpeed; /* speed status call back */
|
||||
FUNCPTR hbFail; /* heart beat fail */
|
||||
FUNCPTR intDisc; /* disconnect Function */
|
||||
FUNCPTR dpramFree;
|
||||
FUNCPTR dpramFccMalloc;
|
||||
FUNCPTR dpramFccFree;
|
||||
FUNCPTR reserved[4]; /* future use */
|
||||
} FCC_END_FUNCS;
|
||||
|
||||
/*
|
||||
* user flags: full duplex mode, loopback mode, serial interface etc.
|
||||
* the user may configure some of this options according to his needs
|
||||
* by setting the related bits in the <userFlags> field of the load string.
|
||||
*/
|
||||
|
||||
#define MOT_FCC_USR_PHY_NO_AN 0x00000001 /* do not auto-negotiate */
|
||||
#define MOT_FCC_USR_PHY_TBL 0x00000002 /* use negotiation table */
|
||||
#define MOT_FCC_USR_PHY_NO_FD 0x00000004 /* do not use full duplex */
|
||||
#define MOT_FCC_USR_PHY_NO_100 0x00000008 /* do not use 100Mbit speed */
|
||||
#define MOT_FCC_USR_PHY_NO_HD 0x00000010 /* do not use half duplex */
|
||||
#define MOT_FCC_USR_PHY_NO_10 0x00000020 /* do not use 10Mbit speed */
|
||||
#define MOT_FCC_USR_PHY_MON 0x00000040 /* use PHY Monitor */
|
||||
#define MOT_FCC_USR_PHY_ISO 0x00000100 /* isolate a PHY */
|
||||
#define MOT_FCC_USR_RMON 0x00000200 /* enable RMON support */
|
||||
#define MOT_FCC_USR_LOOP 0x00000400 /* external loopback mode */
|
||||
/* only use it for testing */
|
||||
#define MOT_FCC_USR_HBC 0x00000800 /* perform heartbeat control */
|
||||
#define MOT_FCC_USR_BUF_LBUS 0x00001000 /* buffers are on the local bus */
|
||||
#define MOT_FCC_USR_BD_LBUS 0x00002000 /* BDs are on the local bus */
|
||||
#define MOT_FCC_USR_NO_ZCOPY 0x00004000 /* inhibit zcopy mode */
|
||||
|
||||
/* required if bufs are on local bus, optional otherwise */
|
||||
#define MOT_FCC_USR_DPRAM_ALOC 0x00008000 /* Using DPRAM auto allocation */
|
||||
/* allow snooping of memory operations */
|
||||
#define MOT_FCC_USR_SNOOP_ENABLE 0x00010000 /* Enable snooping from FCC */
|
||||
|
||||
#ifndef BSP_VERSION
|
||||
|
||||
#define FCC_CLSIZE 1600
|
||||
#define FCC_NAME "motfcc"
|
||||
#define FCC_TIMEOUT 10000
|
||||
#define FCC_INTRS \
|
||||
(M8260_FEM_ETH_BSY|M8260_FEM_ETH_RXF|M8260_FEM_ETH_RXC| \
|
||||
M8260_FEM_ETH_TXB|M8260_FEM_ETH_TXC|M8260_FEM_ETH_TXE)
|
||||
|
||||
#define FCC_RXINTRS (M8260_FEM_ETH_BSY|M8260_FEM_ETH_RXF|M8260_FEM_ETH_RXC)
|
||||
#define FCC_TXINTRS (M8260_FEM_ETH_TXB|M8260_FEM_ETH_TXC|M8260_FEM_ETH_TXE)
|
||||
|
||||
#define FCC_ADJ(x) m_adj(x, 18)
|
||||
#define FCC_INC_DESC(x, y) (x) = (((x) + 1) % y)
|
||||
#define FCC_MAXFRAG 16
|
||||
#define FCC_MAX_RX 16
|
||||
|
||||
#define FCC_RX_DESC_CNT 32
|
||||
#define FCC_TX_DESC_CNT 32
|
||||
|
||||
#define ETHER_ADDR_LEN 6
|
||||
#define ETHER_CRC_LEN 4
|
||||
|
||||
typedef struct endNetPool
|
||||
{
|
||||
NET_POOL pool;
|
||||
void * pMblkMemArea;
|
||||
void * pClMemArea;
|
||||
} END_NET_POOL;
|
||||
|
||||
#define fccEndPoolTupleFree(x) netMblkClChainFree(x)
|
||||
#define fccEndPoolTupleGet(x) \
|
||||
netTupleGet((x), (x)->clTbl[0]->clSize, M_DONTWAIT, MT_DATA, 0)
|
||||
|
||||
#define FCC_PRAM 0
|
||||
#define FCC_IRAM 1
|
||||
|
||||
#define IFM_ETHER 0x00000020
|
||||
#define IFM_10_T 3 /* 10BaseT - RJ45 */
|
||||
#define IFM_10_2 4 /* 10Base2 - Thinnet */
|
||||
#define IFM_10_5 5 /* 10Base5 - AUI */
|
||||
#define IFM_100_TX 6 /* 100BaseTX - RJ45 */
|
||||
#define IFM_100_FX 7 /* 100BaseFX - Fiber */
|
||||
#define IFM_100_T4 8 /* 100BaseT4 - 4 pair cat 3 */
|
||||
#define IFM_100_VG 9 /* 100VG-AnyLAN */
|
||||
#define IFM_100_T2 10 /* 100BaseT2 */
|
||||
#define IFM_1000_SX 11 /* 1000BaseSX - multi-mode fiber */
|
||||
#define IFM_10_STP 12 /* 10BaseT over shielded TP */
|
||||
#define IFM_10_FL 13 /* 10BaseFL - Fiber */
|
||||
#define IFM_1000_LX 14 /* 1000baseLX - single-mode fiber */
|
||||
#define IFM_1000_CX 15 /* 1000baseCX - 150ohm STP */
|
||||
#define IFM_1000_T 16 /* 1000baseT - 4 pair cat 5 */
|
||||
#define IFM_HPNA_1 17 /* HomePNA 1.0 (1Mb/s) */
|
||||
|
||||
/*
|
||||
* Shared media sub-types
|
||||
*/
|
||||
#define IFM_AUTO 0 /* Autoselect best media */
|
||||
#define IFM_MANUAL 1 /* Jumper/dipswitch selects media */
|
||||
#define IFM_NONE 2 /* Deselect all media */
|
||||
|
||||
/*
|
||||
* Shared options
|
||||
*/
|
||||
#define IFM_FDX 0x00100000 /* Force full duplex */
|
||||
#define IFM_HDX 0x00200000 /* Force half duplex */
|
||||
#define IFM_FLAG0 0x01000000 /* Driver defined flag */
|
||||
#define IFM_FLAG1 0x02000000 /* Driver defined flag */
|
||||
#define IFM_FLAG2 0x04000000 /* Driver defined flag */
|
||||
#define IFM_LOOP 0x08000000 /* Put hardware in loopback */
|
||||
|
||||
/*
|
||||
* Masks
|
||||
*/
|
||||
#define IFM_NMASK 0x000000e0 /* Network type */
|
||||
#define IFM_TMASK 0x0000001f /* Media sub-type */
|
||||
#define IFM_IMASK 0xf0000000 /* Instance */
|
||||
#define IFM_ISHIFT 28 /* Instance shift */
|
||||
#define IFM_OMASK 0x0000ff00 /* Type specific options */
|
||||
#define IFM_MMASK 0x00070000 /* Mode */
|
||||
#define IFM_MSHIFT 16 /* Mode shift */
|
||||
#define IFM_GMASK 0x0ff00000 /* Global options */
|
||||
|
||||
/*
|
||||
* Status bits
|
||||
*/
|
||||
#define IFM_AVALID 0x00000001 /* Active bit valid */
|
||||
#define IFM_ACTIVE 0x00000002 /* Interface attached to working net */
|
||||
|
||||
/*
|
||||
* Macros to extract various bits of information from the media word.
|
||||
*/
|
||||
#define IFM_TYPE(x) ((x) & IFM_NMASK)
|
||||
#define IFM_SUBTYPE(x) ((x) & IFM_TMASK)
|
||||
#define IFM_TYPE_OPTIONS(x) ((x) & IFM_OMASK)
|
||||
#define IFM_INST(x) (((x) & IFM_IMASK) >> IFM_ISHIFT)
|
||||
#define IFM_OPTIONS(x) ((x) & (IFM_OMASK|IFM_GMASK))
|
||||
#define IFM_MODE(x) ((x) & IFM_MMASK)
|
||||
|
||||
#define IFM_INST_MAX IFM_INST(IFM_IMASK)
|
||||
|
||||
typedef struct _FCC_MEDIA
|
||||
{
|
||||
UINT32 endMediaActive;
|
||||
UINT32 endMediaStatus;
|
||||
} FCC_MEDIA;
|
||||
|
||||
/* number of seconds to wait between link state checks */
|
||||
|
||||
#define FCC_LINKPOLL 3
|
||||
|
||||
typedef struct fcc_desc
|
||||
{
|
||||
volatile UINT16 bdSts;
|
||||
volatile UINT16 bdLen;
|
||||
volatile UINT32 bdAddr;
|
||||
} FCC_DESC;
|
||||
|
||||
/*
|
||||
* Private adapter context structure.
|
||||
*/
|
||||
|
||||
typedef struct fcc_drv_ctrl
|
||||
{
|
||||
END_OBJ fccEndObj;
|
||||
UINT32 fccImmrVal;
|
||||
int fccUnit;
|
||||
void * fccPram;
|
||||
void * fccIram;
|
||||
int fccIvec;
|
||||
|
||||
volatile BOOL fccIntPending;
|
||||
|
||||
volatile BOOL fccRxPending;
|
||||
|
||||
volatile BOOL fccTxPending;
|
||||
UINT8 fccTxCur;
|
||||
UINT8 fccTxLast;
|
||||
volatile BOOL fccTxStall;
|
||||
UINT16 fccTxThresh;
|
||||
|
||||
BOOL fccPolling;
|
||||
M_BLK_ID fccPollBuf;
|
||||
UINT16 fccIntMask;
|
||||
|
||||
UINT8 fccAddr[ETHER_ADDR_LEN];
|
||||
|
||||
FCC_DESC *fccRxDescMem;
|
||||
|
||||
FCC_DESC *fccTxDescMem;
|
||||
|
||||
M_BLK_ID fccRxMblk[FCC_RX_DESC_CNT];
|
||||
M_BLK_ID fccTxMblk[FCC_TX_DESC_CNT];
|
||||
|
||||
UINT32 fccTxProd;
|
||||
UINT32 fccTxCons;
|
||||
UINT32 fccTxFree;
|
||||
UINT32 fccRxIdx;
|
||||
|
||||
int fccNum;
|
||||
int fccPhyAddr;
|
||||
END_ERR fccLastError;
|
||||
|
||||
UINT16 fccMiiSts;
|
||||
UINT32 fccCurMedia;
|
||||
UINT32 fccCurStatus;
|
||||
WDOG_ID fccMiiWd;
|
||||
|
||||
void * fccRxDpram;
|
||||
void * fccTxDpram;
|
||||
void * fccPadDpram;
|
||||
|
||||
UINT32 fccMdioClk;
|
||||
UINT32 fccMdioData;
|
||||
|
||||
/* Compatibility with old driver. */
|
||||
BOOL intrConnect;
|
||||
} FCC_DRV_CTRL;
|
||||
|
||||
LOCAL UINT32 csr_read_4
|
||||
(
|
||||
FCC_DRV_CTRL * pDrv,
|
||||
UINT32 addr,
|
||||
int ix
|
||||
)
|
||||
{
|
||||
UINT32 data;
|
||||
if (ix == FCC_PRAM)
|
||||
data = *(UINT32 *)((UINT8 *)pDrv->fccPram + addr);
|
||||
else
|
||||
data = *(UINT32 *)((UINT8 *)pDrv->fccIram + addr);
|
||||
return (data);
|
||||
}
|
||||
|
||||
LOCAL void csr_write_4
|
||||
(
|
||||
FCC_DRV_CTRL * pDrv,
|
||||
UINT32 addr,
|
||||
int ix,
|
||||
UINT32 data
|
||||
)
|
||||
{
|
||||
UINT32 * reg;
|
||||
|
||||
if (ix == FCC_PRAM)
|
||||
reg = (UINT32 *)((UINT8 *)pDrv->fccPram + addr);
|
||||
else
|
||||
reg = (UINT32 *)((UINT8 *)pDrv->fccIram + addr);
|
||||
*reg = data;
|
||||
return;
|
||||
}
|
||||
|
||||
LOCAL UINT16 csr_read_2
|
||||
(
|
||||
FCC_DRV_CTRL * pDrv,
|
||||
UINT16 addr,
|
||||
int ix
|
||||
)
|
||||
{
|
||||
UINT16 data;
|
||||
if (ix == FCC_PRAM)
|
||||
data = *(UINT16 *)((UINT8 *)pDrv->fccPram + addr);
|
||||
else
|
||||
data = *(UINT16 *)((UINT8 *)pDrv->fccIram + addr);
|
||||
return (data);
|
||||
}
|
||||
|
||||
LOCAL void csr_write_2
|
||||
(
|
||||
FCC_DRV_CTRL * pDrv,
|
||||
UINT16 addr,
|
||||
int ix,
|
||||
UINT16 data
|
||||
)
|
||||
{
|
||||
UINT16 * reg;
|
||||
|
||||
if (ix == FCC_PRAM)
|
||||
reg = (UINT16 *)((UINT8 *)pDrv->fccPram + addr);
|
||||
else
|
||||
reg = (UINT16 *)((UINT8 *)pDrv->fccIram + addr);
|
||||
*reg = data;
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef notused
|
||||
LOCAL UINT8 csr_read_1
|
||||
(
|
||||
FCC_DRV_CTRL * pDrv,
|
||||
UINT8 addr,
|
||||
int ix
|
||||
)
|
||||
{
|
||||
UINT16 data;
|
||||
if (ix == FCC_PRAM)
|
||||
data = *(UINT8 *)((UINT8 *)pDrv->fccPram + addr);
|
||||
else
|
||||
data = *(UINT8 *)((UINT8 *)pDrv->fccIram + addr);
|
||||
return (data);
|
||||
}
|
||||
#endif
|
||||
|
||||
LOCAL void csr_write_1
|
||||
(
|
||||
FCC_DRV_CTRL * pDrv,
|
||||
UINT8 addr,
|
||||
int ix,
|
||||
UINT8 data
|
||||
)
|
||||
{
|
||||
UINT8 * reg;
|
||||
|
||||
if (ix == FCC_PRAM)
|
||||
reg = (UINT8 *)((UINT8 *)pDrv->fccPram + addr);
|
||||
else
|
||||
reg = (UINT8 *)((UINT8 *)pDrv->fccIram + addr);
|
||||
*reg = data;
|
||||
return;
|
||||
}
|
||||
|
||||
#define CSR_READ_4 csr_read_4
|
||||
#define CSR_READ_2 csr_read_2
|
||||
#define CSR_READ_1 csr_read_1
|
||||
#define CSR_WRITE_4 csr_write_4
|
||||
#define CSR_WRITE_2 csr_write_2
|
||||
#define CSR_WRITE_1 csr_write_1
|
||||
|
||||
#define CSR_SETBIT_1(pDev, offset, ix, val) \
|
||||
CSR_WRITE_1(pDev, offset, ix, CSR_READ_1(pDev, offset, ix) | (val))
|
||||
|
||||
#define CSR_CLRBIT_1(pDev, offset, ix, val) \
|
||||
CSR_WRITE_1(pDev, offset, CSR_READ_1(pDev, offset, ix) & ~(val))
|
||||
|
||||
#define CSR_SETBIT_2(pDev, offset, ix, val) \
|
||||
CSR_WRITE_2(pDev, offset, ix, CSR_READ_2(pDev, offset, ix) | (val))
|
||||
|
||||
#define CSR_CLRBIT_2(pDev, offset, ix, val) \
|
||||
CSR_WRITE_2(pDev, offset, ix, CSR_READ_2(pDev, offset, ix) & ~(val))
|
||||
|
||||
#define CSR_SETBIT_4(pDev, offset, ix, val) \
|
||||
CSR_WRITE_4(pDev, offset, ix, CSR_READ_4(pDev, offset, ix) | (val))
|
||||
|
||||
#define CSR_CLRBIT_4(pDev, offset, ix, val) \
|
||||
CSR_WRITE_4(pDev, offset, ix, CSR_READ_4(pDev, offset, ix) & ~(val))
|
||||
|
||||
/* Most boards use port C, pins 9/10 for MDIO. */
|
||||
|
||||
#define FCC_PC10 (0x00200000)
|
||||
#define FCC_PC9 (0x00400000)
|
||||
|
||||
/* The ADS8272 uses port C, pins 18/19 */
|
||||
|
||||
#define FCC_PC19 (0x00001000)
|
||||
#define FCC_PC18 (0x00002000)
|
||||
|
||||
#define MII_CLK_DIR_OUT *M8260_IOP_PCDIR(pDrvCtrl->fccImmrVal) |= (pDrvCtrl->fccMdioClk)
|
||||
#define MII_CLK_DIR_IN *M8260_IOP_PCDIR(pDrvCtrl->fccImmrVal) &= ~(pDrvCtrl->fccMdioClk)
|
||||
|
||||
#define MII_CLK_HIGH *M8260_IOP_PCDAT(pDrvCtrl->fccImmrVal) |= (pDrvCtrl->fccMdioClk)
|
||||
#define MII_CLK_LOW *M8260_IOP_PCDAT(pDrvCtrl->fccImmrVal) &= ~(pDrvCtrl->fccMdioClk)
|
||||
|
||||
#define MII_DATA_DIR_OUT *M8260_IOP_PCDIR(pDrvCtrl->fccImmrVal) |= (pDrvCtrl->fccMdioData)
|
||||
#define MII_DATA_DIR_IN *M8260_IOP_PCDIR(pDrvCtrl->fccImmrVal) &= ~(pDrvCtrl->fccMdioData)
|
||||
|
||||
#define MII_DATA_HIGH *M8260_IOP_PCDAT(pDrvCtrl->fccImmrVal) |= (pDrvCtrl->fccMdioData)
|
||||
#define MII_DATA_LOW *M8260_IOP_PCDAT(pDrvCtrl->fccImmrVal) &= ~(pDrvCtrl->fccMdioData)
|
||||
#define MII_DATA_GET *M8260_IOP_PCDAT(pDrvCtrl->fccImmrVal) & (pDrvCtrl->fccMdioData)
|
||||
|
||||
#define IDR2_OUILSB 0xfc00 /* OUI LSB */
|
||||
#define IDR2_MODEL 0x03f0 /* vendor model */
|
||||
#define IDR2_REV 0x000f /* vendor revision */
|
||||
|
||||
#define MII_OUI(id1, id2) (((id1) << 6) | ((id2) >> 10))
|
||||
#define MII_MODEL(id2) (((id2) & IDR2_MODEL) >> 4)
|
||||
#define MII_REV(id2) ((id2) & IDR2_REV)
|
||||
|
||||
#define MII_OUI_8260ATM 0x0004de
|
||||
#define MII_MODEL_8260ATM 0x000e
|
||||
|
||||
#define LXT_CR 16
|
||||
|
||||
#define LXT_CR_FORCELNK 0x4000 /* force link pass */
|
||||
#define LXT_CR_TXDIS 0x2000 /* disable transmit */
|
||||
#define LXT_CR_SCRAM 0x1000 /* bypass scrambler/descrambler */
|
||||
#define LXT_CR_JABDIS 0x0400 /* disable jabber detection */
|
||||
#define LXT_CR_SQE 0x0200 /* enable heartbeat */
|
||||
#define LXT_CR_TPLOOPDIS 0x0100 /* disable loopback in half-duplex */
|
||||
#define LXT_CR_CRS 0x0080 /* CRS select */
|
||||
#define LXT_CR_PREAMBLE 0x0020 /* preamble enable */
|
||||
#define LXT_CR_ALTNP 0x0002 /* alternate next-page feature */
|
||||
|
||||
#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
|
||||
#define MII_MODEL_BROADCOM_BCM5221 0x001e
|
||||
|
||||
/* Auxiliary control/status register */
|
||||
|
||||
#define BMT_ACSR 24
|
||||
|
||||
#define BMT_ACSR_JABBER_DIS 0x8000 /* jabber disable */
|
||||
#define BMT_ACSR_FLINK 0x4000 /* force 10baseT link pass */
|
||||
#define BMT_ACSR_TXPWR 0x0100 /* 10Mbps tx power: 0 = low, 1 = hi */
|
||||
#define BMT_ACSR_HSQ 0x0080 /* SQ high */
|
||||
#define BMT_ACSR_LSQ 0x0040 /* SQ low */
|
||||
#define BMT_ACSR_ER1 0x0020 /* edge rate 1 */
|
||||
#define BMT_ACSR_ER0 0x0010 /* edge rate 0 */
|
||||
#define BMT_ACSR_ANEG 0x0008 /* auto-negotiation activated */
|
||||
#define BMT_ACSR_F100 0x0004 /* force 100base */
|
||||
#define BMT_ACSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
|
||||
#define BMT_ACSR_FDX 0x0001 /* full-duplex */
|
||||
|
||||
#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
|
||||
#define MII_MODEL_DAVICOM_DM9161 0x0008
|
||||
#define MII_MODEL_DAVICOM_DM9161A 0x000a
|
||||
|
||||
/* Specified configuration register */
|
||||
|
||||
#define DAVICOM_SCR 16
|
||||
|
||||
#define DAVICOM_SCR_BP_4B5B 0x8000 /* bypass 4B5B encoding/decoding */
|
||||
#define DAVICOM_SCR_BP_SCRAM 0x4000 /* bypass scrambler/descrambler */
|
||||
#define DAVICOM_SCR_BP_ALIGN 0x2000 /* bypass symbol alignment */
|
||||
#define DAVICOM_SCR_BP_ADPOK 0x1000 /* bypass ADPOK */
|
||||
#define DAVICOM_SCR_REPEATER 0x0800 /* repeater mode enable */
|
||||
#define DAVICOM_SCR_TX 0x0400 /* 1 = 100baseTX, 0 = 100baseFX */
|
||||
#define DAVICOM_SCR_FEF 0x0200 /* far end fault enable */
|
||||
#define DAVICOM_SCR_RMII 0x0100 /* reduced MII enable */
|
||||
#define DAVICOM_SCR_FORCE100 0x0080 /* force good 100Mbps link */
|
||||
#define DAVICOM_SCR_SPDLED 0x0040 /* speed LED enable */
|
||||
#define DAVICOM_SCR_COLLED 0x0020 /* collision LED enable */
|
||||
#define DAVICOM_SCR_RPWREN 0x0010 /* reduced power down enable */
|
||||
#define DAVICOM_SCR_SMRST 0x0008 /* reset state machine */
|
||||
#define DAVICOM_SCR_MFPSC 0x0004 /* management preamble suppression */
|
||||
#define DAVICOM_SCR_SLEEP 0x0002 /* sleep mode */
|
||||
#define DAVICOM_SCR_RLOUT 0x0001 /* remote loopout control */
|
||||
|
||||
/* 10baseT config/status register */
|
||||
|
||||
#define DAVICOM_10BTCSR 18
|
||||
|
||||
#define DAVICOM_10BTCSR_LPEN 0x4000 /* enable link pulse transmission */
|
||||
#define DAVICOM_10BTCSR_HBE 0x2000 /* heartbeat enable */
|
||||
#define DAVICOM_10BTCSR_SQUELCH 0x1000 /* squelch enable */
|
||||
#define DAVICOM_10BTCSR_JABEN 0x0800 /* jabber detect enable */
|
||||
#define DAVICOM_10BTCSR_10BTSER 0x0400 /* 0 = 10BT MII, 1 == 10BT GPSI */
|
||||
#define DAVICOM_10BTCSR_POLR 0x0001 /* polarity reversal indicator */
|
||||
|
||||
#endif /* BSP_VERSION */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCfccVxbEndh */
|
||||
@@ -0,0 +1,835 @@
|
||||
/* motFecEnd.h - Motorola FEC Ethernet network interface header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1990-2006 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/* Copyright 1999-2000 Motorola, Inc., All Rights Reserved */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01k,25jan06,wap Add handlerQueued flag
|
||||
01j,11nov05,wap Merge in coldfire FEC support
|
||||
01i,13oct05,mmi update cache routine references
|
||||
01h,05dec03,rcs fixed warnings for base6
|
||||
01g,01apr02,pmr SPR 72070: passing unit number to sysFecEnetAddrGet.
|
||||
01f,07dec01,rcs added define REV_D_3 SPR# 71420
|
||||
01e,26oct01,crg added support for proper setting of MII management interface
|
||||
speed (SPR 33812)
|
||||
01d,21nov00,rhk added define for revision D4 processor and for pin mux bit.
|
||||
01c,11jun00,ham removed reference to etherLib.
|
||||
01b,09feb99,cn changes required by performance improvement (SPR# 24883).
|
||||
01a,09nov98,cn written.
|
||||
*/
|
||||
|
||||
#ifndef __INCmotFecEndh
|
||||
#define __INCmotFecEndh
|
||||
|
||||
/* includes */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
/* revision D.3 and greater processors require special FEC initialization */
|
||||
|
||||
#define REV_D_4 0x0502
|
||||
#define REV_D_3 0x0501
|
||||
|
||||
/*
|
||||
* redefine the macro below in the bsp if you need to access the device
|
||||
* registers/descriptors in a more suitable way.
|
||||
*/
|
||||
|
||||
#ifndef MOT_FEC_LONG_WR
|
||||
#define MOT_FEC_LONG_WR(addr, value) \
|
||||
(* (addr) = ((UINT32) (value)))
|
||||
#endif /* MOT_FEC_LONG_WR */
|
||||
|
||||
#ifndef MOT_FEC_WORD_WR
|
||||
#define MOT_FEC_WORD_WR(addr, value) \
|
||||
(* (addr) = ((UINT16) (value)))
|
||||
#endif /* MOT_FEC_WORD_WR */
|
||||
|
||||
#ifndef MOT_FEC_BYTE_WR
|
||||
#define MOT_FEC_BYTE_WR(addr, value) \
|
||||
(* (addr) = ((UINT8) (value)))
|
||||
#endif /* MOT_FEC_BYTE_WR */
|
||||
|
||||
#ifndef MOT_FEC_LONG_RD
|
||||
#define MOT_FEC_LONG_RD(addr, value) \
|
||||
((value) = (* (UINT32 *) (addr)))
|
||||
#endif /* MOT_FEC_LONG_RD */
|
||||
|
||||
#ifndef MOT_FEC_WORD_RD
|
||||
#define MOT_FEC_WORD_RD(addr, value) \
|
||||
((value) = (* (UINT16 *) (addr)))
|
||||
#endif /* MOT_FEC_WORD_RD */
|
||||
|
||||
#ifndef MOT_FEC_BYTE_RD
|
||||
#define MOT_FEC_BYTE_RD(addr, value) \
|
||||
((value) = (* (UINT8 *) (addr)))
|
||||
#endif /* MOT_FEC_BYTE_RD */
|
||||
|
||||
/*
|
||||
* Default macro definitions for BSP interface.
|
||||
* These macros can be redefined in a wrapper file, to generate
|
||||
* a new module with an optimized interface.
|
||||
*/
|
||||
|
||||
#ifndef SYS_FEC_INT_CONNECT
|
||||
#define SYS_FEC_INT_CONNECT(pDrvCtrl, pFunc, arg, ret) \
|
||||
{ \
|
||||
IMPORT STATUS intConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int); \
|
||||
ret = OK; \
|
||||
\
|
||||
if (MOT_FEC_VECTOR (pDrvCtrl) && (!(pDrvCtrl->intrConnect))) \
|
||||
{ \
|
||||
pDrvCtrl->intrConnect = TRUE; \
|
||||
ret = (intConnect) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)), \
|
||||
(pFunc), (int) (arg)); \
|
||||
} \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_CONNECT */
|
||||
|
||||
#ifndef SYS_FEC_INT_DISCONNECT
|
||||
#define SYS_FEC_INT_DISCONNECT(pDrvCtrl, pFunc, arg, ret) \
|
||||
{ \
|
||||
ret = OK; \
|
||||
\
|
||||
if (MOT_FEC_VECTOR (pDrvCtrl) && (motFecIntDisc != NULL)) \
|
||||
{ \
|
||||
pDrvCtrl->intrConnect = FALSE; \
|
||||
ret = (*motFecIntDisc) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)), \
|
||||
(pFunc)); \
|
||||
} \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_DISCONNECT */
|
||||
|
||||
#ifndef SYS_FEC_INT_ENABLE
|
||||
#define SYS_FEC_INT_ENABLE(pDrvCtrl, ret) \
|
||||
{ \
|
||||
IMPORT int intEnable (int); \
|
||||
ret = OK; \
|
||||
\
|
||||
if (MOT_FEC_VECTOR (pDrvCtrl)) \
|
||||
ret = intEnable ((int) (MOT_FEC_VECTOR (pDrvCtrl))); \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_ENABLE */
|
||||
|
||||
#ifndef SYS_FEC_INT_DISABLE
|
||||
#define SYS_FEC_INT_DISABLE(pDrvCtrl, ret) \
|
||||
{ \
|
||||
IMPORT int intDisable (int); \
|
||||
ret = OK; \
|
||||
\
|
||||
if (MOT_FEC_VECTOR (pDrvCtrl)) \
|
||||
ret = intDisable ((int) (MOT_FEC_VECTOR (pDrvCtrl))); \
|
||||
}
|
||||
#endif /* SYS_FEC_INT_DISABLE */
|
||||
|
||||
#define SYS_FEC_ENET_ADDR_GET(address) \
|
||||
if (sysFecEnetAddrGet != NULL) \
|
||||
if (sysFecEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR) \
|
||||
{ \
|
||||
errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS); \
|
||||
return (NULL); \
|
||||
}
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
|
||||
#define SYS_FEC_ENET_ENABLE \
|
||||
if (sysFecEnetEnable != NULL) \
|
||||
if (sysFecEnetEnable (pDrvCtrl, motFecDmaInt) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#define SYS_FEC_ENET_DISABLE \
|
||||
if (sysFecEnetDisable != NULL) \
|
||||
if (sysFecEnetDisable (pDrvCtrl, motFecDmaInt) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#else /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#define SYS_FEC_ENET_ENABLE \
|
||||
if (sysFecEnetEnable != NULL) \
|
||||
if (sysFecEnetEnable (pDrvCtrl->motCpmAddr) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#define SYS_FEC_ENET_DISABLE \
|
||||
if (sysFecEnetDisable != NULL) \
|
||||
if (sysFecEnetDisable (pDrvCtrl->motCpmAddr) == ERROR) \
|
||||
return (ERROR);
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#define MOT_FEC_DEV_NAME "motfec"
|
||||
#define MOT_FEC_DEV_NAME_LEN 7
|
||||
#define MOT_FEC_TBD_DEF_NUM 64 /* default number of TBDs */
|
||||
#define MOT_FEC_RBD_DEF_NUM 48 /* default number of RBDs */
|
||||
#define MOT_FEC_TX_CL_NUM 6 /* number of tx clusters */
|
||||
#define MOT_FEC_BD_LOAN_NUM 32 /* loaned BDs */
|
||||
#define MOT_FEC_TBD_MAX 128 /* max number of TBDs */
|
||||
#define MOT_FEC_RBD_MAX 128 /* max number of TBDs */
|
||||
#define MOT_FEC_WAIT_MAX 0xf0000000 /* max delay after sending */
|
||||
|
||||
#define MOT_FEC_ADDR_LEN 6 /* ethernet address length */
|
||||
|
||||
/* Control/Status Registers (CSR) definitions */
|
||||
|
||||
/*
|
||||
* There are two sets of these, one for PPC and another for Coldfire.
|
||||
* Names are kept consistent whereever possible.
|
||||
*/
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
|
||||
#define MOT_FEC0_CSR_OFF 0x9000 /* CSRs offset in the MCF5475 RAM */
|
||||
#define MOT_FEC1_CSR_OFF 0x9800 /* CSRs offset in the MCF5475 RAM */
|
||||
#define MOT_FEC_CSR_OFF MOT_FEC0_CSR_OFF
|
||||
|
||||
#define MOT_FEC_EVENT_OFF 0x9004 /* interrupt event register */
|
||||
#define MOT_FEC_MASK_OFF 0x9008 /* interrupt mask register */
|
||||
#define MOT_FEC_CTRL_OFF 0x9024 /* FEC control register */
|
||||
#define MOT_FEC_MII_DATA_OFF 0x9040 /* MII data register */
|
||||
#define MOT_FEC_MII_SPEED_OFF 0x9044 /* MII speed register */
|
||||
#define MOT_FEC_MIB_CSR_OFF 0x9064 /* MII speed register */
|
||||
#define MOT_FEC_RX_CTRL_OFF 0x9084 /* rx control register */
|
||||
#define MOT_FEC_RX_HASH_OFF 0x9088 /* rx hash register */
|
||||
#define MOT_FEC_TX_CTRL_OFF 0x90c4 /* tx control register */
|
||||
#define MOT_FEC_ADDR_L_OFF 0x90e4 /* lower 32-bits of MAC address */
|
||||
#define MOT_FEC_ADDR_H_OFF 0x90e8 /* upper 16-bits of MAC address */
|
||||
#define MOT_FEC_OPC_OFF 0x90eC /* Opcode pause duration reg address */
|
||||
#define MOT_FEC_IAHASH_H_OFF 0x9118 /* upper 32-bits of IA hash table */
|
||||
#define MOT_FEC_IAHASH_L_OFF 0x911c /* lower 32-bits of IA hash table */
|
||||
#define MOT_FEC_HASH_H_OFF 0x9120 /* upper 32-bits of group address */
|
||||
#define MOT_FEC_HASH_L_OFF 0x9124 /* lower 32-bits of group address */
|
||||
#define MOT_FEC_TFWR_OFF 0x9144 /* FEC Transmit FIFO Watermark */
|
||||
#define MOT_FEC_RFDR_OFF 0x9184 /* FEC RX FIFO Data Register*/
|
||||
#define MOT_FEC_RFSR_OFF 0x9188 /* FEC RX FIFO Status Register*/
|
||||
#define MOT_FEC_RFCR_OFF 0x918C /* FEC RX FIFO Control Register*/
|
||||
#define MOT_FEC_RLRFP_OFF 0x9190 /* FEC RX FIFO Last Read Frame Ptr */
|
||||
#define MOT_FEC_RLWFP_OFF 0x9194 /* FEC RX FIFO Last Write Frame Ptr*/
|
||||
#define MOT_FEC_RFAR_OFF 0x9198 /* FEC RX FIFO Alarm Register*/
|
||||
#define MOT_FEC_RFRP_OFF 0x919C /* FEC RX FIFO Read Pointer Register*/
|
||||
#define MOT_FEC_RFWP_OFF 0x91A0 /* FEC RX FIFO Write Pointer Register*/
|
||||
#define MOT_FEC_TFDR_OFF 0x91A4 /* FEC TX FIFO Data Register*/
|
||||
#define MOT_FEC_TFSR_OFF 0x91A8 /* FEC TX FIFO Status Register*/
|
||||
#define MOT_FEC_TFCR_OFF 0x91AC /* FEC TX FIFO Control Register*/
|
||||
#define MOT_FEC_TLRFP_OFF 0x91B0 /* FEC TX FIFO Last Read Frame Ptr */
|
||||
#define MOT_FEC_TLWFP_OFF 0x91B4 /* FEC TX FIFO Last Write Frame Ptr */
|
||||
#define MOT_FEC_TFAR_OFF 0x91B8 /* FEC TX FIFO Alarm Register*/
|
||||
#define MOT_FEC_TFRP_OFF 0x91BC /* FEC TX FIFO Read Pointer Register*/
|
||||
#define MOT_FEC_TFWP_OFF 0x91C0 /* FEC TX FIFO Write Pointer Register*/
|
||||
#define MOT_FEC_FRST_OFF 0x91C4 /* FEC FIFO Reset Register*/
|
||||
#define MOT_FEC_CTCWR_OFF 0x91C8 /* FEC CRC and Transmit Frame Control Register*/
|
||||
#define MOT_FEC_RX_ACT_OFF 0x918c /* rx FIFO control register*/
|
||||
#define MOT_FEC_TX_ACT_OFF 0x91ac /* tx FIFO control register*/
|
||||
|
||||
#else /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#define MOT_FEC_CSR_OFF 0x0e00 /* CSRs offset in the 860T RAM */
|
||||
#define MOT_FEC_ADDR_L_OFF 0x0e00 /* lower 32-bits of MAC address */
|
||||
#define MOT_FEC_ADDR_H_OFF 0x0e04 /* upper 16-bits of MAC address */
|
||||
#define MOT_FEC_HASH_H_OFF 0x0e08 /* upper 32-bits of hash table */
|
||||
#define MOT_FEC_HASH_L_OFF 0x0e0c /* lower 32-bits of hash table */
|
||||
#define MOT_FEC_RX_START_OFF 0x0e10 /* rx ring start address */
|
||||
#define MOT_FEC_TX_START_OFF 0x0e14 /* tx ring start address */
|
||||
#define MOT_FEC_RX_BUF_OFF 0x0e18 /* max rx buf length */
|
||||
#define MOT_FEC_CTRL_OFF 0x0e40 /* FEC control register */
|
||||
#define MOT_FEC_EVENT_OFF 0x0e44 /* interrupt event register */
|
||||
#define MOT_FEC_MASK_OFF 0x0e48 /* interrupt mask register */
|
||||
#define MOT_FEC_VEC_OFF 0x0e4c /* interrupt level/vector register */
|
||||
#define MOT_FEC_RX_ACT_OFF 0x0e50 /* rx ring has been updated */
|
||||
#define MOT_FEC_TX_ACT_OFF 0x0e54 /* tx ring has been updated */
|
||||
#define MOT_FEC_MII_DATA_OFF 0x0e80 /* MII data register */
|
||||
#define MOT_FEC_MII_SPEED_OFF 0x0e84 /* MII speed register */
|
||||
#define MOT_FEC_RX_BOUND_OFF 0x0ecc /* rx fifo limit in the 860T ram */
|
||||
#define MOT_FEC_RX_FIFO_OFF 0x0ed0 /* rx fifo base in the 860T ram */
|
||||
#define MOT_FEC_TX_FIFO_OFF 0x0eec /* tx fifo base in the 860T ram */
|
||||
#define MOT_FEC_SDMA_OFF 0x0f34 /* function code to SDMA */
|
||||
#define MOT_FEC_RX_CTRL_OFF 0x0f44 /* rx control register */
|
||||
#define MOT_FEC_RX_FR_OFF 0x0f48 /* max rx frame length */
|
||||
#define MOT_FEC_TX_CTRL_OFF 0x0f84 /* tx control register */
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
/* Control/Status Registers (CSR) bit definitions */
|
||||
|
||||
#define MOT_FEC_RX_START_MSK 0xfffffffc /* quad-word alignment */
|
||||
/* required for rx BDs */
|
||||
|
||||
#define MOT_FEC_TX_START_MSK 0xfffffffc /* quad-word alignment */
|
||||
/* required for tx BDs */
|
||||
/* Ethernet CSR bit definitions */
|
||||
|
||||
#define MOT_FEC_ETH_PINMUX 0x00000004 /* select FEC for port D pins */
|
||||
#define MOT_FEC_ETH_EN 0x00000002 /* enable Ethernet operation */
|
||||
#define MOT_FEC_ETH_DIS 0x00000000 /* disable Ethernet operation */
|
||||
#define MOT_FEC_ETH_RES 0x00000001 /* reset the FEC */
|
||||
#define MOT_FEC_CTRL_MASK 0x00000007 /* FEC control register mask */
|
||||
|
||||
/*
|
||||
* interrupt bits definitions: these are common to both the
|
||||
* mask and the event register.
|
||||
*/
|
||||
|
||||
#define MOT_FEC_EVENT_HB 0x80000000 /* heartbeat error */
|
||||
#define MOT_FEC_EVENT_BABR 0x40000000 /* babbling rx error */
|
||||
#define MOT_FEC_EVENT_BABT 0x20000000 /* babbling tx error */
|
||||
#define MOT_FEC_EVENT_GRA 0x10000000 /* graceful stop complete */
|
||||
#define MOT_FEC_EVENT_TXF 0x08000000 /* tx frame */
|
||||
#define MOT_FEC_EVENT_TXB 0x04000000 /* tx buffer */
|
||||
#define MOT_FEC_EVENT_RXF 0x02000000 /* rx frame */
|
||||
#define MOT_FEC_EVENT_RXB 0x01000000 /* rx buffer */
|
||||
#define MOT_FEC_EVENT_MII 0x00800000 /* MII transfer */
|
||||
#define MOT_FEC_EVENT_BERR 0x00400000 /* U-bus access error */
|
||||
#define MOT_FEC_EVENT_MSK 0xffc00000 /* clear all interrupts */
|
||||
#define MOT_FEC_MASK_ALL MOT_FEC_EVENT_MSK /* mask all interrupts */
|
||||
|
||||
/* bit masks for the interrupt level/vector CSR */
|
||||
|
||||
#define MOT_FEC_LVL_MSK 0xe0000000 /* intr level */
|
||||
#define MOT_FEC_TYPE_MSK 0x0000000c /* highest pending intr */
|
||||
#define MOT_FEC_VEC_MSK 0xe000000c /* this register mask */
|
||||
#define MOT_FEC_RES_MSK 0x1ffffff3 /* reserved bits */
|
||||
#define MOT_FEC_LVL_SHIFT 0x1d /* intr level bits location */
|
||||
|
||||
/* transmit and receive active registers definitions */
|
||||
|
||||
#define MOT_FEC_TX_ACT 0x01000000 /* tx active bit */
|
||||
#define MOT_FEC_RX_ACT 0x01000000 /* rx active bit */
|
||||
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
/* bit settings for the transmit watermark register */
|
||||
#define MOT_FEC_TFWR_X_WMRK_64 0x00000000 /* watermark = 64 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_128 0x00000001 /* watermark = 128 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_192 0x00000002 /* watermark = 192 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_256 0x00000003 /* watermark = 256 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_320 0x00000004 /* watermark = 320 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_384 0x00000005 /* watermark = 384 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_448 0x00000006 /* watermark = 448 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_512 0x00000007 /* watermark = 512 bytes */
|
||||
|
||||
#define MOT_FEC_TFWR_X_WMRK_576 0x00000008 /* watermark = 576 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_640 0x00000009 /* watermark = 640 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_704 0x0000000a /* watermark = 704 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_768 0x0000000b /* watermark = 768 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_832 0x0000000c /* watermark = 832 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_896 0x0000000d /* watermark = 896 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_960 0x0000000e /* watermark = 960 bytes */
|
||||
#define MOT_FEC_TFWR_X_WMRK_1024 0x0000000f /* watermark = 1024 bytes */
|
||||
|
||||
/* bit settings for the transmit FIFO alarm register */
|
||||
#define MOT_FEC_TFAR(x) (((x)&0x000003FF)<<0)
|
||||
|
||||
/* bit settings for the transmit FIFO control register */
|
||||
#define MOT_FEC_TFCR_WFR 0x20000000
|
||||
#define MOT_FEC_TFCR_FRMEN 0x08000000
|
||||
#define MOT_FEC_TFCR_TXWMSK 0x00040000
|
||||
#define MOT_FEC_TFCR_GR(x) (((x)&0x00000007)<<24|0x00200000)
|
||||
|
||||
/* bit settings for the receive FIFO control register */
|
||||
#define MOT_FEC_RFCR_FRMEN 0x08000000
|
||||
#define MOT_FEC_RFCR_RXWMSK 0x00000000
|
||||
#define MOT_FEC_RFCR_GR(x) (((x)&0x00000007)<<24)
|
||||
|
||||
/* bit settings for the receive FIFO alarm register */
|
||||
#define MOT_FEC_RFAR(x) (((x)&0x000003FF)<<0)
|
||||
|
||||
|
||||
/* bit settings for the CTCWR register */
|
||||
#define MOT_FEC_CTCWR_TFCW 0x01000000
|
||||
#define MOT_FEC_CTCWR_CRC 0x02000000
|
||||
|
||||
#define MOT_FEC_TYPE_MSK 0x0000000c /* highest pending intr */
|
||||
#define MOT_FEC_VEC_MSK 0xe000000c /* this register mask */
|
||||
#define MOT_FEC_RES_MSK 0x1ffffff3 /* reserved bits */
|
||||
#define MOT_FEC_LVL_SHIFT 0x1d /* intr level bits location */
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
/* MII management frame CSRs */
|
||||
|
||||
#define MOT_FEC_MII_ST 0x40000000 /* start of frame delimiter */
|
||||
#define MOT_FEC_MII_OP_RD 0x20000000 /* perform a read operation */
|
||||
#define MOT_FEC_MII_OP_WR 0x10000000 /* perform a write operation */
|
||||
#define MOT_FEC_MII_ADDR_MSK 0x0f800000 /* PHY address field mask */
|
||||
#define MOT_FEC_MII_REG_MSK 0x007c0000 /* PHY register field mask */
|
||||
#define MOT_FEC_MII_TA 0x00020000 /* turnaround */
|
||||
#define MOT_FEC_MII_DATA_MSK 0x0000ffff /* PHY data field */
|
||||
#define MOT_FEC_MII_RA_SHIFT 0x12 /* mii reg address bits */
|
||||
#define MOT_FEC_MII_PA_SHIFT 0x17 /* mii PHY address bits */
|
||||
|
||||
#define MOT_FEC_MII_PRE_DIS 0x00000080 /* desable preamble */
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
|
||||
/*
|
||||
* For the Coldfire: MDCfreq = sys-freq/(4*MII_SPEED)
|
||||
* So MII_SPEED = sys-freq/(4*MDCfreq)
|
||||
* The max MDCfreq (compliant with IEEE MII spec) is 2.5 MHz
|
||||
* These are the recommended values of MII_SPEED for various
|
||||
* CPU frequencies. The calculation we use is
|
||||
* ((sysCpuSpeed()+9999999)/10000000)<<1
|
||||
*/
|
||||
|
||||
#define MOT_FEC_MII_SPEED_25 (3 << 1) /* recommended for 25Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_33 (4 << 1) /* recommended for 33Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_50 (5 << 1) /* recommended for 50Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_66 (7 << 1) /* recommended for 66Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED (((sysCpuSpeed()+9999999)/10000000)<<1)
|
||||
|
||||
IMPORT unsigned long sysCpuSpeed(void);
|
||||
|
||||
#else /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#define MOT_FEC_MII_SPEED_25 0x00000005 /* recommended for 25Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_33 0x00000007 /* recommended for 33Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_40 0x00000008 /* recommended for 40Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_50 0x0000000a /* recommended for 50Mhz CPU */
|
||||
#define MOT_FEC_MII_SPEED_SHIFT 1 /* MII_SPEED bits location */
|
||||
#define MOT_FEC_MII_CLOCK_MAX 2500000 /* max freq of MII clock (Hz) */
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#define MOT_FEC_MII_MAN_DIS 0x00000000 /* disable the MII management */
|
||||
/* interface */
|
||||
#define MOT_FEC_MII_SPEED_MSK 0xffffff81 /* speed field mask */
|
||||
|
||||
/* FIFO transmit and receive CSRs definitions */
|
||||
|
||||
#define MOT_FEC_FIFO_MSK 0x000003ff /* FIFO rx/tx/bound mask */
|
||||
|
||||
/* SDMA function code CSR */
|
||||
|
||||
#define MOT_FEC_SDMA_DATA_BE 0x60000000 /* big-endian byte-ordering */
|
||||
/* for SDMA data transfer */
|
||||
|
||||
#define MOT_FEC_SDMA_DATA_PPC 0x20000000 /* PPC byte-ordering */
|
||||
/* for SDMA data transfer */
|
||||
|
||||
#define MOT_FEC_SDMA_DATA_RES 0x00000000 /* reserved value */
|
||||
|
||||
#define MOT_FEC_SDMA_BD_BE 0x18000000 /* big-endian byte-ordering */
|
||||
/* for SDMA BDs transfer */
|
||||
|
||||
#define MOT_FEC_SDMA_BD_PPC 0x08000000 /* PPC byte-ordering */
|
||||
/* for SDMA BDs transfer */
|
||||
|
||||
|
||||
#define MOT_FEC_SDMA_BD_RES 0x00000000 /* reserved value */
|
||||
#define MOT_FEC_SDMA_FUNC_0 0x00000000 /* no function code */
|
||||
|
||||
/* receive control/hash registers bit definitions */
|
||||
|
||||
#define MOT_FEC_RX_CTRL_PROM 0x00000008 /* promiscous mode */
|
||||
#define MOT_FEC_RX_CTRL_MII 0x00000004 /* select MII interface */
|
||||
#define MOT_FEC_RX_CTRL_DRT 0x00000002 /* disable rx on transmit */
|
||||
#define MOT_FEC_RX_CTRL_LOOP 0x00000001 /* loopback mode */
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
|
||||
#define MOT_FEC_RX_FR_MSK 0x07ff0000 /* rx frame length mask */
|
||||
#define MOT_FEC_RX_FCE 0x00000020 /* rx flow control enable */
|
||||
|
||||
#else /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#define MOT_FEC_RX_FR_MSK 0x000007ff /* rx frame length mask */
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
|
||||
/* transmit control register bit definitions */
|
||||
|
||||
#define MOT_FEC_TX_CTRL_FD 0x00000004 /* enable full duplex mode */
|
||||
#define MOT_FEC_TX_CTRL_HBC 0x00000002 /* HB check is performed */
|
||||
#define MOT_FEC_TX_CTRL_GRA 0x00000001 /* issue a graceful tx stop */
|
||||
|
||||
/* rx/tx buffer descriptors definitions */
|
||||
|
||||
#define MOT_FEC_RBD_SZ 8 /* RBD size in byte */
|
||||
#define MOT_FEC_TBD_SZ 8 /* TBD size in byte */
|
||||
#define MOT_FEC_TBD_MIN 6 /* min number of TBDs */
|
||||
#define MOT_FEC_RBD_MIN 4 /* min number of RBDs */
|
||||
#define MOT_FEC_TBD_POLL_NUM 1 /* one TBD for poll operation */
|
||||
#define CL_OVERHEAD 4 /* prepended cluster overhead */
|
||||
#define CL_ALIGNMENT 4 /* cluster required alignment */
|
||||
#define MBLK_ALIGNMENT 4 /* mBlks required alignment */
|
||||
#define MOT_FEC_BD_ALIGN 0x10 /* required alignment for RBDs */
|
||||
#define MOT_FEC_MAX_PCK_SZ (ETHERMTU + SIZEOF_ETHERHEADER \
|
||||
+ ETHER_CRC_LEN)
|
||||
|
||||
#define MOT_FEC_BD_STAT_OFF 0 /* offset of the status word */
|
||||
#define MOT_FEC_BD_LEN_OFF 2 /* offset of the data length word */
|
||||
#define MOT_FEC_BD_ADDR_OFF 4 /* offset of the data pointer word */
|
||||
|
||||
/* TBD bits definitions */
|
||||
|
||||
#define MOT_FEC_TBD_RDY 0x8000 /* ready for transmission */
|
||||
#define MOT_FEC_TBD_TO1 0x4000 /* transmit ownership bit 1 */
|
||||
#define MOT_FEC_TBD_WRAP 0x2000 /* look at CSR5 for next bd */
|
||||
#define MOT_FEC_TBD_TO2 0x1000 /* transmit ownership bit 2 */
|
||||
#define MOT_FEC_TBD_INTERRUPT 0x1000 /* interrupt on transmit MCF547x/8x only */
|
||||
#define MOT_FEC_TBD_LAST 0x0800 /* last bd in this frame */
|
||||
#define MOT_FEC_TBD_CRC 0x0400 /* transmit the CRC sequence */
|
||||
#define MOT_FEC_TBD_DEF 0x0200 /* deferred transmission */
|
||||
#define MOT_FEC_TBD_HB 0x0100 /* heartbeat error */
|
||||
#define MOT_FEC_TBD_LC 0x0080 /* late collision */
|
||||
#define MOT_FEC_TBD_RL 0x0040 /* retransmission limit */
|
||||
#define MOT_FEC_TBD_UN 0x0002 /* underrun error */
|
||||
#define MOT_FEC_TBD_CSL 0x0001 /* carrier sense lost */
|
||||
#define MOT_FEC_TBD_RC_MASK 0x003c /* retransmission count mask */
|
||||
|
||||
/* RBD bits definitions */
|
||||
|
||||
#define MOT_FEC_RBD_EMPTY 0x8000 /* ready for reception */
|
||||
#define MOT_FEC_RBD_RO1 0x4000 /* receive ownership bit 1 */
|
||||
#define MOT_FEC_RBD_WRAP 0x2000 /* look at CSR4 for next bd */
|
||||
#define MOT_FEC_RBD_RO2 0x1000 /* receive ownership bit 2 */
|
||||
#define MOT_FEC_RBD_INTERRUPT 0x1000 /* interrupt on receive MCF547x/8x only */
|
||||
#define MOT_FEC_RBD_LAST 0x0800 /* last bd in this frame */
|
||||
#define MOT_FEC_RBD_RES1 0x0400 /* reserved bit 1 */
|
||||
#define MOT_FEC_RBD_RES2 0x0200 /* reserved bit 2 */
|
||||
#define MOT_FEC_RBD_MISS 0x0100 /* address recognition miss */
|
||||
#define MOT_FEC_RBD_BC 0x0080 /* broadcast frame */
|
||||
#define MOT_FEC_RBD_MC 0x0040 /* multicast frame */
|
||||
#define MOT_FEC_RBD_LG 0x0020 /* frame length violation */
|
||||
#define MOT_FEC_RBD_NO 0x0010 /* nonoctet aligned frame */
|
||||
#define MOT_FEC_RBD_SH 0x0008 /* short frame error */
|
||||
/* not supported by the 860T */
|
||||
#define MOT_FEC_RBD_CRC 0x0004 /* CRC error */
|
||||
#define MOT_FEC_RBD_OV 0x0002 /* overrun error */
|
||||
#define MOT_FEC_RBD_TR 0x0001 /* truncated frame (>2KB) */
|
||||
#define MOT_FEC_RBD_ERR (MOT_FEC_RBD_LG | \
|
||||
MOT_FEC_RBD_NO | \
|
||||
MOT_FEC_RBD_CRC | \
|
||||
MOT_FEC_RBD_OV | \
|
||||
MOT_FEC_RBD_TR)
|
||||
|
||||
#define MOT_FEC_CRC_POLY 0x04c11db7 /* CRC polynomium: */
|
||||
/* x^32 + x^26 + x^23 + */
|
||||
/* x^22 + x^16 + x^12 + */
|
||||
/* x^11 + x^10 + x^8 + */
|
||||
/* x^7 + x^5 + x^4 + */
|
||||
/* x^2 + x^1 + x^0 + */
|
||||
|
||||
|
||||
#define MOT_FEC_HASH_MASK 0x7c000000 /* bits 27-31 */
|
||||
#define MOT_FEC_HASH_SHIFT 0x1a /* to get the index */
|
||||
|
||||
/* defines related to the PHY device */
|
||||
|
||||
#define MOT_FEC_PHY_PRE_INIT 0x0001 /* PHY info initialized */
|
||||
#define MOT_FEC_PHY_AUTO 0x0010 /* enable auto-negotiation */
|
||||
#define MOT_FEC_PHY_TBL 0x0020 /* use negotiation table */
|
||||
#define MOT_FEC_PHY_100 0x0040 /* PHY may use 100Mbit speed */
|
||||
#define MOT_FEC_PHY_10 0x0080 /* PHY may use 10Mbit speed */
|
||||
#define MOT_FEC_PHY_FD 0x0100 /* PHY may use full duplex */
|
||||
#define MOT_FEC_PHY_HD 0x0200 /* PHY may use half duplex */
|
||||
#define MOT_FEC_PHY_MAX_WAIT 0x100 /* max delay before */
|
||||
#define MOT_FEC_PHY_NULL 0xff /* PHY is not present */
|
||||
#define MOT_FEC_PHY_DEF 0x0 /* PHY's logical address */
|
||||
|
||||
/* allowed PHY's speeds */
|
||||
|
||||
#define MOT_FEC_100MBS 100000000 /* bits per sec */
|
||||
#define MOT_FEC_10MBS 10000000 /* bits per sec */
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
|
||||
/* FIFO reset register bit definitions */
|
||||
|
||||
#define MOT_FEC_FIFO_SW_RST 0x02000000
|
||||
#define MOT_FEC_FIFO_RST_CTL 0x01000000
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
/*
|
||||
* user flags: full duplex mode, loopback mode, serial interface etc.
|
||||
* the user may configure some of this options according to his needs
|
||||
* by setting the related bits in the <userFlags> field of the load string.
|
||||
*/
|
||||
|
||||
#define MOT_FEC_USR_PHY_NO_AN 0x00000001 /* do not auto-negotiate */
|
||||
#define MOT_FEC_USR_PHY_TBL 0x00000002 /* use negotiation table */
|
||||
#define MOT_FEC_USR_PHY_NO_FD 0x00000004 /* do not use full duplex */
|
||||
#define MOT_FEC_USR_PHY_NO_100 0x00000008 /* do not use 100Mbit speed */
|
||||
#define MOT_FEC_USR_PHY_NO_HD 0x00000010 /* do not use half duplex */
|
||||
#define MOT_FEC_USR_PHY_NO_10 0x00000020 /* do not use 10Mbit speed */
|
||||
#define MOT_FEC_USR_PHY_ISO 0x00000100 /* isolate a PHY */
|
||||
#define MOT_FEC_USR_SER 0x00000200 /* 7-wire serial interface */
|
||||
#define MOT_FEC_USR_LOOP 0x00000400 /* loopback mode */
|
||||
/* only use it for testing */
|
||||
#define MOT_FEC_USR_HBC 0x00000080 /* perform heartbeat control */
|
||||
|
||||
#define MOT_FEC_TBD_OK 0x1 /* the TBD is a good one */
|
||||
#define MOT_FEC_TBD_BUSY 0x2 /* the TBD has not been used */
|
||||
#define MOT_FEC_TBD_ERROR 0x4 /* the TBD is errored */
|
||||
|
||||
#define PKT_TYPE_MULTI 0x1 /* packet with a multicast address */
|
||||
#define PKT_TYPE_UNI 0x2 /* packet with a unicast address */
|
||||
#define PKT_TYPE_NONE 0x4 /* address type is not meaningful */
|
||||
|
||||
#define BUF_TYPE_CL 0x1 /* this's a cluster pointer */
|
||||
#define BUF_TYPE_MBLK 0x2 /* this's a mblk pointer */
|
||||
|
||||
/* frame descriptors definitions */
|
||||
|
||||
typedef char * MOT_FEC_BD_ID;
|
||||
typedef MOT_FEC_BD_ID MOT_FEC_TBD_ID;
|
||||
typedef MOT_FEC_BD_ID MOT_FEC_RBD_ID;
|
||||
|
||||
/* MII definitions */
|
||||
|
||||
#ifndef ETHER_CRC_LEN
|
||||
#define ETHER_CRC_LEN 0x4 /* CRC length in bytes */
|
||||
#endif
|
||||
#define MII_MAX_PHY_NUM 0x20 /* max number of attached PHYs */
|
||||
|
||||
#define MII_CTRL_REG 0x0 /* Control Register */
|
||||
#define MII_STAT_REG 0x1 /* Status Register */
|
||||
#define MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
|
||||
#define MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
|
||||
#define MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
|
||||
/* Advertisement Register */
|
||||
#define MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
|
||||
/* partner ability Register */
|
||||
#define MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
|
||||
/* Expansion Register */
|
||||
#define MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
|
||||
/* next-page transmit Register */
|
||||
|
||||
/* MII control register bit */
|
||||
|
||||
#define MII_CR_COLL_TEST 0x0080 /* collision test */
|
||||
#define MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
|
||||
#define MII_CR_RESTART 0x0200 /* restart auto negotiation */
|
||||
#define MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
|
||||
#define MII_CR_POWER_DOWN 0x0800 /* power down */
|
||||
#define MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
|
||||
#define MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
|
||||
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
#define MII_CR_NORM_EN 0x0000 /* just enable the PHY */
|
||||
|
||||
/* MII Status register bit definitions */
|
||||
|
||||
#define MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
|
||||
#define MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
|
||||
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
|
||||
#define MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
|
||||
#define MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
|
||||
#define MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
|
||||
#define MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
|
||||
#define MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
|
||||
#define MII_SR_T4 0x8000 /* T4 capable */
|
||||
|
||||
/* MII Link Code word bit definitions */
|
||||
|
||||
#define MII_BP_FAULT 0x2000 /* remote fault */
|
||||
#define MII_BP_ACK 0x4000 /* acknowledge */
|
||||
#define MII_BP_NP 0x8000 /* nexp page is supported */
|
||||
|
||||
/* MII Next Page bit definitions */
|
||||
|
||||
#define MII_NP_TOGGLE 0x0800 /* toggle bit */
|
||||
#define MII_NP_ACK2 0x1000 /* acknowledge two */
|
||||
#define MII_NP_MSG 0x2000 /* message page */
|
||||
#define MII_NP_ACK1 0x4000 /* acknowledge one */
|
||||
#define MII_NP_NP 0x8000 /* nexp page will follow */
|
||||
|
||||
/* MII Expansion Register bit definitions */
|
||||
|
||||
#define MII_EXP_FAULT 0x0010 /* parallel detection fault */
|
||||
#define MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
|
||||
#define MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
|
||||
#define MII_EXP_PR 0x0002 /* full page received */
|
||||
#define MII_EXP_PRT_AN 0x0001 /* link partner auto negotiation able */
|
||||
|
||||
/* technology ability field bit definitions */
|
||||
|
||||
#define MII_TECH_10BASE_T 0x0020 /* 10Base-T */
|
||||
#define MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
|
||||
#define MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
|
||||
#define MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
|
||||
#define MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
|
||||
#define MII_TECH_MASK 0x1fe0 /* technology abilities mask */
|
||||
|
||||
#define MII_AN_FAIL 0x10 /* auto-negotiation fail */
|
||||
#define MII_STAT_FAIL 0x20 /* errors in the status register */
|
||||
#define MOT_FEC_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
|
||||
/*
|
||||
* DMA Task Priorities
|
||||
*/
|
||||
#define FEC0RX_DMA_PRI 5
|
||||
#define FEC1RX_DMA_PRI 5
|
||||
#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
|
||||
#define FEC0TX_DMA_PRI 6
|
||||
#define FEC1TX_DMA_PRI 6
|
||||
#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
|
||||
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
|
||||
#ifndef BSP_VERSION
|
||||
/*
|
||||
* this table may be customized by the user in configNet.h
|
||||
*/
|
||||
|
||||
IMPORT INT16 motFecPhyAnOrderTbl [];
|
||||
|
||||
/*
|
||||
* the table below is used to translate user settings
|
||||
* into MII-standard values for technology abilities.
|
||||
*/
|
||||
|
||||
LOCAL UINT16 miiAnLookupTbl [] = {
|
||||
MII_TECH_10BASE_T,
|
||||
MII_TECH_10BASE_FD,
|
||||
MII_TECH_100BASE_TX,
|
||||
MII_TECH_100BASE_TX_FD,
|
||||
MII_TECH_100BASE_T4
|
||||
};
|
||||
|
||||
LOCAL UINT16 miiCrLookupTbl [] = {
|
||||
MII_CR_NORM_EN,
|
||||
MII_CR_FDX,
|
||||
MII_CR_100,
|
||||
(MII_CR_100 | MII_CR_FDX),
|
||||
(MII_CR_100 | MII_CR_FDX)
|
||||
};
|
||||
#endif
|
||||
|
||||
typedef struct mii_regs
|
||||
{
|
||||
UINT16 phyStatus; /* PHY's status register */
|
||||
UINT16 phyCtrl; /* PHY's control register */
|
||||
UINT16 phyId1; /* PHY's identifier field 1 */
|
||||
UINT16 phyId2; /* PHY's identifier field 2 */
|
||||
UINT16 phyAds; /* PHY's advertisement register */
|
||||
UINT16 phyPrtn; /* PHY's partner register */
|
||||
UINT16 phyExp; /* PHY's expansion register */
|
||||
UINT16 phyNext; /* PHY's next paget transmit register */
|
||||
} MII_REGS;
|
||||
|
||||
typedef struct phy_info
|
||||
{
|
||||
MII_REGS miiRegs; /* PHY registers */
|
||||
UINT8 phyAddr; /* address of the PHY to be used */
|
||||
UINT8 isoPhyAddr; /* address of a PHY to isolate */
|
||||
UINT32 phyFlags; /* some flags */
|
||||
UINT32 phySpeed; /* 10/100 Mbit/sec */
|
||||
UINT32 phyMode; /* half/full duplex mode */
|
||||
UINT32 phyDefMode; /* default operating mode */
|
||||
} PHY_INFO;
|
||||
|
||||
typedef struct mot_fec_tbd_list
|
||||
{
|
||||
UINT16 fragNum;
|
||||
UINT16 pktType;
|
||||
UCHAR * pBuf;
|
||||
UINT16 bufType;
|
||||
struct mot_fec_tbd_list * pNext;
|
||||
MOT_FEC_TBD_ID pTbd;
|
||||
} MOT_FEC_TBD_LIST;
|
||||
|
||||
typedef MOT_FEC_TBD_LIST * MOT_FEC_TBD_LIST_ID;
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct drv_ctrl
|
||||
{
|
||||
END_OBJ endObj; /* base class */
|
||||
int unit; /* unit number */
|
||||
UINT32 motCpmAddr; /* internal RAM base address */
|
||||
int ivec; /* interrupt vector number */
|
||||
int ilevel; /* interrupt level */
|
||||
UINT32 fifoTxBase; /* address of Tx FIFO in internal RAM */
|
||||
UINT32 fifoRxBase; /* address of Rx FIFO in internal RAM */
|
||||
char * pBufBase; /* FEC memory pool base */
|
||||
ULONG bufSize; /* FEC memory pool size */
|
||||
UINT16 rbdNum; /* number of RBDs */
|
||||
MOT_FEC_RBD_ID rbdBase; /* RBD ring */
|
||||
UINT16 rbdIndex; /* RBD index */
|
||||
UINT16 tbdNum; /* number of TBDs */
|
||||
MOT_FEC_TBD_ID tbdBase; /* TBD ring */
|
||||
UINT16 tbdIndex; /* TBD index */
|
||||
UINT16 usedTbdIndex; /* used TBD index */
|
||||
UINT16 cleanTbdNum; /* number of clean TBDs */
|
||||
BOOL txStall; /* tx handler stalled - no Tbd */
|
||||
MOT_FEC_TBD_LIST * pTbdList [MOT_FEC_TBD_MAX];
|
||||
/* list of TBDs */
|
||||
ULONG userFlags; /* some user flags */
|
||||
INT8 flags; /* driver state */
|
||||
BOOL loaded; /* interface has been loaded */
|
||||
BOOL intrConnect; /* interrupt has been connected */
|
||||
UINT32 intMask; /* interrupt mask register */
|
||||
UCHAR * pTxPollBuf; /* cluster pointer for poll mode */
|
||||
UCHAR * rxBuf[MOT_FEC_RBD_MAX];
|
||||
/* array of pointers to clusters */
|
||||
SEM_ID miiSem; /* synch semaphore for mii frames */
|
||||
SEM_ID graSem; /* synch semaphore for graceful */
|
||||
/* transmit command */
|
||||
char * pClBlkArea; /* cluster block pointer */
|
||||
UINT32 clBlkSize; /* clusters block memory size */
|
||||
char * pMBlkArea; /* mBlock area pointer */
|
||||
UINT32 mBlkSize; /* mBlocks area memory size */
|
||||
CACHE_FUNCS bdCacheFuncs; /* cache descriptor */
|
||||
CACHE_FUNCS bufCacheFuncs; /* cache descriptor */
|
||||
CL_POOL_ID pClPoolId; /* cluster pool identifier */
|
||||
PHY_INFO *phyInfo; /* info on a MII-compliant PHY */
|
||||
UINT32 clockSpeed; /* clock speed (Hz) for MII_SPEED */
|
||||
BOOL handlerQueued;
|
||||
} DRV_CTRL;
|
||||
|
||||
/*
|
||||
* this cache functions descriptors is used to flush/invalidate
|
||||
* the FEC's data buffers. They are set to the system's cache
|
||||
* flush and invalidate routine. This will allow proper operation
|
||||
* of the driver if data cache are turned on.
|
||||
*/
|
||||
|
||||
IMPORT STATUS cacheInvalidate (CACHE_TYPE, void *, size_t);
|
||||
|
||||
IMPORT STATUS cacheFlush (CACHE_TYPE, void *, size_t);
|
||||
|
||||
#ifndef BSP_VERSION
|
||||
LOCAL CACHE_FUNCS motFecBufCacheFuncs;
|
||||
LOCAL FUNCPTR motFecBufInvRtn = cacheInvalidate;
|
||||
LOCAL FUNCPTR motFecBufFlushRtn = cacheFlush;
|
||||
FUNCPTR motFecIntDisc = NULL; /* assign a proper disc routine */
|
||||
#endif
|
||||
|
||||
#if (CPU_FAMILY == COLDFIRE)
|
||||
IMPORT STATUS sysFecEnetAddrGet (UINT32 unit, UCHAR * address);
|
||||
IMPORT STATUS sysFecEnetEnable (DRV_CTRL *pDrvCtrl, VOIDFUNCPTR isr);
|
||||
IMPORT STATUS sysFecEnetDisable (DRV_CTRL *pDrvCtrl, VOIDFUNCPTR isr);
|
||||
IMPORT void sysFecEnetTxResume (DRV_CTRL *pDrvCtrl);
|
||||
IMPORT void sysFecEnetRxResume (DRV_CTRL *pDrvCtrl);
|
||||
#define MOT_FEC_RX_BUF_SZ 2048
|
||||
#else /* CPU_FAMILY == COLDFIRE */
|
||||
IMPORT STATUS sysFecEnetAddrGet (UINT32 motCmpAddr, UCHAR * address);
|
||||
IMPORT STATUS sysFecEnetEnable (UINT32 motCmpAddr);
|
||||
IMPORT STATUS sysFecEnetDisable (UINT32 motCmpAddr);
|
||||
#endif /* CPU_FAMILY == COLDFIRE */
|
||||
IMPORT FUNCPTR _func_motFecPhyInit;
|
||||
IMPORT FUNCPTR _func_motFecHbFail;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmotFecEndh */
|
||||
|
||||
@@ -0,0 +1,768 @@
|
||||
/* motTsecEnd.h - Motorola TSEC Ethernet network interface.*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003-2009 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01r,05feb09,wap Complete driver rewrite (legacy maintenance)
|
||||
01q,22mar07,dlk Remove references to netJobInfo.
|
||||
01p,06mar06,dlk Initialize the RXIC register.
|
||||
01o,26jun05,dlk Replace netJobAdd() with jobQueuePost().
|
||||
01j,24mar05,dtr Changes from code review.
|
||||
01i,31jan05,dtr Decouple from interrupt controller.
|
||||
01h,23nov04,rcs Fixed SPR 104568 - fails large pings when attached to a
|
||||
gigabit switch
|
||||
01g,22oct04,dtr Added Interrupt coalescing defines. Changed some defaults
|
||||
for increased performance.SPR 102536
|
||||
01f,22jul04,rcs Added PHY Access definitions
|
||||
01e,21jun04,mil Changed cacheArchXXX funcs to cacheXXX funcs.
|
||||
01d,27apr04,mdo Latest updates for B6 build
|
||||
01c,13apr04,mil Fixed location of header file.
|
||||
01c,26mar04,rcs Fixed SPR 95432
|
||||
01b,12feb04,rcs Adjusted default settings
|
||||
01b,04feb04,mil Fixed problem if compiled with GNU.
|
||||
01a,10mar03,gjc Motorola TSEC Ethernet.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __INCmotTsecEndh
|
||||
#define __INCmotTsecEndh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef BSP_VERSION
|
||||
|
||||
#define TSEC_IEVENT 0x010
|
||||
#define TSEC_IMASK 0x014
|
||||
#define TSEC_EDIS 0x018
|
||||
#define TSEC_ECNTRL 0x020
|
||||
#define TSEC_MINFLR 0x024
|
||||
#define TSEC_PTV 0x028
|
||||
#define TSEC_DMACTRL 0x02C
|
||||
#define TSEC_TBIPA 0x030
|
||||
#define TSEC_FIFO_PAUSE_CTRL 0x04C
|
||||
#define TSEC_FIFO_TX_THR 0x08C
|
||||
#define TSEC_FIFO_STRV 0x098
|
||||
#define TSEC_FIFO_STRV_SHUT 0x09C
|
||||
#define TSEC_TCTRL 0x100
|
||||
#define TSEC_TSTAT 0x104
|
||||
#define TSEC_TBDLEN 0x10C
|
||||
#define TSEC_TXIC 0x110
|
||||
#define TSEC_CTBPTR 0x124
|
||||
#define TSEC_TBPTR 0x184
|
||||
#define TSEC_TBASE 0x204
|
||||
#define TSEC_OSTBD 0x2b0
|
||||
#define TSEC_OSTBDP 0x2b4
|
||||
#define TSEC_RCTRL 0x300
|
||||
#define TSEC_RSTAT 0x304
|
||||
#define TSEC_RBDLEN 0x30C
|
||||
#define TSEC_RXIC 0x310
|
||||
#define TSEC_CRBPTR 0x324
|
||||
#define TSEC_MRBLR 0x340
|
||||
#define TSEC_RBPTR 0x384
|
||||
#define TSEC_RBASE 0x404
|
||||
#define TSEC_MACCFG1 0x500
|
||||
#define TSEC_MACCFG2 0x504
|
||||
#define TSEC_IPGIFG 0x508
|
||||
#define TSEC_HAFDUP 0x50C
|
||||
#define TSEC_MAXFRM 0x510
|
||||
#define TSEC_MIIMCFG 0x520
|
||||
#define TSEC_MIIMCOM 0x524
|
||||
#define TSEC_MIIMADD 0x528
|
||||
#define TSEC_MIIMCON 0x52C
|
||||
#define TSEC_MIIMSTAT 0x530
|
||||
#define TSEC_MIIMIND 0x534
|
||||
#define TSEC_IFSTAT 0x53C
|
||||
#define TSEC_PAR0 0x540
|
||||
#define TSEC_PAR1 0x544
|
||||
#define TSEC_TR64 0x680
|
||||
#define TSEC_TR127 0x684
|
||||
#define TSEC_TR255 0x688
|
||||
#define TSEC_TR511 0x68C
|
||||
#define TSEC_TR1K 0x690
|
||||
#define TSEC_TRMAX 0x694
|
||||
#define TSEC_TRMGV 0x698
|
||||
#define TSEC_RBYT 0x69C
|
||||
#define TSEC_RPKT 0x6A0
|
||||
#define TSEC_RFCS 0x6A4
|
||||
#define TSEC_RMCA 0x6A8
|
||||
#define TSEC_RBCA 0x6AC
|
||||
#define TSEC_RXCF 0x6B0
|
||||
#define TSEC_RXPF 0x6B4
|
||||
#define TSEC_RXUO 0x6B8
|
||||
#define TSEC_RALN 0x6BC
|
||||
#define TSEC_RFLR 0x6C0
|
||||
#define TSEC_RCDE 0x6C4
|
||||
#define TSEC_RCSE 0x6C8
|
||||
#define TSEC_RUND 0x6CC
|
||||
#define TSEC_ROVR 0x6D0
|
||||
#define TSEC_RFRG 0x6D4
|
||||
#define TSEC_RJBR 0x6D8
|
||||
#define TSEC_RDRP 0x6DC
|
||||
#define TSEC_TBYT 0x6E0
|
||||
#define TSEC_TPKT 0x6E4
|
||||
#define TSEC_TMCA 0x6E8
|
||||
#define TSEC_TBCA 0x6EC
|
||||
#define TSEC_TXPF 0x6F0
|
||||
#define TSEC_TDFR 0x6F4
|
||||
#define TSEC_TEDF 0x6F8
|
||||
#define TSEC_TSCL 0x6FC
|
||||
#define TSEC_TMCL 0x700
|
||||
#define TSEC_TLCL 0x704
|
||||
#define TSEC_TXCL 0x708
|
||||
#define TSEC_TNCL 0x70C
|
||||
#define TSEC_TDRP 0x714
|
||||
#define TSEC_TJBR 0x718
|
||||
#define TSEC_TFCS 0x71C
|
||||
#define TSEC_TXCF 0x720
|
||||
#define TSEC_TOVR 0x724
|
||||
#define TSEC_TUND 0x728
|
||||
#define TSEC_TFRG 0x72C
|
||||
#define TSEC_CAR1 0x730
|
||||
#define TSEC_CAR2 0x734
|
||||
#define TSEC_CAM1 0x738
|
||||
#define TSEC_CAM2 0x73C
|
||||
#define TSEC_IADDR0 0x800
|
||||
#define TSEC_IADDR1 0x804
|
||||
#define TSEC_IADDR2 0x808
|
||||
#define TSEC_IADDR3 0x80C
|
||||
#define TSEC_IADDR4 0x810
|
||||
#define TSEC_IADDR5 0x814
|
||||
#define TSEC_IADDR6 0x818
|
||||
#define TSEC_IADDR7 0x81C
|
||||
#define TSEC_GADDR0 0x880
|
||||
#define TSEC_GADDR1 0x884
|
||||
#define TSEC_GADDR2 0x888
|
||||
#define TSEC_GADDR3 0x88C
|
||||
#define TSEC_GADDR4 0x890
|
||||
#define TSEC_GADDR5 0x894
|
||||
#define TSEC_GADDR6 0x898
|
||||
#define TSEC_GADDR7 0x89C
|
||||
#define TSEC_ATTR 0xBF8
|
||||
#define TSEC_ATTRELI 0xBFC
|
||||
|
||||
/* IEVENT and IMASK Register definitions */
|
||||
|
||||
#define TSEC_IEVENT_BABR 0x80000000 /* giant frame RXed */
|
||||
#define TSEC_IEVENT_RXC 0x40000000 /* pause frame RXed */
|
||||
#define TSEC_IEVENT_BSY 0x20000000 /* RX overrun */
|
||||
#define TSEC_IEVENT_EBERR 0x10000000 /* eth bus error */
|
||||
#define TSEC_IEVENT_MSRO 0x04000000 /* stats oflow */
|
||||
#define TSEC_IEVENT_GTSC 0x02000000 /* graceful TX stop done */
|
||||
#define TSEC_IEVENT_BABT 0x01000000 /* giant frame TXed */
|
||||
#define TSEC_IEVENT_TXC 0x00800000 /* pause frame TXed */
|
||||
#define TSEC_IEVENT_TXE 0x00400000 /* TX error */
|
||||
#define TSEC_IEVENT_TXB 0x00200000 /* TX descriptor updated */
|
||||
#define TSEC_IEVENT_TXF 0x00100000 /* TX frame completed */
|
||||
#define TSEC_IEVENT_LC 0x00040000 /* late collision */
|
||||
#define TSEC_IEVENT_CRL 0x00020000 /* excess collision */
|
||||
#define TSEC_IEVENT_XFUN 0x00010000 /* TX underrun */
|
||||
#define TSEC_IEVENT_RXB 0x00008000 /* RX descriptor updated */
|
||||
#define TSEC_IEVENT_MMRD 0x00000400 /* MDIO read, 8349 only */
|
||||
#define TSEC_IEVENT_MMWR 0x00000200 /* MDIO write, 8349 only */
|
||||
#define TSEC_IEVENT_GRSC 0x00000100 /* graceful RX stop done */
|
||||
#define TSEC_IEVENT_RXF 0x00000080 /* RX frame completed */
|
||||
|
||||
/*
|
||||
* Error event disable register. Note that with the IMASK
|
||||
* register, setting a bit enables the interrupt, whereas with
|
||||
* this register, setting a bit disables the interrupt.
|
||||
*/
|
||||
|
||||
#define TSEC_EDIS_BSYDIS 0x20000000
|
||||
#define TSEC_EDIS_EBERRDIS 0x10000000
|
||||
#define TSEC_EDIS_TXEDIS 0x00400000
|
||||
#define TSEC_EDIS_LCDIS 0x00040000
|
||||
#define TSEC_EDIS_CRLDIS 0x00020000
|
||||
#define TSEC_EDIS_XFUNDIS 0x00010000
|
||||
|
||||
/* Ethernet Control Register */
|
||||
|
||||
#define TSEC_ECNTRL_CLRCNT 0x00004000 /* zero status counters */
|
||||
#define TSEC_ECNTRL_AUTOZ 0x00002000 /* zero counter on read */
|
||||
#define TSEC_ECNTRL_STEN 0x00001000 /* status enable */
|
||||
#define TSEC_ECNTRL_GMIIM 0x00000040 /* GMII mode (strap) */
|
||||
#define TSEC_ECNTRL_TBIM 0x00000020 /* TBI mode (strap) */
|
||||
#define TSEC_ECNTRL_RPM 0x00000010 /* reduced pin mode 1000 */
|
||||
#define TSEC_ECNTRL_R100M 0x00000008 /* 0 = R10, 1 == R100 */
|
||||
#define TSEC_ECNTRL_RMM 0x00000004 /* reduced pin mode 10/100*/
|
||||
|
||||
/* Pause time value register */
|
||||
|
||||
#define TSEC_PTV_PT 0x0000FFFF /* pause time value */
|
||||
#define TSEC_PTV_PTE 0xFFFF0000 /* extended pause control */
|
||||
|
||||
/* DMA control register */
|
||||
|
||||
#define TSEC_DMACTRL_TDSEN 0x00000080 /* TX data snoop */
|
||||
#define TSEC_DMACTRL_TBDSEN 0x00000040 /* TX bd snoop */
|
||||
#define TSEC_DMACTRL_GRS 0x00000010 /* graceful RX stop */
|
||||
#define TSEC_DMACTRL_GTS 0x00000008 /* graceful TX stop */
|
||||
#define TSEC_DMACTRL_TOD 0x00000004 /* TX on demand */
|
||||
#define TSEC_DMACTRL_WWR 0x00000002 /* write with response */
|
||||
#define TSEC_DMACTRL_WOP 0x00000001 /* wait or poll */
|
||||
|
||||
/* Transmit control register */
|
||||
|
||||
#define TSEC_TCTRL_THDF 0x00000800 /* half duplex flow ctl */
|
||||
#define TSEC_TCTRL_RFC_PAUSE 0x00000010 /* received pause frame */
|
||||
#define TSEC_TCTRL_TFC_PAUSE 0x00000008 /* send pause frame */
|
||||
|
||||
/*
|
||||
* Transmit status register
|
||||
* The THLT bit will be set whenever the TX DMA engine encounters
|
||||
* an error condition, including when it runs out of ready descriptors
|
||||
* to process. The transmitter is resumed by clearing the bit (i.e.
|
||||
* writing 0 to this register).
|
||||
*/
|
||||
|
||||
#define TSEC_TSTAT_THLT 0x80000000 /* TX halted / resume */
|
||||
|
||||
/* Transmit interrupt coalescing register */
|
||||
|
||||
#define TSEC_TXIC_ICEN 0x80000000 /* TX coal enable */
|
||||
#define TSEC_TXIC_ICFCT 0x1FE00000 /* frame count thresh */
|
||||
#define TSEC_TXIC_ICTT 0x0000FFFF /* timer thresh */
|
||||
|
||||
/* Receive control register */
|
||||
|
||||
#define TSEC_RCTRL_BC_REJ 0x00000010 /* reject broadcasts */
|
||||
#define TSEC_RCTRL_PROM 0x00000008 /* promisc mode */
|
||||
#define TSEC_RCTRL_RSF 0x00000004 /* receive short frames */
|
||||
|
||||
/*
|
||||
* Receive status register
|
||||
* Like the TSTAT register, the QHLT bit indicates the RX DMA engine
|
||||
* has stalled due to running out of descriptors, or encountering an
|
||||
* error. The bit must be cleared to resume the RX engine.
|
||||
*/
|
||||
|
||||
#define TSEC_RSTAT_QHLT 0x00800000 /* RX halted / resume */
|
||||
|
||||
/* Receive interrupt coalescing register */
|
||||
|
||||
#define TSEC_RXIC_ICEN 0x80000000 /* RX coal enable */
|
||||
#define TSEC_RXIC_ICFCT 0x1FE00000 /* frame count thresh */
|
||||
#define TSEC_RXIC_ICTT 0x0000FFFF /* timer thresh */
|
||||
|
||||
#define TSEC_COAL_FRAMES(x) ((x) & 0xFF) << 21
|
||||
#define TSEC_COAL_TIMER(x) ((x) & 0xFFFF)
|
||||
|
||||
/* MAC configuration 1 register */
|
||||
|
||||
#define TSEC_MACCFG1_SOFT_RESET 0x80000000 /* Reset the entire MAC */
|
||||
#define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset RX mac control */
|
||||
#define TSEC_MACCFG1_RESET_TX_MC 0x00040000 /* Reset TX mac control */
|
||||
#define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset RX function */
|
||||
#define TSEC_MACCFG1_RESET_TX_FUN 0x00010000 /* Reset TX function */
|
||||
#define TSEC_MACCFG1_LOOPBACK 0x00000100 /* MAC loopback mode */
|
||||
#define TSEC_MACCFG1_RX_FLOW 0x00000020 /* enable RX flow control */
|
||||
#define TSEC_MACCFG1_TX_FLOW 0x00000010 /* enable TX flow control */
|
||||
#define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* RX sync'ed */
|
||||
#define TSEC_MACCFG1_RX_EN 0x00000004 /* RX enable */
|
||||
#define TSEC_MACCFG1_SYNCD_TX_EN 0x00000002 /* TX sync'ed */
|
||||
#define TSEC_MACCFG1_TX_EN 0x00000001 /* TX enable */
|
||||
|
||||
|
||||
/* MAC configuration 2 register */
|
||||
|
||||
#define TSEC_MACCFG2_IF_MODE_MASK 0x00000003
|
||||
#define TSEC_MACCFG2_IF_MODE_MII 0x00000001
|
||||
#define TSEC_MACCFG2_IF_MODE_GMII_TBI 0x00000002
|
||||
|
||||
#define TSEC_MACCFG2_PREAMBLE_LEN 0x0000F000
|
||||
#define TSEC_MACCFG2_IF_MODE 0x00000300
|
||||
#define TSEC_MACCFG2_HUGE_FRAME 0x00000020
|
||||
#define TSEC_MACCFG2_LENGTH_CHECK 0x00000010
|
||||
#define TSEC_MACCFG2_PADCRC 0x00000004
|
||||
#define TSEC_MACCFG2_CRC_EN 0x00000002
|
||||
#define TSEC_MACCFG2_FULL_DUPLEX 0x00000001
|
||||
|
||||
#define TSEC_IFMODE_RSVD0 0x00000000
|
||||
#define TSEC_IFMODE_MII 0x00000100 /* nibble mode */
|
||||
#define TSEC_IFMODE_GMII_TBI 0x00000200 /* byte mode */
|
||||
#define TSEC_IFMODE_RSVD1 0x00000300
|
||||
|
||||
/* Interpacket gap register */
|
||||
|
||||
#define TSEC_IPGIFG_BACKTOBACK 0x0000007F
|
||||
#define TSEC_IPGIFG_MINIMUM 0x00007F00
|
||||
#define TSEC_IPGIFG_NONBACKTOBACK1 0x007F0000
|
||||
#define TSEC_IPGIFG_NONBACKTOBACK2 0x7F000000
|
||||
|
||||
/* Halfduplex register */
|
||||
|
||||
#define TSEC_HALFDUP_ALTBEB_TRUNC 0x00F00000
|
||||
#define TSEC_HALFDUP_BEB 0x00080000
|
||||
#define TSEC_HALFDUP_BPNBO 0x00040000
|
||||
#define TSEC_HALFDUP_NBO 0x00020000
|
||||
#define TSEC_HALFDUP_EXCESS_DEF 0x00010000
|
||||
#define TSEC_HALFDUP_RETRY 0x0000F000
|
||||
#define TSEC_HALFDUP_COL_WINDOW 0x0000003F
|
||||
|
||||
/* MII management configuration register */
|
||||
|
||||
#define TSEC_MIIMCFG_RESET 0x80000000
|
||||
#define TSEC_MIIMCFG_NO_PRE 0x00000010
|
||||
#define TSEC_MIIMCFG_MGMT_CLK 0x0000000F
|
||||
|
||||
#define TSEC_MIIMCFG_MCS_2 0x00000000
|
||||
#define TSEC_MIIMCFG_MCS_4 0x00000001
|
||||
#define TSEC_MIIMCFG_MCS_6 0x00000002
|
||||
#define TSEC_MIIMCFG_MCS_8 0x00000003
|
||||
#define TSEC_MIIMCFG_MCS_10 0x00000004
|
||||
#define TSEC_MIIMCFG_MCS_14 0x00000005
|
||||
#define TSEC_MIIMCFG_MCS_20 0x00000006
|
||||
#define TSEC_MIIMCFG_MCS_28 0x00000007
|
||||
|
||||
/* MII management command register */
|
||||
|
||||
#define TSEC_MIIMCOM_SCAN 0x00000002
|
||||
#define TSEC_MIIMCOM_READ 0x00000001
|
||||
|
||||
/* MII management address register */
|
||||
|
||||
#define TSEC_MIIMADD_PHYADDR 0x0000001F
|
||||
#define TSEC_MIIMADD_REGADDR 0x00001F00
|
||||
|
||||
/* MII management control register */
|
||||
|
||||
#define TSEC_MIIMCON_WRDATA 0x0000FFFF
|
||||
|
||||
/* MII management status register */
|
||||
|
||||
#define TSEC_MIIMSTAT_RDDATA 0x0000FFFF
|
||||
|
||||
/* MII management indicator register */
|
||||
|
||||
#define TSEC_MIIMIND_NOT_VALID 0x00000004
|
||||
#define TSEC_MIIMIND_SCAN 0x00000002
|
||||
#define TSEC_MIIMIND_BUSY 0x00000001
|
||||
|
||||
/* Attribute register */
|
||||
|
||||
#define TSEC_ATTR_ELCWT 0x00006000 /* data L2 cache extract */
|
||||
#define TSEC_ATTR_BDLWT 0x00000C00 /* BD L2 cache extract */
|
||||
#define TSEC_ATTR_RDSEN 0x00000080 /* RX buffer snooping */
|
||||
#define TSEC_ATTR_RBDSEN 0x00000040 /* RX descriptor snooping */
|
||||
|
||||
#define TSEC_ELCWT_NONE 0x00000000
|
||||
#define TSEC_ELCWT_RSVD 0x00002000
|
||||
#define TSEC_ELCWT_L2 0x00004000
|
||||
#define TSEC_ELCWT_L2_LOCK 0x00006000
|
||||
|
||||
#define TSEC_BDLWT_NONE 0x00000000
|
||||
#define TSEC_BDLWT_RSVD 0x00000400
|
||||
#define TSEC_BDLWT_L2 0x00000800
|
||||
#define TSEC_BDLWT_L2_LOCK 0x00000C00
|
||||
|
||||
/* Attribute extract length and index register */
|
||||
|
||||
#define TSEC_ATTRELI_EXTLEN 0x3FFF0000
|
||||
#define TSEC_ATTRELI_EXTIDX 0x00003FFF
|
||||
|
||||
#define TSEC_ATTRELI_EL(x) (((x) & 0x3FFF) << 16)
|
||||
#define TSEC_ATTRELI_EI(x) ((x) & 0x3FFF)
|
||||
|
||||
/*
|
||||
* Buffer descriptor format
|
||||
*
|
||||
* The descriptor structure is always 8 bytes. For the ETSEC, there's
|
||||
* an additional field frame descriptor field which is hidden in
|
||||
* the packet buffer, which is used for specifying additional
|
||||
* information related to checksum offload.
|
||||
*
|
||||
* The descriptor layout is much the same as it is for all of
|
||||
* Motorola/Freescale's ethernet MACs (including the TSEC, SCC
|
||||
* and CPM). There's a 16 bit status field, 16 bit length field,
|
||||
* and a 32-bit address field. Each descriptor describes a single
|
||||
* fragment. The last fragment has the 'last in frame' bit set.
|
||||
* Since there is no 'next' pointer, descriptors are allocated
|
||||
* in contiguous arrays. The last descriptor in the array must
|
||||
* have the 'wrap' bit set.
|
||||
*/
|
||||
|
||||
typedef struct tsecDesc
|
||||
{
|
||||
volatile UINT16 bdSts;
|
||||
volatile UINT16 bdLen;
|
||||
volatile UINT32 bdAddr;
|
||||
} TSEC_DESC;
|
||||
|
||||
/* Transmit descriptor status bits */
|
||||
|
||||
#define TSEC_TBD_R 0x8000 /* owner, 0 == host, 1 == chip */
|
||||
#define TSEC_TBD_PADCRC 0x4000 /* autopad and append CRC */
|
||||
#define TSEC_TBD_W 0x2000 /* wrap, last descriptor in ring */
|
||||
#define TSEC_TBD_I 0x1000 /* interrupt after processing is done */
|
||||
#define TSEC_TBD_L 0x0800 /* last descriptor in frame */
|
||||
#define TSEC_TBD_TC 0x0400 /* append CRC */
|
||||
#define TSEC_TBD_DEF 0x0200 /* excess deferral condition */
|
||||
#define TSEC_TBD_TO1 0x0100 /* software scratch bit */
|
||||
#define TSEC_TBD_HFE_LC 0x0080 /* huge frame, or late collision */
|
||||
#define TSEC_TBD_RL 0x0040 /* retry limit exceeded */
|
||||
#define TSEC_TBD_RC 0x003C /* retry count */
|
||||
#define TSEC_TBD_UN 0x0002 /* TX underrun */
|
||||
#define TSEC_TBD_TR 0x0001 /* packet truncated */
|
||||
|
||||
/* Receive descriptor status bits */
|
||||
|
||||
#define TSEC_RBD_E 0x8000 /* owner, 0 == host, 1 == chip */
|
||||
#define TSEC_RBD_RO1 0x4000 /* software scratch bit */
|
||||
#define TSEC_RBD_W 0x2000 /* wrap, last descriptor in ring */
|
||||
#define TSEC_RBD_I 0x1000 /* interrupt after processing is done */
|
||||
#define TSEC_RBD_L 0x0800 /* last descriptor in frame */
|
||||
#define TSEC_RBD_F 0x0400 /* first descriptor in frame */
|
||||
#define TSEC_RBD_M 0x0200 /* filter miss */
|
||||
#define TSEC_RBD_BC 0x0080 /* broadcast frame */
|
||||
#define TSEC_RBD_MC 0x0040 /* multicast frame */
|
||||
#define TSEC_RBD_LG 0x0020 /* giant frame error */
|
||||
#define TSEC_RBD_NO 0x0010 /* alignment error */
|
||||
#define TSEC_RBD_SH 0x0008 /* runt frame error */
|
||||
#define TSEC_RBD_CR 0x0004 /* CRC error */
|
||||
#define TSEC_RBD_OV 0x0002 /* FIFO overrun */
|
||||
#define TSEC_RBD_TR 0x0001 /* packet truncated */
|
||||
|
||||
#define TSEC_RX_DESC_CNT 128
|
||||
#define TSEC_TX_DESC_CNT 128
|
||||
|
||||
/*#define TSEC_INC_DESC(x, y) (x) = (((x) + 1) % y)*/
|
||||
#define TSEC_INC_DESC(x, y) (x) = ((x + 1) & (y - 1))
|
||||
#define TSEC_MAXFRAG 16
|
||||
#define TSEC_MAX_RX 16
|
||||
|
||||
#define TSEC_MTU 1500
|
||||
#define TSEC_JUMBO_MTU 9000
|
||||
#define TSEC_CLSIZE 1600
|
||||
#define TSEC_JUMBO_CLSIZE 9056
|
||||
|
||||
#define TSEC_BOUND (_CACHE_ALIGN_SIZE - 1)
|
||||
#define TSEC_ALIGN(x) \
|
||||
(char *)(((UINT32)(x) + (TSEC_BOUND)) & ~(TSEC_BOUND))
|
||||
|
||||
#define TSEC_ADJ(x) \
|
||||
(x)->m_data = TSEC_ALIGN((x)->m_data)
|
||||
|
||||
#define TSEC_NAME "mottsec"
|
||||
#define TSEC_TIMEOUT 10000
|
||||
#define TSEC_INTRS (TSEC_RXINTRS|TSEC_TXINTRS|TSEC_ERRINTRS)
|
||||
#define TSEC_RXINTRS (/*TSEC_IEVENT_RXB|*/TSEC_IEVENT_RXF|TSEC_IEVENT_RXC)
|
||||
#define TSEC_TXINTRS (/*TSEC_IEVENT_TXB|*/TSEC_IEVENT_TXF|TSEC_IEVENT_TXC)
|
||||
#define TSEC_ERRINTRS (TSEC_IEVENT_XFUN|TSEC_IEVENT_EBERR|TSEC_IEVENT_BSY)
|
||||
|
||||
#define ETHER_CRC_LEN 4
|
||||
#define ETHER_CRC_POLY_BE 0x04c11db6
|
||||
|
||||
#ifndef MII_SR_EXT_STS
|
||||
#define MII_SR_EXT_STS 0x0100 /* extended sts in reg 15 */
|
||||
#endif
|
||||
|
||||
#ifndef MII_CR_1000
|
||||
#define MII_CR_1000 0x0040 /* 1 = 1000mb when
|
||||
MII_CR_100 is also 1 */
|
||||
#endif
|
||||
|
||||
#define bswap16(x) ((LSB(x) << 8) | MSB(x))
|
||||
#define bswap32(x) LONGSWAP((UINT32)(x))
|
||||
#define bswap64(x) /* not yet */
|
||||
|
||||
typedef struct endNetPool
|
||||
{
|
||||
NET_POOL pool;
|
||||
void * pMblkMemArea;
|
||||
void * pClMemArea;
|
||||
} END_NET_POOL;
|
||||
|
||||
#define tsecEndPoolTupleFree(x) netMblkClChainFree(x)
|
||||
#define tsecEndPoolTupleGet(x) \
|
||||
netTupleGet((x), (x)->clTbl[0]->clSize, M_DONTWAIT, MT_DATA, 0)
|
||||
|
||||
#define IFM_ETHER 0x00000020
|
||||
#define IFM_10_T 3 /* 10BaseT - RJ45 */
|
||||
#define IFM_10_2 4 /* 10Base2 - Thinnet */
|
||||
#define IFM_10_5 5 /* 10Base5 - AUI */
|
||||
#define IFM_100_TX 6 /* 100BaseTX - RJ45 */
|
||||
#define IFM_100_FX 7 /* 100BaseFX - Fiber */
|
||||
#define IFM_100_T4 8 /* 100BaseT4 - 4 pair cat 3 */
|
||||
#define IFM_100_VG 9 /* 100VG-AnyLAN */
|
||||
#define IFM_100_T2 10 /* 100BaseT2 */
|
||||
#define IFM_1000_SX 11 /* 1000BaseSX - multi-mode fiber */
|
||||
#define IFM_10_STP 12 /* 10BaseT over shielded TP */
|
||||
#define IFM_10_FL 13 /* 10BaseFL - Fiber */
|
||||
#define IFM_1000_LX 14 /* 1000baseLX - single-mode fiber */
|
||||
#define IFM_1000_CX 15 /* 1000baseCX - 150ohm STP */
|
||||
#define IFM_1000_T 16 /* 1000baseT - 4 pair cat 5 */
|
||||
#define IFM_HPNA_1 17 /* HomePNA 1.0 (1Mb/s) */
|
||||
|
||||
/*
|
||||
* Shared media sub-types
|
||||
*/
|
||||
#define IFM_AUTO 0 /* Autoselect best media */
|
||||
#define IFM_MANUAL 1 /* Jumper/dipswitch selects media */
|
||||
#define IFM_NONE 2 /* Deselect all media */
|
||||
|
||||
/*
|
||||
* Shared options
|
||||
*/
|
||||
#define IFM_FDX 0x00100000 /* Force full duplex */
|
||||
#define IFM_HDX 0x00200000 /* Force half duplex */
|
||||
#define IFM_FLAG0 0x01000000 /* Driver defined flag */
|
||||
#define IFM_FLAG1 0x02000000 /* Driver defined flag */
|
||||
#define IFM_FLAG2 0x04000000 /* Driver defined flag */
|
||||
#define IFM_LOOP 0x08000000 /* Put hardware in loopback */
|
||||
|
||||
/*
|
||||
* Masks
|
||||
*/
|
||||
#define IFM_NMASK 0x000000e0 /* Network type */
|
||||
#define IFM_TMASK 0x0000001f /* Media sub-type */
|
||||
#define IFM_IMASK 0xf0000000 /* Instance */
|
||||
#define IFM_ISHIFT 28 /* Instance shift */
|
||||
#define IFM_OMASK 0x0000ff00 /* Type specific options */
|
||||
#define IFM_MMASK 0x00070000 /* Mode */
|
||||
#define IFM_MSHIFT 16 /* Mode shift */
|
||||
#define IFM_GMASK 0x0ff00000 /* Global options */
|
||||
|
||||
/*
|
||||
* Status bits
|
||||
*/
|
||||
#define IFM_AVALID 0x00000001 /* Active bit valid */
|
||||
#define IFM_ACTIVE 0x00000002 /* Interface attached to working net */
|
||||
|
||||
/*
|
||||
* Macros to extract various bits of information from the media word.
|
||||
*/
|
||||
#define IFM_TYPE(x) ((x) & IFM_NMASK)
|
||||
#define IFM_SUBTYPE(x) ((x) & IFM_TMASK)
|
||||
#define IFM_TYPE_OPTIONS(x) ((x) & IFM_OMASK)
|
||||
#define IFM_INST(x) (((x) & IFM_IMASK) >> IFM_ISHIFT)
|
||||
#define IFM_OPTIONS(x) ((x) & (IFM_OMASK|IFM_GMASK))
|
||||
#define IFM_MODE(x) ((x) & IFM_MMASK)
|
||||
|
||||
#define IFM_INST_MAX IFM_INST(IFM_IMASK)
|
||||
|
||||
typedef struct _TSEC_END_MEDIA
|
||||
{
|
||||
UINT32 endMediaActive;
|
||||
UINT32 endMediaStatus;
|
||||
} TSEC_END_MEDIA;
|
||||
|
||||
/* number of seconds to wait between link state checks */
|
||||
|
||||
#define TSEC_LINKPOLL 2
|
||||
|
||||
/* Default interrupt vectors */
|
||||
|
||||
#define TSEC_TXINUM 25
|
||||
#define TSEC_RXINUM 26
|
||||
#define TSEC_ERRINUM 30
|
||||
|
||||
#define ETHER_ADDR_LEN 6
|
||||
|
||||
/*
|
||||
* Private adapter context structure.
|
||||
*/
|
||||
|
||||
typedef struct tsec_drv_ctrl
|
||||
{
|
||||
END_OBJ tsecEndObj;
|
||||
int tsecUnit;
|
||||
void * tsecRegBase;
|
||||
UINT32 tsecInumTx;
|
||||
UINT32 tsecInumRx;
|
||||
UINT32 tsecInumErr;
|
||||
|
||||
volatile BOOL tsecErrPending;
|
||||
|
||||
volatile BOOL tsecRxPending;
|
||||
|
||||
volatile BOOL tsecTxPending;
|
||||
UINT8 tsecTxCur;
|
||||
UINT8 tsecTxLast;
|
||||
volatile BOOL tsecTxStall;
|
||||
UINT16 tsecTxThresh;
|
||||
|
||||
BOOL tsecPolling;
|
||||
M_BLK_ID tsecPollBuf;
|
||||
UINT32 tsecIntMask;
|
||||
UINT32 tsecRxIntrs;
|
||||
UINT32 tsecTxIntrs;
|
||||
UINT32 tsecErrIntrs;
|
||||
|
||||
UINT8 tsecAddr[ETHER_ADDR_LEN];
|
||||
|
||||
UINT16 tsecMiiSts;
|
||||
WDOG_ID tsecMiiWd;
|
||||
END_ERR tsecLastError;
|
||||
UINT32 tsecCurMedia;
|
||||
UINT32 tsecCurStatus;
|
||||
struct tsec_drv_ctrl *tsecMiiDev;
|
||||
int tsecMiiPhyAddr;
|
||||
|
||||
/* DMA tags and maps. */
|
||||
|
||||
TSEC_DESC *tsecRxDesc;
|
||||
TSEC_DESC *tsecTxDesc;
|
||||
|
||||
M_BLK_ID tsecRxMblk[TSEC_RX_DESC_CNT];
|
||||
M_BLK_ID tsecTxMblk[TSEC_TX_DESC_CNT];
|
||||
|
||||
UINT32 tsecTxProd;
|
||||
UINT32 tsecTxCons;
|
||||
UINT32 tsecTxFree;
|
||||
UINT32 tsecRxIdx;
|
||||
|
||||
SEM_ID tsecDevSem;
|
||||
|
||||
UINT32 tsecErrInt;
|
||||
} TSEC_DRV_CTRL;
|
||||
|
||||
#define CSR_READ_4(pDev, addr) \
|
||||
*(volatile UINT32 *)((UINT32)pDev->tsecRegBase + addr)
|
||||
|
||||
#define CSR_WRITE_4(pDev, addr, data) \
|
||||
do { \
|
||||
volatile UINT32 *pReg = \
|
||||
(UINT32 *)((UINT32)pDev->tsecRegBase + addr); \
|
||||
*(pReg) = (UINT32)(data); \
|
||||
WRS_ASM("eieio"); \
|
||||
} while ((0))
|
||||
|
||||
#define CSR_SETBIT_4(pDev, offset, val) \
|
||||
CSR_WRITE_4(pDev, offset, CSR_READ_4(pDev, offset) | (val))
|
||||
|
||||
#define CSR_CLRBIT_4(pDev, offset, val) \
|
||||
CSR_WRITE_4(pDev, offset, CSR_READ_4(pDev, offset) & ~(val))
|
||||
|
||||
|
||||
#endif /* BSP_VERSION */
|
||||
|
||||
/* Compatibility cruft with old motTsecEnd driver */
|
||||
|
||||
/* MII/PHY PHY_DEF_MODE flags to init the phy driver */
|
||||
#define MOT_TSEC_USR_MODE_DEFAULT 0
|
||||
#define MOT_TSEC_USR_PHY_NO_AN 0x00000001 /* do not auto-negotiate */
|
||||
#define MOT_TSEC_USR_PHY_TBL 0x00000002 /* use negotiation table */
|
||||
#define MOT_TSEC_USR_PHY_NO_FD 0x00000004 /* do not use full duplex */
|
||||
#define MOT_TSEC_USR_PHY_NO_100 0x00000008 /* do not use 100Mbit speed */
|
||||
#define MOT_TSEC_USR_PHY_NO_HD 0x00000010 /* do not use half duplex */
|
||||
#define MOT_TSEC_USR_PHY_NO_10 0x00000020 /* do not use 10Mbit speed */
|
||||
#define MOT_TSEC_USR_PHY_MON 0x00000040 /* use PHY Monitor */
|
||||
#define MOT_TSEC_USR_PHY_ISO 0x00000080 /* isolate a PHY */
|
||||
|
||||
|
||||
/* ECNTRL Ethernet Control */
|
||||
#define MOT_TSEC_USR_STAT_CLEAR 0x00000100 /* init + runtime clear mstats*/
|
||||
#define MOT_TSEC_USR_STAT_AUTOZ 0x00000200 /* init */
|
||||
#define MOT_TSEC_USR_STAT_ENABLE 0x00000400 /* init */
|
||||
|
||||
/* PHY bus configuration selections */
|
||||
#define MOT_TSEC_USR_MODE_MASK 0x0003f800
|
||||
#define MOT_TSEC_USR_MODE_TBI 0x00000800
|
||||
#define MOT_TSEC_USR_MODE_RTBI 0x00001000
|
||||
#define MOT_TSEC_USR_MODE_MII 0x00002000
|
||||
#define MOT_TSEC_USR_MODE_GMII 0x00004000
|
||||
#define MOT_TSEC_USR_MODE_RGMII 0x00008000
|
||||
#define MOT_TSEC_USR_MODE_RGMII_10 0x00010000
|
||||
#define MOT_TSEC_USR_MODE_RGMII_100 0x00020000
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* function pointers for BSP and Driver call backs */
|
||||
FUNCPTR miiPhyInit; /* BSP Phy driver init callback */
|
||||
FUNCPTR miiPhyInt; /* BSP call back to process PHY status change interrupt */
|
||||
FUNCPTR miiPhyStatusGet; /* Driver call back to get duplex status */
|
||||
FUNCPTR miiPhyRead; /* BSP call back to read MII/PHY registers */
|
||||
FUNCPTR miiPhyWrite; /* BSP call back to write MII/PHY registers */
|
||||
FUNCPTR enetAddrGet; /* Driver call back to get the Ethernet address */
|
||||
FUNCPTR enetAddrSet; /* Driver call back to set the Ethernet address */
|
||||
FUNCPTR enetEnable; /* Driver call back to enable the ENET interface */
|
||||
FUNCPTR enetDisable; /* Driver call back to disable the ENET interface */
|
||||
FUNCPTR extWriteL2AllocFunc; /* Driver call back to put tx bd in L2 */
|
||||
} MOT_TSEC_FUNC_TABLE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 phyAddr; /* phy physical address */
|
||||
UINT32 phyDefMode; /* default mode */
|
||||
UINT32 phyMaxDelay; /* max delay */
|
||||
UINT32 phyDelayParm; /* poll interval if in poll mode */
|
||||
MII_AN_ORDER_TBL * phyAnOrderTbl; /* autonegotiation table */
|
||||
} MOT_TSEC_PHY_PARAMS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 autonegError; /* 0-N/A, 0 - none, 1- error */
|
||||
UINT8 duplex; /* 1 - half, 2- full */
|
||||
#define MOT_TSEC_PHY_DUPLEX_HALF (1)
|
||||
#define MOT_TSEC_PHY_DUPLEX_FULL (2)
|
||||
UINT8 speed; /* 0-N/A, 1 - 10, 2- 100, 3 -1G */
|
||||
#define MOT_TSEC_PHY_SPEED_10 (1)
|
||||
#define MOT_TSEC_PHY_SPEED_100 (2)
|
||||
#define MOT_TSEC_PHY_SPEED_1000 (3)
|
||||
UINT8 link; /* 0-N/A, 1 - down, 2- up */
|
||||
UINT8 symbolError; /* 0-N/A, 1 - none, 2- error */
|
||||
UINT8 autoNegComplete; /* 0-N/A, 1 - no, 2- completed */
|
||||
UINT8 energyDetect; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 falseCarrier; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 downShift; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 fifoError; /* 0-N/A, 1 - none, 2- error */
|
||||
UINT8 xover; /* 0-N/A, 1 - MDI, 2- MDIX */
|
||||
UINT8 polarity; /* 0-N/A, 1 - normal, 2- reversed */
|
||||
UINT8 jabber; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 pageReceived; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 cableLength; /* 0-N/A */
|
||||
UINT8 txPause; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 rxPause; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT8 farEndFault; /* 0-N/A, 1 - no, 2- detected */
|
||||
UINT32 rxErrorCntr; /* 0-N/A, number of rx errors */
|
||||
UINT32 reserved[4]; /* future use */
|
||||
} MOT_TSEC_PHY_STATUS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 *memBufPtr; /* Buffer pointer for allocated buffer space */
|
||||
UINT32 memBufSize; /* Buffer pool size */
|
||||
void *bdBasePtr; /* Descriptor Base Address */
|
||||
UINT32 bdSize; /* Descriptor Size */
|
||||
UINT32 rbdNum; /* Number of Receive Buffer Descriptors */
|
||||
UINT32 tbdNum; /* Number of Transmit Buffer Descriptors */
|
||||
UINT32 unit0TxVec;
|
||||
UINT32 unit0RxVec;
|
||||
UINT32 unit0ErrVec;
|
||||
UINT32 unit1TxVec;
|
||||
UINT32 unit1RxVec;
|
||||
UINT32 unit1ErrVec;
|
||||
} MOT_TSEC_PARAMS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 inum_tsecTx; /* Transmit Interrupt */
|
||||
UINT32 inum_tsecRx; /* Receive Interrupt */
|
||||
UINT32 inum_tsecErr; /* Error Interrupt */
|
||||
FUNCPTR inumToIvec; /* function to convert INUM to IVEC */
|
||||
FUNCPTR ivecToInum; /* function to convert IVEC to INUM */
|
||||
} MOT_TSEC_INT_CTRL;
|
||||
|
||||
#define MOT_TSEC_MAX_DEVS 2
|
||||
#define MOT_TSEC_DEV_1 0
|
||||
#define MOT_TSEC_DEV_2 1
|
||||
#define MOT_TSEC_ADRS_OFFSET_1 0x00024000
|
||||
#define MOT_TSEC_ADRS_OFFSET_2 0x00025000
|
||||
#define MOT_TSEC_DEV_NAME "mottsec"
|
||||
#define MOT_TSEC_DEV_NAME_LEN 8
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCmotTsecEndh */
|
||||
@@ -0,0 +1,200 @@
|
||||
/* ne2000End.h - Novell/Eagle 2000 network interface header */
|
||||
|
||||
/* Copyright 1984-2000, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,29apr10,pad Moved extern C statement after include statements.
|
||||
01d,02dec02,m_h PSTOP is not 0x80 on 8 bit devices (80785)
|
||||
01c,11jun00,ham removed reference to etherLib.
|
||||
01b,28may00,dat added more macros, gen clean up
|
||||
01a,16mar98,mem written, based on drv/netif/if_ene.h
|
||||
*/
|
||||
|
||||
#ifndef __INCne2000Endh
|
||||
#define __INCne2000Endh
|
||||
|
||||
#include "netinet/if_ether.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EADDR_LEN 6
|
||||
#define NE2000_BUFSIZ (ETHERMTU + SIZEOF_ETHERHEADER + EADDR_LEN)
|
||||
|
||||
/* NE 2000 on-board memory page addresses */
|
||||
|
||||
#define NE2000_CONFIG_PAGE 0x00 /* where the Ethernet address is */
|
||||
#define NE2000_EADDR_LOC 0x00 /* location within config. page */
|
||||
#define NE2000_TSTART 0x40
|
||||
#define NE2000_PSTART 0x46
|
||||
#define NE2000_PSTOP16 0x80
|
||||
#define NE2000_PSTOP8 0x60
|
||||
#define NE2000_PSTOP NE2000_PSTOP16
|
||||
|
||||
#define ENE_PAGESIZE 256
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UCHAR rstat;
|
||||
UCHAR next;
|
||||
UCHAR lowByteCnt;
|
||||
UCHAR uppByteCnt;
|
||||
} NE2000_HEADER;
|
||||
|
||||
/* NS 8390 (Ethernet LAN Controller) */
|
||||
|
||||
/* page-0, read */
|
||||
|
||||
#define ENE_CMD 0x00 /* command */
|
||||
#define ENE_TRINCRL 0x01 /* TRDMA incrementer */
|
||||
#define ENE_TRINCRH 0x02 /* TRDMA incrementer */
|
||||
#define ENE_BOUND 0x03 /* boundary page */
|
||||
#define ENE_TSTAT 0x04 /* transmit status */
|
||||
#define ENE_COLCNT 0x05 /* collision error */
|
||||
#define ENE_INTSTAT 0x07 /* interrupt status */
|
||||
#define ENE_RSTAT 0x0c /* receive status */
|
||||
#define ENE_ALICNT 0x0d /* alignment error */
|
||||
#define ENE_CRCCNT 0x0e /* crc error */
|
||||
#define ENE_MPCNT 0x0f /* missed packet */
|
||||
|
||||
/* page-0, write */
|
||||
|
||||
#define ENE_RSTART 0x01 /* receive start */
|
||||
#define ENE_RSTOP 0x02 /* receive stop */
|
||||
#define ENE_TSTART 0x04 /* transmit start */
|
||||
#define ENE_TCNTL 0x05 /* transmit counter */
|
||||
#define ENE_TCNTH 0x06 /* transmit counter */
|
||||
#define ENE_RSAR0 0x08 /* remote address */
|
||||
#define ENE_RSAR1 0x09 /* remote address */
|
||||
#define ENE_RBCR0 0x0a /* remote byte count */
|
||||
#define ENE_RBCR1 0x0b /* remote byte count */
|
||||
#define ENE_RCON 0x0c /* receive config */
|
||||
#define ENE_TCON 0x0d /* transmit config */
|
||||
#define ENE_DCON 0x0e /* data config */
|
||||
#define ENE_INTMASK 0x0f /* interrupt mask */
|
||||
|
||||
/* page-1, read and write */
|
||||
|
||||
#define ENE_STA0 0x01 /* station address */
|
||||
#define ENE_STA1 0x02 /* station address */
|
||||
#define ENE_STA2 0x03 /* station address */
|
||||
#define ENE_STA3 0x04 /* station address */
|
||||
#define ENE_STA4 0x05 /* station address */
|
||||
#define ENE_STA5 0x06 /* station address */
|
||||
#define ENE_CURR 0x07 /* current page */
|
||||
#define ENE_MAR0 0x08 /* multicast address */
|
||||
#define ENE_MAR1 0x09 /* multicast address */
|
||||
#define ENE_MAR2 0x0a /* multicast address */
|
||||
#define ENE_MAR3 0x0b /* multicast address */
|
||||
#define ENE_MAR4 0x0c /* multicast address */
|
||||
#define ENE_MAR5 0x0d /* multicast address */
|
||||
#define ENE_MAR6 0x0e /* multicast address */
|
||||
#define ENE_MAR7 0x0f /* multicast address */
|
||||
|
||||
/* page-2, read and write */
|
||||
|
||||
#define ENE_NEXT 0x05 /* next page */
|
||||
#define ENE_BLOCK 0x06 /* block address */
|
||||
#define ENE_ENH 0x07 /* enable features */
|
||||
|
||||
/* NE2000 board registers */
|
||||
|
||||
#define ENE_DATA 0x10 /* data window */
|
||||
#define ENE_RESET 0x1f /* read here to reset */
|
||||
|
||||
/* COMMAND: Command Register */
|
||||
#define CMD_PAGE2 0x80
|
||||
#define CMD_PAGE1 0x40
|
||||
#define CMD_PAGE0 0x00
|
||||
#define CMD_NODMA 0x20
|
||||
#define CMD_RWRITE 0x10
|
||||
#define CMD_RREAD 0x08
|
||||
#define CMD_TXP 0x04
|
||||
#define CMD_START 0x02
|
||||
#define CMD_STOP 0x01
|
||||
|
||||
/* RCON: Receive Configuration Register */
|
||||
#define RCON_MON 0x20
|
||||
#define RCON_PROM 0x10
|
||||
#define RCON_GROUP 0x08
|
||||
#define RCON_BROAD 0x04
|
||||
#define RCON_RUNTS 0x02
|
||||
#define RCON_SEP 0x01
|
||||
|
||||
/* TCON: Transmit Configuration Register */
|
||||
#define TCON_LB1 0x04
|
||||
#define TCON_LB0 0x02
|
||||
#define TCON_CRCN 0x01
|
||||
#define TCON_NORMAL 0x00 /* normal operation mode */
|
||||
|
||||
/* DCON: Data Configuration Register */
|
||||
#define DCON_BSIZE1 0x40
|
||||
#define DCON_BSIZE0 0x20
|
||||
#define DCON_AUTO_INIT 0x10
|
||||
#define DCON_LOOPBK_OFF 0x08
|
||||
#define DCON_LOOPBK_ON 0x00
|
||||
#define DCON_DMA_32 0x04
|
||||
#define DCON_DMA_16 0x00
|
||||
#define DCON_BIG_ENDIAN 0x02
|
||||
#define DCON_LITTLE_ENDIAN 0x00
|
||||
#define DCON_BUS16 0x01
|
||||
#define DCON_BUS_8 0x00
|
||||
|
||||
/* INTMASK: Interrupt Mask Register */
|
||||
#define IM_XDCE 0x40
|
||||
#define IM_CNTE 0x20
|
||||
#define IM_OVWE 0x10
|
||||
#define IM_TXEE 0x08
|
||||
#define IM_RXEE 0x04
|
||||
#define IM_PTXE 0x02
|
||||
#define IM_PRXE 0x01
|
||||
|
||||
/* INTSTAT: Interrupt Status Register */
|
||||
#define ISTAT_RST 0x80
|
||||
#define ISTAT_RDC 0x40 /* remote DMA complete */
|
||||
#define ISTAT_CNT 0x20
|
||||
#define ISTAT_OVW 0x10
|
||||
#define ISTAT_TXE 0x08
|
||||
#define ISTAT_RXE 0x04
|
||||
#define ISTAT_PTX 0x02
|
||||
#define ISTAT_PRX 0x01
|
||||
|
||||
/* TSTAT: Transmit Status Register */
|
||||
#define TSTAT_OWC 0x80
|
||||
#define TSTAT_CDH 0x40
|
||||
#define TSTAT_UNDER 0x20
|
||||
#define TSTAT_CRL 0x10
|
||||
#define TSTAT_ABORT 0x08
|
||||
#define TSTAT_TWC 0x04
|
||||
#define TSTAT_NDT 0x02
|
||||
#define TSTAT_PTX 0x01
|
||||
|
||||
/* RSTAT: Receive Status Register */
|
||||
#define RSTAT_DFR 0x80
|
||||
#define RSTAT_DIS 0x40
|
||||
#define RSTAT_GROUP 0x20
|
||||
#define RSTAT_MPA 0x10
|
||||
#define RSTAT_OVER 0x08
|
||||
#define RSTAT_FAE 0x04
|
||||
#define RSTAT_CRC 0x02
|
||||
#define RSTAT_PRX 0x01
|
||||
|
||||
/* ENH: Enable Features */
|
||||
#define ENH_WAIT1 0x80
|
||||
#define ENH_WAIT0 0x40
|
||||
#define ENH_SLOT1 0x10
|
||||
#define ENH_SLOT0 0x08
|
||||
|
||||
/* flags - software synchronize bit definitions */
|
||||
#define TXING 0x01
|
||||
#define RXING 0x02
|
||||
#define TXREQ 0x04
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCne2000Endh */
|
||||
@@ -0,0 +1,242 @@
|
||||
/* nicEvbEnd.h - NIC driver header (for EVB403) */
|
||||
|
||||
/* Copyright 1984-1999 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,20jan99,sut from netif/if_nicEvb.h
|
||||
*/
|
||||
|
||||
#ifndef __INCnicEvbEndh
|
||||
#define __INCnicEvbEndh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* driver flags */
|
||||
typedef UINT8 NIC_DRV_FLAG;
|
||||
|
||||
#define NIC_FLAG_POLL 0x01
|
||||
|
||||
typedef union nic_regs
|
||||
{
|
||||
u_char reg [16];
|
||||
struct
|
||||
{
|
||||
volatile u_char cr;
|
||||
volatile u_char pstart;
|
||||
volatile u_char pstop;
|
||||
volatile u_char bnry;
|
||||
volatile u_char tpsr;
|
||||
volatile u_char tbcr0;
|
||||
volatile u_char tbcr1;
|
||||
volatile u_char isr;
|
||||
volatile u_char rsar0;
|
||||
volatile u_char rsar1;
|
||||
volatile u_char rbcr0;
|
||||
volatile u_char rbcr1;
|
||||
volatile u_char rcr;
|
||||
volatile u_char tcr;
|
||||
volatile u_char dcr;
|
||||
volatile u_char imr;
|
||||
} nic_pg0;
|
||||
struct
|
||||
{
|
||||
volatile u_char cr;
|
||||
volatile u_char par0;
|
||||
volatile u_char par1;
|
||||
volatile u_char par2;
|
||||
volatile u_char par3;
|
||||
volatile u_char par4;
|
||||
volatile u_char par5;
|
||||
volatile u_char curr;
|
||||
volatile u_char mar0;
|
||||
volatile u_char mar1;
|
||||
volatile u_char mar2;
|
||||
volatile u_char mar3;
|
||||
volatile u_char mar4;
|
||||
volatile u_char mar5;
|
||||
volatile u_char mar6;
|
||||
volatile u_char mar7;
|
||||
} nic_pg1;
|
||||
} NIC_DEVICE;
|
||||
|
||||
/* Page 1 offsets IR - Internal Register */
|
||||
#define NIC_IR_CR 0x00 /* Command register */
|
||||
#define NIC_IR_PAR0 0x01 /* Phsical Address Register 0 */
|
||||
#define NIC_IR_PAR1 0x02 /* Phsical Address Register 1 */
|
||||
#define NIC_IR_PAR2 0x03 /* Phsical Address Register 2 */
|
||||
#define NIC_IR_PAR3 0x04 /* Phsical Address Register 3 */
|
||||
#define NIC_IR_PAR4 0x05 /* Phsical Address Register 4 */
|
||||
#define NIC_IR_PAR5 0x06 /* Phsical Address Register 5 */
|
||||
#define NIC_IR_CURR 0x07 /* Current Page Register */
|
||||
#define NIC_IR_MAR0 0x08 /* Multicast Address Register 0 */
|
||||
#define NIC_IR_MAR1 0x09 /* Multicast Address Register 1 */
|
||||
#define NIC_IR_MAR2 0x0a /* Multicast Address Register 2 */
|
||||
#define NIC_IR_MAR3 0x0b /* Multicast Address Register 3 */
|
||||
#define NIC_IR_MAR4 0x0c /* Multicast Address Register 4 */
|
||||
#define NIC_IR_MAR5 0x0d /* Multicast Address Register 5 */
|
||||
#define NIC_IR_MAR6 0x0e /* Multicast Address Register 6 */
|
||||
#define NIC_IR_MAR7 0x0f /* Multicast Address Register 7 */
|
||||
|
||||
#define Cr nic_pg0.cr
|
||||
#define Pstart nic_pg0.pstart
|
||||
#define Pstop nic_pg0.pstop
|
||||
#define Bnry nic_pg0.bnry
|
||||
#define Tpsr nic_pg0.tpsr
|
||||
#define Tsr nic_pg0.tpsr
|
||||
#define Tbcr0 nic_pg0.tbcr0
|
||||
#define Tbcr1 nic_pg0.tbcr1
|
||||
#define Isr nic_pg0.isr
|
||||
#define Rsar0 nic_pg0.rsar0
|
||||
#define Rsar1 nic_pg0.rsar1
|
||||
#define Rbcr0 nic_pg0.rbcr0
|
||||
#define Rbcr1 nic_pg0.rbcr1
|
||||
#define Rcr nic_pg0.rcr
|
||||
#define Rsr nic_pg0.rcr
|
||||
#define Tcr nic_pg0.tcr
|
||||
#define Dcr nic_pg0.dcr
|
||||
#define Imr nic_pg0.imr
|
||||
|
||||
#define Par0 nic_pg1.par0
|
||||
#define Par1 nic_pg1.par1
|
||||
#define Par2 nic_pg1.par2
|
||||
#define Par3 nic_pg1.par3
|
||||
#define Par4 nic_pg1.par4
|
||||
#define Par5 nic_pg1.par5
|
||||
#define Curr nic_pg1.curr
|
||||
|
||||
#define NIC_BASE 0xf4000000
|
||||
#define NIC_PORT 0xf4000010
|
||||
#define NIC_ACC 0xf4000030
|
||||
#define NIC_DMA 0xf4000020
|
||||
|
||||
#define NICRAM_BOT 0x8000
|
||||
#define NICRAM_TOP 0xFFFF
|
||||
#define NICROM_BOT 0x0000
|
||||
#define NICROM_TOP 0x001F
|
||||
#define NICROMSIZ (NICROM_TOP - NICROM_BOT)
|
||||
#define NICRAMSIZ (NICRAM_TOP - NICRAM_BOT)
|
||||
|
||||
#define PBMASK 0xc0 /* XXX */
|
||||
#define ACC_MASK 0x01 /* XXX */
|
||||
#define PACKET_SIZE 256
|
||||
|
||||
|
||||
#define PSTART 8
|
||||
#define PSTOP 32
|
||||
#define MAXXMT 10
|
||||
#define BNRY PSTART
|
||||
#define CURR PSTART+1
|
||||
#define XMTBUF 0xe100
|
||||
|
||||
/*
|
||||
* CR Register bits (SAME)
|
||||
*/
|
||||
|
||||
#define STP 0x1
|
||||
#define STA 0x2
|
||||
#define TXP 0x4
|
||||
#define RREAD 0x8
|
||||
#define RWRITE 0x10
|
||||
#define SPKT 0x18
|
||||
#define ABORT 0x20
|
||||
#define RPAGE0 0x00
|
||||
#define RPAGE1 0x40
|
||||
#define RPAGE2 0x80
|
||||
|
||||
/*
|
||||
* ISR Register (SAME)
|
||||
*/
|
||||
|
||||
#define PRX 0x1
|
||||
#define PTX 0x2
|
||||
#define RXE 0x4
|
||||
#define TXE 0x8
|
||||
#define OVW 0x10
|
||||
#define CNT 0x20
|
||||
#define RDC 0x40
|
||||
#define RST 0x80
|
||||
|
||||
/*
|
||||
* IMR(SAme)
|
||||
*/
|
||||
|
||||
#define PRXE 0x1
|
||||
#define PTXE 0x2
|
||||
#define RXEE 0x4
|
||||
#define TXEE 0x8
|
||||
#define OVWE 0x10
|
||||
#define CNTE 0x20
|
||||
#define RDCE 0x40
|
||||
|
||||
/*
|
||||
* DCR
|
||||
*/
|
||||
|
||||
#define WTS 0x1
|
||||
#define BOS 0x2
|
||||
#define LAS 0x4
|
||||
#define NOTLS 0x8
|
||||
#define DCR_ARM 0x10
|
||||
#define FIFO2 0x00
|
||||
#define FIFO4 0x20
|
||||
#define FIFO8 0x40
|
||||
#define FIFO12 0x60
|
||||
|
||||
/*
|
||||
* TCR
|
||||
*/
|
||||
|
||||
#define CRC 0x1
|
||||
#define MODE0 0x0
|
||||
#define MODE1 0x2
|
||||
#define MODE2 0x4
|
||||
#define MODE3 0x6
|
||||
#define ATD 0x8
|
||||
#define OFST 0x10
|
||||
|
||||
/*
|
||||
* TSR
|
||||
*/
|
||||
|
||||
#define TPTX 0x1
|
||||
#define COL 0x4
|
||||
#define ABT 0x8
|
||||
#define CRS 0x10
|
||||
#define FU 0x20
|
||||
#define CDH 0x40
|
||||
#define OWC 0x80
|
||||
|
||||
/*
|
||||
* RCR
|
||||
*/
|
||||
|
||||
#define SEP 0x1
|
||||
#define AR 0x2
|
||||
#define AB 0x4
|
||||
#define AM 0x8
|
||||
#define PRO 0x10
|
||||
#define MON 0x20
|
||||
|
||||
/*
|
||||
* RSR
|
||||
*/
|
||||
|
||||
#define CRCR 0x2
|
||||
#define FAE 0x4
|
||||
#define FO 0x8
|
||||
#define MPA 0x10
|
||||
#define PHY 0x20
|
||||
#define DIS 0x40
|
||||
#define DFR 0x80
|
||||
|
||||
#define MINPKTSIZE 64
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCnicEvbEndh */
|
||||
@@ -0,0 +1,189 @@
|
||||
/* ns83902End.h - NIC driver header */
|
||||
|
||||
/* Copyright 1984-2000 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01c,11apr00,zl added more register definitions
|
||||
01b,10apr00,zl renamed file to ns83902End.h, cleaned up
|
||||
01a,20jan99,zl written based on nicEvbEnd.h
|
||||
*/
|
||||
|
||||
#ifndef __INCns83902Endh
|
||||
#define __INCns83902Endh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* driver flags */
|
||||
|
||||
typedef UINT8 NS83902_DRV_FLAG;
|
||||
|
||||
#define NS83902_FLAG_POLL 0x01 /* for poll mode */
|
||||
|
||||
#define NS83902_WIDE_MASK 0x01 /* option bit 0 (LSB) */
|
||||
#define NS83902_INTERVAL_MASK 0x02 /* option bit 1 */
|
||||
#define MINPKTSIZE 64 /* Minimum packet size */
|
||||
#define NS83902_PAGE_SIZE 256 /* Page size in buffer memory */
|
||||
#define NS83902_TX_POOL_SIZE 1514 /* TX pool size */
|
||||
|
||||
/* Page 0 Internal register offsets */
|
||||
|
||||
#define NS83902_CR 0x00 /* R/W: Command Register R/W */
|
||||
#define NS83902_PSTART 0x01 /* W: Page Start Register */
|
||||
#define NS83902_CLDA0 0x01 /* R: Current Local DMA Address0 */
|
||||
#define NS83902_PSTOP 0x02 /* W: Page Stop Register */
|
||||
#define NS83902_CLDA1 0x02 /* R: Current Local DMA Address1 */
|
||||
#define NS83902_BNRY 0x03 /* R/W: Boundary Pointer Register */
|
||||
#define NS83902_TPSR 0x04 /* W: Transmit Page Start Register */
|
||||
#define NS83902_TSR 0x04 /* R: Transmit Status Register */
|
||||
#define NS83902_TBCR0 0x05 /* W: Transmit Byte Count0 Register */
|
||||
#define NS83902_NCR 0x05 /* R: Number of Collisions */
|
||||
#define NS83902_TBCR1 0x06 /* W: Transmit Byte Count1 Register */
|
||||
#define NS83902_FIFO 0x06 /* R: FIFO Register */
|
||||
#define NS83902_ISR 0x07 /* R/W: Interrup Status Register */
|
||||
#define NS83902_RSAR0 0x08 /* W: Remote Start Address0 Register */
|
||||
#define NS83902_CRDA0 0x08 /* R: Current Remote DMA Address0 Reg.*/
|
||||
#define NS83902_RSAR1 0x09 /* W: Remote Start Address1 Register */
|
||||
#define NS83902_CRDA1 0x09 /* R: Current Remote DMA Address1 Reg.*/
|
||||
#define NS83902_RBCR0 0x0A /* W: Remote Byte Count0 Register */
|
||||
#define NS83902_RBCR1 0x0B /* W: Remote Byte Count1 Register */
|
||||
#define NS83902_RCR 0x0C /* W: Receive Configuration Register */
|
||||
#define NS83902_RSR 0x0C /* R: Receive Status Register */
|
||||
#define NS83902_TCR 0x0D /* W: Transmit Configuration Register */
|
||||
#define NS83902_CNTR0 0x0D /* R: Tally Counter 0 (Frm. Alignment.*/
|
||||
#define NS83902_DCR 0x0E /* W: Data Configuration Register */
|
||||
#define NS83902_CNTR1 0x0E /* R: Tally Counter 1 (CRC) */
|
||||
#define NS83902_IMR 0x0F /* W: Interrupt Mask Register */
|
||||
#define NS83902_CNTR2 0x0F /* R: Tally Counter 1 (Missed Pkt.)*/
|
||||
|
||||
/* Page 1 Internal Register Offsets */
|
||||
|
||||
#define NS83902_CR 0x00 /* Command register */
|
||||
#define NS83902_PAR0 0x01 /* Phsical Address Register 0 */
|
||||
#define NS83902_PAR1 0x02 /* Phsical Address Register 1 */
|
||||
#define NS83902_PAR2 0x03 /* Phsical Address Register 2 */
|
||||
#define NS83902_PAR3 0x04 /* Phsical Address Register 3 */
|
||||
#define NS83902_PAR4 0x05 /* Phsical Address Register 4 */
|
||||
#define NS83902_PAR5 0x06 /* Phsical Address Register 5 */
|
||||
#define NS83902_CURR 0x07 /* Current Page Register */
|
||||
#define NS83902_MAR0 0x08 /* Multicast Address Register 0 */
|
||||
#define NS83902_MAR1 0x09 /* Multicast Address Register 1 */
|
||||
#define NS83902_MAR2 0x0a /* Multicast Address Register 2 */
|
||||
#define NS83902_MAR3 0x0b /* Multicast Address Register 3 */
|
||||
#define NS83902_MAR4 0x0c /* Multicast Address Register 4 */
|
||||
#define NS83902_MAR5 0x0d /* Multicast Address Register 5 */
|
||||
#define NS83902_MAR6 0x0e /* Multicast Address Register 6 */
|
||||
#define NS83902_MAR7 0x0f /* Multicast Address Register 7 */
|
||||
|
||||
|
||||
/*
|
||||
* Configuration Register bits
|
||||
*/
|
||||
|
||||
#define CR_STP 0x1 /* Stop */
|
||||
#define CR_STA 0x2 /* Start */
|
||||
#define CR_TXP 0x4 /* Transmit Packet command */
|
||||
#define CR_RREAD 0x8 /* Remote DMA Read command */
|
||||
#define CR_RWRITE 0x10 /* Remote DMA Write command */
|
||||
#define CR_SPKT 0x18 /* Send Packet command */
|
||||
#define CR_ABORT 0x20 /* Abort command */
|
||||
#define CR_RPAGE0 0x00 /* Register Page 0 */
|
||||
#define CR_RPAGE1 0x40 /* Register Page 1 */
|
||||
#define CR_RPAGE2 0x80 /* Register Page 2 */
|
||||
#define CR_PAGE_MASK 0xc0 /* Register Page mask */
|
||||
|
||||
/*
|
||||
* Interrupt Status Register
|
||||
*/
|
||||
|
||||
#define ISR_PRX 0x1 /* Packet Received */
|
||||
#define ISR_PTX 0x2 /* Packet Transmitted */
|
||||
#define ISR_RXE 0x4 /* Receive Error */
|
||||
#define ISR_TXE 0x8 /* Transmit Error */
|
||||
#define ISR_OVW 0x10 /* Overwrite Warning */
|
||||
#define ISR_CNT 0x20 /* Counter Overflow */
|
||||
#define ISR_RDC 0x40 /* Remote DMA complete */
|
||||
#define ISR_RST 0x80 /* Reset Status */
|
||||
|
||||
/*
|
||||
* Interrupt Mode Register
|
||||
*/
|
||||
|
||||
#define IMR_PRXE 0x1 /* Packet Received Intr. Enable */
|
||||
#define IMR_PTXE 0x2 /* Packet Transmitted Intr. Enable */
|
||||
#define IMR_RXEE 0x4 /* Receive Error Intr. Enable */
|
||||
#define IMR_TXEE 0x8 /* Transmit Error Intr. Enable */
|
||||
#define IMR_OVWE 0x10 /* Overwrite Warning Intr. Enable */
|
||||
#define IMR_CNTE 0x20 /* Counter Overflow Intr. Enable */
|
||||
#define IMR_RDCE 0x40 /* Remote DMA complete Intr. Enable */
|
||||
|
||||
/*
|
||||
* Data Configuration Register
|
||||
*/
|
||||
|
||||
#define DCR_WTS 0x1 /* Word Transfer Select */
|
||||
#define DCR_BOS 0x2 /* Byte Order Select */
|
||||
#define DCR_LAS 0x4 /* Long Address Select */
|
||||
#define DCR_NOTLS 0x8 /* Loopback Select */
|
||||
#define DCR_ARM 0x10 /* Auto-Initialize Select */
|
||||
#define DCR_FIFO2 0x00 /* Fifo Threshold 1 word /2 bytes */
|
||||
#define DCR_FIFO4 0x20 /* Fifo Threshold 2 words / 4 bytes */
|
||||
#define DCR_FIFO8 0x40 /* Fifo Threshold 4 words / 8 bytes */
|
||||
#define DCR_FIFO12 0x60 /* Fifo Threshold 6 words / 12 bytes */
|
||||
|
||||
/*
|
||||
* Transmit Configuration Register
|
||||
*/
|
||||
|
||||
#define TCR_CRC 0x1 /* Inhibit CRC */
|
||||
#define TCR_MODE0 0x0 /* Norman operation */
|
||||
#define TCR_MODE1 0x2 /* Internal NIC Module Loopback */
|
||||
#define TCR_MODE2 0x4 /* Internal ENDEC Module Loopback */
|
||||
#define TCR_MODE3 0x6 /* External Loopback */
|
||||
#define TCR_ATD 0x8 /* Auto Transmit Disable */
|
||||
#define TCR_OFST 0x10 /* Collision Offset Enable */
|
||||
|
||||
/*
|
||||
* Transmit Status Register
|
||||
*/
|
||||
|
||||
#define TSR_PTX 0x1 /* Packet transmitted */
|
||||
#define TSR_COL 0x4 /* Transmit Collided */
|
||||
#define TSR_ABT 0x8 /* Transmit Aborted */
|
||||
#define TSR_CRS 0x10 /* Carrier Sense Lost */
|
||||
#define TSR_FU 0x20 /* FIFO underrun */
|
||||
#define TSR_CDH 0x40 /* CD Heartbeat */
|
||||
#define TSR_OWC 0x80 /* Out of Window Collision */
|
||||
|
||||
/*
|
||||
* Receive Configuration Register
|
||||
*/
|
||||
|
||||
#define RCR_SEP 0x1 /* Save Errored Packets */
|
||||
#define RCR_AR 0x2 /* Accept Runt Packets */
|
||||
#define RCR_AB 0x4 /* Acept Broadcast */
|
||||
#define RCR_AM 0x8 /* Accept Multicast */
|
||||
#define RCR_PRO 0x10 /* Promiscuous Physical */
|
||||
#define RCR_MON 0x20 /* Monitor Mode */
|
||||
|
||||
/*
|
||||
* Receive Status Register
|
||||
*/
|
||||
|
||||
#define RSR_PRX 0x1 /* Packet Received Intact */
|
||||
#define RSR_CRC 0x2 /* CRC Error */
|
||||
#define RSR_FAE 0x4 /* Frame Alignment Error */
|
||||
#define RSR_FO 0x8 /* FIFO Overrun */
|
||||
#define RSR_MPA 0x10 /* Missed Packet */
|
||||
#define RSR_PHY 0x20 /* Physical/Multicast Address */
|
||||
#define RSR_DIS 0x40 /* Receiver Disabled */
|
||||
#define RSR_DFR 0x80 /* Deferring */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCns83902Endh */
|
||||
@@ -0,0 +1,52 @@
|
||||
/* simNetEndDrv.h - END style Simulator Ethernet driver header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003-2004,2008 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this
|
||||
* software may be licensed only pursuant to the terms of an applicable
|
||||
* Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01b,08feb08,elp opacified simnet_pkt type.
|
||||
01a,15apr04,elp added defines to get/set parameters.
|
||||
01a30jul03,elp written.
|
||||
*/
|
||||
|
||||
#ifndef __INCsimEndh
|
||||
#define __INCsimEndh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* SIMNET defines */
|
||||
|
||||
/* macros to get SUBNET information from vxsimnetd */
|
||||
#define SIMNET_SUBNET_MTU 1 /* get subnet mtu */
|
||||
#define SIMNET_SUBNET_PHYS_ADDRLEN 2 /* get MAC address length */
|
||||
#define SIMNET_SUBNET_BROAD_ADDRESS 3 /* get subnet bcast address */
|
||||
#define SIMNET_SUBNET_ADDRESS 4 /* get subnet address */
|
||||
#define SIMNET_SUBNET_MASK 5 /* get subnet mask */
|
||||
#define SIMNET_SUBNET_ADDRESSV6 6 /* get subnet IPv6 prefix */
|
||||
#define SIMNET_SUBNET_ADDRESSV6_LEN 7 /* get subnet IPv6 prefix len */
|
||||
#define SIMNET_SUBNET_BROADCAST 8 /* broadcast support ? */
|
||||
#define SIMNET_SUBNET_MULTICAST 9 /* multicast support ? */
|
||||
|
||||
/* macro to get/set NODE information */
|
||||
#define SIMNET_NODE_PHYS_ADDRESS 10 /* node MAC address */
|
||||
#define SIMNET_NODE_INTERRUPT 11 /* node interrupt enabled */
|
||||
#define SIMNET_NODE_PROMISCUOUS 12 /* node promiscuous */
|
||||
#define SIMNET_NODE_MULTICAST 13 /* node multicasting */
|
||||
#define SIMNET_NODE_ADDRESS 14 /* node address */
|
||||
#define SIMNET_NODE_ADDRESSV6 15 /* IPv6 node address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsimNetEndDrvh */
|
||||
|
||||
@@ -0,0 +1,254 @@
|
||||
/* smEnd.h - WRS shared memory driver header file */
|
||||
|
||||
/* Copyright 1984 - 2004, 2010 Wind River Systems, Inc. */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01n,29apr10,pad Moved extern C statement after include statements.
|
||||
01m,05oct04,jln changed EADDR_LEN to SM_EADDR_LEN (spr#102310)
|
||||
01l,06feb04,jln ported to T221 and Base6;
|
||||
add new configuration flags.
|
||||
01k,20sep01,mas added lastError to SM_END_DEV (SPR 70181)
|
||||
01j,15jun01,mas removed SM_END_CLST_SIZ, fixed SM_PACKET_ROUNDUP, added
|
||||
SM_MTU (SPR 68195)
|
||||
01i,30mar01,mas added netmask storage to SM_END_DEV struct and pre-AE
|
||||
compatibility flag (SPR 64957)
|
||||
01h,15mar01,mas added ethernet address support per IEEE-802.3 (SPR 34766)
|
||||
01g,17jun00,mas added pRxPktCnt and rxInts to SM device control structure
|
||||
01f,11jun00,ham removed reference to etherLib.
|
||||
01e,07apr00,mas moved SM common parameters to smLib.h
|
||||
01d,11feb00,mas added media support for T3
|
||||
01c,08oct99,mas smEnd componentized.
|
||||
01b,16sep99,mas removed unused macros; added IOCTL codes for callout hook
|
||||
routines smEndCopyRtn() and smEndMblkCopyRtn(); released
|
||||
(SPR 25573).
|
||||
01a,28jan99,mas written based on if_sm.h rev 01f,22sep92.
|
||||
*/
|
||||
|
||||
#ifndef __INCsmEndh
|
||||
#define __INCsmEndh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include "end.h"
|
||||
#include "m2Lib.h"
|
||||
#include "netinet/if_ether.h"
|
||||
#include "ioctl.h"
|
||||
#include "bootLib.h"
|
||||
#include "smLib.h"
|
||||
#include "smPktLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* defines */
|
||||
|
||||
/*
|
||||
* Definitions for the shared memory END State flags field
|
||||
*
|
||||
* Flag Use
|
||||
* --------------- ------------------------------------------------------
|
||||
* S_LOADED smEnd successfully loaded
|
||||
* S_CPU_ATTACHED local CPU is attached to shared memory
|
||||
* S_ARP_PUB ethernet H/W address is published to ARP table
|
||||
* S_RUNNING local CPU active in shared memory
|
||||
* S_POLLED_SM shared memory interface is operating in polled mode
|
||||
* S_POLLED_END MUX interface is operating in polled mode
|
||||
* S_RCV_TASK_ACTIVE interrupt driven receive task is active
|
||||
* S_MSTR_PRE_AE_COMPAT pre-AE master node, don't wait for address publishing
|
||||
*/
|
||||
|
||||
#define S_LOADED 0x0001
|
||||
#define S_CPU_ATTACHED 0x0002
|
||||
#define S_RUNNING 0x0004
|
||||
#define S_ARP_PUB 0x0008
|
||||
#define S_POLLED_SM 0x0010
|
||||
#define S_POLLED_END 0x0020
|
||||
#define S_RCV_TASK_ACTIVE 0x0040
|
||||
#define S_MSTR_PRE_AE_COMPAT 0x8000
|
||||
|
||||
#define SM_PARAMS_MAX 256
|
||||
|
||||
#define SM_NAME_MAX 15
|
||||
|
||||
#define SM_END_COOKIE 0xfab0fad0
|
||||
|
||||
#define SM_MIN_MBLK_NUM 0x10
|
||||
#define SM_DFLT_MBLK_NUM 0x30
|
||||
|
||||
#define SM_MIN_CLBLK_NUM 0x10
|
||||
#define SM_DFLT_CLBLK_NUM 0x20
|
||||
|
||||
#define SM_END_MIN_FBUF (1536) /* min first buffer size */
|
||||
|
||||
#define SM_PACKET_ROUNDUP(siz) \
|
||||
( \
|
||||
((((siz) + sizeof(SM_PKT_HDR)) % 16) == 0) ? 0 : \
|
||||
(16 - (((siz) + sizeof(SM_PKT_HDR)) % 16)) \
|
||||
)
|
||||
|
||||
#define SM_END_MIB2_SPEED -1
|
||||
|
||||
/* IP address length */
|
||||
|
||||
#define IPADDR_LEN 4
|
||||
|
||||
/* ethernet address length and positions */
|
||||
|
||||
#define SM_EADDR_LEN (sizeof(struct ether_addr))
|
||||
|
||||
/* maximum smEnd payload (maximum tranfer unit) */
|
||||
|
||||
#define SM_MTU(pDev) \
|
||||
((UINT)pDev->maxPktBytes - (SIZEOF_ETHERHEADER + SM_EADDR_LEN))
|
||||
|
||||
/* smEnd ethernet MAC address octet positions */
|
||||
|
||||
#define SM_ETHER_ID_FIRST (0)
|
||||
#define SM_ETHER_ID_SECOND (1)
|
||||
#define SM_ETHER_ID_THIRD (2)
|
||||
#define SM_ETHER_EUI64_FOURTH (3)
|
||||
#define SM_ETHER_EUI64_FIFTH (4)
|
||||
#define SM_ETHER_USER_OPT (SM_EADDR_LEN-3)
|
||||
#define SM_ETHER_UNIT (SM_EADDR_LEN-2)
|
||||
#define SM_ETHER_CPU (SM_EADDR_LEN-1)
|
||||
|
||||
/* configuration flag for SM end */
|
||||
|
||||
#define SMEND_SM_SEQ_ADDR 0x0001
|
||||
#define SMEND_PROXY_SERVER_FLAG 0x0002
|
||||
#define SMEND_PROXY_CLIENT_FLAG 0x0004
|
||||
#define SMEND_PROXY_DEFAULT_ADDR_FLAG 0x0008
|
||||
|
||||
/*
|
||||
* Maximum delay for initial access to sm from slave processor in ticks.
|
||||
* At 100 ticks per second, this is about 30 seconds.
|
||||
*/
|
||||
|
||||
#define SM_MAX_WAIT 3000
|
||||
|
||||
#define M_BLK_OVERHEAD 4
|
||||
#define CL_BLK_OVERHEAD 4
|
||||
#define CL_OVERHEAD 4
|
||||
|
||||
#define PKT_TYPE_MULTI 0x1 /* packet with a multicast address */
|
||||
#define PKT_TYPE_UNI 0x2 /* packet with a unicast address */
|
||||
#define PKT_TYPE_NONE 0x4 /* address type is not meaningful */
|
||||
|
||||
#define SMEND_DEV_NAME "sm"
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* Macros */
|
||||
|
||||
#define etherAdrsPtr(eaddr) (u_char *)(eaddr)
|
||||
|
||||
#define smEndInputCount(pSmEndDev, cpu) \
|
||||
(pSmEndDev)->smPktDesc.cpuLocalAdrs [(cpu)].inputList.count
|
||||
|
||||
#define SM_END_ETHER_ADDR_GET(pEnd) \
|
||||
((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)
|
||||
|
||||
#define SM_END_ETHER_ADDR_LEN_GET(pEnd) \
|
||||
((pEnd)->mib2Tbl.ifPhysAddress.addrLength)
|
||||
|
||||
/* IOCTL codes */
|
||||
|
||||
/* get mblk copy routine pointer */
|
||||
|
||||
#define SMIOCGMCPYRTN _IOR('s', 1, FUNCPTR)
|
||||
|
||||
/* set mblk copy routine pointer */
|
||||
|
||||
#define SMIOCSMCPYRTN _IOW('s', 2, FUNCPTR)
|
||||
|
||||
/* get chained mblk copy routine pointer */
|
||||
|
||||
#define SMIOCGCCPYRTN _IOR('s', 3, FUNCPTR)
|
||||
|
||||
/* set chained mblk copy routine pointer */
|
||||
|
||||
#define SMIOCSCCPYRTN _IOW('s', 4, FUNCPTR)
|
||||
|
||||
/* typedefs */
|
||||
|
||||
/* The definition of the shared memory device control structure */
|
||||
|
||||
typedef struct sm_end_device /* SM_END_DEV */
|
||||
{
|
||||
END_OBJ end; /* The class we inherit from. */
|
||||
UINT cookie; /* sm device validation cookie */
|
||||
int unit; /* unit number */
|
||||
char devName[SM_NAME_MAX+1]; /* device name */
|
||||
SM_ANCHOR * pAnchor; /* SM anchor local address */
|
||||
char * pMem; /* SM local base address */
|
||||
char * pMemAlloc; /* memory allocated by smEnd */
|
||||
ULONG memSize; /* total shared memory size in bytes */
|
||||
unsigned tasType; /* test-and-set type (HARD/SOFT) */
|
||||
unsigned maxCpus; /* max #CPUs supported in 'sm' */
|
||||
unsigned masterCpu; /* master CPU number */
|
||||
unsigned localCpu; /* local cpu number */
|
||||
ULONG maxPktBytes; /* max size of shared memory packet */
|
||||
ULONG startAddr; /* start of seq addrs (0 = not seq) */
|
||||
ULONG ipAddr; /* network address of node */
|
||||
int maxPackets; /* max #packets CPU can receive */
|
||||
int intType; /* interrupt method */
|
||||
int intArg1; /* 1st interrupt argument */
|
||||
int intArg2; /* 2nd interrupt argument */
|
||||
int intArg3; /* 3rd interrupt argument */
|
||||
int ticksPerBeat; /* #CPU ticks per heartbeat */
|
||||
ULONG mbNum; /* number of mBlks to allocate */
|
||||
ULONG cbNum; /* number of clBlks to allocate */
|
||||
void (* pSmFree) (void *); /* routine to free memory*/
|
||||
BOOL smAlloc; /* sm allocated? */
|
||||
BOOL isMaster; /* we are master CPU? */
|
||||
BOOL isBoot; /* we are boot device? */
|
||||
ULONG flags; /* Our local flags. */
|
||||
SM_PKT_MEM_HDR * pSmPktHdr; /* sm packet header */
|
||||
int * pRxPktCnt; /* SM pkt CPU input pkt count */
|
||||
UINT rxInts; /* interrupt counter for rec'vd pkts */
|
||||
CL_POOL_ID clPoolId; /* cluster pool ID */
|
||||
M_BLK_ID tupleId; /* receive-ready tuple (mBlk) ID */
|
||||
M_BLK_ID pollQ; /* polled tuple queue */
|
||||
M_BLK_ID pollQLast; /* polled tuple queue last entry */
|
||||
void * pMclBlkCfg; /* mBlk/clBlk config memory */
|
||||
void * pClustMem; /* cluster pool memory */
|
||||
u_char enPhyAddr[MAXIFPHYADDR]; /* ethernet physical address*/
|
||||
SM_PKT_DESC smPktDesc; /* shared mem packet desc */
|
||||
u_long masterAddr; /* master's IP address */
|
||||
unsigned netmask; /* network address mask */
|
||||
END_ERR lastError; /* last Mux error recorded */
|
||||
BOOT_PARAMS * pBootParams; /* pointer to the boot parameter structure */
|
||||
ULONG configFlag; /* configuration flag passed by user */
|
||||
} SM_END_DEV;
|
||||
|
||||
/* externals */
|
||||
|
||||
extern SM_END_DEV ** unitTbl;
|
||||
|
||||
/* function prototypes */
|
||||
|
||||
#if defined(__STDC__) || defined(__cplusplus)
|
||||
extern STATUS smEndDevInit (SM_END_DEV * pSmEndDev);
|
||||
extern void smEndShowInit (void);
|
||||
extern STATUS smNetShow (char * ifName, BOOL zero);
|
||||
extern END_OBJ * smEndLoad (char * initString);
|
||||
extern STATUS smEndInetAddrGet (char *, int, int, char *);
|
||||
#else
|
||||
extern STATUS smEndDevInit ();
|
||||
extern void smEndShowInit ();
|
||||
extern STATUS smNetShow ();
|
||||
extern END_OBJ * smEndLoad ();
|
||||
extern STATUS smEndInetAddrGet ();
|
||||
#endif /* defined(__STDC__) || defined(__cplusplus) */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsmEndh */
|
||||
@@ -0,0 +1,446 @@
|
||||
/* wancomEnd.h - Marvel/Galileo GT642xx network interface header */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2004-2005, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
/* Copyright 2002 Motorola, Inc. All Rights Reserved */
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,06may10,c_t change WANCOM_BUF_DEF_SIZE from 1518 to 1520(WIND00204839)
|
||||
01e,09feb05,mdo Documentation fixes for apigen
|
||||
01d,28jun04,h_k added pNetBufCfg and initType, deleted memBaseState and
|
||||
hashState in WANCOM_DRV_CTRL and pMblk in RX_DESC.
|
||||
01c,11jun04,h_k changed comment for baseAddr. merged wancomDefs.h.
|
||||
01b,26mar04,h_k merged from cp7000g BSP.
|
||||
01a,28oct02,scb Copied from hxeb100 base version 01a.
|
||||
*/
|
||||
|
||||
/*
|
||||
********************************************************************************
|
||||
* (c), Copyright 2001, Marvell International Ltd. *
|
||||
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC. *
|
||||
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
|
||||
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE *
|
||||
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. *
|
||||
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESS, IMPLIED *
|
||||
* OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. *
|
||||
********************************************************************************
|
||||
* wancomEnd.h - Header File for : GT-642xx network interface header
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This file defines the network devices that can be attached to the MUX.
|
||||
*
|
||||
* DEPENDENCIES:
|
||||
* WRS endLib library.
|
||||
*
|
||||
********************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __INCwancomEndh
|
||||
#define __INCwancomEndh
|
||||
|
||||
/* includes */
|
||||
|
||||
#include "etherLib.h"
|
||||
#include "miiLib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* defines */
|
||||
|
||||
#define DRV_NAME "wancom"
|
||||
|
||||
/* descriptor defines */
|
||||
|
||||
#define SHADOW_OWNER_BY_GT 1
|
||||
#define SHADOW_OWNER_BY_CPU 0
|
||||
#define OWNER_BY_GT (1<<31)
|
||||
#define FIRST (1<<17)
|
||||
#define LAST (1<<16)
|
||||
#define ENABLE_INTERRUPT (1<<23)
|
||||
#define PADDING (1<<18)
|
||||
#define GENERATE_CRC (1<<22)
|
||||
#define ERROR_SUMMARY (1<<15)
|
||||
|
||||
/* this macros are used to enable access to MPSC_SDCMR */
|
||||
|
||||
#define ENABLE_RX_DMA (1<<7)
|
||||
#define ABORT_RECEIVE (1<<15)
|
||||
#define STOP_TRANSMIT (1<<16)
|
||||
#define PORT_SDMA_STOP_TX_LOW (1<<17)
|
||||
#define TX_DEMAND (1<<23)
|
||||
#define PORT_SDMA_START_TX_LOW (1<<24)
|
||||
#define ABORT_TRANSMIT (1<<31)
|
||||
|
||||
/* Serial second layer cause registers bits definition */
|
||||
/* Ethernet mask bits */
|
||||
|
||||
#define RX_BUFFER_RETURN 0x1
|
||||
#define TX_BUFFER_HIGH_PRIO 0x4
|
||||
#define TX_BUFFER_LOW_PRIO 0x8
|
||||
#define TX_END_HIGH_PRIO 0x40
|
||||
#define TX_END_LOW_PRIO 0x80
|
||||
#define RX_RESOURCE_ERR 0x100
|
||||
#define TX_RESOURCE_ERR_HIGH_PRIO 0x400
|
||||
#define TX_RESOURCE_ERR_LOW_PRIO 0x800
|
||||
#define RX_OVERRUN 0x1000
|
||||
#define TX_UNDERRUN 0x2000
|
||||
#define RX_BUFFER_QUEUE_0 (1<<16)
|
||||
#define RX_BUFFER_QUEUE_1 (1<<17)
|
||||
#define RX_BUFFER_QUEUE_2 (1<<18)
|
||||
#define RX_BUFFER_QUEUE_3 (1<<19)
|
||||
#define RX_ERROR_QUEUE_0 (1<<20)
|
||||
#define RX_ERROR_QUEUE_1 (1<<21)
|
||||
#define RX_ERROR_QUEUE_2 (1<<22)
|
||||
#define RX_ERROR_QUEUE_3 (1<<23)
|
||||
#define MII_PHYS_STATUS_CHANGE 0x10000000
|
||||
#define SMI_COMMAND_DONE 0x20000000
|
||||
#define ETHER_INT_SUM 0x80000000
|
||||
|
||||
/* Serial Port Multiplex register (connect to MII control) */
|
||||
|
||||
#define SERIAL_PORT_MULTIPLEX 0xf010
|
||||
|
||||
#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
|
||||
|
||||
#define NIBBLE_SWAPPING_16_BIT(X) (((X&0xf)<<4) | ((X&0xf0)>>4) | \
|
||||
((X&0xf00)<<4) | ((X&0xf000)>>4))
|
||||
|
||||
#define NIBBLE_SWAPPING_32_BIT(X) (((X&0xf)<<4) | ((X&0xf0)>>4) | \
|
||||
((X&0xf00)<<4) | ((X&0xf000)>>4) | ((X&0xf0000)<<4) | \
|
||||
((X&0xf00000)>>4) | ((X&0xf000000)<<4) | ((X&0xf0000000)>>4))
|
||||
|
||||
#define GT_NIBBLE(X) ((X&0x1)<<3)+((X&0x2)<<1)+((X&0x4)>>1)+((X&0x8)>>3)
|
||||
|
||||
#define FLIP_6_BITS(X) (((X&0x1)<<5)+((X&0x2)<<3)+((X&0x4)<<1)+ \
|
||||
((X&0x8)>>1)+((X&0x10)>>3)+((X&0x20)>>5))
|
||||
|
||||
#define FLIP_9_BITS(X) (((X&0x1)<<8)+((X&0x2)<<6)+((X&0x4)<<4)+ \
|
||||
((X&0x8)<<2)+((X&0x10)<<0)+((X&0x20)>>2)+((X&0x40)>>4)+ \
|
||||
((X&0x80)>>6)+((X&0x100)>>8))
|
||||
|
||||
#define _8K_TABLE 0
|
||||
/* size of hash entry for an address */
|
||||
|
||||
#define MAC_ENTRY_SIZE 8
|
||||
/* hash table entry fields */
|
||||
|
||||
#define VALID_BIT 0
|
||||
#define VALID 1
|
||||
#define NOT_VALID 0
|
||||
#define SKIP_BIT 1
|
||||
#define SKIP (1<<1)
|
||||
#define DONT_SKIP 0
|
||||
#define RD_BIT 2
|
||||
#define RCV_PKT 1
|
||||
#define DROP_RCV_PKT 0
|
||||
|
||||
#define HOP_NUMBER 12
|
||||
|
||||
#define EIGHT_K 0x8000
|
||||
#define HALF_K 0x8000/16
|
||||
|
||||
#define HASH_DEFUALT_MODE 14
|
||||
#define HASH_MODE 13
|
||||
#define HASH_SIZE 12
|
||||
#define PROMISCUOUS_MODE 0
|
||||
|
||||
#define WANCOM_BUF_DEF_SIZE (SIZEOF_ETHERHEADER + ETHERMTU + 4 + 2)
|
||||
|
||||
/* For buffers less than 8 bytes */
|
||||
|
||||
#define TX_BUF_OFFSET_IN_DESC 0x18
|
||||
/* ethernet configuration value */
|
||||
|
||||
#define PORT_CONFIG_VALUE 0x00000081
|
||||
|
||||
/* Ethernet config ext. value */
|
||||
|
||||
#define PORT_CONFIG_EXTEND_VALUE 0x00010800
|
||||
|
||||
/* SDMA configure value */
|
||||
|
||||
#if (_BYTE_ORDER == _BIG_ENDIAN)
|
||||
/* big endian DMA transfer mode */
|
||||
|
||||
#define PORT_SDMA_CONFIG_VALUE 0x00002000
|
||||
|
||||
#else
|
||||
/* little endian DMA transfer mode */
|
||||
|
||||
#define PORT_SDMA_CONFIG_VALUE 0x000020c0
|
||||
|
||||
#endif /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
|
||||
/* serial ports multiple x reg (RMII and mpsc's connected) */
|
||||
|
||||
#define GT_SERIAL_PORT_MUX 0x00000001
|
||||
|
||||
#ifndef WANCOM_SYS_INT_CONNECT
|
||||
#define WANCOM_SYS_INT_CONNECT(pDrvCtrl, pFunc, arg, pRet) \
|
||||
{ \
|
||||
*pRet = ERROR ; \
|
||||
if(wancomEndIntConnect != NULL) \
|
||||
{ \
|
||||
*pRet = (wancomEndIntConnect) ( \
|
||||
INUM_TO_IVEC (pDrvCtrl->port.vector), \
|
||||
(VOIDFUNCPTR*)(pFunc), (int) (arg)); \
|
||||
} \
|
||||
}
|
||||
#endif /* WANCOM_SYS_INT_CONNECT */
|
||||
|
||||
#ifndef WANCOM_SYS_INT_DISCONNECT
|
||||
#define WANCOM_SYS_INT_DISCONNECT(pDrvCtrl, pFunc, arg, pRet) \
|
||||
{ \
|
||||
*pRet = ERROR ; \
|
||||
if(wancomEndIntDisconnect != NULL) \
|
||||
{ \
|
||||
*pRet = (wancomEndIntDisconnect) ((VOIDFUNCPTR*) \
|
||||
INUM_TO_IVEC (pDrvCtrl->port.level), \
|
||||
(pFunc), (int) (arg)); \
|
||||
} \
|
||||
}
|
||||
#endif /* WANCOM_SYS_INT_DISCONNECT */
|
||||
|
||||
#ifndef WANCOM_SYS_INT_ENABLE
|
||||
#define WANCOM_SYS_INT_ENABLE(pDrvCtrl) \
|
||||
if (WANCOM_INT_ENABLE (pDrvCtrl)) \
|
||||
((*(FUNCPTR) (WANCOM_INT_ENABLE (pDrvCtrl))) (pDrvCtrl->unit))
|
||||
#endif /* WANCOM_SYS_INT_ENABLE */
|
||||
|
||||
#ifndef WANCOM_SYS_INT_DISABLE
|
||||
#define WANCOM_SYS_INT_DISABLE(pDrvCtrl) \
|
||||
if (WANCOM_INT_DISABLE (pDrvCtrl)) \
|
||||
((*(FUNCPTR) (WANCOM_INT_DISABLE (pDrvCtrl))) (pDrvCtrl->unit))
|
||||
#endif /* WANCOM_SYS_INT_DISABLE */
|
||||
|
||||
#ifndef WANCOM_SYS_INT_ACK
|
||||
#define WANCOM_SYS_INT_ACK(pDrvCtrl) \
|
||||
if (WANCOM_INT_ACK (pDrvCtrl)) \
|
||||
((*(FUNCPTR) (WANCOM_INT_ACK (pDrvCtrl))) (pDrvCtrl->unit))
|
||||
#endif /* WANCOM_SYS_INT_ACK */
|
||||
|
||||
#ifndef LOCAL_TO_SYS_ADDR
|
||||
#define LOCAL_TO_SYS_ADDR(unit,localAddr) \
|
||||
((int) pDrvCtrl->port.sysLocalToBus ? \
|
||||
(*pDrvCtrl->port.sysLocalToBus) (unit, localAddr) : localAddr)
|
||||
#endif /* LOCAL_TO_SYS_ADDR */
|
||||
|
||||
#ifndef SYS_TO_LOCAL_ADDR
|
||||
#define SYS_TO_LOCAL_ADDR(unit,sysAddr) \
|
||||
((int) pDrvCtrl->port.sysBusToLocal ? \
|
||||
(*pDrvCtrl->port.sysBusToLocal)(unit, sysAddr) : sysAddr)
|
||||
#endif /* SYS_TO_LOCAL_ADDR */
|
||||
|
||||
|
||||
/* CPU interface registers */
|
||||
|
||||
#define WANCOM_DEV_NAME "wancom"
|
||||
#define WANCOM_DEV_NAME_LEN 7
|
||||
#define DEF_NUM_CFDS 32 /* default number of CFDs (Hex) */
|
||||
#define DEF_NUM_RFDS 32 /* default number of RFDs (Hex) */
|
||||
#define WANCOM_100MBS 100000000 /* bits per sec */
|
||||
#define WANCOM_10MBS 10000000 /* bits per sec */
|
||||
#define WANCOM_ADDR_LEN 6 /* ethernet address length */
|
||||
|
||||
/* constants needed within this file */
|
||||
|
||||
#define EH_SIZE 14 /* avoid structure padding issues */
|
||||
#define N_MCAST 12
|
||||
|
||||
/* offsets from 642xx register base address */
|
||||
|
||||
#define PORT0_BASE_OFFSET 0x2400 /* ethernet 0 base addr */
|
||||
#define ETH_SMIR_BASE_OFFSET 0x2010 /* SMIR register */
|
||||
#define ETH_PHY_BASE_OFFSET 0x2000 /* Phy register */
|
||||
|
||||
/* Ethernet port register offsets from port base address */
|
||||
|
||||
#define PORT_CONFIG_REG 0x000
|
||||
#define PORT_CONFIG_EXTEND_REG 0x008
|
||||
#define PORT_COMMAND_REG 0x010
|
||||
#define PORT_STATUS_REG 0x018
|
||||
#define SERIAL_PARAMETERS_REG 0x020
|
||||
#define HASH_TABLE_POINTER_REG 0x028
|
||||
#define FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x030
|
||||
#define FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x038
|
||||
#define SDMA_CONFIGURATION_REG 0x040
|
||||
#define SDMA_COMMAND_REG 0x048
|
||||
#define INTERRUPT_CAUSE_REG 0x050
|
||||
#define INTERRUPT_MASK_REG 0x058
|
||||
#define FIRST_RX_DESC_PTR0_OFFSET 0x080
|
||||
#define FIRST_RX_DESC_PTR1_OFFSET 0x084
|
||||
#define FIRST_RX_DESC_PTR2_OFFSET 0x088
|
||||
#define FIRST_RX_DESC_PTR3_OFFSET 0x08c
|
||||
#define CURRENT_RX_DESC_PTR0_OFFSET 0x0a0
|
||||
#define CURRENT_RX_DESC_PTR1_OFFSET 0x0a4
|
||||
#define CURRENT_RX_DESC_PTR2_OFFSET 0x0a8
|
||||
#define CURRENT_RX_DESC_PTR3_OFFSET 0x0ac
|
||||
#define CURRENT_TX_DESC_PTR0_OFFSET 0x0e0
|
||||
#define CURRENT_TX_DESC_PTR1_OFFSET 0x0e4
|
||||
#define MIB_COUNTER_BASE 0x100
|
||||
#define MIB_COUNTER_END 0x200
|
||||
|
||||
/* Port status register bits offset in register */
|
||||
|
||||
#define SPEED_100MBS (1<<0)
|
||||
#define LINK_UP_BIT (1<<3)
|
||||
#define TX_LOW_RUNNING (1<<5)
|
||||
#define TX_HIGH_RUNNING (1<<6)
|
||||
#define TX_IN_PROGRESS (1<<7)
|
||||
|
||||
/* Port Config register bits offset in register */
|
||||
|
||||
#define PROMISCUOUS_MODE_BIT (1<<0)
|
||||
|
||||
|
||||
/* typedefs */
|
||||
/* board specific information */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT32 vector; /* interrupt vector */
|
||||
UINT32 level; /* interrupt level */
|
||||
UINT32 baseAddr; /* Port registers base address */
|
||||
UCHAR enetAddr[8]; /* eth address with 2 byte pad */
|
||||
int (*intEnable)(int unit); /* port interrupt enable routine */
|
||||
int (*intDisable)(int unit); /* port interrupt disable routine */
|
||||
int (*intAck) (int unit); /* interrupt ack */
|
||||
UINT32 portConfig;
|
||||
UINT32 portConfigExtend;
|
||||
UINT32 portCommand;
|
||||
UINT32 portSdmaConfig;
|
||||
int offset;
|
||||
} WANCOM_PORT_INFO;
|
||||
|
||||
typedef unsigned int RX_COMMAND;
|
||||
|
||||
typedef struct SdmaRxDesc
|
||||
{
|
||||
#if (_BYTE_ORDER == _BIG_ENDIAN)
|
||||
unsigned int bufsize :16;
|
||||
volatile unsigned int bytecnt :16;
|
||||
volatile RX_COMMAND cmd_sts;
|
||||
unsigned int next_desc_ptr;
|
||||
volatile unsigned int buf_ptr;
|
||||
#else /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
volatile RX_COMMAND cmd_sts;
|
||||
volatile unsigned int bytecnt :16;
|
||||
unsigned int bufsize :16;
|
||||
unsigned int buf_ptr;
|
||||
unsigned int next_desc_ptr;
|
||||
#endif /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
M_BLK_ID pMblk;
|
||||
/* to be safe, align the structure size multiple of 32 bytes */
|
||||
unsigned int reserved [3];
|
||||
} RX_DESC;
|
||||
|
||||
typedef unsigned int TX_COMMAND;
|
||||
|
||||
/* tx descriptor definition. buf is used for sending small buffers
|
||||
* less than 8 bytes in size. buf is placed so it is on a boundary
|
||||
* that is divisible by 8 (required for buffers <= 8 bytes) and
|
||||
* sized so the descriptor is divisible evenly by 16
|
||||
*/
|
||||
|
||||
typedef struct SdmaTxDesc
|
||||
{
|
||||
#if (_BYTE_ORDER == _BIG_ENDIAN)
|
||||
unsigned int bytecnt :16;
|
||||
unsigned int shadowOwner :16;
|
||||
volatile TX_COMMAND cmd_sts;
|
||||
unsigned int next_desc_ptr;
|
||||
unsigned int buf_ptr;
|
||||
#else /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
volatile TX_COMMAND cmd_sts;
|
||||
unsigned int shadowOwner :16;
|
||||
unsigned int bytecnt :16;
|
||||
unsigned int buf_ptr;
|
||||
unsigned int next_desc_ptr;
|
||||
#endif /* _BYTE_ORDER == _BIG_ENDIAN */
|
||||
UINT8 buf [8];
|
||||
M_BLK * pointerToRxQueue;
|
||||
char * txBuffPtr;
|
||||
} TX_DESC;
|
||||
|
||||
/* The definition of the driver control structure */
|
||||
|
||||
typedef struct wancom_drv_ctrl
|
||||
{
|
||||
END_OBJ endObj; /* base class */
|
||||
int unit; /* unit number */
|
||||
char * pMemBase; /* memory pool base */
|
||||
ULONG memSize; /* memory pool size */
|
||||
char * pClsBase; /* cluster pool base */
|
||||
char * pMemArea; /* Mblk Clblk pool pointer */
|
||||
char * pTxBuffBase; /* tx buffer base address */
|
||||
int nCFDs; /* how many CFDs to create */
|
||||
volatile int nFreeCFDs; /* how many CFDs freed */
|
||||
int nRFDs; /* how many RFDs to create */
|
||||
UINT32 pCSR; /* pointer to CSR base */
|
||||
|
||||
RX_DESC* headRxDescPtr; /* Pointer to head Rx desc queue */
|
||||
RX_DESC* rxDescMem; /* Pointer to start of Rx desc memory */
|
||||
TX_DESC* usedTxDescPtr; /* Pointer to head Tx desc queue */
|
||||
TX_DESC* currTxDescPtr; /* Pointer to next available Tx desc */
|
||||
TX_DESC* txDescMem; /* Pointer to start of Tx desc memory */
|
||||
|
||||
UINT16 flags; /* driver state */
|
||||
BOOL attached; /* interface has been attached */
|
||||
BOOL rxHandle; /* rx handler scheduled */
|
||||
BOOL txHandle; /* tx handler scheduled */
|
||||
BOOL txStall; /* tx handler stalled - no CFDs */
|
||||
END_ERR lastError; /* Last error passed to muxError */
|
||||
WANCOM_PORT_INFO port; /* port specific info */
|
||||
CL_POOL_ID pClPoolId; /* cluster pool identifier */
|
||||
int addressTableHashMode ;
|
||||
int addressTableHashSize ;
|
||||
UINT32 addressTableBase ;
|
||||
char * addressTableMalloc ;
|
||||
int initType; /* memory pool initialization type */
|
||||
NETBUF_CFG * pNetBufCfg;
|
||||
} WANCOM_DRV_CTRL;
|
||||
|
||||
#if (_BYTE_ORDER == _BIG_ENDIAN)
|
||||
#define PSWAP(x) LONGSWAP(x)
|
||||
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
|
||||
#define PSWAP(x) (x)
|
||||
#endif
|
||||
|
||||
#ifndef EIEIO
|
||||
#define EIEIO
|
||||
#endif
|
||||
|
||||
#define WANCOM_REG_RD(x,val) \
|
||||
{ \
|
||||
UINT32 tmp ; \
|
||||
tmp = *((volatile UINT32*)(x)); \
|
||||
EIEIO ; \
|
||||
(*val) = PSWAP(tmp); \
|
||||
EIEIO ; \
|
||||
}
|
||||
|
||||
#define WANCOM_REG_WR(x,val) \
|
||||
{ \
|
||||
UINT32 tmp ; \
|
||||
tmp = PSWAP(val); \
|
||||
EIEIO ; \
|
||||
*((volatile UINT32*)(x)) = tmp ; \
|
||||
EIEIO ; \
|
||||
tmp = *((volatile UINT32*)(x)); \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCwancomEndh */
|
||||
|
||||
Reference in New Issue
Block a user