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neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
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vxworks-6.9/target/h/drv/dma/i8237Dma.h
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/* i8237Dma.h - Intel 8237 DMA controller header */
/* Copyright 1984-1993 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,30sep93,hdn written.
*/
#ifndef __INCi8237Dmah
#define __INCi8237Dmah
#ifdef __cplusplus
extern "C" {
#endif
/* DMA chip-1 IO address */
#define DMA1_BASE 0x00
#define DMA1_ADDR(chan) (DMA1_BASE + (chan << 1))
#define DMA1_COUNT(chan) (DMA1_BASE + (chan << 1) + 1)
#define DMA1_STATUS 0x08
#define DMA1_CMD 0x08
#define DMA1_MASK_SINGLE 0x0a
#define DMA1_MODE 0x0b
#define DMA1_CLEAR_FF 0x0c
#define DMA1_CLEAR_ALL 0x0d
#define DMA1_CLEAR_MASK 0x0e
#define DMA1_MASK_ALL 0x0f
/* DMA chip-2 IO address */
#define DMA2_BASE 0xc0
#define DMA2_ADDR(chan) (DMA2_BASE + ((chan - 4) << 2))
#define DMA2_COUNT(chan) (DMA2_BASE + ((chan - 4) << 2) + 2)
#define DMA2_STATUS 0xd0
#define DMA2_CMD 0xd0
#define DMA2_MASK_SINGLE 0xd4
#define DMA2_MODE 0xd6
#define DMA2_CLEAR_FF 0xd8
#define DMA2_CLEAR_ALL 0xda
#define DMA2_CLEAR_MASK 0xdc
#define DMA2_MASK_ALL 0xde
/* mode register bit */
#define DMA_MODE_DEMAND 0x00
#define DMA_MODE_SINGLE 0x40
#define DMA_MODE_BLOCK 0x80
#define DMA_MODE_CASCADE 0xc0
#define DMA_MODE_DECREMENT 0x20
#define DMA_MODE_INCREMENT 0x00
#define DMA_MODE_AUTO_ENABLE 0x10
#define DMA_MODE_AUTO_DISABLE 0x00
#define DMA_MODE_WRITE 0x08
#define DMA_MODE_READ 0x04
/* mask register bit */
#define DMA_MASK_SET 0x04
#define DMA_MASK_RESET 0x00
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
STATUS dmaSetup (int direction, void *pBuf, UINT nBytes, UINT chan);
#else
STATUS dmaSetup ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* __INCi8237Dmah */
vxworks-6.9/target/h/drv/dma/iPIIX4Dma.h
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/* iPIIX4Dma.h - Intel 82371ab PCI-TO-ISA/IDEXCELERATOR(PIIX4) Driver Header file */
/*
* Copyright (c) 2001, 2005, 2007, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify, or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01g,06jul10,sye Add support to 82801DB(ICH4). (WIND00125477)
01f,29apr10,pad Moved extern C statement after include statements.
01e,15jun07,dee WIND00097125 - support 82801 and 6300esb I/O hub controllers
01d,23sep05,dee SPR#112529, define additional dma controller pci types
01c,02aug05,dee dma support for PIIX4 ATA controller
01b,20dec01,bsp function declaration changed.
01a,21Nov01,bsp written.
*/
/*
* Please refer to Intel Document Order Number: 290562-001
* 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
*/
#ifndef __INCiPIIX4Dmah
#define __INCiPIIX4Dmah
#ifndef _ASMLANGUAGE
/* includes */
#include <vxWorks.h>
#include <drv/pci/pciConfigLib.h>
#include <drv/pci/pciHeaderDefs.h>
#include <wdLib.h>
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define I82371AB_VENDOR_ID 0x8086 /* Intel Corp. */
#define I82371AB_DEVICE_ID 0x7111 /* i82371AB PIIX4 */
#define I82801AA_DEVICE_ID 0x2411 /* i82801AA ICH */
#define I82801AB_DEVICE_ID 0x2421 /* i82801AB ICH0 */
#define I82801DB_DEVICE_ID 0x24CB /* i82801DB ICH4 */
#define I82801_ICH6_DEVICE_ID 0x2651 /* i82801FB ICH6 sata */
#define I82801FB_DEVICE_ID 0x266F /* i82801FB ICH6 ide */
#define I82801_ICH7A_DEVICE_ID 0x27C4 /* i82801FB ICH7 sata */
#define I82801_ICH7B_DEVICE_ID 0x27C0 /* i82801FB ICH7 ata */
#define I82372FB_DEVICE_ID 0x7601 /* i82372FB */
#define I6300ESB_P_DEVICE_ID 0x25A2 /* 6300esb ata mode */
#define I6300ESB_C_DEVICE_ID 0x25A3 /* 6300esb combined mode */
#define I82371AB_MAC_64_K 0x10000 /* pow(2,16) */
#define I82371AB_MAC_4_K 0x01000 /* pow(2,12) */
#define I82371AB_MAC_512 0x00200 /* pow(2,9) */
/* max number of controllers */
#define I82371AB_MAX_CTRLS 0x2 /* 0 and 1 only */
/* Offset in the PCI configuaration space */
#define PCI_CFG_BMIBA PCI_CFG_BASE_ADDRESS_4
/* 0x20-0x23 default = 0x0000 R/W */
#define PCI_CFG_IDETIM(ctrl) (0x40 + ctrl * 2)
#define PCI_CFG_IDETIM_PRI 0x40 /* 0x40-0x41 default = 0x0000 R/W */
#define PCI_CFG_IDETIM_SEC 0x42 /* 0x42-0x43 default = 0x0000 R/W */
#define PCI_CFG_SIDETIME 0x44 /* 0x44 default = 0x00 R/W */
#define PCI_CFG_UDMACTL 0x48 /* 0x48 default = 0x00 R/W */
#define PCI_CFG_UDMATIM 0x4A /* 0x4A-0x4B default = 0x0000 R/W */
/* Page-78, 2.7, Ref-1 */
#define I82371AB_BMICOMadd(ctrl) (ideController.ioBaseAddress + 0x0 + ctrl * 8)
#define I82371AB_BMISTAadd(ctrl) (ideController.ioBaseAddress + 0x2 + ctrl * 8)
#define I82371AB_BMIDTPadd(ctrl) (ideController.ioBaseAddress + 0x4 + ctrl * 8)
#define I82371AB_BMI_ALL 0xff
#define I82371AB_BMICOM 0x00
#define I82371AB_BMISTA 0x01
#define I82371AB_BMIDTP 0x02
/* BMICOM */
#define I82371AB_RWCON 0x08
#define I82371AB_SSBM 0x01
/* BMISTA */
#define I82371AB_DMA1CAP 0x40
#define I82371AB_DMA0CAP 0x20
#define I82371AB_INT_STATUS 0x04
#define I82371AB_IDEDMA_ERROR 0x02
#define I82371AB_BMIDE_ACTIVE 0x01
/* bit masks */
#define I82371AB_BMBIA_ADD_MASK 0xfff0 /* valid bits 15 to 4 */
/* PCI status */
#define I82371AB_PCISTS_BME 0x0004 /* bus master enable bit*/
#define I82371AB_PCISTS_IOSE 0x0001 /* I/O space enable bit */
/* IDE Timing Register */
#define I82371AB_IDETIM_ENE 0x8000 /* IDE enable */
#define I82371AB_IDETIM_PPE0 0x0004 /* PPC0 enable */
#define I82371AB_IDETIM_IE0 0x0002 /* IORDY Sample Point
Enable Drive 0 */
/* A small delay for register hardware settling time*/
#define I82371AB_DELAY(ctrl) sysInByte(I82371AB_BMISTAadd(ctrl)); \
sysInByte(I82371AB_BMISTAadd(ctrl)); \
sysInByte(I82371AB_BMISTAadd(ctrl)); \
sysInByte(I82371AB_BMISTAadd(ctrl))
/* typedefs */
typedef struct pci_ide_controller
{
int pciBusNo;
int pciDeviceNo;
int pciFuncNo;
/* PCI configuaration Registers */
PCI_HEADER_DEVICE pciHeader;
UINT16 ideTim[2]; /* Primary channel - 40,41 */
/* Secondary channel - 42,43 */
UINT8 slaveIdeTim; /* 44 */
UINT8 uDmaCtl; /* 48 */
UINT16 uDmaTime; /* 4A-4B */
/* IO Space Registers */
UINT32 ioBaseAddress;
UINT8 bmiCom[2]; /* 0x00 */
UINT8 bmiSta[2]; /* 0x02 */
UINT32 bmiDtp[2]; /* 0x04 */
WDOG_ID bmiWdogId[2];
BOOL bmiWdogOkay[2];
UINT32 * pPRDTable[I82371AB_MAX_CTRLS];
}PCI_IDE_CONTROLLER;
typedef struct i82371DescTable
{
void * buffer;
UINT16 count;
UINT16 eot;
#define END_OF_TABLE 0x8000; /* end of table bit indication */
} i82371_DESC_TBL;
/* function declarations */
extern STATUS iPIIX4PciIdeCtrlInit (int ctrl);
extern STATUS iPIIX4InitAtaDmaEngine (int ctrl, int drive, char * pBuf,
UINT32 bufLength, int direction);
extern STATUS iPIIX4StartAtaDmaEngine (int ctrl);
extern STATUS iPIIX4StopAtaDmaEngine (int ctrl);
extern STATUS iPIIX4AtaDmaTrnsfrWait (int ctrl, int time);
extern short iPIIX4AtaDmaModeNegotiate (short rwmode);
extern void iPIIX4IdeCtrlReset (void);
extern STATUS iPIIX4AtaDmaModeSet (int ctrl,int drive,short rwmode);
#ifdef IDEDMA_DEBUG
extern void iPIIX4IdeDebugVerbosityLevelSet (int level);
extern int iPIIX4IdeDebugVerbosityLevelGet (void);
#endif /* IDEDMA_DEBUG */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCiPIIX4Dmah */
vxworks-6.9/target/h/drv/dma/ibmMalDma.h
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/* ibmMalDma.h - IBM Memory Access Layer (MAL) library header */
/*
*******************************************************************************
This source and object code has been made available to you by IBM on an
AS-IS basis.
IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
OF THIRD PARTY RIGHTS. IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES. IBM'S OR ITS LICENSOR'S
DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE. No license
under IBM patents or patent applications is to be implied by the copyright
license.
Any user of this software should understand that neither IBM nor its
licensors will be responsible for any consequences resulting from the use
of this software.
Any person who transfers this source code or any derivative work must
include the IBM copyright notice, this paragraph, and the preceding two
paragraphs in the transferred software.
Any person who transfers this object code or any derivative work must
include the IBM copyright notice in the transferred software.
COPYRIGHT I B M CORPORATION 2000
LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
********************************************************************************
\NOMANUAL
*/
/* Copyright 1984-2004 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,03sep04,mdo Documentation fixes for apigen
01g,28may04,jln add MAL_RX_GROUP_HANDLER_RUNING
01f,26aug03,jln change malLib.c to ibmMalDma.h;
change ibmMalRxGroupHandlerEnable() API
01e,07jul03,jln rename EMAC_RXCHAN_GROUP to MAL_RXCHAN_GROUP
01d,11jun03,jln modified MAL_DATA structure, more comments.
01c,16may01,mcg common driver for walnut (405GP), cedar (NPe405x)
01b,15jan00,mcg added alignment requirement for buffer descriptor rings
01a,18oct99,mcg created
*/
/*
This file contains constants for the IBM Memory Access Layer core.
The emacEnd driver is tightly coupling with this header file, if any change
in the MAL data structure and APIs, the emacEnd.c should be recompiled.
*/
#ifndef INCibmMalDmah
#define INCibmMalDmah
#ifdef __cplusplus
extern "C" {
#endif
#define MAL_NUM_TYPES 2
#define MAL_TX_TYPE 0
#define MAL_RX_TYPE 1
#define MAL_MAX_CHANNELS 32 /* 32 for receive, 32 for transmit */
/*
* Reduced configurations of MAL are used for chips with fewer communication
* cores inside.
*/
#define MAL_NO_INTS 0x00000000
#define MAL_EOB_INT_EN 0x00000001
#define MAL_DE_INT_EN 0x00000002
#define MAL_SERR_INT_EN 0x00000004
#define MAL_MAX_DESC 256 /* max descriptors per channel */
#define MAL_MAX_DESC_TBL_SIZE (MAL_MAX_DESC * sizeof(MAL_BD))
#define MAL_DESC_REQ_ALIGN (512*1024) /* 512KB */
/* MAX RX channels in a board */
#ifndef MAX_MAL_RX_CHANS
#define MAX_MAL_RX_CHANS 4
#endif
/* MAL flags */
#define MAL_RX_GROUP_ENABLE 0x0001
#define MAL_RX_GROUP_POLL_ENABLE 0x0002
#define MAL_RX_GROUP_HANDLER_RUNING 0x0004
/* MAL Channel structure */
typedef struct
{
UINT channelType; /* TX_TYPE or RX_TYPE */
UINT channelNum; /* channel number (0 through 31) */
UINT bufferSizeRX; /* receive buffer size if an RX channel */
UINT channelIntMask; /* interrupt mask for this channel */
VOIDFUNCPTR functionEOB; /* function for EOB int on this channel */
UINT parmEOB; /* parameter for the above function */
VOIDFUNCPTR functionDescErr; /* function for DE int on this channel */
UINT parmDescErr; /* parameter for the above function */
VOIDFUNCPTR functionSERR; /* function for MAL SERR int for this chn */
UINT parmSERR; /* parameter for the above function */
} MAL_CHANNEL;
/*
* MAL initialization structure. This information is passed to the MAL driver
* in malInit().
*/
typedef struct
{
UINT dcrBaseReg;
UINT validChannels[MAL_NUM_TYPES];
UINT intLvlTxeob;
UINT intVecTxeob;
UINT intLvlRxeob;
UINT intVecRxeob;
UINT intLvlTxde;
UINT intVecTxde;
UINT intLvlRxde;
UINT intVecRxde;
UINT intLvlSerr;
UINT intVecSerr;
} MAL_INIT;
/* Structure to group all EMAC_RX channels */
typedef struct
{
int rotateIndex [MAX_MAL_RX_CHANS]; /* channel order to search */
UINT rotateRx [MAX_MAL_RX_CHANS]; /* RX channels index in order */
UINT chanNum; /* number of RX channels in group */
UINT maxRxPktsPerInterrupt; /* Max RX packets in a interrupt */
} MAL_RXCHAN_GROUP;
/*
* MAL driver control structure.
*/
typedef struct
{
MAL_INIT malInit;
char *descTablesAlloc;
char *descTables;
UINT reserved1;
MAL_CHANNEL malChannelArray[MAL_NUM_TYPES][MAL_MAX_CHANNELS];
UINT malInitializedChannels[MAL_NUM_TYPES];
UINT malFlags;
UINT reserved2;
MAL_RXCHAN_GROUP malRxChanGrp;
UINT reserved3;
UINT reserved4;
} MAL_DATA;
/*
* MAL Buffer Descriptor Structure. The same structure is used for both
* Transmit and Receive channels.
*/
typedef struct
{
USHORT statusControl; /* Shared between MAL and comm core */
USHORT dataLen; /* Buffer byte count */
char * bufferAdrs; /* Buffer address */
} MAL_BD;
/*
* The status/control bits in the MAL buffer descriptor structure have different
* meaning if the descriptor is used by a TX channel versus an RX channel.
* Bits 0:5 are used to convey MAL control/status. Bits 6:15 are
* used to convey the communication core's (EMAC for example) control/status.
*/
/* MAL TX Descriptor Control/Status bits */
#define MAL_TX_CTRL_READY 0x8000 /* Packet ready to transmit */
#define MAL_TX_CTRL_WRAP 0x4000 /* Last descriptor in the ring */
#define MAL_TX_CTRL_CM 0x2000
#define MAL_TX_CTRL_LAST 0x1000 /* Last buffer for this packet */
#define MAL_TX_CTRL_INTR 0x0400 /* Intr when packet TX complete*/
/* MAL RX Descriptor Control/Status bits */
#define MAL_RX_CTRL_EMPTY 0x8000 /* Buffer empty, ready to RX */
#define MAL_RX_CTRL_WRAP 0x4000 /* Last descriptor in the ring */
#define MAL_RX_CTRL_CM 0x2000
#define MAL_RX_CTRL_LAST 0x1000 /* Last buffer for this packet */
#define MAL_RX_CTRL_FIRST 0x0800 /* 1st buffer for this packet */
#define MAL_RX_CTRL_INTR 0x0400 /* Intr when packet RX complete*/
/* Masks */
#define MAL_MAL_CTRL_BITS 0xFC00 /* All descriptor bits for MAL */
#define MAL_COMMAC_CTRL_BITS 0x03FF /* All descriptor bits for the */
/* communications core */
#define MAL_RX_ONE_BUFFER (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)
/* External functions */
#if defined(__STDC__) || defined(__cplusplus)
void ibmMalReset (UINT dcrBaseReg);
MAL_DATA * ibmMalInit (MAL_INIT *pMalInit);
STATUS ibmMalChannelInit (MAL_DATA *pMalData, MAL_CHANNEL *pChannel);
STATUS ibmMalChannelDelete (MAL_DATA *pMalData, UINT channelType, UINT channelNum);
STATUS ibmMalChannelActivate (MAL_DATA *pMalData, UINT channelType, UINT channelNum);
STATUS ibmMalChannelStop (MAL_DATA *pMalData, UINT channelType, UINT channelNum);
STATUS ibmMalChannelIntMaskGet (MAL_DATA *pMalData, UINT channelType, UINT channelNum, UINT * intMask);
STATUS ibmMalChannelIntMaskSet (MAL_DATA *pMalData, UINT channelType, UINT channelNum, UINT intMask);
STATUS ibmMalChannelDescTblPtrGet (MAL_DATA *pMalData, UINT channelType, UINT channelNum,
MAL_BD ** descTblAdrs);
STATUS ibmMalShutDown (MAL_DATA * pMalData);
void ibmMalRxGroupHandlerEnable (MAL_DATA *, BOOL, BOOL);
#else
void ibmMalReset ();
MAL_DATA * ibmMalInit ();
STATUS ibmMalChannelInit ();
STATUS ibmMalChannelDelete ();
STATUS ibmMalChannelActivate ();
STATUS ibmMalChannelStop ();
STATUS ibmMalChannelIntMaskGet ();
STATUS ibmMalChannelIntMaskSet ();
STATUS ibmMalChannelDescTblPtrGet ();
STATUS ibmMalShutDown ();
void ibmMalRxGroupHandlerEnable ();
#endif /* defined(__STDC__) || defined(__cplusplus) */
#ifdef __cplusplus
}
#endif
#endif /* INCibmMalDmah */
vxworks-6.9/target/h/drv/dma/m5200Sdma.h
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/* sysM5200Sdma.h - Motorola MPC5200 Smartcomm DMA controller interface header */
/* Copyright 1990-2005 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,27dec04,k_p cleanups
01a,17Jul03,pkr written
*/
#ifndef __INCm5200Sdmah
#define __INCm5200Sdmah
/* includes */
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sdma_register_set
{
volatile UINT32 taskBar; /* MBAR_SDMA + 0x00 sdTpb */
volatile UINT32 currentPointer; /* MBAR_SDMA + 0x04 sdMdeComplex */
volatile UINT32 endPointer; /* MBAR_SDMA + 0x08 sdMdeComplex */
volatile UINT32 variablePointer; /* MBAR_SDMA + 0x0c sdMdeComplex */
/* The following are Priority Task Decoder (ptd) UINTs in
* sdma/rtl_v/sdPtd.v.
*
* The ptd UINTister map below is from the smartcomm spec, table 3-2,
* page 3-54.
*
* The spec shows the ptd map as 20 words, but sdPtd.v has only
* implemented 19
*
* The word commented out below is the one which is not implemented.
*/
volatile UINT8 IntVect1; /* MBAR_SDMA + 0x10 sdPtd */
volatile UINT8 IntVect2; /* MBAR_SDMA + 0x11 sdPtd */
volatile UINT16 PtdCntrl; /* MBAR_SDMA + 0x12 sdPtd */
volatile UINT32 IntPend; /* MBAR_SDMA + 0x14 sdPtd */
volatile UINT32 IntMask; /* MBAR_SDMA + 0x18 sdPtd */
volatile UINT32 TCR01; /* MBAR_SDMA + 0x1c sdPtd */
volatile UINT32 TCR23; /* MBAR_SDMA + 0x20 sdPtd */
volatile UINT32 TCR45; /* MBAR_SDMA + 0x24 sdPtd */
volatile UINT32 TCR67; /* MBAR_SDMA + 0x28 sdPtd */
volatile UINT32 TCR89; /* MBAR_SDMA + 0x2c sdPtd */
volatile UINT32 TCRAB; /* MBAR_SDMA + 0x30 sdPtd */
volatile UINT32 TCRCD; /* MBAR_SDMA + 0x34 sdPtd */
volatile UINT32 TCREF; /* MBAR_SDMA + 0x38 sdPtd */
volatile UINT8 IPR[32]; /*MBAR_SDMA + 0x3c ..
* MBAR_SDMA + 0x5b sdPtd
*/
volatile UINT32 res1; /* reserved */
volatile UINT32 res2; /* reserved */
volatile UINT32 res3; /* reserved */
volatile UINT32 MDEDebug; /* MBAR_SDMA + 0x68 sdMdeComplex */
volatile UINT32 ADSDebug; /* MBAR_SDMA + 0x6c sdAdsTop */
volatile UINT32 Value1; /* MBAR_SDMA + 0x70 sdDbg */
volatile UINT32 Value2; /* MBAR_SDMA + 0x74 sdDbg */
volatile UINT32 Control; /* MBAR_SDMA + 0x78 sdDbg */
volatile UINT32 Status; /* MBAR_SDMA + 0x7c sdDbg */
volatile UINT32 EU00; /* MBAR_SDMA + 0x80 sdMac macer UINT */
volatile UINT32 EU01; /* MBAR_SDMA + 0x84 sdMac macemr UINT */
volatile UINT32 EU02; /* MBAR_SDMA + 0x88 unused */
volatile UINT32 EU03; /* MBAR_SDMA + 0x8c unused */
volatile UINT32 EU04; /* MBAR_SDMA + 0x90 unused */
volatile UINT32 EU05; /* MBAR_SDMA + 0x94 unused */
volatile UINT32 EU06; /* MBAR_SDMA + 0x98 unused */
volatile UINT32 EU07; /* MBAR_SDMA + 0x9c unused */
volatile UINT32 EU10; /* MBAR_SDMA + 0xa0 unused */
volatile UINT32 EU11; /* MBAR_SDMA + 0xa4 unused */
volatile UINT32 EU12; /* MBAR_SDMA + 0xa8 unused */
volatile UINT32 EU13; /* MBAR_SDMA + 0xac unused */
volatile UINT32 EU14; /* MBAR_SDMA + 0xb0 unused */
volatile UINT32 EU15; /* MBAR_SDMA + 0xb4 unused */
volatile UINT32 EU16; /* MBAR_SDMA + 0xb8 unused */
volatile UINT32 EU17; /* MBAR_SDMA + 0xbc unused */
volatile UINT32 EU20; /* MBAR_SDMA + 0xc0 unused */
volatile UINT32 EU21; /* MBAR_SDMA + 0xc4 unused */
volatile UINT32 EU22; /* MBAR_SDMA + 0xc8 unused */
volatile UINT32 EU23; /* MBAR_SDMA + 0xcc unused */
volatile UINT32 EU24; /* MBAR_SDMA + 0xd0 unused */
volatile UINT32 EU25; /* MBAR_SDMA + 0xd4 unused */
volatile UINT32 EU26; /* MBAR_SDMA + 0xd8 unused */
volatile UINT32 EU27; /* MBAR_SDMA + 0xdc unused */
volatile UINT32 EU30; /* MBAR_SDMA + 0xe0 unused */
volatile UINT32 EU31; /* MBAR_SDMA + 0xe4 unused */
volatile UINT32 EU32; /* MBAR_SDMA + 0xe8 unused */
volatile UINT32 EU33; /* MBAR_SDMA + 0xec unused */
volatile UINT32 EU34; /* MBAR_SDMA + 0xf0 unused */
volatile UINT32 EU35; /* MBAR_SDMA + 0xf4 unused */
volatile UINT32 EU36; /* MBAR_SDMA + 0xf8 unused */
volatile UINT32 EU37; /* MBAR_SDMA + 0xfc unused */
} sdma_regs;
extern sdma_regs *sysSDMA;
#define SDMA_PTDCNTRL_PE 1
#ifdef __cplusplus
}
#endif
#endif /* __INCm5200Sdmah */
vxworks-6.9/target/h/drv/dma/mpc107Dma.h
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/* mpc107Dma.h - MPC107 DMA registers definitions */
/* Copyright 1984-2000, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,11sep00,rcs fix include path for mpc107.h
01a,06jun00,bri written
*/
#ifndef __INCmpc107Dmah
#define __INCmpc107Dmah
/* includes */
#include "drv/multi/mpc107.h"
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
/* MPC107 configuration registers for DMA interface */
#define MPC107_DMA_EUMBBAR 0x1000 /* Offset of DMA registers */
/* in EUMBBAR Space */
/* DMA Channel Zero Register Definitions */
#define MPC107_DMA_DMR0 (MPC107_DMA_EUMBBAR + 0x100)/* Mode Register */
#define MPC107_DMA_DSR0 (MPC107_DMA_EUMBBAR + 0x104)/* Status Register */
#define MPC107_DMA_CDAR0 (MPC107_DMA_EUMBBAR + 0x108)/* Current Descriptor */
#define MPC107_DMA_SAR0 (MPC107_DMA_EUMBBAR + 0x110)/* Source Address */
#define MPC107_DMA_DAR0 (MPC107_DMA_EUMBBAR + 0x118)/* Destination Address */
#define MPC107_DMA_BCR0 (MPC107_DMA_EUMBBAR + 0x120)/* Byte Count */
#define MPC107_DMA_NDAR0 (MPC107_DMA_EUMBBAR + 0x124)/* Next Descriptor */
/* DMA Channel One Register Definitions */
#define MPC107_DMA_DMR1 (MPC107_DMA_EUMBBAR + 0x200) /* Mode Register */
#define MPC107_DMA_DSR1 (MPC107_DMA_EUMBBAR + 0x204) /* Status Register */
#define MPC107_DMA_CDAR1 (MPC107_DMA_EUMBBAR + 0x208) /* Current Descriptor */
#define MPC107_DMA_SAR1 (MPC107_DMA_EUMBBAR + 0x210) /* Source Address */
#define MPC107_DMA_DAR1 (MPC107_DMA_EUMBBAR + 0x218) /* Destination Address */
#define MPC107_DMA_BCR1 (MPC107_DMA_EUMBBAR + 0x220) /* Byte Count */
#define MPC107_DMA_NDAR1 (MPC107_DMA_EUMBBAR + 0x224) /* Next Descriptor */
/* Bit Definitions */
/* Mode Register Bit Definitons */
#define MPC107_DMA_DMR_CS 0x00000001 /* Channel Start */
#define MPC107_DMA_DMR_CC 0x00000002 /* Channel Continue */
#define MPC107_DMA_DMR_CTM 0x00000004 /* Direct DMA mode */
/* Channel Transfer */
#define MPC107_DMA_DMR_DL 0x00000008 /* Descriptor Location */
#define MPC107_DMA_DMR_EOTIE 0x00000080 /* End of Transfer */
/* Interrupt Enable */
#define MPC107_DMA_DMR_EIE 0x00000100 /* Error Interrupt Enable */
#define MPC107_DMA_DMR_PDE 0x00040000 /* Periodic DMA Enable */
/* Status Register Bit Definitions */
#define MPC107_DMA_DSR_EOCAI 0x00000001 /* End of chain or */
/* direct Interrupt */
#define MPC107_DMA_DSR_EOSI 0x00000002 /* End of Segment Interrupt */
#define MPC107_DMA_DSR_CB 0x00000004 /* Channel Busy */
#define MPC107_DMA_DSR_PE 0x00000010 /* PCI Error */
#define MPC107_DMA_DSR_LME 0x00000080 /* Local Memory Error */
/* Current Descriptor Address Register Bit definitions */
#define MPC107_DMA_CDAR_CTT_SHIFT 0x2 /* Transfer Type Shift */
#define MPC107_DMA_CDAR_ADDR_MASK 0xffffffc0 /* Address Mask */
#define MPC107_DMA_CDAR_EOSIE 0x00000008 /* End of Segment Interrupt */
#define MPC107_DMA_CDAR_SNEN 0x00000010 /* Snoop Enable */
/* Next Descriptor Address Register Bit definitions */
#define MPC107_DMA_NDAR_EOTD 0x00000001 /* End of transfer descriptor */
#define MPC107_DMA_NDAR_NDEOSIE 0x00000008 /* Next descriptor */
/* end-of-segment interrupt */
/* enable */
#define MPC107_DMA_NDAR_NDSNEN 0x00000010 /* Snoop Enable */
#define MPC107_DMA_NDAR_ADDR_MASK 0xffffffc0 /* Address Mask */
/*
* DMA 0 Mode register default value
* Error Interrupt Disabled ,End of Transfer
* Interrupt Disabled and Direct Mode DMA transfer
*/
#define MPC107_DMA_DMR0_DEFAULT 0x04
/*
* DMA 1 Mode register default value
* Error Interrupt Disabled ,End of Transfer
* Interrupt Disabled and Direct Mode DMA transfer
*/
#define MPC107_DMA_DMR1_DEFAULT 0x04
/* General Definitions */
#define MPC107_DMA_CHANNEL0 0x0 /* Channel Zero */
#define MPC107_DMA_CHANNEL1 0x1 /* Channel One */
#define MPC107_DMA_MEM_ALIGN 0x3 /* For aligining to 8 words */
/* 2exp3 = 8 */
#define MPC107_DMA_CH_BUSY_MASK 0x00000001 /* Channel busy mask */
#define MPC107_DMA_TIMEOUT_BUSY 0x10000
/* Error Numbers and Return Values */
#define MPC107_DMA_PERIODIC_CH 0x01 /* Channel configured for */
/* Periodic DMA */
#define MPC107_DMA_CHAIN_CH 0x02 /* Channel configured for */
/* Chained DMA */
#define MPC107_DMA_DIRECT_CH 0x03 /* Channel configured for */
/* Direct DMA */
#define MPC107_DMA_PERIODIC_CH_FREE 0x04 /* periodic DMA is configured */
/* and channel is free */
#define MPC107_DMA_PERIODIC_CH_BUSY 0x05 /* "periodic" DMA is configured */
/* and channel is Busy */
#define MPC107_DMA_CHAIN_CH_FREE 0x06 /* chained DMA is configured */
/* and channel is free */
#define MPC107_DMA_CHAIN_CH_BUSY 0x07 /* chained DMA is configured */
/* and channel is busy */
#define MPC107_DMA_DIRECT_CH_FREE 0x08 /* direct DMA is configured */
/* and channel is free */
#define MPC107_DMA_DIRECT_CH_BUSY 0x09 /* direct DMA is configured */
/* and channel is busy */
#define MPC107_DMA_NUM_BYTES 0x0a /* Number of bytes is zero */
#define MPC107_DMA_UNDEF_CH 0x0b /* Undefined Channel Number */
/* typedefs */
/*
* Descriptors for Chained /Periodic DMA transfers .
* Descriptors should be alligned on a 8 word byte boundary
*/
typedef struct mpc107DmaDescriptors
{
UCHAR *pSourceAddress; /* Pointer to Source address */
ULONG reserved1; /* Reserved 1 */
UCHAR *pDestinationAddress; /* Pointer to Destination address */
ULONG reserved2; /* Reserved 2 */
struct mpc107DmaDescriptors *pNextDescriptorAddress; /* Pointer to next */
/* descriptor */
ULONG reserved3; /* Reserved 3 */
ULONG numberOfBytes; /* Number of bytes */
ULONG reserved4; /* Reserved 4 */
} MPC107_DMA_DESCRIPTOR;
/* function declrations */
IMPORT void mpc107DmaInit (void);
IMPORT STATUS mpc107DmaStartDirect (UINT32 channelNumber, UINT32 transferType,
UINT32 sourceAddress ,
UINT32 destinationAddress,
UINT32 numberOfBytes);
IMPORT STATUS mpc107DmaChainedStart (UINT32 channelNumber,UINT32 timePeriod);
IMPORT STATUS mpc107DmaPeriodicStop (UINT32 channelNumber );
IMPORT STATUS mpc107DmaBuildDecsriptor (UINT32 channelNumber,
UCHAR *pSourceAddress,
UCHAR *pDestinationAddress,
UINT32 transferType,
UINT32 numberOfBytes);
IMPORT INT32 mpc107DmaStatus (ULONG channel);
#ifdef __cplusplus
}
#endif
#endif /* __INCmpc107Dmah */
vxworks-6.9/target/h/drv/dma/we32104.h
+143
View File
@@ -0,0 +1,143 @@
/* we32104.h - Western Electric 32104 DMA controller header file */
/* Copyright 1984-1992 Wind River Systems, Inc. */
/*
modification history
--------------------
01f,22sep92,rrr added support for c++
01e,26may92,rrr the tree shuffle
01d,26may92,ajm got rid of HOST_DEC def's (new compiler)
updated copyright
01c,04oct91,rrr passed through the ansification filter
-changed copyright notice
01b,28sep91,ajm ifdef'd HOST_DEC for compiler problem
01e,02Aug91,rfs created
*/
#ifndef __INCwe32104h
#define __INCwe32104h
#ifdef __cplusplus
extern "C" {
#endif
typedef struct we32104_chan
{
volatile u_int SourceAdd;
volatile u_int DestAdd;
u_int Dummy1;
volatile u_int BaseAdd;
volatile u_int TranCount;
u_int Dummy2;
volatile u_int IntVect;
u_int Dummy3;
volatile u_int StatCont;
u_int Mode;
u_int DevControl;
u_int Fill [21];
} WE32104_CHAN;
typedef struct we32104
{
WE32104_CHAN Ch0;
WE32104_CHAN Ch1;
WE32104_CHAN Ch2;
WE32104_CHAN Ch3;
u_int Dummy1 [4];
u_int Mask;
u_int Dummy5 [123];
volatile u_int DataBuf0 [8];
u_int Dummy6 [24];
volatile u_int DataBuf1 [8];
u_int Dummy7 [24];
volatile u_int DataBuf2 [8];
u_int Dummy8 [24];
volatile u_int DataBuf3 [8];
} WE32104;
/***** mode register bit defs *****/
#define MODE_IE 0x0004 /* interrupt enable */
#define MODE_DS_MASK 0x00e0 /* system buss data size bits */
#define MODE_DS_CHAR 0x00e0 /* size is 8 bits */
#define MODE_DS_SHORT 0x00c0 /* size is 16 bits */
#define MODE_DS_LONG 0x0080 /* size is 32 bits */
#define MODE_DS_DOUBLE 0x00a0 /* size is 64 bits */
#define MODE_DS_QUAD 0x0000 /* size is 128 bits */
#define MODE_DAC 0x0200 /* dest addr constant */
#define MODE_SAC 0x0800 /* src addr constant */
#define MODE_TT_MASK 0x6000 /* transfer type bits */
#define MODE_TT_MM 0x0000 /* memory to memory */
#define MODE_TT_PM 0x2000 /* peripheral to memory */
#define MODE_TT_MP 0x4000 /* memory to peripheral */
#define MODE_TT_MF 0x6000 /* memory fill */
#define MODE_BR 0x8000 /* burst mode */
/***** device control register bit defs *****/
#define DCR_PA_MASK 0x007c /* peripheral buss address bits.
* there are 32 possible addresses,
* too many to give indidual defs.
*/
#define DCR_SF_MASK 0x0380 /* stretch field bits, in sync mode */
#define DCR_SF_0 0x0000 /* insert 0 wait state */
#define DCR_SF_1 0x0010 /* insert 1 wait state, etc. */
#define DCR_SF_2 0x0100
#define DCR_SF_4 0x0180
#define DCR_SF_8 0x0200
#define DCR_SF_16 0x0280
#define DCR_SF_32 0x0300
#define DCR_SF_64 0x0380
#define DCR_SA_MASK 0x0400 /* sync/async bit mask */
#define DCR_SYNC 0x0400 /* sync mode, use SF field */
#define DCR_ASYNC 0x0000 /* async mode */
#define DCR_BL 0x2000 /* burst length */
#define DCR_CS_MASK 0xc000 /* peripheral buss chip select bits */
#define DCR_CS_0 0x0000 /* chip select 0 */
#define DCR_CS_1 0x4000 /* chip select 1 */
#define DCR_CS_2 0x8000 /* chip select 2 */
#define DCR_CS_3 0xc000 /* chip select 3 */
/***** status and control register bit defs *****/
#define SCR_NT 0x0001 /* normal transfer complete */
#define SCR_ERR_MASK 0x0037 /* error bits mask */
#define SCR_ERR_NONE 0x0000
#define SCR_ERR_BERR 0x0002 /* buss error */
#define SCR_ERR_CS 0x0004 /* CS pin active when master */
#define SCR_ERR_SA 0x0008 /* software abort issued */
#define SCR_ERR_TIME 0x0020 /* peripheral buss time out */
#define SCR_ACT 0x0100 /* channel is active status */
#define SCR_SA 0x0200 /* software abort cmd */
#define SCR_HB 0x0400 /* channel halt cmd */
#define SCR_STR 0x0800 /* channel start cmd */
#define SCR_CH 0x1000 /* use chaining cmd */
/***** mask register bit defs *****/
#define MASK_CH0 0x1
#define MASK_CH1 0x2
#define MASK_CH2 0x4
#define MASK_CH3 0x8
#ifdef __cplusplus
}
#endif
#endif /* __INCwe32104h */