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neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
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vxworks-6.9/target/h/arch/simnt/archSimnt.h
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/* archSimnt.h - i86 VxSim specific header */
/*
* Copyright (c) 1997-2008,2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
02q,07feb11,rlp Enabled system mode agent for LP64.
02p,27oct10,zl defined _WRS_ARCH_DEFERS_KERNEL_UNLOCK (WIND00227404
and WIND00232955).
02o,16sep10,gls added VX_OBJ_ALIGN_SIZE
02n,13sep10,elp fixed STACK_ALIGN_SIZE.
02m,29jul10,pad Moved extern C statement after include statements.
02m,26may10,dbt Fixed idle mode if no power management is enabled.
02l,01feb10,elp 64 bits support: added _WRS_MMU_HAS_BLOCK_INFO_API.
02k,27aug08,jpb Renamed VSB header file
02j,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
02i,13mar08,rlp Removed obsolete _WRS_ARCH_HAS_DBG_IPI macro.
02h,15aug07,mmi add _WRS_ARCH_HAS_CPU_PWR_MGMT
02g,14may07,elp added _WRS_MMU_HAS_MAP_STATE_API
02f,04may07,zl updated portable library build configuration.
02e,25apr07,kk move VX_MAX_SMP_CPUS to here
02d,05apr07,rlp Added _WRS_ARCH_HAS_DBG_IPI macro.
02c,07mar07,jmg Added include for vxPortableP.h
02b,14feb07,elp added SIMNT SMP support.
02a,13dec06,kk removed references to _WRS_BASE6_SCHEDULER and
_WRS_ARCH_HAS_RESCHEDULE_STACK, no longer needed
01z,08dec06,elp removed _WRS_HAS_RESCHEDULE_STACK.
01y,27jul06,elp Added WRS_ARCH_HAS_RESCHEDULE_STACK, _WRS_VX_NO_GLOBAL_ERRNO.
01x,12apr05,kk removed _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
01w,31mar05,elp added _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK macro
01v,27aug04,dbt Added _WRS_OBJLIB_SUPPORT_VERIFY_TRAP.
01u,18may04,tam removed _WRS_KERNEL_TEXT_START_ADRS definition
01t,18may04,jmp fixed _WRS_FRAMEP_FROM_JMP_BUF macro.
01s,15may04,zl fixed _WRS_FRAMEP_FROM_JMP_BUF()
01r,14may04,jmp removed obsolete stuff.
01q,23mar04,jmp added support for portable trcLib.
added macros for getting frame and return PC from a jmp_buf.
01p,09feb04,aeg moved _WRS_PAL_COPROC_LIB to archSimntCommon.h
01o,04dec03,dbt Added support for DIAB compiler.
01n,02dec03,dbt Updated power management support.
01m,25nov03,pes Move definition of _BYTE_ORDER to arch<Arch>Common.h.
01l,14nov03,job Moved blib stuff to archSimntCommon.h
01k,13nov03,pes Add include of common header
01j,23sep03,dbt Use new B6 scheduler.
01i,18aug03,dbt Added PAL support for VxSim.
01h,22jul03,kam removed define of WV_INSTRUMENTATION
01g,28may03,jmp removed X86_EXT structure.
01f,22apr03,dbt Added _WRS_ARCH_IS_SIMULATOR definition.
01e,27mar03,jmp added X86_EXT. no longer include ntcontext.h
01d,13mar01,sn SPR 73723 - define supported toolchains
01c,21sep01,jmp only include ntcontext.h if _ASMLANGUAGE not defined
(SPR# 34669).
01b,29jul98,ms added WV_INSTRUMENTATION
01a,03sep97,cym written
*/
#ifndef __INCarchSimnth
#define __INCarchSimnth
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Begin PAL */
#define _ALLOC_ALIGN_SIZE 8 /* 8-byte alignment */
#ifdef _WRS_CONFIG_LP64
/* 16-bytes alignment for sse and sse2 instructions */
#define _STACK_ALIGN_SIZE 16
#else
#define _STACK_ALIGN_SIZE 8 /* 8-byte alignment */
#endif /* _WRS_CONFIG_LP64 */
/*
* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
* This is used for both statically and dynamically allocated objects.
*/
#define VX_OBJ_ALIGN_SIZE 8 /* 8-byte alignment */
#define _DYNAMIC_BUS_SIZING FALSE /* no dynamic bus sizing */
#ifdef _WRS_CONFIG_LP64
/* 64-bit Virt and Physical addresses */
#define _WRS_PHYS_ADDR_IS_64_BITS
#define _TYPE_PHYS_ADDR typedef unsigned long PHYS_ADDR
#define _TYPE_VX_PHYS_ADDR typedef unsigned long _Vx_PHYS_ADDR
#endif /* _WRS_CONFIG_LP64 */
#define _WRS_ARCH_IS_SIMULATOR /* This is a simulator */
#define _WRS_VX_NO_GLOBAL_ERRNO /* no longer save errno on ctx switch */
#define _WRS_ARCH_HAS_IDLE_TASK
#define _WRS_ARCH_HAS_NEW_KERNEL_LOCK
#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
/* defer kernel unlock to windLoadContext() */
#define _WRS_ARCH_DEFERS_KERNEL_UNLOCK
/* specify that arch supports cpu power management framework */
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
#define _ARCH_SUPPORTS_GCC /* GCC compiler is supported on this arch. */
#define _ARCH_SUPPORTS_DCC /* DCC compiler is supported on this arch. */
/* Used in usrDepend.c and usrKernelStack.c */
#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
/* moved here from h/private/javaLibP.h */
#define JAVA_C_SYM_PREFIX ""
#ifndef _ASMLANGUAGE
/* macros for getting frame and return PC from a jmp_buf */
#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_fp)
#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
#endif /* _ASMLANGUAGE */
/* from loadElfLib.c */
#define _WRS_USE_ELF_LOAD_FORMAT
/* from xdr_float.c */
#define FLOAT_NORM
/* from schedLib.c */
#define _WRS_VXLIB_SUPPORT
#ifdef _WRS_CONFIG_SMP
#define _WRS_ENABLE_IDLE_INTS intCpuUnlock (0)
#else
/*
* There is no need to unlock interrupts in UP VxSim in order to enter
* idle mode unless power management is not enabled.
*/
#define _WRS_ENABLE_IDLE_INTS \
if (_func_cpuPwrIdleEnter == NULL) intCpuUnlock (0)
#endif /* _WRS_CONFIG_SMP */
#undef VX_MAX_SMP_CPUS
#define VX_MAX_SMP_CPUS 32 /* maximum processors in SMP configuration */
/* from spyLib.c */
#define _WRS_SPY_TASK_SIZE 10000
/* arch support new MMU APIs */
#define _WRS_MMU_HAS_MAP_STATE_API
#define _WRS_MMU_HAS_SPL_TRANSLATE_API
#define _WRS_MMU_HAS_BLOCK_INFO_API
/* End PAL */
#ifdef __cplusplus
}
#endif
#if (CPU==SIMLINUX)
#include "arch/simlinux/archSimlinuxCommon.h"
#elif (CPU==SIMNT)
#include "arch/simnt/archSimntCommon.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*
* Since on host side ULONG is always a 32 bits on Windows, we use VXSIM_ULONG
* instead. VXSIM_ULONG follows ILP32 and LP64 models
*/
#ifndef _ASMLANGUAGE
typedef unsigned long VXSIM_ULONG;
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCarchSimnth */
vxworks-6.9/target/h/arch/simnt/archSimntCommon.h
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/* archSimpentiumCommon.h - common PENTIUM VxSim architecture specific header */
/*
* Copyright 2003-2004, 2006-2007, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01k,23mar12,jpb Updated for POSIX namespace isolation conformance (part of
defect Defect WIND000307800).
01j,04may07,zl updated portable library build configuration.
01i,14feb06,pes Updated for POSIX namespace conformance
01h,13may04,zl enabled user-mode trcLib
01g,22apr04,jmp added support for portable trcLib.
01f,23mar04,dbt Updated comments.
01e,09feb04,aeg added _WRS_PAL_COPROC_LIB
01d,25nov03,pes Move definition of _BYTE_ORDER to arch<Arch>Common.h.
01c,17nov03,jmp added SYSCALL_TRAP_HANDLE_INIT.
01b,12nov03,job Moved some blib stuff from archSimnt.h
01a,11nov03,pes written.
*/
#ifndef __INCarchSimpentiumCommonh
#define __INCarchSimpentiumCommonh
#ifdef __cplusplus
extern "C" {
#endif
#define _BYTE_ORDER _LITTLE_ENDIAN
#ifndef _ASMLANGUAGE
typedef unsigned char _Vx_INSTR; /* char instructions */
#endif /* !_ASMLANGUAGE */
#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) && \
!defined(_POSIX_AEP_RT_CONTROLLER_C_SOURCE)
/* from bLib.c */
#define _WRS_BLIB_ALIGNMENT 3 /* quad byte alignment mask */
/*
* SYSCALL_TRAP_HANDLE_INIT - system call trap magic number
*
* On VxSim, the system call infrastucture is based on a mechanism to directly
* call kernel services from RTP via the syscallTrapHandle() routine.
* Since the RTP does not have access to syscallTrapHandle() routine, each RTP
* contains a function pointer _func_syscallTrapHandle which is initialized to
* an invalid address: SYSCALL_TRAP_HANDLE_INIT. On the first system call
* performed by the RTP, an exception will be generated, the exception
* handling will invoke syscallTrapHandlerInit() if installed, and
* syscallTrapHandlerInit() will fix _func_syscallTrapHandle to point to
* syscallTrapHandle().
*/
#define SYSCALL_TRAP_HANDLE_INIT 0x1234
/* Enable Coprocessor Abstraction */
#define _WRS_PAL_COPROC_LIB
#define _WRS_TRC_ARGS_COUNT 5 /* number of arguments to print in */
/* stack trace */
#ifndef _ASMLANGUAGE
typedef _Vx_INSTR INSTR;
#endif /* !_ASMLANGUAGE */
#endif /* !_POSIX_xxx_SOURCE */
#ifdef __cplusplus
}
#endif
#endif /* __INCarchSimpentiumCommonh */
vxworks-6.9/target/h/arch/simnt/asmSimnt.h
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/* asmSimpentium.h - i86 simulator assembler definitions header file */
/*
* Copyright (c) 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,12feb10,elp written to select 32 or 64bits version
*/
#ifndef __INCasmSimpentiumh
#define __INCasmSimpentiumh
#include <vsbConfig.h>
#ifdef _WRS_CONFIG_LP64
#ifdef _WRS_KERNEL
#if CPU==SIMNT
#include <arch/simnt/asmSimpentium64.h>
#elif CPU==SIMLINUX
#include <arch/simlinux/asmSimpentium64.h>
#endif
#else /* _WRS_KERNEL */
#include <arch/simpentium/asmSimpentium64.h>
#endif /* _WRS_KERNEL */
#else /* __WRS_CONFIG_LP64 */
#ifdef _WRS_KERNEL
#if CPU==SIMNT
#include <arch/simnt/asmSimpentium32.h>
#elif CPU==SIMLINUX
#include <arch/simlinux/asmSimpentium32.h>
#endif
#else /* _WRS_KERNEL */
#include <arch/simpentium/asmSimpentium32.h>
#endif /* _WRS_KERNEL */
#endif /* _WRS_CONFIG_LP64 */
#endif /* __INCasmSimpentiumh */
vxworks-6.9/target/h/arch/simnt/asmSimpentium32.h
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/* asmI86.h - i80x86 assembler definitions header file */
/*
* Copyright (c) 1992,1993.1998,2001,2003,2006,2008
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01o,26mar08,dbt Added FUNC_BEGIN & FUNC_END macros (Defect WIND00066731)
01n,21jul06,scm Move SMP macros to private header.
01m,13jul06,scm correct for UNI mode RTP/OSM support...
01l,07jul06,scm update macros for smp/uni...
01k,28jun06,scm SMP GDT support macros added.
01j,06jun06,scm Add SMP support.
01i,17nov05,zmm Use .type directive to declare assembly language symbols that
weren't typed properly by GNU assembler. SPR 114490.
01h,04may04,dbt Added ARG8-12 and SP_ARG8-12.
01g,17nov03,jb Adding additional ARG defines
01f,01nov01,hdn added ARG8 and SP_ARG8
01e,01oct01,pad Turn off the underscore prepending to assembly routines.
01d,14aug01,hdn imported FUNC/FUNC_LABEL GTEXT/GDATA macros from T31 ver 01i
01c,28aug98,hdn added INT_CONNECT_CODE29 for intEnt().
01b,07jun93,hdn added support for c++
01a,28feb92,hdn written based on TRON, 68k version.
*/
#ifndef __INCasmI86h
#define __INCasmI86h
/************************************************************/
/*
* The following definitions are used for symbol name compatibility.
*
* When #if 1, sources are assembled assuming the compiler
* you are using does not generate global symbols prefixed by "_".
* (e.g. elf/dwarf)
*
* When #if 0, sources are assembled assuming the compiler
* you are using generates global symbols prefixed by "_".
* (e.g. coff/stabs)
*/
#if TRUE
#define FUNC(sym) sym
#define FUNC_LABEL(sym) sym:
#else
#define FUNC(sym) _##sym
#define FUNC_LABEL(sym) _##sym:
#endif
#define VAR(sym) FUNC(sym)
/*
* These macros are used to declare assembly language symbols that need
* to be typed properly(func or data) to be visible to the OMF tool.
* So that the build tool could mark them as an entry point to be linked
* correctly. This is an elfism. Use #if 0 for a.out.
*/
#if TRUE
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@function
#define GDATA(sym) FUNC(sym) ; .type FUNC(sym),@object
#else
#define GTEXT(sym) FUNC(sym)
#define GDATA(sym) FUNC(sym)
#endif
/* Introduced to abstract assembler idiosyncrasies */
#define FUNC_BEGIN(func) FUNC_LABEL(func)
#define FUNC_END(func) .size FUNC(func), . - FUNC(func)
/************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/* fp offsets to arguments */
#define ARG1 8
#define ARG1W 10
#define ARG2 12
#define ARG2W 14
#define ARG3 16
#define ARG3W 18
#define ARG4 20
#define ARG5 24
#define ARG6 28
#define ARG7 32
#define ARG8 36
#define ARG9 40
#define ARG10 44
#define ARG11 48
#define ARG12 52
#define DARG1 8 /* double arguments */
#define DARG1L 12
#define DARG2 16
#define DARG2L 20
#define DARG3 24
#define DARG3L 28
#define DARG4 32
#define DARG4L 36
/* sp offsets to arguments */
#define SP_ARG0 0
#define SP_ARG1 4
#define SP_ARG1W 6
#define SP_ARG2 8
#define SP_ARG2W 10
#define SP_ARG3 12
#define SP_ARG3W 14
#define SP_ARG4 16
#define SP_ARG5 20
#define SP_ARG6 24
#define SP_ARG7 28
#define SP_ARG8 32
#define SP_ARG9 36
#define SP_ARG10 40
#define SP_ARG11 44
#define SP_ARG12 48
/* offset to the IRQ number in the intConnectCode[] */
#define INT_CONNECT_CODE29 24 /* from the return address of intEnt() */
#ifdef __cplusplus
}
#endif
#endif /* __INCasmI86h */
vxworks-6.9/target/h/arch/simnt/asmSimpentium64.h
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/* asmX86_64.h - x86_64 assembler definitions header file */
/*
* Copyright (c) 2009
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,17mar09,jb Update INT_CONNECT_CODE29
01a,20jan09,jb Derived from 32-bit version 01o
*/
#ifndef __INCasmX86_64h
#define __INCasmX86_64h
/************************************************************/
/*
* The following definitions are used for symbol name compatibility.
*
* When #if 1, sources are assembled assuming the compiler
* you are using does not generate global symbols prefixed by "_".
* (e.g. elf/dwarf)
*
* When #if 0, sources are assembled assuming the compiler
* you are using generates global symbols prefixed by "_".
* (e.g. coff/stabs)
*/
#if TRUE
#define FUNC(sym) sym
#define FUNC_LABEL(sym) sym:
#else
#define FUNC(sym) _##sym
#define FUNC_LABEL(sym) _##sym:
#endif
#define VAR(sym) FUNC(sym)
/*
* These macros are used to declare assembly language symbols that need
* to be typed properly(func or data) to be visible to the OMF tool.
* So that the build tool could mark them as an entry point to be linked
* correctly. This is an elfism. Use #if 0 for a.out.
*/
#if TRUE
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@function
#define GDATA(sym) FUNC(sym) ; .type FUNC(sym),@object
#else
#define GTEXT(sym) FUNC(sym)
#define GDATA(sym) FUNC(sym)
#endif
/* Introduced to abstract assembler idiosyncrasies */
#define FUNC_BEGIN(func) FUNC_LABEL(func)
#define FUNC_END(func) .size FUNC(func), . - FUNC(func)
/************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*
* fp offsets to arguments
*
* In 64-bits the first six arguments are in registers,
* the rest are on the stack. ARG0 - ARG6 should not
* be used.
*/
#define ARG7 16
#define ARG8 24
#define ARG9 32
#define ARG10 40
#define ARG11 48
#define ARG12 56
/* Should not be any double args. Will be in registers? */
#if 0
#define DARG1 8 /* double arguments */
#define DARG1L 12
#define DARG2 16
#define DARG2L 20
#define DARG3 24
#define DARG3L 28
#define DARG4 32
#define DARG4L 36
#endif
/*
* sp offsets to arguments
*
* In 64-bits the first six arguments are in registers,
* the rest are on the stack. SP_ARG0 - SP_ARG6 should
* not be used.
*/
#define SP_ARG7 0
#define SP_ARG8 8
#define SP_ARG9 16
#define SP_ARG10 24
#define SP_ARG11 32
#define SP_ARG12 40
/* offset to the IRQ number in the intConnectCode[] */
#define INT_CONNECT_CODE29 26 /* from the return address of intEnt() */
#ifdef __cplusplus
}
#endif
#endif /* __INCasmX86_64h */
vxworks-6.9/target/h/arch/simnt/coprocSimnt.h
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/* coprocSimsolaris.h - coprocessor management library header */
/*
* Copyright 2004, 2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify, or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01c,15may12,jmp CQID: Fix WIND00309977 : Added VX_COPROCS_ALL_TASK
definition.
01b,28apr10,pad Moved extern C statement after include statements.
01a,19aug04,dbt Written
*/
#ifndef __INCcoprocSimsolarish
#define __INCcoprocSimsolarish
/* includes */
#include "taskLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define VX_FP_TASK VX_COPROC1_TASK
#define VX_COPROCS_ALL_TASK VX_FP_TASK
#ifdef __cplusplus
}
#endif
#endif /* __INCcoprocSimsolarish */
vxworks-6.9/target/h/arch/simnt/dbgSimntLib.h
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/* dbgSimntLib.h - header file for arch dependent portion of debugger */
/*
* Copyright (c) 1998,2004,2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01g,22oct10,jmp Removed obsolete DSM() macro - Replaced by VXDBG_INSTR_CMP().
01f,19may10,elp 64 bits support.
01f,29apr10,pad Moved extern C statement after include statements.
01e,18may04,jmp fixed instrI86.h reference.
01d,07apr04,jmp adapted to share trcArchLib between VxSim/i86 and i86 arches.
01c,11feb04,elg Add syscall instruction size macro.
01b,09feb04,jeg added DSM() macro definition
01a,29apr98,cym written based on x86 version.
*/
#ifndef __INCdbgSimntLibh
#define __INCdbgSimntLibh
/* includes */
#include <vsbConfig.h>
#if (CPU==SIMNT)
#include <arch/simnt/instrSimpentium.h>
#elif (CPU==SIMLINUX)
#include <arch/simlinux/instrSimpentium.h>
#endif /* CPU == SIMNT */
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define BRK_INST 0x1000 /* instruction hardware breakpoint */
#define BRK_DATAW1 0x1400 /* data write 1 byte breakpoint */
#define BRK_DATAW2 0x1500 /* data write 2 byte breakpoint */
#define BRK_DATAW4 0x1700 /* data write 4 byte breakpoint */
#define BRK_DATARW1 0x1c00 /* data read-write 1 byte breakpoint */
#define BRK_DATARW2 0x1d00 /* data read-write 2 byte breakpoint */
#define BRK_DATARW4 0x1f00 /* data read-write 4 byte breakpoint */
#define BRK_HARDWARE 0x1000 /* hardware breakpoint bit */
#define BRK_HARDMASK 0x1f00 /* hardware breakpoint mask */
#define TRACE_FLAG (0x0100) /* TF in EFLAGS */
#define INT_FLAG (0x0200) /* IF in EFLAGS */
#define DBG_INST_ALIGN (1)
#ifndef _ASMLANGUAGE
#define BREAK_INST 0xcc /* int 3 */
#define DBG_BREAK_INST 0xcc /* int 3 */
#define DBG_SYSCALL_SIZE 2
#define BREAK_ESF EXC_INFO
#define TRACE_ESF EXC_INFO
/* register indexes */
#ifdef _WRS_CONFIG_LP64
#define R15 (0)
#define R14 (1)
#define R13 (2)
#define R12 (3)
#define R11 (4)
#define R10 (5)
#define R9 (6)
#define R8 (7)
#define RDI (8)
#define RSI (9)
#define RBP (10)
#define RSP (11)
#define RBX (12)
#define RDX (13)
#define RCX (14)
#define RAX (15)
#define RFLAGS (16)
#else /* _WRS_CONFIG_LP64 */
#define EDI (0)
#define ESI (1)
#define EBP (2)
#define ESP (3)
#define EBX (4)
#define EDX (5)
#define ECX (6)
#define EAX (7)
#define EFLAGS (8)
#endif /* _WRS_CONFIG_LP64 */
#define _WRS_TRC_ARGS_COUNT 5 /* number of arguments to print in */
/* stack trace */
/* hardware breakpoint registers */
typedef struct /* DBG_REGS */
{
unsigned int db0; /* debug register 0 */
unsigned int db1; /* debug register 1 */
unsigned int db2; /* debug register 2 */
unsigned int db3; /* debug register 3 */
unsigned int db6; /* debug register 6 */
unsigned int db7; /* debug register 7 */
} DBG_REGS;
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* INCdbgSimntLibh */
vxworks-6.9/target/h/arch/simnt/dsmSimntLib.h
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vxworks-6.9/target/h/arch/simnt/elfI86.h
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/* elfI86.h - i86-specific ELF loader header */
/*
* Copyright (c) 2001, 2004-2005, 2009 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software may be
* licensed only pursuant to the terms of an applicable Wind River license
* agreement.
*/
/*
modification history
--------------------
01e,14dec09,pgh Add EM_ARCH_MACHINE_x macro definition.
01d,05jun09,v_r Added ELF64 support (from Professional Services EMT64 Data
Access project).
01c,25jul05,v_r Updated copyright.
01b,27feb04,pad Renamed relocation type R_386_JUMP_SLOT as R_386_JMP_SLOT as
per ABI.
01a,12sep01,pad Backported from TAE 3.1 to T2.2 with necessary adaptations
(base version: elfI86.h@@/main/tor3_x/1).
*/
#ifndef __INCelfI86h
#define __INCelfI86h
#ifdef __cplusplus
extern "C" {
#endif
/*
* The following macros define the ELF machine type values that can be loaded
* into an i86 CPU.
*/
#define EM_ARCH_MACHINE_1 EM_386
#define EM_ARCH_MACHINE_2 EM_486
#define EM_ARCH_MACHINE_3 EM_X86_64
#ifdef _WRS_CONFIG_LP64
#define EM_ARCH_MACHINE EM_X86_64
#else /* _WRS_CONFIG_LP64 */
#define EM_ARCH_MACHINE EM_386
#define EM_ARCH_MACH_ALT EM_486 /* not used */
#endif /* !_WRS_CONFIG_LP64 */
/*
* Relocation Type Definitions
* The only ones that appear in vxWorks archives are "1" and "2"
*/
#define R_386_NONE 0 /* No reloc */
#define R_386_32 1 /* Direct 32 bit */
#define R_386_PC32 2 /* PC relative 32 bit */
#define R_386_GOT32 3 /* 32 bit GOT entry */
#define R_386_PLT32 4 /* 32 bit PLT address */
#define R_386_COPY 5 /* Copy symbol at runtime */
#define R_386_GLOB_DAT 6 /* Create GOT entry */
#define R_386_JMP_SLOT 7 /* Create PLT entry */
#define R_386_RELATIVE 8 /* Adjust by program base */
#define R_386_GOTOFF 9 /* 32 bit offset to GOT */
#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */
/* These 16-bit and 8-bit relocs should never show up */
#define R_386_16 20
#define R_386_PC16 21
#define R_386_8 22
#define R_386_PC8 23
#define R_386_max 24
/* These are GNU extensions to enable C++ vtable garbage collection. */
#define R_386_GNU_VTINHERIT 250
#define R_386_GNU_VTENTRY 251
/* AMD x86-64 relocations. */
#define R_X86_64_NONE 0 /* No reloc */
#define R_X86_64_64 1 /* Direct 64 bit */
#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
#define R_X86_64_PLT32 4 /* 32 bit PLT address */
#define R_X86_64_COPY 5 /* Copy symbol at runtime */
#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative
offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */
#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
#define R_X86_64_8 14 /* Direct 8 bit sign extended */
#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */
#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */
#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */
#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset
to two GOT entries for GD symbol */
#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset
to two GOT entries for LD symbol */
#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */
#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset
to GOT entry for IE symbol */
#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */
#define R_X86_64_PC64 24 /* PC-relative 64 bits */
#define R_X86_64_GOTOFF64 25
#define R_X86_64_GOTPC32 26
#define R_X86_64_SIZE32 32
#define R_X86_64_SIZE64 33
#define R_X86_64_GOTPC32_TLSDESC 34
#define R_X86_64_TLSDESC_CALL 35
#define R_X86_64_TLSDESC 36
#ifdef __cplusplus
}
#endif
#endif /* __INCelfI86h */
vxworks-6.9/target/h/arch/simnt/esfSimnt.h
+39
View File
@@ -0,0 +1,39 @@
/* esfSimsparc.h - vxSim for Windows exception stack frame */
/* Copyright 1993-1995, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,29apr10,pad Moved extern C statement after include statements.
01a,29apr98,cym derived from simsolaris
*/
#ifndef __INCesfSimnth
#define __INCesfSimnth
#include "regs.h"
#include "excLib.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESF EXC_INFO
/* Overflow/Underflow Stack Frame */
#define STACK_FRAME 0x00 /* Stack Frame */
#define SF_LOCALS (STACK_FRAME + 0x00) /* Local Registers */
#define SF_INS (STACK_FRAME + 0x20) /* In Registers */
#define SF_SPARE (STACK_FRAME + 0x5C) /* Spare Slot */
#define STACK_FRAME_SIZE 0x60
#define INIT_STACK_FRAME STACK_ROUND_UP ((((MAX_TASK_ARGS - 6) \
* sizeof (int)) + (STACK_FRAME_SIZE - 4)))
#ifdef __cplusplus
}
#endif
#endif /* __INCesfSimnth */
vxworks-6.9/target/h/arch/simnt/excSimntLib.h
+115
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@@ -0,0 +1,115 @@
/* excSimntLib.h - exception library header */
/*
* Copyright (c) 1998,2000,2003,2004,2006,2007,2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01i,21may10,elp 64bits support.
01h,19jun07,elp added access violation type macros.
01g,08nov06,elp can be included in assembly file
01f,10mar04,dbt Fixed _WRS_IS_SUP_EXC() macro.
01e,09feb04,jmp added _WRS_IS_SUPV_EXC() macro.
01d,21oct03,jmp replaced padding field of EXC_INFO by access type.
01c,28mar03,jmp added exception numbers.
replaced INSTR by UCHAR to use this file from host side.
01b,30may00,elp renamed errCode in accessAddr.
01a,29apr98,cym written based x86 version.
*/
#ifndef __INCexcSimntLibh
#define __INCexcSimntLibh
#ifndef HOST
#include <arch/simnt/archSimnt.h>
#endif /* !HOST */
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/* typedefs */
typedef struct
{
UINT16 valid; /* indicators that following fields are valid */
UINT16 vecNum; /* vector number */
VXSIM_ULONG accessAddr; /* access address */
UCHAR * pc; /* program counter */
UINT32 statusReg; /* status register */
UINT16 csReg; /* code segment register */
UINT16 accessType; /* type of access (read or write) */
} EXC_INFO;
#endif /* _ASMLANGUAGE */
/* defines */
#define _WRS_IS_SUPV_EXC() VXSIM_SUP_MODE_GET(pRegs->reg_status)
#define LOW_VEC 0 /* lowest initialized vector */
#define HIGH_VEC 0xff /* highest initialized vector */
/* exception info valid bits */
#define EXC_VEC_NUM 0x01 /* vector number valid */
#define EXC_ACCESS_READ 0x02 /* accessAddr is valid (READ access) */
#define EXC_ACCESS_WRITE 0x04 /* accessAddr is valid (WRITE access) */
#define EXC_PC 0x08 /* pc valid */
#define EXC_STATUS_REG 0x10 /* status register valid */
#define EXC_CS_REG 0x20 /* code segment register valid */
#define EXC_INVALID_TYPE 0x80 /* special indicator: ESF type was bad;
* type is in funcCode field */
/* access violation type */
#define EXC_READ_ACCESS 0 /* read access violation */
#define EXC_WRITE_ACCESS 1 /* write access violation */
#define EXC_EXEC_ACCESS 8 /* execute access violation */
/* exception numbers */
#define EXC_INT_DIVIDE_BY_ZERO 0
#define EXC_SINGLE_STEP 1
#define EXC_DATATYPE_MISALIGNMENT 2
#define EXC_BREAKPOINT 3
#define EXC_IN_PAGE_ERROR 4
#define EXC_ILLEGAL_INSTRUCTION 5
#define EXC_INVALID_DISPOSITION 6
#define EXC_ARRAY_BOUNDS_EXCEEDED 7
#define EXC_FLT_DENORMAL_OPERAND 8
#define EXC_FLT_DIVIDE_BY_ZERO 9
#define EXC_FLT_INEXACT_RESULT 10
#define EXC_FLT_INVALID_OPERATION 11
#define EXC_FLT_OVERFLOW 12
#define EXC_ACCESS_VIOLATION 13
#define EXC_FLT_STACK_CHECK 14
#define EXC_FLT_UNDERFLOW 15
#define EXC_INT_OVERFLOW 16
#define EXC_PRIV_INSTRUCTION 17
#define EXC_STACK_OVERFLOW 18
#define EXC_UNKNOWN 19
#ifndef _ASMLANGUAGE
/* variable declarations */
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
/* function declarations */
extern void excStub (void);
extern void excIntStub (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCexcSimntLibh */
vxworks-6.9/target/h/arch/simnt/fppSimntLib.h
+287
View File
@@ -0,0 +1,287 @@
/* fppLib.h - floating-point coprocessor support library header */
/*
* Copyright (c) 1998,2002-2003,2010,2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01j,05sep11,elp Added xmm registers to host regset (CQID: WIND00286339)
01i,06apr11,elp added xmm8-xmm15
01h,30sep10,elp fixed FPXREG_FPX() macro.
01g,14sep10,elp Added SSE support (64-bits).
01f,14jan10,elp 64bits support.
01e,19aug03,dbt Added PAL support.
01d,17jun03,jmp code cleanup.
01c,27mar03,jmp rewrote from i86.
01b,03may02,jmp added fppDtoDx() & fppDxtoD().
01a,29apr98,cym derived from i86
*/
#ifndef __INCfppSimntLibh
#define __INCfppSimntLibh
#ifdef __cplusplus
extern "C" {
#endif
/* number of fp registers on coprocessor */
#define FP_NUM_REGS 8 /* number of FP registers */
#define XSAVE_HEADER 64 /* number of bytes in the XSAVE header */
#ifdef _WRS_CONFIG_LP64
#define XMM_NUM_REGS 16 /* number of XMM registers */
#define FP_NUM_RESERVED 6 /* reserved area in FPX_CONTEXT */
/* FPREG_SET structure offsets */
#define FPREG_FPCR 0x00 /* offset to FPCR in FPREG_SET */
#define FPREG_FPSR 0x04 /* offset to FPSR in FPREG_SET */
#define FPREG_FPTAG 0x08 /* offset to FPTAG in FPREG_SET */
#define FPREG_OP 0x0c /* offset to OP in FPREG_SET */
#define FPREG_IP 0x10 /* offset to IP in FPREG_SET */
#define FPREG_CS 0x14 /* offset to CS in FPREG_SET */
#define FPREG_DP 0x18 /* offset to DP in FPREG_SET */
#define FPREG_DS 0x1c /* offset to DS in FPREG_SET */
#define FPREG_FPX(n) (0x20 + (n)*sizeof(DOUBLEX)) /* offset to FPX(n) */
#else /* _WRS_CONFIG_LP64 */
#define XMM_NUM_REGS 8 /* number of XMM registers */
#define FP_NUM_RESERVED 14 /* reserved area in FPX_CONTEXT */
/* FPREG_SET structure offsets */
#define FPREG_FPCR 0x00 /* offset to FPCR in FPREG_SET */
#define FPREG_FPSR 0x04 /* offset to FPSR in FPREG_SET */
#define FPREG_FPTAG 0x08 /* offset to FPTAG in FPREG_SET */
#define FPREG_OP 0x0c /* offset to OP in FPREG_SET */
#define FPREG_IP 0x10 /* offset to IP in FPREG_SET */
#define FPREG_CS 0x12 /* offset to CS in FPREG_SET */
#define FPREG_DP 0x14 /* offset to DP in FPREG_SET */
#define FPREG_DS 0x18 /* offset to DS in FPREG_SET */
#define FPREG_FPX(n) (0x1c + (n)*sizeof(DOUBLEX)) /* offset to FPX(n) */
#endif /* _WRS_CONFIG_LP64 */
/* FPO_CONTEXT structure offsets */
#define FPO_CONTEXT_FPCR 0x00 /* offset to FPCR in FPO_CONTEXT */
#define FPO_CONTEXT_FPSR 0x04 /* offset to FPSR in FPO_CONTEXT */
#define FPO_CONTEXT_FPTAG 0x08 /* offset to FPTAG in FPO_CONTEXT */
#define FPO_CONTEXT_IP 0x0c /* offset to IP in FPO_CONTEXT */
#define FPO_CONTEXT_CS 0x10 /* offset to CS in FPO_CONTEXT */
#define FPO_CONTEXT_OP 0x12 /* offset to OP in FPO_CONTEXT */
#define FPO_CONTEXT_DP 0x14 /* offset to DP in FPO_CONTEXT */
#define FPO_CONTEXT_DS 0x18 /* offset to DS in FPO_CONTEXT */
#define FPO_CONTEXT_FPX(n) (0x1c + (n)*sizeof(DOUBLEX))
/* FPX_CONTEXT - structure offsets for New FP context */
#define FPX_CONTEXT_FPCR 0x00 /* offset to FPCR in FPX_CONTEXT */
#define FPX_CONTEXT_FPSR 0x02 /* offset to FPSR in FPX_CONTEXT */
#define FPX_CONTEXT_FPTAG 0x04 /* offset to FPTAG in FPX_CONTEXT */
#define FPX_CONTEXT_OP 0x06 /* offset to OP in FPX_CONTEXT */
#define FPX_CONTEXT_IP 0x08 /* offset to IP in FPX_CONTEXT */
#define FPX_CONTEXT_CS 0x0c /* offset to CS in FPX_CONTEXT */
#define FPX_CONTEXT_DP 0x10 /* offset to DP in FPX_CONTEXT */
#define FPX_CONTEXT_DS 0x14 /* offset to DS in FPX_CONTEXT */
#define FPX_CONTEXT_RSVD0 0x18 /* offset to RESERVED0 in FPX_CONTEXT */
#define FPX_CONTEXT_RSVD1 0x1c /* offset to RESERVED1 in FPX_CONTEXT */
#define FPX_CONTEXT_FPX(n) (0x20 + (n)*sizeof(DOUBLEX_SSE)) /* FPX(n) */
/* FPU Control Word register */
#define FPCR_PC_MASK 0xfcff /* Precision Control Field mask */
#define FPCR_PC_DOUBLE 0x0200 /* Double precision */
#ifndef _ASMLANGUAGE
/* DOUBLEX - double extended precision */
typedef struct
{
unsigned char f[10];
} DOUBLEX;
typedef struct
{
UCHAR f[10]; /* ST[0-7] or MM[0-7] */
UCHAR r[6]; /* reserved */
} DOUBLEX_SSE;
/* FPO_CONTEXT - Old FP context used by fsave/frstor instruction */
typedef struct fpOcontext
{
int fpcr; /* 0x00: 4 control word */
int fpsr; /* 0x04: 4 status word */
int fptag; /* 0x08: 4 tag word */
int ip; /* 0x0c: 4 instruction pointer */
short cs; /* 0x10: 2 instr pointer selector */
short op; /* 0x12: 2 last FP instr op code */
int dp; /* 0x14: 4 data pointer */
int ds; /* 0x18: 4 data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* 0x1c: 8*10 FR[0-7] non-TOS rel. order */
} FPO_CONTEXT; /* 108 bytes total */
/* FPX_CONTEXT - New FP context used by fxsave/fxrstor instruction */
typedef struct fpXcontext
{
short fpcr; /* 0x00: 2 control word */
short fpsr; /* 0x02: 2 status word */
short fptag; /* 0x04: 2 tag word */
short op; /* 0x06: 2 last FP instr op code */
int ip; /* 0x08: 4 instruction pointer */
int cs; /* 0x0c: 4 instr pointer selector */
int dp; /* 0x10: 4 data pointer */
int ds; /* 0x14: 4 data pointer selector */
int reserved0; /* 0x18: 4 reserved */
int reserved1; /* 0x1c: 4 reserved */
DOUBLEX_SSE fpx[FP_NUM_REGS]; /* 0x20: 8*16 FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 8*16 XMM[0-7] */
DOUBLEX_SSE res2[FP_NUM_RESERVED]; /* 14*16 reserved */
} FPX_CONTEXT; /* 512 bytes total */
/* FPX_EXT_CONTEXT - Extended FP context used by xsave/xrstor instruction */
typedef struct fpXExtContext
{
short fpcr; /* 0x00: 2 control word */
short fpsr; /* 0x02: 2 status word */
short fptag; /* 0x04: 2 tag word */
short op; /* 0x06: 2 last FP instr op code */
int ip; /* 0x08: 4 instr pointer */
int cs; /* 0x0c: 4 instr pointer selector */
int dp; /* 0x10: 4 data pointer */
int ds; /* 0x14: 4 data pointer selector */
int reserved0; /* 0x18: 4 reserved */
int reserved1; /* 0x20: 4 reserved */
DOUBLEX_SSE fpx[FP_NUM_REGS]; /* 0x24: 8*16 FR[0-7] */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 8*16 XMM[0-7] */
DOUBLEX_SSE res2[FP_NUM_RESERVED]; /* 14*16 reserved */
UCHAR xSaveHeader[XSAVE_HEADER]; /* 64 XSave header */
DOUBLEX_SSE ymm[XMM_NUM_REGS]; /* 8*16 higher 128 bits of YMM[0-7] */
} FPX_EXT_CONTEXT; /* 704 bytes total */
/* FP_CONTEXT - Common FP context */
typedef struct fpContext
{
union u
{
FPO_CONTEXT o; /* old FPO_CONTEXT for fsave/frstor */
FPX_CONTEXT x; /* new FPX_CONTEXT for fxsave/fxrstor */
FPX_EXT_CONTEXT x_ext; /* FPX_EXT_CONTEXT xsave/xrestore */
} u;
} FP_CONTEXT;
#ifdef _WRS_CONFIG_LP64
/* FPREG_SET - FP register set that is different from FP_CONTEXT */
typedef struct fpregOSet
{
int fpcr; /* 0x00: control word */
int fpsr; /* 0x04: status word */
int fptag; /* 0x08: tag word */
int op; /* 0x0c: last FP instruction op code */
int ip; /* 0x10: instruction pointer */
int cs; /* 0x14: instruction pointer selector */
int dp; /* 0x18: data pointer */
int ds; /* 0x1c: data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* 0x20: FR[0-7] non-TOS rel. order */
} FPREGO_SET;
#else /* _WRS_CONFIG_LP64 */
typedef FPO_CONTEXT FPREGO_SET;
#endif /* _WRS_CONFIG_LP64 */
typedef struct fpregXSet
{
int fpcr; /* 0x00: control word */
int fpsr; /* 0x04: status word */
int fptag; /* 0x08: tag word */
int op; /* 0x0c: last FP instruction op code */
int ip; /* 0x10: instruction pointer */
int cs; /* 0x14: instruction pointer selector */
int dp; /* 0x18: data pointer */
int ds; /* 0x1c: data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* 0x20: FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* [8|16]*16 XMM[0-[7|15]] */
} FPREGX_SET;
typedef struct fpregXExtSet
{
int fpcr; /* 0x00: control word */
int fpsr; /* 0x04: status word */
int fptag; /* 0x08: tag word */
int op; /* 0x0c: last FP instruction op code */
int ip; /* 0x10: instruction pointer */
int cs; /* 0x14: instruction pointer selector */
int dp; /* 0x18: data pointer */
int ds; /* 0x1c: data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* 0x20: FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* [8|16]*16 XMM[0-[7|15]] */
DOUBLEX_SSE ymm[XMM_NUM_REGS]; /* [8|16]*16 higher 128 bits of YMM */
} FPREGXEXT_SET;
typedef struct fpregSet
{
union n
{
FPREGO_SET o;
FPREGX_SET x;
FPREGXEXT_SET x_ext;
} n;
} FPREG_SET;
/* variable declarations */
extern REG_INDEX fpRegName[]; /* f-point data register table */
extern REG_INDEX fpCtlRegName[]; /* f-point control register table */
extern FUNCPTR fppCreateHookRtn; /* arch dependent create hook routine */
extern FUNCPTR fppDisplayHookRtn; /* arch dependent display routine */
/* func ptr to fppSave/fppXsave */
extern void (* _func_fppSaveRtn) (FP_CONTEXT *);
/* func ptr to fppRestore/fppXrestore */
extern void (* _func_fppRestoreRtn) (FP_CONTEXT *);
/* function declarations */
extern void fppArchInit (void);
extern STATUS fppProbe (void);
extern void fppDtoDx (DOUBLEX * pDx, double * pDouble);
extern void fppDxtoD (double * pDouble, DOUBLEX * pDx);
extern void fppRegsToCtx (FPREG_SET * pFpRegSet, FP_CONTEXT * pFpContext);
extern void fppCtxToRegs (FP_CONTEXT * pFpContext, FPREG_SET * pFpRegSet);
#ifdef _WRS_CONFIG_LP64
extern void fppXregsToCtx (FPREG_SET * pFpRegSet, FP_CONTEXT * pFpContext);
extern void fppXctxToRegs (FP_CONTEXT * pFpContext, FPREG_SET * pFpRegSet);
#endif /* _WRS_CONFIG_LP64 */
extern FP_CONTEXT * fppCtxCreate (TASK_ID tid);
extern STATUS fppCtxDelete (FP_CONTEXT * pCtx);
extern void fppCtxShow (FP_CONTEXT * pFpContext);
extern STATUS fppEnable (void);
extern STATUS fppDisable (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCfppSimntLibh */
vxworks-6.9/target/h/arch/simnt/in_cksum.h
+176
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@@ -0,0 +1,176 @@
/* in_cksum.h - x86 version in_cksum header file */
/* Copyright 2001-2002 Wind River Systems, Inc. */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from tahoe: in_cksum.c 1.2 86/01/05
* from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91
* from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
* $FreeBSD: src/sys/i386/include/in_cksum.h,v 1.7.2.1 2000/05/05 13:37:00 jlemon Exp $
*/
/*
modification history
--------------------
01f,25aug05,dlk Add section tags.
01e,24mar04,m_h INternet Checksum
01d,20nov03,niq Remove copyright_wrs.h file inclusion
01c,15nov03,rp updating header file path
01b,25jul02,rvr removed DCC specific code
01a,13sep01,hsh Created from BSD 4.3
*/
#ifndef _MACHINE_IN_CKSUM_H_
#define _MACHINE_IN_CKSUM_H_ 1
#include <sys/cdefs.h>
/*
* in_cksum_hdr - checksum on header only
*
* It is useful to have an Internet checksum routine which is inlineable
* and optimized specifically for the task of computing IP header checksums
* in the normal case (where there are no options and the header length is
* therefore always exactly five 32-bit words.
*/
static __inline
u_int in_cksum_hdr
(
const struct ip *ip
)
{
register u_int sum = 0;
int hlen = sizeof (struct ip);
register u_short *w = (u_short *) ip;
u_short remaining = 0;
while (hlen > 1)
{
sum += *w++;
hlen -= 2;
}
if (hlen == 1)
{
*(u_char *) (&remaining) = *(u_char *) w;
sum += remaining;
}
sum = (sum & 0xffff) + (sum >> 16);
if (sum > 0xffff)
sum -= 0xffff;
return ~sum & 0xffff;
}
/*
* in_cksum_update
*/
static __inline
void in_cksum_update
(
struct ip *ip
)
{
int __tmpsum;
__tmpsum = (int)ntohs(ip->ip_sum) + 256;
ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
}
/*
* in_pseudo - pre-checksum parts of pseudo-header
*
* Compute significant parts of the IPv4 checksum pseudo-header * for use in a
* delayed TCP/UDP checksum calculation.
*
* Args:
*
* src Source IP address
* dst Destination IP address
* lenproto htons(proto-hdr-len + proto-number)
*/
static __inline
u_int16_t in_pseudo
(
u_int32_t src,
u_int32_t dst,
u_int32_t lenproto
)
{
u_int32_t sum;
sum = lenproto +
(u_int16_t)(src >> 16) +
(u_int16_t)(src /*& 0xffff*/) +
(u_int16_t)(dst >> 16) +
(u_int16_t)(dst /*& 0xffff*/);
sum = (u_int16_t)(sum >> 16) + (u_int16_t)(sum /*& 0xffff*/);
if (sum > 0xffff)
sum -= 0xffff;
return (sum);
}
/*
* in_addword - Add two 16-bit workd
*
* Add the two 16-bit network-order values, carry, and return.
*/
static __inline
u_int16_t in_addword
(
u_int16_t a,
u_int16_t b
)
{
u_int32_t sum = a + b;
if (sum > 0xffff)
sum -= 0xffff;
return (sum);
}
_WRS_FASTTEXT
u_short in_cksum_skip(struct mbuf *m, int len, int skip);
#endif /* _MACHINE_IN_CKSUM_H_ */
vxworks-6.9/target/h/arch/simnt/instrSimpentium.h
+48
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@@ -0,0 +1,48 @@
/* instrSimpentium.h - i86 simulator assembler definitions header file */
/*
* Copyright (c) 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,12feb10,elp written to select 32 or 64bits version
*/
#ifndef __INCinstrSimpentiumh
#define __INCinstrSimpentiumh
#include <vsbConfig.h>
#ifdef _WRS_CONFIG_LP64
#ifdef _WRS_KERNEL
#if CPU==SIMNT
#include <arch/simnt/instrSimpentium64.h>
#elif CPU==SIMLINUX
#include <arch/simlinux/instrSimpentium64.h>
#endif
#else /* _WRS_KERNEL */
#include <arch/simpentium/instrSimpentium64.h>
#endif /* _WRS_KERNEL */
#else /* __WRS_CONFIG_LP64 */
#ifdef _WRS_KERNEL
#if CPU==SIMNT
#include <arch/simnt/instrSimpentium32.h>
#elif CPU==SIMLINUX
#include <arch/simlinux/instrSimpentium32.h>
#endif
#else /* _WRS_KERNEL */
#include <arch/simpentium/instrSimpentium32.h>
#endif /* _WRS_KERNEL */
#endif /* _WRS_CONFIG_LP64 */
#endif /* __INCinstrSimpentiumh */
vxworks-6.9/target/h/arch/simnt/instrSimpentium32.h
+86
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@@ -0,0 +1,86 @@
/* instrI86.h - header for I86 instruction fields */
/* Copyright 2004 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,26apr04,jmp created from target/h/dbgI86Lib.h
*/
/*
* WARNING: This file is shared between i86 and VxSim/i86 arches,
* and between Kernel and User sides.
* Please make sure that any modifications to this file
* does not break other arches.
*/
#ifndef __INCinstrI86h
#define __INCinstrI86h
/* defines */
#define ADDI08_0 (0x83)
#define ADDI08_1 (0xc4)
#define ADDI32_0 (0x81)
#define ADDI32_1 (0xc4)
#define LEAD08_0 (0x8d)
#define LEAD08_1 (0x64)
#define LEAD08_2 (0x24)
#define LEAD32_0 (0x8d)
#define LEAD32_1 (0xa4)
#define LEAD32_2 (0x24)
#define JMPD08 (0xeb)
#define JMPD32 (0xe9)
#define ENTER (0xc8)
#define PUSH_EBX (0x53)
#define PUSH_EBP (0x55)
#define PUSH_ESI (0x56)
#define MOV_ESP0 (0x89)
#define MOV_ESP1 (0xe5)
#define MOV_ESP_ESI (0xe689)
#define LEAVE (0xc9)
#define RET (0xc3)
#define RETADD (0xc2)
#define CALL_DIR (0xe8)
#define CALL_INDIR0 (0xff)
#define CALL_INDIR1 (0x10)
#define CALL_INDIR_REG_EAX (0xd0)
#define CALL_INDIR_REG_ECX (0xd1)
#define CALL_INDIR_REG_EDX (0xd2)
#define CALL_INDIR_REG_EBX (0xd3)
#define MOV_ECX (0x0d8b)
#define MOV_EDX (0x158b)
#define MOV_EBP_ESP (0xe589)
#define ADDI08_0_MASK (0xff)
#define ADDI08_1_MASK (0xff)
#define ADDI32_0_MASK (0xff)
#define ADDI32_1_MASK (0xff)
#define LEAD08_0_MASK (0xff)
#define LEAD08_1_MASK (0xff)
#define LEAD08_2_MASK (0xff)
#define LEAD32_0_MASK (0xff)
#define LEAD32_1_MASK (0xff)
#define LEAD32_2_MASK (0xff)
#define JMPD08_MASK (0xff)
#define JMPD32_MASK (0xff)
#define ENTER_MASK (0xff)
#define PUSH_EBX_MASK (0xff)
#define PUSH_EBP_MASK (0xff)
#define PUSH_ESI_MASK (0xff)
#define MOV_ESP0_MASK (0xff)
#define MOV_ESP1_MASK (0xff)
#define MOV_ESP_ESI_MASK (0xffff)
#define LEAVE_MASK (0xff)
#define RET_MASK (0xff)
#define RETADD_MASK (0xff)
#define CALL_DIR_MASK (0xff)
#define CALL_INDIR0_MASK (0xff)
#define CALL_INDIR1_MASK (0x38)
#define CALL_INDIR_REG_MASK (0xdf)
#define MOV_ECX_MASK (0xffff)
#define MOV_EDX_MASK (0xffff)
#define MOV_EBP_ESP_MASK (0xffff)
#endif /* __INCinstrI86h */
vxworks-6.9/target/h/arch/simnt/instrSimpentium64.h
+129
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@@ -0,0 +1,129 @@
/* instrx86_64.h - header for x86_64 instruction fields */
/*
* Copyright (c) 2004,2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,20sep10,scm add additional trc/dbg constants...
01c,01apr10,scm update instruction codes...
01b,01jun09,scm add REX and RIP idents...
01a,26apr04,jmp created from target/h/dbgI86Lib.h
*/
/*
* WARNING: This file is shared between i86 and VxSim/i86 arches,
* and between Kernel and User sides.
* Please make sure that any modifications to this file
* does not break other arches.
*/
#ifndef __INCinstrI86h
#define __INCinstrI86h
/* defines */
#define ADDI08_0 (0x83)
#define ADDI08_1 (0xc4)
#define ADDI32_0 (0x81)
#define ADDI32_1 (0xc4)
#define ADD_EAX (0x01)
#define SUB_EAX (0x29)
#define INC_EDX (0xff)
#define LEAD08_0 (0x8d)
#define LEAD08_1 (0x64)
#define LEAD08_2 (0x24)
#define LEAD32_0 (0x8d)
#define LEAD32_1 (0xa4)
#define LEAD32_2 (0x24)
#define JMPD08 (0xeb)
#define JMPD32 (0xe9)
#define ENTER (0xc8)
#define SC_PUSH (0x68)
#define PUSH_EBX (0x53)
#define POP_EBX (0x5b)
#define POP_EBP (0x5d)
#define POP_REG (0x50)
#define PUSH_EBP (0x55)
#define PUSH_ESI (0x56)
#define MOV_EAX (0x89)
#define MOV_EDI (0xbf)
#define MOV_ESP0 (0x89)
#define MOV_ESP1 (0xe5)
#define MOV_ESP_ESI (0xe689)
#define MOV_RIP (0x8b)
#define CMP1_EAX (0x39)
#define CMP2_EAX (0x38)
#define LEAVE (0xc9)
#define RET (0xc3)
#define RETADD (0xc2)
#define REX_PRE (0x40)
#define REX_PRE_B (0x41)
#define REX_PRE_X (0x42)
#define REX_PRE_R (0x44)
#define REX_PRE_W (0x48)
#define RIP_REL (0x05)
#define SC_CALL0 (0xff)
#define SC_CALL1 (0x1c)
#define SC_CALL2 (0x25)
#define CALL_DIR (0xe8)
#define CALL_INDIR0 (0xff)
#define CALL_INDIR1 (0x10)
#define CALL_INDIR_REG_EAX (0xd0)
#define CALL_INDIR_REG_ECX (0xd1)
#define CALL_INDIR_REG_EDX (0xd2)
#define CALL_INDIR_REG_EBX (0xd3)
#define MOV_ECX (0x0d8b)
#define MOV_EDX (0x158b)
#define MOV_EBP_ESP (0xe589)
#define ADDI08_0_MASK (0xff)
#define ADDI08_1_MASK (0xff)
#define ADDI32_0_MASK (0xff)
#define ADDI32_1_MASK (0xff)
#define ADD_MASK (0xff)
#define SUB_MASK (0xff)
#define INC_MASK (0xff)
#define LEAD08_0_MASK (0xff)
#define LEAD08_1_MASK (0xff)
#define LEAD08_2_MASK (0xff)
#define LEAD32_0_MASK (0xff)
#define LEAD32_1_MASK (0xff)
#define LEAD32_2_MASK (0xff)
#define JMPD08_MASK (0xff)
#define JMPD32_MASK (0xff)
#define ENTER_MASK (0xff)
#define POP_EBX_MASK (0xff)
#define POP_EBP_MASK (0xff)
#define POP_REG_MASK (0xff)
#define SC_PUSH_MASK (0xff)
#define PUSH_EBX_MASK (0xff)
#define PUSH_EBP_MASK (0xff)
#define PUSH_ESI_MASK (0xff)
#define MOV_MASK (0xff)
#define MOV_ESP0_MASK (0xff)
#define MOV_ESP1_MASK (0xff)
#define MOV_ESP_ESI_MASK (0xffff)
#define MOV_RIP_MASK (0xff)
#define CMP_MASK (0xff)
#define LEAVE_MASK (0xff)
#define RET_MASK (0xff)
#define RETADD_MASK (0xff)
#define REX_PRE_MASK (0xff)
#define RIP_REL_MASK (0xff)
#define SC_CALL_MASK (0xff)
#define CALL_DIR_MASK (0xff)
#define CALL_INDIR0_MASK (0xff)
#define CALL_INDIR1_MASK (0x38)
#define CALL_INDIR_REG_MASK (0xdf)
#define MOV_ECX_MASK (0xffff)
#define MOV_EDX_MASK (0xffff)
#define MOV_EBP_ESP_MASK (0xffff)
#endif /* __INCinstrx86_64h */
vxworks-6.9/target/h/arch/simnt/ivSimnt.h
+69
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@@ -0,0 +1,69 @@
/* ivSimnt.h - simnt interrupt vectors */
/*
* Copyright (c) 1997,2003,2004,2007 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01d,05oct07,elp moved interrupt vector definitions.
01c,09feb04,dat Diab lint fix, chg INUM_TO_IVEC
01b,21may03,jmp moved IV_MAX from intArchLib.c.
01a,06oct97,cym written
*/
#ifndef __INCivSimnth
#define __INCivSimnth
#ifdef __cplusplus
extern "C" {
#endif
/* maximun number of interrupt vectors */
#define IV_MAX 0x0300 /* This value must be coherent with */
/* VXSIM_MAX_INTS defined on host side. */
/* See vxsimwin32.h . */
/* macros to convert interrupt vectors <-> interrupt numbers */
#define IVEC_TO_INUM(intVec) (intVec)
#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *)intNum)
#define IVEC_TO_MESSAGE(intVec) (intVec)
#define MESSAGE_TO_IVEC(message) (message)
/* interrupt vector definitions */
#define TIMER_SYS_CLK_INT 0x0000 /* System clock interrupt */
#define TIMER_AUX_CLK_INT 0x0001 /* Auxiliary clock interrupt */
#define TIMER_TS_ROLL_OVER_INT 0x0002 /* Timestamp rollover interrupt */
#define MAILSLOT_INT 0x0003 /* Backend pipe interrupt */
#define CONSOLE_SIO_INT 0x0004 /* SIO driver interrupt */
#define BUS_INT 0x0005 /* BUS interrupt */
/* level0 IPI interrupt aka IPI_INTR_ID_CPC */
#define IV_IPI0 0x0006
/* level1 IPI interrupt aka IPI_INTR_ID_DEBUG */
#define IV_IPI1 0x0007
#define IV_IPI2 0x0008 /* level2 IPI interrupt */
#define IV_IPI3 0x0009 /* level3 IPI interrupt */
#define WINDML_INT_RANGE_BASE 0x00f0 /* WindML interrupts range base */
#define WINDML_INT_RANGE_END 0x00ff /* WindML interrupts range end */
#define USER_INT_RANGE_BASE 0x0200 /* User interrupts range base */
#define USER_INT_RANGE_END 0x02ff /* User interrupts range end */
#ifdef __cplusplus
}
#endif
#endif /* __INCivSimnth */
vxworks-6.9/target/h/arch/simnt/mmuArchLib.h
+64
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@@ -0,0 +1,64 @@
/* mmuArchLib.h - mmu library header for VxSim */
/*
* Copyright (c) 1999-2004,2007 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01g,23jul07,elp moved type definition to mmuArchLibSP.h..
01f,03may07,elp added SMP support.
01e,19aug04,dbt Removed obsolote mmuArchCurrentSet() prototype.
01d,03dec03,jmp added mmuArchLibInit().
01c,26nov03,jmp added mmuArchCurrentSet().
01c,30dec03,kab Update for VIRT_ADDR type
01b,07oct03,jmp added MMU_STATE_VALID_NOT.
added MMU cache simulation.
01a,17jul03,jmp imported from VxWorksAE.
*/
#ifndef __INCmmuArchLibh
#define __INCmmuArchLibh
#ifdef __cplusplus
extern "C" {
#endif
/* MMU Page Size */
#ifdef HOST
#ifndef WIN32
#define MMU_PAGE_SIZE 0x2000 /* pages are 8 kbytes */
#else /* !WIN32 */
#define MMU_PAGE_SIZE 0x10000 /* pages are 64 kbytes */
#endif /* WIN32 */
#else
#if CPU != SIMNT
#define MMU_PAGE_SIZE 0x2000 /* pages are 8 kbytes */
#else /* CPU != SIMNT */
#define MMU_PAGE_SIZE 0x10000 /* pages are 64 kbytes */
#endif /* CPU != SIMNT */
#endif /* HOST */
#if MMU_PAGE_SIZE == 0x10000
#define MMU_PAGE_TBL_SIZE 0x200000 /* page table is 2Mbytes */
#else
#define MMU_PAGE_TBL_SIZE 0x100000 /* page table is 1Mbytes */
#endif /* MMU_PAGE_SIZE == 0x10000 */
#ifndef HOST
extern STATUS mmuArchLibInit (UINT pageSize);
#endif /* HOST */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuArchLibh */
vxworks-6.9/target/h/arch/simnt/private/adrSpaceArchLibP.h
+83
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@@ -0,0 +1,83 @@
/* adrSpaceArchLibP.h - address space header file for x86_64 */
/*
* Copyright (c) 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,01feb10,elp created from x86_64 with 64-bit region definitions.
*/
#ifndef __INCadrSpaceArchLibPh
#define __INCadrSpaceArchLibPh
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
/* virtual memory region definitions */
#define KERNEL_SYS_MEM_RGN_BASE \
(adrSpaceArchRgnBaseGet(ADR_SPACE_ARCH_KERNEL_SYS_MEM_RGN))
#define KERNEL_SYS_MEM_RGN_SIZE \
(adrSpaceArchRgnSizeGet(ADR_SPACE_ARCH_KERNEL_SYS_MEM_RGN))
#define KERNEL_VIRT_POOL_RGN_BASE \
(adrSpaceArchRgnBaseGet(ADR_SPACE_ARCH_KERNEL_VIRT_POOL_RGN))
#define KERNEL_VIRT_POOL_RGN_SIZE \
(adrSpaceArchRgnSizeGet(ADR_SPACE_ARCH_KERNEL_VIRT_POOL_RGN))
#define KERNEL_DIRECT_MAP_RGN_BASE \
(adrSpaceArchRgnBaseGet(ADR_SPACE_ARCH_KERNEL_DIRECT_MAP_RGN))
#define KERNEL_DIRECT_MAP_RGN_SIZE \
(adrSpaceArchRgnSizeGet(ADR_SPACE_ARCH_KERNEL_DIRECT_MAP_RGN))
#define SHARED_RGN_BASE \
(adrSpaceArchRgnBaseGet(ADR_SPACE_ARCH_SHARED_RGN))
#define SHARED_RGN_SIZE \
(adrSpaceArchRgnSizeGet(ADR_SPACE_ARCH_SHARED_RGN))
#define RTP_PRIVATE_RGN_BASE \
(adrSpaceArchRgnBaseGet(ADR_SPACE_ARCH_RTP_PRIV_RGN))
#define RTP_PRIVATE_RGN_SIZE \
(adrSpaceArchRgnSizeGet(ADR_SPACE_ARCH_RTP_PRIV_RGN))
#define ADR_SPACE_ARCH_RGN_NUM 5 /* number of regions */
/* typedefs */
typedef enum
{
ADR_SPACE_ARCH_KERNEL_SYS_MEM_RGN = 0,
ADR_SPACE_ARCH_KERNEL_VIRT_POOL_RGN = 1,
ADR_SPACE_ARCH_KERNEL_DIRECT_MAP_RGN = 2,
ADR_SPACE_ARCH_SHARED_RGN = 3,
ADR_SPACE_ARCH_RTP_PRIV_RGN = 4
} ADR_SPACE_ARCH_RGN_TYPE;
/* BSP configured values */
extern VIRT_ADDR sysKernelSysMemRgnBase;
extern size_t sysKernelSysMemRgnSize;
extern VIRT_ADDR sysRtpPrivMemRgnBase;
extern size_t sysRtpPrivMemRgnSize;
extern VIRT_ADDR sysSharedMemRgnBase;
extern size_t sysSharedMemRgnSize;
extern VIRT_ADDR sysKernelVirtPoolMemRgnBase;
extern size_t sysKernelVirtPoolMemRgnSize;
extern VIRT_ADDR adrSpaceArchRgnBaseGet (ADR_SPACE_ARCH_RGN_TYPE rgnType);
extern size_t adrSpaceArchRgnSizeGet (ADR_SPACE_ARCH_RGN_TYPE rgnType);
#ifdef __cplusplus
}
#endif
#endif /* __INCadrSpaceArchLibPh */
vxworks-6.9/target/h/arch/simnt/private/smpSimntP.h
+337
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/* smpSimntP.h - simnt/simlinux private SMP assembler definitions header file */
/*
* Copyright (c) 2006-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01v,24feb11,elp added vxsimHostCpuDelay() vxsimHostCpuWakeup()
(CQ:WIND00151275).
01u,29dec10,dbt Fixed _SIMIA_PER_CPU_VALUE32_INC macro in 64-bit mode to
correct return value.
01t,18oct10,elp implement LP64 SMP macros.
01s,03aug10,elp fixed _SIMIA_PER_CPU_ADRS_GET(64 bits).
01r,29jul10,pad Moved extern C statement after include statements.
01q,02jun10,elp 64 bits support.
01p,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
01o,26sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
01n,27aug08,jpb Renamed VSB header file
01m,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01l,18jan08,gls added VX_INSTR_BARRIER()
01k,09jan08,elp removed previous temporary fix.
01j,19jul07,rlp Declared vxsimHostSleep() as extern, this is a temporary fix
to be able to build the aim directory.
01i,16jul07,elp added _WRS_ARCH_CPU_DELAY() macro.
01h,17apr07,kk move VX_MAX_SMP_CPUS to archSimnt.h
01g,16mar07,elp fixed cplus build
01f,08mar07,dbt Removed inclusion of mmuArchLib.h
01e,19dec06,elp added macros to get WIND_VARS locked, moved simStatus and
simPendingIntLvl to host variables.
01d,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
01c,30nov06,dbt Increased maximum number of CPUs to 32.
01b,23nov06,dbt Fixed syntax for GNU compiler.
Removed _WRS_WIND_VARS_OFFSET_archVars definition
Increased maximum CPU number to 16
01a,07sep07,elp created
*/
#ifndef __INCsmpSimntPh
#define __INCsmpSimntPh
/************************************************************/
#include <vsbConfig.h>
#ifndef _ASMLANGUAGE
#include <private/vxsimHostLibP.h>
#endif /* ASMLANGUAGE */
#ifdef __cplusplus
extern "C" {
#endif
#define REG32_rax eax
#define REG32_rbx ebx
#define REG32_rcx ecx
#define REG32_rdx edx
#define REG32_r10 r10d
#define REG32_r11 r11d
#ifdef _WRS_CONFIG_SMP
#ifndef _ASMLANGUAGE
#define _WRS_ARCH_CPU_DELAY() (vxsimHostCpuDelay(0))
#define _WRS_ARCH_CPU_DELAY_MS(ms) (vxsimHostCpuDelay(ms))
#define _WRS_ARCH_CPU_WAKEUP(cpuIx) (vxsimHostCpuWakeup(cpuIx))
/* optimized access without function call */
#define _WRS_CPU_INDEX_GET() (*pVxCpuIndex)
#endif /* ASMLANGUAGE */
/*
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
* XSCALE, etc), representing the maximum cache line size of the variants of
* the respective arch.
*
* For SIMNT/SIMLINUX this is 128 bytes.
*/
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
/*
* This macro defines the alignment requirement for the WIND_VARS structure.
*
* There are 3 factors involved in selection of this value.
*
* 1. It's definition is no LESS than the maximum value of
* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
* cache line length growth.
* 2. It must be at least as large as the WIND_VARS structure.
* 3. It must be a power of 2.
*
* For example:
* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
* (rule 1).
* if WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
* (rules 2 and 3).
*/
#ifdef _WRS_CONFIG_LP64
/* WIND_VARS size is 0x70+0x58=0xc8(200) */
#define _WRS_WIND_VARS_ALIGN 256
#define _WRS_WIND_VARS_ALIGN_SHIFT 8
#else /* _WRS_CONFIG_LP64 */
/* WIND_VARS size is 0x4c+0x28=0x74(116) */
#define _WRS_WIND_VARS_ALIGN 128
#define _WRS_WIND_VARS_ALIGN_SHIFT 7
#endif /* _WRS_CONFIG_LP64 */
#ifndef _ASMLANGUAGE
typedef struct wind_vars_arch
{
struct mmuTransTblStruct * cpu_pMmuCurrentTransTbl;
/* 0x00|0x00: current MMU table */
#ifdef _WRS_CONFIG_LP64
ULONG cpu_ctxLoadTmpRegs[8]; /* 0x08:
* ss,rsp,rflags,cs,rip,rax,rcx,rdx */
#else
ULONG cpu_ctxLoadPc; /* 0x04 context load pc */
ULONG cpu_ctxLoadEax; /* 0x08 context load eax */
ULONG cpu_ctxLoadEcx; /* 0x0c context load ebx */
ULONG cpu_ctxLoadEflags; /* 0x10 context load eflags */
#endif /* _WRS_CONFIG_LP64 */
UINT32 cpu_ctxLoadIntLock; /* 0x14|0x48: context load intlock */
BOOL cpu_windSchedDefer; /* 0x18|0x4c: defer rescheduling */
BOOL cpu_windSchedIsLocked; /* 0x1c|0x50: scheduler locked */
UINT32 cpu_intNest; /* 0x20|0x54: interrupt mask and mode */
} WIND_VARS_ARCH;
#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
/* macros to access the arch-specific fields of the vxKernelVars struct */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
#define _WRS_WIND_VARS_ARCH_LOCKED_GET(glob,var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET (archVars.cpu_##glob,var)
#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
extern UINT32 * pVxCpuIndex;
#else /* _ASMLANGUAGE */
#ifdef _WRS_CONFIG_LP64
#define _WRS_WIND_VARS_OFFSET_pMmuCurrentTransTbl \
(_WRS_WIND_VARS_OFFSET_archVars+0x0)
#define _WRS_WIND_VARS_OFFSET_ctxLoadTmpRegs \
(_WRS_WIND_VARS_OFFSET_archVars+0x08)
#define _WRS_WIND_VARS_OFFSET_intNest \
(_WRS_WIND_VARS_OFFSET_archVars+0x54)
#define _WRS_WIND_VARS_OFFSET(reg) rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
#define _WRS_SIMIA_VAR_ADRS(label) FUNC(vxKernelVars+OFFSET_##label)
/*
* take the value at *pVxCpuIndex and shift to get the vxKernelVar index
* 0,128,256 ...
*/
#define _SIMIA_CPU_INDEX_GET(regSuffix) \
movabsq $VAR(pVxCpuIndex),%r##regSuffix; \
movq (%r##regSuffix),%r##regSuffix; \
movl (%r##regSuffix),%REG32_r##regSuffix; \
rol $_WRS_WIND_VARS_ALIGN_SHIFT,%REG32_r##regSuffix;
/* put windVars->label address in reg */
#define _WRS_LOAD_REG_WITH_VAR_BASE(label,regSuffix) \
movabsq $FUNC(vxKernelVars),%r##regSuffix; \
add $_WRS_WIND_VARS_OFFSET_##label,%r##regSuffix;
/* put windvar->label address in r<regSuffix> */
#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
add %r##scratch,%r##regSuffix;
/* put windVars->label field 32 bits value in e<regSuffix> */
#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
add %r##regSuffix,%r##scratch; \
movl 0x0(%r##scratch),%REG32_r##regSuffix;
/* put windVars->label field 64 bits value in r<regSuffix> */
#define _SIMIA_PER_CPU_VALUE64_GET(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
add %r##regSuffix,%r##scratch; \
movq 0x0(%r##scratch),%r##regSuffix;
/* increment windVars->label field (int) */
#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
add %r##regSuffix,%r##scratch; \
movl 0x0(%r##scratch),%REG32_r##regSuffix; \
incl %REG32_r##regSuffix; \
movl %REG32_r##regSuffix,0x0(%r##scratch);
#else /* _WRS_CONFIG_LP64 */
#define _WRS_WIND_VARS_OFFSET_pMmuCurrentTransTbl \
(_WRS_WIND_VARS_OFFSET_archVars+0x0)
#define _WRS_WIND_VARS_OFFSET_ctxLoadPc \
(_WRS_WIND_VARS_OFFSET_archVars+0x04)
#define _WRS_WIND_VARS_OFFSET_ctxLoadEax \
(_WRS_WIND_VARS_OFFSET_archVars+0x08)
#define _WRS_WIND_VARS_OFFSET_ctxLoadEbx \
(_WRS_WIND_VARS_OFFSET_archVars+0x0c)
#define _WRS_WIND_VARS_OFFSET_ctxLoadEflags \
(_WRS_WIND_VARS_OFFSET_archVars+0x10)
#define _WRS_WIND_VARS_OFFSET_ctxLoadIntLock \
(_WRS_WIND_VARS_OFFSET_archVars+0x14)
#define _WRS_WIND_VARS_OFFSET_intNest \
(_WRS_WIND_VARS_OFFSET_archVars+0x20)
#define _WRS_WIND_VARS_OFFSET(reg) rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
#define _WRS_SIMIA_VAR_ADRS(label) FUNC(vxKernelVars+OFFSET_##label)
/*
* take the value at *pVxCpuIndex and shift to get the vxKernelVar index
* 0,128,256 ...
*/
#define _SIMIA_CPU_INDEX_GET(regSuffix) \
movl VAR(pVxCpuIndex),%REG32_r##regSuffix; \
movl (%REG32_r##regSuffix),%REG32_r##regSuffix;\
rol $_WRS_WIND_VARS_ALIGN_SHIFT,%REG32_r##regSuffix;
#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
leal FUNC(vxKernelVars),%REG32_r##reg; \
addl $_WRS_WIND_VARS_OFFSET_##label,%REG32_r##reg;
#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl %REG32_r##scratch,%REG32_r##regSuffix;
#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl %REG32_r##regSuffix,%REG32_r##scratch; \
movl 0x0(%REG32_r##scratch),%REG32_r##regSuffix;
#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
_SIMIA_CPU_INDEX_GET(regSuffix) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl %REG32_r##regSuffix,%REG32_r##scratch; \
movl 0x0(%REG32_r##scratch),%REG32_r##regSuffix; \
incl %REG32_r##regSuffix; \
movl %REG32_r##regSuffix,0x0(%REG32_r##scratch);
#endif /* _WRS_CONFIG_LP64 */
#endif /* _ASMLANGUAGE */
#else /* _WRS_CONFIG_SMP */
#define _WRS_CPU_INDEX_GET() 0
/* macro to access the arch-specific fields */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (glob)
#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
#define _WRS_WIND_VARS_ARCH_LOCKED_GET(glob,var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET (glob,var)
#ifdef _ASMLANGUAGE
#ifdef _WRS_CONFIG_LP64
#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
movabsq $FUNC(label),%r##regSuffix;
#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
movabsq $FUNC(label),%r##regSuffix; \
movl (%r##regSuffix),%REG32_r##regSuffix;
#define _SIMIA_PER_CPU_VALUE64_GET(regSuffix,scratch,label) \
movabsq $FUNC(label),%r##regSuffix; \
mov (%r##regSuffix),%r##regSuffix
#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
movabsq $FUNC(label),%r##scratch; \
movl (%r##scratch),%REG32_r##regSuffix; \
incl %REG32_r##regSuffix; \
movl %REG32_r##regSuffix,(%r##scratch);
#else /* _WRS_CONFIG_LP64 */
#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
leal FUNC(label),%REG32_r##regSuffix;
#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
movl FUNC(label),%REG32_r##regSuffix;
#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
incl FUNC(label); \
movl FUNC(label),%REG32_r##regSuffix;
#endif /* _WRS_CONFIG_LP64 */
#endif /* _ASMLANGUAGE */
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCsmpSimntPh */
vxworks-6.9/target/h/arch/simnt/private/vxPortableArchP.h
+49
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@@ -0,0 +1,49 @@
/* vxPortableArchP.h - VxSim portable library configuration */
/*
* Copyright (c) 2007, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,20oct10,s_s Added _WRS_PORTABLE_vxCpuLibInit and _WRS_PORTABLE_vxCpuIdGet
macros (CQ:WIND00199670)
01a,04may07,zl created
*/
#ifndef __INCvxPortableArchPh
#define __INCvxPortableArchPh
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <private/vxPortableP.h>. It may undefine
* portable library definitions in order to enable architecture specific
* implementation of a library or routine.
*/
/* the following can be overridden with PORTABLE */
#ifndef PORTABLE
#endif
/* the following cannot be overridden with PORTABLE */
#undef _WRS_PORTABLE_vxAtomicLib
#undef _WRS_PORTABLE_vxCpuIndexGet
#undef _WRS_PORTABLE_vxCpuLibInit
#undef _WRS_PORTABLE_vxCpuIdGet
#ifdef __cplusplus
}
#endif
#endif /* __INCvxPortableArchPh */
vxworks-6.9/target/h/arch/simnt/private/vxdbgSimntLibP.h
+54
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@@ -0,0 +1,54 @@
/* vxdbgSimsolarisLibP.h - private simsolaris VxDBG library header file */
/*
* Copyright (c) 2007-2008, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01f,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
SMP (CQ:WIND00253870).
01e,29apr10,pad Moved extern C statement after include statements.
01d,27aug08,jpb Renamed VSB header file
01c,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01b,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
01a,11oct07,rlp Written
*/
#ifndef __INCvxdbgSimsolarisLibPh
#define __INCvxdbgSimsolarisLibPh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This macro returns the <level> parameter modified with the interrupt lock
* level defined into the <value> parameter. The <level> parameter must be
* previously get with either intCpuLock() or intRegsLock() API.
*/
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~SIM_STATUS_INTLOCK) | (value & SIM_STATUS_INTLOCK))
#ifdef _WRS_CONFIG_SMP
/* return TRUE if interrupts are locked in specified register set. */
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) VXSIM_INT_MASK_GET (pRegs->reg_status)
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxdbgSimsolarisLibPh */
vxworks-6.9/target/h/arch/simnt/regsSimnt.h
+354
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@@ -0,0 +1,354 @@
/* regsSimnt.h - simnt registers header */
/*
* Copyright (c) 1997-1998,2003-2004,2006-2008,2010,2011
* Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable
* Wind River license agreement.
*/
/*
modification history
--------------------
01w,05sep11,elp added CPUID type and definitions (CQID: WIND00286339).
01v,24jun11,elp added fsBase to regset for tools (CQ:WIND00278823).
01u,04jan11,elp added simulator specific TCB for fsBase (CQ:WINd00247541).
01t,29jul10,elp fixed VXSIM_SIMSTATUS_VALUE_GET()
01s,18jun10,elp added address register in VXSIM_SIMSTATUS_VALUE_GET().
01r,13apr10,elp added ELFAGS_BRANDNEW define, replaced ULONG by VXSIM_ULONG.
01q,29apr10,pad Moved extern C statement after include statements.
01p,01mar10,elp 64bits support.
01o,27may08,elp fixed warnings.
01n,05jan07,elp added pSimStatus and pSimIntPendingLvl declarations,
added interrupt level macros.
01m,17oct06,elp added WIND_CPU_STATE.
01l,31aug04,jmp made SIMLINUX REG_SET indentical to SIMNT.
01k,01dec03,jmp added mmuTransTbl (current MMU translation table) to REG_SET.
01j,24nov03,jeg added macros to manage supervisor bit
01i,14nov03,jmp added SIM_STATUS_USR.
01h,18sep03,jeg removed SIM_STATUS_INIT macro.
01g,12sep03,jeg updated REG_SET structure to split intLockKey by a status bit
field. Removed the WIND_TCB_* macros.
01f,27may03,jmp added Register offsets in TCB.
01e,26mar03,jmp replaced INSTR by UCHAR to use this file from host side.
01d,17mar03,jmp renamed macros REG_* in REG_SET_*.
01c,16jan03,elp added REGS defines (SPR #84278).
01b,29apr98,cym added intLockKey
01a,27aug97,cym written
*/
#ifndef __INCregsSimnth
#define __INCregsSimnth
#ifndef HOST
#include <vsbConfig.h>
#include <types/vxArch.h>
#endif /* HOST */
#ifdef __cplusplus
extern "C" {
#endif
#define EFLAGS_BRANDNEW 0x10202
#ifdef _WRS_CONFIG_LP64
#ifndef _ASMLANGUAGE
#define GREG_NUM 16 /* has 64-bit general registers */
typedef struct /* REG_SET - simnt register set (based on x86_64) */
{
UINT32 reg_status; /* status bit field */
UINT32 unused;
VXSIM_ULONG mmuTransTbl; /* current MMU translation table */
VXSIM_ULONG r15; /* general register */
VXSIM_ULONG r14; /* general register */
VXSIM_ULONG r13; /* general register */
VXSIM_ULONG r12; /* general register */
VXSIM_ULONG r11; /* general register */
VXSIM_ULONG r10; /* general register */
VXSIM_ULONG r9; /* general register */
VXSIM_ULONG r8; /* general register */
VXSIM_ULONG rdi; /* general register */
VXSIM_ULONG rsi; /* general register */
VXSIM_ULONG rbp; /* frame pointer register */
VXSIM_ULONG rsp; /* stack pointer register */
VXSIM_ULONG rbx; /* general register */
VXSIM_ULONG rdx; /* general register */
VXSIM_ULONG rcx; /* general register */
VXSIM_ULONG rax; /* general register */
VXSIM_ULONG rflags; /* status register */
UCHAR * pc; /* program counter */
VXSIM_ULONG fsBase; /* fsBase for tool easy access,
* synchronized with extraRegs value when saving,
* never used when loading */
} REG_SET;
typedef struct /* SIM_REG_SET - simulator specific part of TCB */
{
VXSIM_ULONG fsBase;
} SIM_REG_SET;
/* some common names for registers */
#undef spReg
#undef pc
#define fpReg rbp /* frame pointer */
#define spReg rsp /* stack pointer */
#define flReg rflags /* flags register */
#define eflags rflags
#define reg_pc pc
#define reg_sp spReg
#define reg_fp fpReg
#define G_REG_BASE 0x10 /* data reg's base offset to REG_SET */
#define G_REG_OFFSET(n) (G_REG_BASE + (n) * sizeof(VXSIM_ULONG))
#define SR_OFFSET G_REG_OFFSET(GREG_NUM)
#define PC_OFFSET (SR_OFFSET + sizeof(VXSIM_ULONG))
#else /* _ASMLANGUAGE */
#define VXSIM_SIMSTATUS_ADDR_GET(reg) \
movabsq $VAR(pSimStatus),reg; \
mov (reg),reg
#define VXSIM_SIMSTATUS_VALUE_GET(addrRegSuffix,valRegSuffix) \
movabsq $VAR(pSimStatus),%r##addrRegSuffix; \
mov (%r##addrRegSuffix), %r##addrRegSuffix; \
movl 0x0(%r##addrRegSuffix),%e##valRegSuffix;
#endif /* _ASMLANGUAGE */
/* Register offsets */
#define REG_SET_SIMSTATUS 0x00
#define REG_SET_MMU_TRANS_TBL 0x08
#define REG_SET_R15 0x10
#define REG_SET_R14 0x18
#define REG_SET_R13 0x20
#define REG_SET_R12 0x28
#define REG_SET_R11 0x30
#define REG_SET_R10 0x38
#define REG_SET_R9 0x40
#define REG_SET_R8 0x48
#define REG_SET_RDI 0x50
#define REG_SET_RSI 0x58
#define REG_SET_RBP 0x60
#define REG_SET_RSP 0x68
#define REG_SET_RBX 0x70
#define REG_SET_RDX 0x78
#define REG_SET_RCX 0x80
#define REG_SET_RAX 0x88
#define REG_SET_RFLAGS 0x90
#define REG_SET_RIP 0x98
#define REG_SET_PC 0x98
#else /* _WRS_CONFIG_LP64 */
#ifndef _ASMLANGUAGE
#define GREG_NUM 8
typedef struct /* REG_SET - simnt register set (based on x86) */
{
VXSIM_ULONG edi; /* general register */
VXSIM_ULONG esi; /* general register */
VXSIM_ULONG ebp; /* general register */
VXSIM_ULONG esp; /* general register */
VXSIM_ULONG ebx; /* general register */
VXSIM_ULONG edx; /* general register */
VXSIM_ULONG ecx; /* frame pointer register */
VXSIM_ULONG eax; /* stack pointer register */
VXSIM_ULONG eflags; /* status register */
UCHAR * pc; /* program counter */
VXSIM_ULONG reg_status; /* status bit field */
UINT32 mmuTransTbl; /* current MMU translation table */
char unused[0xc8]; /* unused - keep for SIMNT backward */
/* compatibility with T2.x releases */
} REG_SET;
#undef spReg
#undef pc
#define spReg esp
#define fpReg ebp
#define flReg eflags
#define reg_pc pc
#define reg_sp spReg
#define reg_fp fpReg
#define G_REG_BASE 0x00 /* data reg's base offset to REG_SET */
#define G_REG_OFFSET(n) (G_REG_BASE + (n) * sizeof(VXSIM_ULONG))
#define SR_OFFSET G_REG_OFFSET(GREG_NUM)
#define PC_OFFSET (SR_OFFSET + sizeof(VXSIM_ULONG))
#else /* _ASMLANGUAGE */
#define VXSIM_SIMSTATUS_ADDR_GET(reg) \
movl VAR(pSimStatus),reg; \
#define VXSIM_SIMSTATUS_VALUE_GET(addrRegSuffix,valRegSuffix) \
movl VAR(pSimStatus),%e##addrRegSuffix; \
movl 0x0(%e##addrRegSuffix),%e##valRegSuffix;
#endif /* _ASMLANGUAGE */
/* Register offsets */
#define REG_SET_EDI 0x00
#define REG_SET_ESI 0x04
#define REG_SET_EBP 0x08
#define REG_SET_ESP 0x0c
#define REG_SET_EBX 0x10
#define REG_SET_EDX 0x14
#define REG_SET_ECX 0x18
#define REG_SET_EAX 0x1c
#define REG_SET_EFLAGS 0x20
#define REG_SET_PC 0x24
#define REG_SET_SIMSTATUS 0x28
#define REG_SET_MMU_TRANS_TBL 0x2c
#endif /* _WRS_CONFIG_LP64 */
#ifndef _ASMLANGUAGE
typedef struct wind_cpu_state /* CPU initial state */
{
REG_SET regs; /* initial register set */
} WIND_CPU_STATE;
typedef struct cpuid /* CPUID - 80x86 cpuid version/feature */
{
int highestValue; /* EAX=0: highest integer value */
int vendorId[3]; /* EAX=0: vendor identification string */
int signature; /* EAX=1: processor signature */
int featuresEbx; /* EAX=1: feature flags EBX */
int featuresEcx; /* EAX=1: feature flags ECX */
int featuresEdx; /* EAX=1: feature flags EDX */
int cacheEax; /* EAX=2: config parameters EAX */
int cacheEbx; /* EAX=2: config parameters EBX */
int cacheEcx; /* EAX=2: config parameters ECX */
int cacheEdx; /* EAX=2: config parameters EDX */
int serialNo64[2]; /* EAX=3: lower 64 of 96 bit serial no */
int brandString[12]; /* EAX=0x8000000[234]: brand strings */
} CPUID;
extern volatile UINT32 * pSimStatus;
extern volatile UINT32 * pSimIntPendingLvl;
#define VXSIM_PENDING_INT_CHECK(minLvl) \
((*pSimIntPendingLvl) > (minLvl))
#endif /* _ASMLANGUAGE */
/* status bit fields */
#define SIM_STATUS_INTLOCK 0x0001 /* interrupt locked */
#define SIM_STATUS_INTUNLOCK 0x0000 /* interrupt unlocked */
#define SIM_STATUS_SUP 0x0002 /* supervisor mode */
#define SIM_STATUS_USR 0x0000 /* user mode */
#define SIM_STATUS_INTLVL_MASK 0x0f00 /* interrupt level mask */
#define SIM_STATUS_INTLVL_SHIFT 8
/* macros to access interrupt status field */
#define VXSIM_INT_MASK_SET(vxsimStatus) \
(vxsimStatus |= SIM_STATUS_INTLOCK)
#define VXSIM_INT_MASK_CLEAR(vxsimStatus) \
(vxsimStatus &= ~(SIM_STATUS_INTLOCK))
#define VXSIM_INT_MASK_GET(vxsimStatus) \
(((vxsimStatus & SIM_STATUS_INTLOCK) == 0) ? FALSE : TRUE)
#define VXSIM_SUP_MODE_SET(vxsimStatus) \
(vxsimStatus |= SIM_STATUS_SUP)
#define VXSIM_USR_MODE_SET(vxsimStatus) \
(vxsimStatus &= ~(SIM_STATUS_SUP))
#define VXSIM_SUP_MODE_GET(vxsimStatus) \
(((vxsimStatus & SIM_STATUS_SUP) == 0) ? FALSE : TRUE)
#define VXSIM_INT_LVL_GET(vxsimStatus) \
(((vxsimStatus & SIM_STATUS_INTLVL_MASK) >> SIM_STATUS_INTLVL_SHIFT))
#define VXSIM_INT_LVL_SET(vxsimStatus,intLvl) \
(vxsimStatus = (vxsimStatus & ~SIM_STATUS_INTLVL_MASK) | \
((intLvl << SIM_STATUS_INTLVL_SHIFT) & \
SIM_STATUS_INTLVL_MASK))
#define VX_CPUID_HIGHVALUE 0 /* offset to highestValue */
#define VX_CPUID_VENDORID 4 /* offset to vendorId */
#define VX_CPUID_SIGNATURE 16 /* offset to signature */
#define VX_CPUID_FEATURES_EBX 20 /* offset to featuresEbx */
#define VX_CPUID_FEATURES_ECX 24 /* offset to featuresEcx */
#define VX_CPUID_FEATURES_EDX 28 /* offset to featuresEdx */
#define VX_CPUID_CACHE_EAX 32 /* offset to cacheEax */
#define VX_CPUID_CACHE_EBX 36 /* offset to cacheEbx */
#define VX_CPUID_CACHE_ECX 40 /* offset to cacheEcx */
#define VX_CPUID_CACHE_EDX 44 /* offset to cacheEdx */
#define VX_CPUID_SERIALNO 48 /* offset to serialNo64 */
#define VX_CPUID_BRAND_STR 56 /* offset to brandString[0] */
#define VX_CPUID_HIGHVALUE_EXT 104 /* offset to highestValue Extended */
#define VX_CPUID_EXT_FEATURES_EDX 108 /* offset to featuresEdx Extended */
#define VX_CPUID_EXT_FEATURES_ECX 112 /* offset to featuresEcx Extended */
#define VX_CPUID_CACHE_COUNT 116 /* offset to cache count */
#define VX_CPUID_CACHE_PARAMS 120 /* offset to cache parameters */
#define VX_CPUID_MONITOR_EAX 216 /* offset to montor/mwait parameters */
#define VX_CPUID_MONITOR_EBX 220 /* offset to montor/mwait parameters */
#define VX_CPUID_MONITOR_ECX 224 /* offset to montor/mwait parameters */
#define VX_CPUID_MONITOR_EDX 228 /* offset to montor/mwait parameters */
#define VX_CPUID_DTSPM_EAX 232 /* offset to DTSPM parameters */
#define VX_CPUID_DTSPM_EBX 236 /* offset to DTSPM parameters */
#define VX_CPUID_DTSPM_ECX 240 /* offset to DTSPM parameters */
#define VX_CPUID_DTSPM_EDX 244 /* offset to DTSPM parameters */
#define VX_CPUID_DCA_EAX 248 /* offset to DCA parameters */
#define VX_CPUID_PMON_EAX 252 /* offset to PMON parameters */
#define VX_CPUID_PMON_EBX 256 /* offset to PMON parameters */
#define VX_CPUID_PMON_ECX 260 /* offset to PMON parameters */
#define VX_CPUID_PMON_EDX 264 /* offset to PMON parameters */
#define VX_CPUID_PTOP_COUNT 268 /* offset to PTOP count */
#define VX_CPUID_PTOP_PARAMS 272 /* offset to PTOP parameters */
#define VX_CPUID_XSAVE_EAX 336 /* offset to XSAVE parameters */
#define VX_CPUID_XSAVE_EBX 340 /* offset to XSAVE parameters */
#define VX_CPUID_XSAVE_ECX 344 /* offset to XSAVE parameters */
#define VX_CPUID_XSAVE_EDX 348 /* offset to XSAVE parameters */
#define VX_CPUID_L2CACHE_EAX 352 /* offset to L2 Cache parameters */
#define VX_CPUID_L2CACHE_EBX 356 /* offset to L2 Cache parameters */
#define VX_CPUID_L2CACHE_ECX 360 /* offset to L2 Cache parameters */
#define VX_CPUID_L2CACHE_EDX 364 /* offset to L2 Cache parameters */
#define VX_CPUID_APM_EAX 368 /* offset to Advanced Power Mgt parameters */
#define VX_CPUID_APM_EBX 372 /* offset to Advanced Power Mgt parameters */
#define VX_CPUID_APM_ECX 376 /* offset to Advanced Power Mgt parameters */
#define VX_CPUID_APM_EDX 380 /* offset to Advanced Power Mgt parameters */
#define VX_CPUID_VPADRS_EAX 384 /* offset to Virt/Phys Adr Size parameters */
#define VX_CPUID_VPADRS_EBX 388 /* offset to Virt/Phys Adr Size parameters */
#define VX_CPUID_VPADRS_ECX 392 /* offset to Virt/Phys Adr Size parameters */
#define VX_CPUID_VPADRS_EDX 396 /* offset to Virt/Phys Adr Size parameters */
/* bit mask in VX_CPUID_FEATURES structure */
#define VX_CPUID_FPU 0x00000001
#define VX_CPUID_MMX 0x00800000
#define VX_CPUID_FXSR 0x01000000
#define VX_CPUID_SSE 0x02000000
#define VX_CPUID_SSE2 0x04000000
/* bit mask in VX_CPUID_FEATURES_EXT structure */
#define VX_CPUID_SSE3 0x00000001
#define VX_CPUID_SSE42 0x00100000
#define VX_CPUID_XSAVE 0x04000000
#define VX_CPUID_OSXSAVE 0x08000000
#define VX_CPUID_AVX 0x10000000
#ifdef __cplusplus
}
#endif
#endif /* __INCregsSimnth */
vxworks-6.9/target/h/arch/simnt/syscallArgsX86_64.h
+1004
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File diff suppressed because it is too large Load Diff
vxworks-6.9/target/h/arch/simnt/syscallArgsx86.h
+870
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@@ -0,0 +1,870 @@
/* Aligned for x86 - no alignment needed */
/* THIS FILE IS AUTO_GENERATED. PLEASE DO NOT EDIT. */
#ifndef _ASMLANGUAGE
#include <vxWorks.h>
#include <taskLib.h>
#include <rtpLib.h>
#include <sdLib.h>
#include <shlLib.h>
#include <signal.h>
#include <socket.h>
#include <time.h>
#include <setjmp.h>
#include <ioLib.h>
#include <private/semSysCall.h>
#include <private/objLibP.h>
#include <private/rtpLibP.h>
#include <private/mqPxSysCall.h>
#include <private/pxObjSysCall.h>
#include <private/semPxSysCall.h>
#include <private/taskSysCall.h>
#include <private/timerSysCall.h>
#include <private/eventSysCall.h>
#include <sys/resource.h>
#include <sys/types.h>
#include <base/b_trace_attr_t.h>
#include <base/b_trace_id_t.h>
#include <base/b_trace_event_id_t.h>
#include <base/b_pthread_t.h>
struct _exitScArgs
{
int status;
};
struct _creatScArgs
{
const char * name;
mode_t flag;
};
struct _openScArgs
{
const char * name;
int flags;
int mode;
};
struct _closeScArgs
{
int fd;
};
struct _readScArgs
{
int fd;
void * buffer;
size_t maxbytes;
};
struct _writeScArgs
{
int fd;
const void * buffer;
size_t nbytes;
};
struct _ioctlScArgs
{
int fd;
int function;
_Vx_ioctl_arg_t arg;
};
struct dupScArgs
{
int fd;
};
struct dup2ScArgs
{
int fd;
int fd2;
};
struct pipeScArgs
{
int filedes[2];
};
struct removeScArgs
{
const char * name;
};
struct selectScArgs
{
int width;
fd_set * readFds;
fd_set * writeFds;
fd_set * excFds;
struct timeval * timeout;
};
struct socketScArgs
{
int domain;
int type;
int protocol;
};
struct bindScArgs
{
int s;
struct sockaddr * name;
int namelen;
};
struct listenScArgs
{
int s;
int backlog;
};
struct acceptScArgs
{
int s;
struct sockaddr * addr;
int *addrlen;
};
struct connectScArgs
{
int s;
struct sockaddr * name;
int namelen;
};
struct sendtoScArgs
{
int s;
caddr_t buf;
int bufLen;
int flags;
struct sockaddr * to;
int tolen;
};
struct sendScArgs
{
int s;
const char * buf;
int bufLen;
int flags;
};
struct sendmsgScArgs
{
int s;
struct msghdr * mp;
int flags;
};
struct recvfromScArgs
{
int s;
char * buf;
int bufLen;
int flags;
struct sockaddr *from;
int * pFromLen;
};
struct recvScArgs
{
int s;
char * buf;
int bufLen;
int flags;
};
struct recvmsgScArgs
{
int s;
struct msghdr * mp;
int flags;
};
struct setsockoptScArgs
{
int s;
int level;
int optname;
char * optval;
int optlen;
};
struct getsockoptScArgs
{
int s;
int level;
int optname;
char * optval;
int * optlen;
};
struct getsocknameScArgs
{
int s;
struct sockaddr *name;
int * namelen;
};
struct getpeernameScArgs
{
int s;
struct sockaddr *name;
int *namelen;
};
struct shutdownScArgs
{
int s;
int how;
};
struct mmapScArgs
{
void * addr;
size_t len;
int prot;
int flags;
int fildes;
off64_t off;
};
struct munmapScArgs
{
void * addr;
size_t len;
};
struct mprotectScArgs
{
void * addr;
size_t len;
int prot;
};
struct killScArgs
{
OBJ_HANDLE rtpId;
int signo;
};
struct sigpendingScArgs
{
sigset_t * pSet;
};
struct sigprocmaskScArgs
{
int how;
const sigset_t * pSet;
sigset_t * pOset;
};
struct _sigqueueScArgs
{
OBJ_HANDLE rtpId;
int signo;
const union sigval * pValue;
int sigCode;
};
struct _sigsuspendScArgs
{
const sigset_t * pSet;
};
struct _sigtimedwaitScArgs
{
const sigset_t * pSet;
struct siginfo * pInfo;
const struct timespec * pTime;
};
struct _sigactionScArgs
{
int signo;
const struct sigaction * pAct;
struct sigaction * pOact;
void * retAddr;
};
struct chdirScArgs
{
const char * name;
};
struct _getcwdScArgs
{
char * buffer;
int length;
};
struct _waitpidScArgs
{
OBJ_HANDLE childRtpId;
int * pStatus;
int options;
};
struct sysctlScArgs
{
int * pName;
u_int nameLen;
void * pOld;
size_t * pOldLen;
void * pNew;
size_t newLen;
};
struct _schedPxInfoGetScArgs
{
BOOL * pTimeSlicingOn;
ULONG * pTimeSlicePeriod;
};
struct sigaltstackScArgs
{
stack_t * ss;
stack_t * oss;
};
struct unlinkScArgs
{
const char * name;
};
struct linkScArgs
{
const char * name;
const char * newname;
};
struct _fsyncScArgs
{
int fd;
};
struct _fdatasyncScArgs
{
int fd;
};
struct renameScArgs
{
const char * oldname;
const char * newname;
};
struct fpathconfScArgs
{
int fd;
int name;
};
struct pathconfScArgs
{
const char * path;
int name;
};
struct accessScArgs
{
const char * path;
int amode;
};
struct chmodScArgs
{
const char * path;
mode_t mode;
};
struct pxTraceCreationScArgs
{
int cmd;
pid_t pid;
trace_attr_t * attr;
int fd;
trace_id_t * trid;
};
struct pxTraceCtlScArgs
{
int cmd;
trace_id_t trid;
struct trace_event_set_t * filter;
int how;
pthread_t thread_id;
void * pc;
void * ptr_out;
};
struct pxTraceEventScArgs
{
int cmd;
int id_in;
char * data;
size_t data_len;
pthread_t thread_id;
void * pc;
trace_event_id_t * id_out;
};
struct pxTraceEventNameQueryScArgs
{
int cmd;
trace_id_t trid;
int id_in1;
int id_in2;
char * name;
trace_event_id_t * id_out;
int * unavailable;
};
struct pxTraceLogScArgs
{
int cmd;
trace_id_t trid_in;
int fd;
trace_id_t *trid_out;
};
struct pxTraceEventGetScArgs
{
int cmd;
trace_id_t trid;
size_t num_bytes;
struct timespec * timeout;
struct posix_trace_event_info * event;
void * data;
size_t * data_len;
int * unavailable;
};
struct eventReceiveScArgs
{
UINT32 events;
UINT32 options;
_Vx_ticks_t timeout;
UINT32 * pEvtsReceived;
};
struct eventSendScArgs
{
int taskId;
UINT32 events;
};
struct eventCtlScArgs
{
OBJ_HANDLE handle;
VX_EVT_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct msgQSendScArgs
{
OBJ_HANDLE handle;
char * buffer;
size_t nBytes;
_Vx_ticks_t timeout;
int priority;
};
struct msgQReceiveScArgs
{
OBJ_HANDLE handle;
char * buffer;
size_t maxNBytes;
_Vx_ticks_t timeout;
};
struct _msgQOpenScArgs
{
const char * name;
size_t maxMsgs;
size_t maxMsgLength;
int options;
int mode;
void * context;
};
struct objDeleteScArgs
{
OBJ_HANDLE handle;
int options;
};
struct objInfoGetScArgs
{
OBJ_HANDLE handle;
void * pInfo;
size_t * pInfoSize;
int level;
};
struct _semTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semGiveScArgs
{
OBJ_HANDLE handle;
};
struct _semOpenScArgs
{
const char * name;
SEM_TYPE type;
int initState;
int options;
int mode;
void * context;
};
struct semCtlScArgs
{
OBJ_HANDLE handle;
VX_SEM_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct _taskOpenScArgs
{
struct vx_task_open_sc_args * pArgs;
};
struct taskCtlScArgs
{
int tid;
VX_TASK_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct taskDelayScArgs
{
_Vx_ticks_t ticks;
};
struct rtpSpawnScArgs
{
const char * rtpFileName;
const char ** argv;
const char ** envp;
int priority;
size_t uStackSize;
int options;
int taskOptions;
};
struct rtpInfoGetScArgs
{
OBJ_HANDLE rtpId;
RTP_DESC * rtpStruct;
};
struct taskKillScArgs
{
OBJ_HANDLE taskHandle;
int signo;
};
struct _taskSigqueueScArgs
{
OBJ_HANDLE taskHandle;
int signo;
const union sigval * pValue;
int sigCode;
};
struct _timer_openScArgs
{
const char * name;
int mode;
clockid_t clockId;
struct sigevent * evp;
void * context;
};
struct timerCtlScArgs
{
TIMER_CTL_CMD cmdCode;
OBJ_HANDLE timerHandle;
void * pArgs;
size_t pArgSize;
};
struct pxOpenScArgs
{
PX_OBJ_TYPE type;
const char * name;
int objOpenMode;
void * attr;
};
struct pxCloseScArgs
{
OBJ_HANDLE handle;
};
struct pxUnlinkScArgs
{
PX_OBJ_TYPE type;
const char * name;
};
struct pxCtlScArgs
{
OBJ_HANDLE handle;
PX_CTL_CMD_CODE cmdCode;
void * pArgs;
size_t * pArgSize;
};
struct pxMqReceiveScArgs
{
OBJ_HANDLE handle;
char * pMsg;
size_t msgLen;
unsigned int * pMsgPrio;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxMqSendScArgs
{
OBJ_HANDLE handle;
const char * pMsg;
size_t msgLen;
unsigned int msgPrio;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxSemWaitScArgs
{
OBJ_HANDLE handle;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxSemPostScArgs
{
OBJ_HANDLE handle;
};
struct pipeDevCreateScArgs
{
const char * name;
size_t nMessages;
size_t nBytes;
};
struct pipeDevDeleteScArgs
{
const char * name;
BOOL force;
};
struct _sdCreateScArgs
{
char * name;
int options;
size_t size;
off64_t physAddress;
MMU_ATTR attr;
void ** pVirtAddress;
};
struct _sdOpenScArgs
{
char * name;
int options;
int mode;
size_t size;
off64_t physAddress;
MMU_ATTR attr;
void ** pVirtAddress;
};
struct sdDeleteScArgs
{
OBJ_HANDLE handle;
int options;
};
struct sdMapScArgs
{
OBJ_HANDLE handle;
MMU_ATTR attr;
int options;
};
struct sdUnmapScArgs
{
OBJ_HANDLE handle;
int options;
};
struct sdProtectScArgs
{
OBJ_HANDLE handle;
MMU_ATTR attr;
};
struct _edrErrorInjectScArgs
{
int kind;
const char *fileName;
int lineNumber;
REG_SET *regset;
void *addr;
const char *msg;
};
struct wvEventScArgs
{
int eventId;
const char * pData;
unsigned int dataSize;
};
struct rtpVarAddScArgs
{
void ** pVar;
void * value;
};
struct sdInfoGetScArgs
{
OBJ_HANDLE handle;
SD_DESC * pSdStruct;
};
struct _shlOpenScArgs
{
const char * name;
int options;
};
struct _shlUnlockScArgs
{
SHL_ID shlId;
};
struct _shlCloseScArgs
{
SHL_ID shlId;
};
struct _shlGetScArgs
{
SHL_ID shlId;
SHLINFO *pInfo;
};
struct _shlPutScArgs
{
SHL_ID shlId;
const SHLINFO *pInfo;
};
struct objUnlinkScArgs
{
const char * name;
enum windObjClassType classType;
};
struct getprlimitScArgs
{
int idtype;
OBJ_HANDLE handle;
int resource;
struct rlimit *rlp;
};
struct setprlimitScArgs
{
int idtype;
OBJ_HANDLE handle;
int resource;
struct rlimit *rlp;
};
struct _mctlScArgs
{
void * addr;
size_t len;
int function;
void * arg;
};
struct _taskOpenWithGuardScArgs
{
struct vx_task_open_guard_sc_args * pArgs;
};
struct clockCtlScArgs
{
clockid_t clock_id;
CLOCK_CTL_CMD cmdCode;
void * pArgStruct;
size_t * pArgSize;
};
struct _semRTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semWTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semExchangeScArgs
{
OBJ_HANDLE giveHandle;
OBJ_HANDLE takeHandle;
_Vx_ticks_t timeout;
};
struct wvRtpEventScArgs
{
int eventId;
const char * pData;
unsigned int dataSize;
};
struct _selectScArgs
{
int width;
fd_set * readFds;
fd_set * writeFds;
fd_set * excFds;
struct timeval * timeout;
};
struct _sigtimedwait2ScArgs
{
const sigset_t * pSet;
struct siginfo * pInfo;
const struct timespec * pTime;
};
#endif /* _ASMLANGUAGE */
vxworks-6.9/target/h/arch/simnt/syscallSimnt.h
+81
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@@ -0,0 +1,81 @@
/* syscallVxSim.h - VxSim specific System Call Infrastructure header */
/*
* Copyright (c) 2003-2004,2007,2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01f,02jun10,elp 64 bits support.
01e,04may07,zl updated portable library build configuration.
01d,10feb04,jeg added _func_syscallTrapHandle to fixe dependency issue
introduced into wdbDbgSysCallCheck() API.
01c,09feb04,jeg added syscallTrapHandle () prototype.
01b,12dec03,jeg added frame pointer and program counter in
SYSCALL_ENTRY_STATE structure
01a,05nov03,jmp written.
*/
/*
DESCRIPTION
This header contains VxSim-specific definitions and constants used by
the System Call Infrastructure library.
*/
#ifndef __INCsyscallVxSimh
#define __INCsyscallVxSimh
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#ifdef _WRS_CONFIG_LP64
#define SYSCALL_ENTRY_FRAME_SIZE 104
#else
#define SYSCALL_ENTRY_FRAME_SIZE 52
#endif
#define _SYSCALL_USER_SP_CHECK(sp) /* XXX To implement */
/* typedefs */
#ifndef _ASMLANGUAGE
/*
* The SYSCALL_ENTRY_STATE structure defines the saved machine state
* when the system call trap is taken. This information is architecture
* specific, and is used by the system call dispatcher to restart system
* calls that have been interrupted by the occurance of signals.
* System call restart is achieved by restoring the saved state at the
* time of the system call trap, and re-issuing the system call.
* Arguments to the system call are saved on the kernel stack, and
* the address of that array is passed as an argument to the dispatcher.
* The layout of this structure must exactly match the ordering of members
* of the system call entry frame in src/arch/sim<arch>/syscallALib.s.
*/
typedef struct syscall_entry_state
{
long args[8]; /* argument list (user stack) */
long scn; /* System Call Number (SCN) in eax */
long * pUStack; /* user-mode stack pointer */
long statusReg; /* saved Status Register */
long * efp; /* saved frame Register */
void * pc; /* Trap return address */
} SYSCALL_ENTRY_STATE;
extern void (*_func_syscallTrapHandle)(void);
extern void syscallTrapHandle (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCsyscallVxSimh */
vxworks-6.9/target/h/arch/simnt/vxAtomicArchLib.h
+39
View File
@@ -0,0 +1,39 @@
/* vxAtomicArchLib.h - VxSim specific atomic library header */
/*
* Copyright (c) 2006, 2008-2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01f,22oct10,elp fixed 32-bits warnings caused by previous changes.
01e,22oct10,elp added inline macros
01d,29apr10,pad Moved extern C statement after include statements.
01c,15may09,gls made memory barriers available in user space
01b,16jun08,zl use _WRS_BARRIER() for memory barrier implementations.
01a,27nov06,dbt created based on PPC version
*/
#ifndef __INCvxAtomicArchLibh
#define __INCvxAtomicArchLibh
#include <arch/simsolaris/vxAtomicArchLibCommon.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _WRS_CONFIG_LP64
#define vxCas_inline vxAtomicCas_inline
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibh */
vxworks-6.9/target/h/arch/simnt/vxCpuSimntLib.h
+41
View File
@@ -0,0 +1,41 @@
/*
* vxCpuSimsolarisLib.h - header for arch/board vxsim dependent CPU
* Identification support routines
*/
/*
* Copyright (c) 2006-2007 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,03jul07,elp added vxCpuAvailableGet().
01a,27jul06,elp written.
*/
#ifndef __INCvxCpuSimsolarisLibh
#define __INCvxCpuSimsolarisLibh
#ifdef __cplusplus
extern "C" {
#endif
/* function declarations */
extern UINT32 vxCpuAvailableGet (void);
extern STATUS vxCpuStateInit (unsigned int cpu,
WIND_CPU_STATE * pCpuState,
char * stackBase, FUNCPTR entry);
extern void vxCpuStart (int cpu, WIND_CPU_STATE * pCpuState);
#ifdef __cplusplus
}
#endif
#endif /* __INCvxCpuSimsolarisLibh */
vxworks-6.9/target/h/arch/simnt/vxInlineArch.h
+35
View File
@@ -0,0 +1,35 @@
/* vxInlineArch.h - VxSim inline macro configuration */
/*
* Copyright (c) 2007 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,19jun07,zl created
*/
#ifndef __INCvxInlineArchh
#define __INCvxInlineArchh
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <vxInline.h>. It may define _WRS_INLINE_xxx
* build configuration macros in order to enable architecture specific
* inlined implementation of a macro definition.
*/
#ifdef __cplusplus
}
#endif
#endif /* __INCvxInlineArchh */
vxworks-6.9/target/h/arch/simnt/vxSimntLib.h
+29
View File
@@ -0,0 +1,29 @@
/* vxSimntLib.h - header for board dependent routines for Windows VxSim */
/* Copyright 2003 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,01dec03,dbt Fixed vxPowerDown prototype.
01a,01apr03,jmp written.
*/
#ifndef __INCvxSimntLibh
#define __INCvxSimntLibh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
IMPORT void vxPowerDown (void);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxSimntLibh */
vxworks-6.9/target/h/arch/simnt/vxsimArchLib.h
+18
View File
@@ -0,0 +1,18 @@
/* vxsimArchLib.h - header for VxSim architecture library */
/* Copyright 2003 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01b,28mar03,jmp added vxsimExceptionDispatch.
01a,30jan03,jmp written.
*/
#ifndef __INCvxsimArchLibh
#define __INCvxsimArchLibh
extern void vxsimExceptionDispatch (EXC_INFO * pExcInfo, REG_SET * pRegs);
#endif /* __INCvxsimArchLibh */