original files of m241
This commit is contained in:
neelimap
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/* smpSimntP.h - simnt/simlinux private SMP assembler definitions header file */
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/*
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* Copyright (c) 2006-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use of this
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* software may be licensed only pursuant to the terms of an applicable
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* Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01v,24feb11,elp added vxsimHostCpuDelay() vxsimHostCpuWakeup()
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(CQ:WIND00151275).
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01u,29dec10,dbt Fixed _SIMIA_PER_CPU_VALUE32_INC macro in 64-bit mode to
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correct return value.
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01t,18oct10,elp implement LP64 SMP macros.
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01s,03aug10,elp fixed _SIMIA_PER_CPU_ADRS_GET(64 bits).
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01r,29jul10,pad Moved extern C statement after include statements.
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01q,02jun10,elp 64 bits support.
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01p,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
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01o,26sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
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01n,27aug08,jpb Renamed VSB header file
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01m,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01l,18jan08,gls added VX_INSTR_BARRIER()
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01k,09jan08,elp removed previous temporary fix.
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01j,19jul07,rlp Declared vxsimHostSleep() as extern, this is a temporary fix
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to be able to build the aim directory.
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01i,16jul07,elp added _WRS_ARCH_CPU_DELAY() macro.
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01h,17apr07,kk move VX_MAX_SMP_CPUS to archSimnt.h
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01g,16mar07,elp fixed cplus build
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01f,08mar07,dbt Removed inclusion of mmuArchLib.h
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01e,19dec06,elp added macros to get WIND_VARS locked, moved simStatus and
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simPendingIntLvl to host variables.
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01d,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
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01c,30nov06,dbt Increased maximum number of CPUs to 32.
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01b,23nov06,dbt Fixed syntax for GNU compiler.
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Removed _WRS_WIND_VARS_OFFSET_archVars definition
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Increased maximum CPU number to 16
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01a,07sep07,elp created
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*/
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#ifndef __INCsmpSimntPh
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#define __INCsmpSimntPh
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/************************************************************/
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#include <vsbConfig.h>
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#ifndef _ASMLANGUAGE
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#include <private/vxsimHostLibP.h>
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#endif /* ASMLANGUAGE */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define REG32_rax eax
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#define REG32_rbx ebx
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#define REG32_rcx ecx
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#define REG32_rdx edx
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#define REG32_r10 r10d
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#define REG32_r11 r11d
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#ifdef _WRS_CONFIG_SMP
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#ifndef _ASMLANGUAGE
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#define _WRS_ARCH_CPU_DELAY() (vxsimHostCpuDelay(0))
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#define _WRS_ARCH_CPU_DELAY_MS(ms) (vxsimHostCpuDelay(ms))
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#define _WRS_ARCH_CPU_WAKEUP(cpuIx) (vxsimHostCpuWakeup(cpuIx))
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/* optimized access without function call */
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#define _WRS_CPU_INDEX_GET() (*pVxCpuIndex)
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#endif /* ASMLANGUAGE */
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/*
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* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
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* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
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* XSCALE, etc), representing the maximum cache line size of the variants of
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* the respective arch.
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*
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* For SIMNT/SIMLINUX this is 128 bytes.
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*/
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#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
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/*
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* This macro defines the alignment requirement for the WIND_VARS structure.
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*
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* There are 3 factors involved in selection of this value.
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*
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* 1. It's definition is no LESS than the maximum value of
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* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
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* cache line length growth.
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* 2. It must be at least as large as the WIND_VARS structure.
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* 3. It must be a power of 2.
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*
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* For example:
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* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
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* (rule 1).
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* if WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
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* (rules 2 and 3).
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*/
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#ifdef _WRS_CONFIG_LP64
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/* WIND_VARS size is 0x70+0x58=0xc8(200) */
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#define _WRS_WIND_VARS_ALIGN 256
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#define _WRS_WIND_VARS_ALIGN_SHIFT 8
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#else /* _WRS_CONFIG_LP64 */
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/* WIND_VARS size is 0x4c+0x28=0x74(116) */
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#define _WRS_WIND_VARS_ALIGN 128
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#define _WRS_WIND_VARS_ALIGN_SHIFT 7
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#endif /* _WRS_CONFIG_LP64 */
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#ifndef _ASMLANGUAGE
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typedef struct wind_vars_arch
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{
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struct mmuTransTblStruct * cpu_pMmuCurrentTransTbl;
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/* 0x00|0x00: current MMU table */
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#ifdef _WRS_CONFIG_LP64
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ULONG cpu_ctxLoadTmpRegs[8]; /* 0x08:
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* ss,rsp,rflags,cs,rip,rax,rcx,rdx */
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#else
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ULONG cpu_ctxLoadPc; /* 0x04 context load pc */
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ULONG cpu_ctxLoadEax; /* 0x08 context load eax */
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ULONG cpu_ctxLoadEcx; /* 0x0c context load ebx */
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ULONG cpu_ctxLoadEflags; /* 0x10 context load eflags */
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#endif /* _WRS_CONFIG_LP64 */
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UINT32 cpu_ctxLoadIntLock; /* 0x14|0x48: context load intlock */
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BOOL cpu_windSchedDefer; /* 0x18|0x4c: defer rescheduling */
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BOOL cpu_windSchedIsLocked; /* 0x1c|0x50: scheduler locked */
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UINT32 cpu_intNest; /* 0x20|0x54: interrupt mask and mode */
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} WIND_VARS_ARCH;
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#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
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/* macros to access the arch-specific fields of the vxKernelVars struct */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
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#define _WRS_WIND_VARS_ARCH_LOCKED_GET(glob,var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET (archVars.cpu_##glob,var)
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#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
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extern UINT32 * pVxCpuIndex;
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#else /* _ASMLANGUAGE */
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#ifdef _WRS_CONFIG_LP64
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#define _WRS_WIND_VARS_OFFSET_pMmuCurrentTransTbl \
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(_WRS_WIND_VARS_OFFSET_archVars+0x0)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadTmpRegs \
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(_WRS_WIND_VARS_OFFSET_archVars+0x08)
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#define _WRS_WIND_VARS_OFFSET_intNest \
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(_WRS_WIND_VARS_OFFSET_archVars+0x54)
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#define _WRS_WIND_VARS_OFFSET(reg) rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
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#define _WRS_SIMIA_VAR_ADRS(label) FUNC(vxKernelVars+OFFSET_##label)
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/*
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* take the value at *pVxCpuIndex and shift to get the vxKernelVar index
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* 0,128,256 ...
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*/
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#define _SIMIA_CPU_INDEX_GET(regSuffix) \
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movabsq $VAR(pVxCpuIndex),%r##regSuffix; \
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movq (%r##regSuffix),%r##regSuffix; \
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movl (%r##regSuffix),%REG32_r##regSuffix; \
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rol $_WRS_WIND_VARS_ALIGN_SHIFT,%REG32_r##regSuffix;
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/* put windVars->label address in reg */
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#define _WRS_LOAD_REG_WITH_VAR_BASE(label,regSuffix) \
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movabsq $FUNC(vxKernelVars),%r##regSuffix; \
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add $_WRS_WIND_VARS_OFFSET_##label,%r##regSuffix;
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/* put windvar->label address in r<regSuffix> */
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#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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add %r##scratch,%r##regSuffix;
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/* put windVars->label field 32 bits value in e<regSuffix> */
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#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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add %r##regSuffix,%r##scratch; \
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movl 0x0(%r##scratch),%REG32_r##regSuffix;
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/* put windVars->label field 64 bits value in r<regSuffix> */
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#define _SIMIA_PER_CPU_VALUE64_GET(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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add %r##regSuffix,%r##scratch; \
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movq 0x0(%r##scratch),%r##regSuffix;
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/* increment windVars->label field (int) */
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#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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add %r##regSuffix,%r##scratch; \
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movl 0x0(%r##scratch),%REG32_r##regSuffix; \
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incl %REG32_r##regSuffix; \
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movl %REG32_r##regSuffix,0x0(%r##scratch);
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#else /* _WRS_CONFIG_LP64 */
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#define _WRS_WIND_VARS_OFFSET_pMmuCurrentTransTbl \
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(_WRS_WIND_VARS_OFFSET_archVars+0x0)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadPc \
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(_WRS_WIND_VARS_OFFSET_archVars+0x04)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadEax \
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(_WRS_WIND_VARS_OFFSET_archVars+0x08)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadEbx \
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(_WRS_WIND_VARS_OFFSET_archVars+0x0c)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadEflags \
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(_WRS_WIND_VARS_OFFSET_archVars+0x10)
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#define _WRS_WIND_VARS_OFFSET_ctxLoadIntLock \
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(_WRS_WIND_VARS_OFFSET_archVars+0x14)
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#define _WRS_WIND_VARS_OFFSET_intNest \
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(_WRS_WIND_VARS_OFFSET_archVars+0x20)
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#define _WRS_WIND_VARS_OFFSET(reg) rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
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#define _WRS_SIMIA_VAR_ADRS(label) FUNC(vxKernelVars+OFFSET_##label)
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/*
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* take the value at *pVxCpuIndex and shift to get the vxKernelVar index
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* 0,128,256 ...
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*/
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#define _SIMIA_CPU_INDEX_GET(regSuffix) \
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movl VAR(pVxCpuIndex),%REG32_r##regSuffix; \
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movl (%REG32_r##regSuffix),%REG32_r##regSuffix;\
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rol $_WRS_WIND_VARS_ALIGN_SHIFT,%REG32_r##regSuffix;
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#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
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leal FUNC(vxKernelVars),%REG32_r##reg; \
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addl $_WRS_WIND_VARS_OFFSET_##label,%REG32_r##reg;
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#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl %REG32_r##scratch,%REG32_r##regSuffix;
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#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl %REG32_r##regSuffix,%REG32_r##scratch; \
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movl 0x0(%REG32_r##scratch),%REG32_r##regSuffix;
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#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
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_SIMIA_CPU_INDEX_GET(regSuffix) \
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
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addl %REG32_r##regSuffix,%REG32_r##scratch; \
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movl 0x0(%REG32_r##scratch),%REG32_r##regSuffix; \
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incl %REG32_r##regSuffix; \
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movl %REG32_r##regSuffix,0x0(%REG32_r##scratch);
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#endif /* _WRS_CONFIG_LP64 */
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#endif /* _ASMLANGUAGE */
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#else /* _WRS_CONFIG_SMP */
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#define _WRS_CPU_INDEX_GET() 0
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/* macro to access the arch-specific fields */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (glob)
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#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
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#define _WRS_WIND_VARS_ARCH_LOCKED_GET(glob,var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET (glob,var)
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#ifdef _ASMLANGUAGE
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#ifdef _WRS_CONFIG_LP64
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#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
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movabsq $FUNC(label),%r##regSuffix;
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#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
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movabsq $FUNC(label),%r##regSuffix; \
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movl (%r##regSuffix),%REG32_r##regSuffix;
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#define _SIMIA_PER_CPU_VALUE64_GET(regSuffix,scratch,label) \
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movabsq $FUNC(label),%r##regSuffix; \
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mov (%r##regSuffix),%r##regSuffix
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#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
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movabsq $FUNC(label),%r##scratch; \
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movl (%r##scratch),%REG32_r##regSuffix; \
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incl %REG32_r##regSuffix; \
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movl %REG32_r##regSuffix,(%r##scratch);
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#else /* _WRS_CONFIG_LP64 */
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#define _SIMIA_PER_CPU_ADRS_GET(regSuffix,scratch,label) \
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leal FUNC(label),%REG32_r##regSuffix;
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#define _SIMIA_PER_CPU_VALUE32_GET(regSuffix,scratch,label) \
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movl FUNC(label),%REG32_r##regSuffix;
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#define _SIMIA_PER_CPU_VALUE32_INC(regSuffix,scratch,label) \
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incl FUNC(label); \
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movl FUNC(label),%REG32_r##regSuffix;
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#endif /* _WRS_CONFIG_LP64 */
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#endif /* _ASMLANGUAGE */
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#endif /* _WRS_CONFIG_SMP */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCsmpSimntPh */
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