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neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
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vxworks-6.9/target/h/arch/ppc/private/excArchLibP.h
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/* excArchLibP.h - PowerPC exception library private exports */
/*
* Copyright (c) 2003-2005, 2008, 2009, 2013, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/* Definitions for use only by PPC excArchLib.c and syscallArchLib.c */
/*
modification history
--------------------
01j,28aug18,jli fixed wrong macro EXT_ENT_CRT_OFF for T4_ERRATUM_CPU6198 (VXW6-86904)
01i,01mar13,h_k added T4_ERRATUM_CPU6198 for e6500.
01h,18nov09,to GUEST: _VB_PISA_EHV support
01g,12may09,rec move guestOs ENT_OFF definition here
01f,23may08,pch CQ118100: clean up SMP support in critical-exception handling
01e,17oct05,pch SPR 113899: exc/intConnectCode must restore 32-bit mode
before calling exc/intEnt
01d,22sep04,pch Add debug/trace capabilities (under #ifdef)
01c,06aug04,pch SPR's 78780 & 100398: support use of standard exception
vectors in MMU and syscall
01b,05may04,pch SPR 92997: use correct symbol name in multiple-include
protection
01a,08Dec03,pch extracted from excArchLib.c vn 02z
*/
#ifndef __INCexcArchLibPh
#define __INCexcArchLibPh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/*
* The following typedefs are used within excArchLib.c in the interest
* of clarity, to keep from making matters worse than they already are.
* (Several existing published API's are defined with types that are just
* plain wrong for the PowerPC port, however, we are stuck with them.)
*/
typedef UINT32 vecTblOffset; /* Offset in vector table, e.g. _EXC_OFF_* */
typedef char * codeBase; /* Base address in normal code space */
typedef char * vectorBase; /* Base address in vector execution space */
typedef char * codePtr; /* Pointer into normal code space */
typedef char * vectorPtr; /* Pointer into vector execution space */
/*
* Convert a (vectorPtr) into a (codePtr), allowing for any difference
* between excVecBase and excVecBaseAltAdrs. The distinction is critical
* during initialization, when vector execution space may not be accessible
* because the MMU has not yet been set up.
*/
#define CODE_PTR_FROM_VECTOR_PTR(vecp) \
(codePtr)((((vectorPtr)(vecp)) - excVecBase) + excVecBaseAltAdrs)
#endif /* _ASMLANGUAGE */
/*
* Word offsets to the branch instructions in
* the exc*ConnectCode arrays in excArchLib.c
*
* Changes affecting ENT_OFF or ENT_CRT_OFF will require corresponding
* changes in excALib.s:excEnt() and excCrtEnt() when calculating the
* original vector address from the LR value.
*/
#if defined(_EXC_OFF_CRTL) || defined(_WRS_PPC_64BIT)
# if defined(T4_ERRATUM_CPU6198) && defined(_WRS_CONFIG_SMP)
# define T4_LIS_OFF 4 /* offset for lis p0,HI(mtmsrwa) */
# define T4_ORI_OFF 5 /* offset for ori p0,p0,LO(mtmsrwa) */
# define T4_LABEL_OFF 8 /* offset for RMCI to */
# define ENT_OFF 9 /* offset for intEnt/excEnt */
# define ISR_OFF 12 /* offset for ISR or exc. handler */
# define EXIT_OFF 14 /* offset for intExit/excExit */
# define EXT_ENT_OFF 10 /* offset for ext intEnt/excEnt */
# define EXT_ISR_OFF 15 /* offset for ext ISR or exc handler */
# define EXT_EXIT_OFF 22 /* offset for ext intExit/excExit */
# else
# define ENT_OFF 6 /* offset for intEnt/excEnt */
# define ISR_OFF 9 /* offset for ISR or exc. handler */
# define EXIT_OFF 11 /* offset for intExit/excExit */
# define EXT_ENT_OFF 7 /* offset for ext intEnt/excEnt */
# define EXT_ISR_OFF 12 /* offset for ext ISR or exc handler */
# define EXT_EXIT_OFF 19 /* offset for ext intExit/excExit */
# endif /* T4_ERRATUM_CPU6198 && _WRS_CONFIG_SMP */
# ifdef _EXC_OFF_CRTL
# define EXT_ENT_CRT_OFF 3 /* offset for ext intEnt/excEnt */
# define EXT_ISR_CRT_OFF 8 /* offset for ext ISR or exc handler */
# define EXT_EXIT_CRT_OFF 15 /* offset for ext intExit/excExit */
# define ENT_CRT_OFF 2 /* offset for intEnt/excEnt */
# define ISR_CRT_OFF 5 /* offset for ISR or exc. handler */
# define EXIT_CRT_OFF 7 /* offset for intCrtExit/excCrtExit */
# endif /* _EXC_OFF_CRTL */
# if defined(_EXC_OFF_CRTL) && defined(LOG_FRAMELESS)
/*
* Logging of "frameless nesting" occurences, used only for testing purposes.
*
* Each log record consists of one word, with the record type (exit case) in
* the most-significant byte and the interrupted vector offset in the least-
* significant halfword. The round-robin log buffer pointer, and the counts
* for the three record types, are stored at addresses 0x80-0x8f.
*
* CRT_COUNT_061C is used when TRAP_DISPATCH_ADDR is also set, for debugging.
*/
/* offsets from address zero */
#define LOG_FML_PTR 0x80 /* where to store next log record */
#define RIV_COUNT 0x84 /* count of resume-in-vector cases */
#define ESF_COUNT 0x88 /* count of copy-ESF cases */
#define STM_COUNT 0x8c /* count of syscall/TLB-miss cases */
#define CRT_COUNT_ENT 0x90 /* count of all critical interrupt entries */
#define CRT_COUNT_EXIT 0x94 /* count of all critical interrupt exits */
#define CRT_COUNT_RESC 0x98 /* calls of reschedule from intCrtExit */
#define CRT_COUNT_061C 0x9c /* dispatches of PC==0x061C in windALib */
#define CRT_COUNT_RESV 0xa0 /* reserved for future use */
/* log record types */
#define RIV_TYPE 0x5000 /* resume-in-vector */
#define ESF_TYPE 0x6000 /* copy-ESF */
#define STM_TYPE 0x7000 /* syscall/TLB-miss */
/* size of log record in bytes */
#define LOG_FML_SIZE 4
/* size of log buffer in bytes, must be a power of 2 */
#define LOG_FML_BUF_SIZE 0x1000
/* bit number corresponding to buffer size, used to wrap log pointer */
#define LOG_FML_BIT 19
# endif /* _EXC_OFF_CRTL && LOG_FRAMELESS */
#else /* _EXC_OFF_CRTL || _WRS_PPC_64BIT */
# define ENT_OFF 2 /* offset for intEnt/excEnt */
# define ISR_OFF 5 /* offset for ISR or exc. handler */
# define EXIT_OFF 7 /* offset for intExit/excExit */
# define EXT_ENT_OFF 3 /* offset for ext intEnt/excEnt */
# define EXT_ISR_OFF 8 /* offset for ext ISR or exc handler */
# define EXT_EXIT_OFF 15 /* offset for ext intExit/excExit */
#endif /* _EXC_OFF_CRTL || _WRS_PPC_64BIT */
#if defined(_WRS_CONFIG_WRHV_GUEST) && !defined(_WRS_CONFIG_VBI_PPC_E500MC)
# undef ENT_OFF
# define ENT_OFF 3 /* 3 words in for guest OS */
#endif /* _WRS_CONFIG_WRHV_GUEST && !_WRS_CONFIG_VBI_PPC_E500MC */
#ifdef LOG_DISPATCH
/* logging of dispatch (rfi/rfci) operations, used only for debugging */
/* offsets from address zero */
#define LOG_DISP_PTR 0xec /* where to store next log record */
#define LOG_DISP_SAVE 0xe8 /* last LOG_DISP_PTR when logging suspended */
/* offsets in log record */
#define LOG_DISP_ID 0x00 /* record type = dispatcher ID */
#define LOG_DISP_LR 0x04 /* LR value (who called dispatcher) */
#define LOG_DISP_SP_IN 0x08 /* SP value when dispatcher called */
#define LOG_DISP_CTX 0x0c /* address context loaded from */
#define LOG_DISP_PC 0x10 /* PC value to be loaded */
#define LOG_DISP_MSR 0x14 /* MSR value to be loaded */
#define LOG_DISP_SP_OUT 0x18 /* SP value to be loaded */
#define LOG_DISP_NXT_FL 0x1c /* current value of LOG_FML_PTR */
/* size of log record in bytes */
#define LOG_DISP_SIZE 32
/* size of log buffer in bytes, must be a power of 2 */
#define LOG_DISP_BUF_SIZE 0x2000
/* bit number corresponding to buffer size, used to wrap log pointer */
#define LOG_DISP_BIT 18
/* log record types */
#define DISP_WIND 0x01 /* windLoadContext */
#define DISP_CTXL 0x02 /* _sigCtxLoad */
#define DISP_EXCN 0x03 /* excExit */
#define DISP_EXCC 0x04 /* excCrtExit */
#define DISP_INTN 0x05 /* intExit, normal case */
#define DISP_INTP 0x06 /* intExit, preempting (reschedule) */
#define DISP_INTI 0x07 /* intExit, idle case */
#define DISP_INTC 0x08 /* intCrtExit, normal case */
#define DISP_INCR 0x09 /* intCrtExit, frameless RIV case */
#define DISP_INCI 0x0a /* intCrtExit, idle case */
#define DISP_INCP 0x0b /* intCrtExit, preempting (reschedule) */
#define DISP_INCF 0x0c /* intCrtExit, frameless preempting (copyESF) */
#define DISP_DTLB 0x0d /* data TLB miss handled */
#define DISP_ITLB 0x0e /* insn TLB miss handled */
#define DISP_RTPI 0x0f /* rtpUserModeSwitch */
#define DISP_SYSC 0x10 /* resume after syscall */
#define DISP_EXCM 0x11 /* excMchkExit */
#define DISP_POW 0x12 /* vxC1StateSet */
#endif /* LOG_DISPATCH */
#ifdef __cplusplus
}
#endif
#endif /* __INCexcArchLibPh */
vxworks-6.9/target/h/arch/ppc/private/ppcArchVarsP.h
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/* ppcArchVarsP.h - PowerPC private variables */
/*
* Copyright (c) 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify, or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,21sep10,jpb created
*/
#ifndef __INCppcArchVarsPh
#define __INCppcArchVarsPh
#ifdef __cplusplus
extern "C" {
#endif
extern FUNCPTR _func_mmuCacheFlushLoadAdrsGet;
extern FUNCPTR _func_ppc440x5RefreshTlb0;
extern FUNCPTR _func_cache440EarlyCleanup;
extern FUNCPTR _func_cacheArchEnable;
extern FUNCPTR _func_cacheArchDisableFromMmu;
#ifdef __cplusplus
}
#endif
#endif /* __INCppcArchVarsPh */
vxworks-6.9/target/h/arch/ppc/private/smpPpcP.h
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/* private/smpPpcP.h - PowerPC-specific definitions for SMP support */
/*
* Copyright (c) 2006-2013 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Any compilation using definitions from this file will not *
* be binary-compatible between the UP and SMP environments. *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*/
/*
modification history
--------------------
02i,08mar13,pcs Fix a type from the previous checkin.
02h,07mar13,pcs Fix the offset for _WRS_WIND_VARS_OFFSET_intCrtSaveArea for
PPC_e6500.
02g,04feb13,pcs cleanup for code review.
02f,08nov12,zl added _WRS_CPU_SMTSET_GET() definition
02e,31oct12,pcs Add struct tlb1EntrySelect to struct wind_vars_arch
02d,08mar12,h_k removed _WRS_ARCH_REQUIRES_TLB_ALL_SYNC_CPC and
_WRS_ARCH_REQUIRES_TLB_SYNC_CPC. (WIND00320752)
02c,22nov11,x_s Define _WRS_ARCH_REQUIRES_TLB_SYNC_CPC for PPC465
02b,18nov10,x_z Add support for PPC476
02a,12jun10,rab update _PPC_CPU_INDEX_GET for guest smp
02b,29apr10,pad Moved extern C statement after include statements.
02a,15mar10,gls added _WRS_ARCH_HAS_OBJ_SAFE
01z,02feb10,liu clear up compile warnings and avoid macro redefined.
(WIND00146270)
01z,05jan10,pmr remove e500mc PIR shift
01y,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
01x,18sep08,gls made _WRS_KERNEL_LOCK_VAR_ALIGN available to assembly files
01w,31aug08,pch change _PPC_CACHE_MODE_IS_CONSISTENT to
_WRS_CONFIG_PPC_CACHE_MODE_IS_CONSISTENT for VSB
01v,27aug08,jpb Renamed VSB header file
01u,25jun08,jpb Added include path for kernel configurations options set in
vsb.
01t,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
01s,18may08,pch CQ118100: Add intCrtSaveArea definition in wind_vars_arch{}
01r,08may08,jpb Modifications for source build. Renamed
INCLUDE_VM_RTP to _WRS_CONFIG_VM_MULTIPLE_CONTEXT,
_WRS_VX_SMP to _WRS_CONFIG_SMP.
01q,05may08,to revised _PPC_PER_CPU_ macros
01p,07apr08,to added attribute macros for kernelStateLock and vxKernelVars
01o,18mar08,h_k added more _PPC_PER_CPU_ macros.
01n,24apr08,pmr shift PIR for e500mc
01m,06mar08,pch Define _PPC_CACHE_MODE_IS_CONSISTENT in SMP build
Move other SMP-dependent settings from archPpc.h
01l,10jan08,gls added VX_INSTR_BARRIER()
01k,27nov07,dtr Add _WRS_ARCH_REQUIRES_TLB_ALL_SYNC_CPC for 85XX SMP AIM MMU.
01j,08jun07,kk added _WRS_MMU_HAS_MAP_STATE_API
01i,17apr07,kk move VX_MAX_SMP_CPUS to archPpc.h
01h,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
01g,26oct06,to define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
simplify _PPC_PER_CPU macros
01f,20oct06,mmi changed WIND_VARS_ARCH fields as void * to remove dependency
on mmuPpcLib.h
01e,11oct06,mmi Enable VX_KERNEL_VARS
01d,12sep06,lei added _PPC_KERNEL_LOCK_OWNER_AND_INDEX_GET
01c,24aug06,to added _PPC_MINIMAL_TRY_LOCK macro
added _PPC_PER_CPU_VALUE_SET_ADRS_GET macro
01b,23aug06,mmi added macro's to access WIND_VARS macro's
01a,19jul06,pch written.
*/
#ifndef __INCsmpPpcPh
#define __INCsmpPpcPh
#include <vsbConfig.h>
#include <private/kernelLockLibP.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifdef _WRS_CONFIG_SMP
/*
* PPC has been adapted to use the new object safe count feature for SMP.
* When all architectures have been adapted this can be removed from
* the code.
*/
#define _WRS_ARCH_HAS_OBJ_SAFE
/*
* WIND_VARS_ARCH must be the same size and alignment for all PPC because
* code using WIND_VARS is built for PPC32 rather than for specific CPUs
* and variants, but as long as its contents are used only by the PPC arch
* code there is no particular reason why the space must be used in the
* same way by all PPC.
*
* Because there are currently no supported (or known) PPC whose MMUs
* incorporate segment registers and which also implement critical
* interrupts, we reuse the currentSrTbl and currentPgTbl pointers in
* WIND_VARS_ARCH as the save area for the critical interrupt handler.
* There is no need for this reuse to be visible to C code, since the
* save area is referenced only within intCrtEnt().
*
* This is purely a matter of saving space: if we ever need to support
* such a processor we can simply enlarge WIND_VARS_ARCH to 4 words
* and adjust the definition of _WRS_WIND_VARS_OFFSET_intCrtSaveArea
* accordingly. The following #if ... #error is provided to ensure
* that, if such a processor is encountered, the need to change the
* definitions here will not be overlooked.
*/
#if defined (_WRS_MMU_CLASS_SR_REGS) && defined (_PPC_MSR_CE_U)
#error WIND_VARS_ARCH does not currently support processors having both segment regs and critical ints
#endif
/*
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
* XSCALE, etc), representing the maximum cache line size of the variants of
* the respective arch.
*
* For PPC this is 128 bytes.
*/
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
/* PPC specific extension fields to the WIND_VARS struct */
#ifndef _ASMLANGUAGE
/*
* 8-byte alignment needed when used as intCrtSaveArea,
* to ensure that both words are in the same cache line
*/
typedef struct wind_vars_arch
{
#if defined (PPC_e6500)
struct tlb1EntrySelect * cpu_tlb1EselPtr;
struct tlb1EntrySelect cpu_tlb1Esel;
#else
union sr * cpu_currentSrTbl;
union level_1_desc * cpu_currentPgTbl;
#endif
} WIND_VARS_ARCH _WRS_DATA_ALIGN_BYTES(8);
#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS(archVars.cpu_##glob)
#if 0
/* XXX putting vxKernelVars[] into SDA degrades performance for some cases. */
#define _WRS_VX_KERNEL_VARS_SECTION_ATTR _WRS_SDA_BSS
#endif /* 0 */
#define _WRS_KERNEL_STATE_LOCK_SECTION_ATTR _WRS_SDA_DATA
#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
extern cpuset_t __vxSmtSet[];
#define _WRS_CPU_SMTSET_GET(smtSet, cpuIx) smtSet = __vxSmtSet[cpuIx]
#else /* !_ASMLANGUAGE */
/*
* offsets required for assembly macros, allowing for above 8-byte alignment
* We can't use ROUND_UP here because its expansion includes a typecast that
* is valid only in C, not in assembly.
*/
#define WIND_VARS_ARCH_BASE (((_WRS_WIND_VARS_OFFSET_archVars) + 7) & ~7)
/*
* It is OK for these definitions to be based on CPU feature set since
* they are used only in assembly code that is built per-variant.
*/
#if defined (PPC_e6500)
#define _WRS_WIND_VARS_OFFSET_tlb1EselPtr (WIND_VARS_ARCH_BASE + 0)
#endif
# if defined (_WRS_MMU_CLASS_SR_REGS)
#define _WRS_WIND_VARS_OFFSET_currentSrTbl (WIND_VARS_ARCH_BASE + 0)
#define _WRS_WIND_VARS_OFFSET_currentPgTbl (WIND_VARS_ARCH_BASE + 4)
# elif defined (_PPC_MSR_CE_U)
#if defined(PPC_e6500)
#define _WRS_WIND_VARS_OFFSET_intCrtSaveArea (WIND_VARS_ARCH_BASE + 8)
#else
#define _WRS_WIND_VARS_OFFSET_intCrtSaveArea (WIND_VARS_ARCH_BASE + 0)
#endif
# endif /* _WRS_MMU_CLASS_SR_REGS, _PPC_MSR_CE_U */
#endif /* _ASMLANGUAGE */
#define _WRS_MMU_HAS_MAP_STATE_API
#define _ARCH_SUPPORTS_PROTECT_IDLE_TASK_STACK
/*
* Defining _WRS_CONFIG_PPC_CACHE_MODE_IS_CONSISTENT removes cache management
* around enabling and disabling the MMU. It is always defined in SMP builds,
* where the cache is required to always be enabled, coherent, and in
* copyback mode (matching the default 60x no-MMU WIMG of 0011). It can
* potentially also be defined in source builds for UP systems, but only
* if the accompanying constraints on cache configuration are met; this
* cannot safely be assumed for UP systems in general due to legacy
* considerations.
*/
#ifndef _WRS_CONFIG_PPC_CACHE_MODE_IS_CONSISTENT
#define _WRS_CONFIG_PPC_CACHE_MODE_IS_CONSISTENT
#endif
/*
* Some PowerPC will fault if an atomic operation (lwarx/stwcx.) is attempted
* before the data cache has been enabled. This flag causes edrBufLock(),
* edrBufUnlock(), and perhaps other places, to consult spinLockApiAvailable()
* before attempting to take a spinlock. It is also used in windALib.s to
* determine whether the spinLockApiAvailable() function should be defined.
*/
#define _WRS_ARCH_HAS_SPINLOCK_API_AVAILABLE
# ifndef _ASMLANGUAGE
/*
* spinLockApiAvailable actually returns BOOL, but neither that name nor
* IMPORT has necessarily been defined by the time this file is included.
*/
extern int spinLockApiAvailable(void);
# endif /* _ASMLANGUAGE */
/*
* _WRS_WIND_VARS_ALIGN sets the alignment constraint for vxKernelVars.
* The value must be:
* a power of two no smaller than sizeof(vxKernelVars), and
* a multiple of the cache line size on every PPC variant that supports SMP.
*/
#define _WRS_WIND_VARS_ALIGN 128
#define _WRS_WIND_VARS_ALIGN_SHIFT 7
/*
* _PPC_ATOMIC_OPS_SEPARATION defines the minimum desirable separation
* between words on which SMP-atomic operations (including spinlock)
* will be performed, and should be set to the largest lwarx/stwcx.
* granularity on any PPC variant that supports SMP (disregarding any
* where the granularity is too large to honor, e.g. the entire address
* space). This turns out to be the cache line size on several SMP PPC.
*/
#define _PPC_ATOMIC_OPS_SEPARATION 128
# ifdef _CPU_CACHE_ALIGN_SIZE
/*
* Validate _WRS_WIND_VARS_ALIGN vs current build's _CPU_CACHE_ALIGN_SIZE
*
* If any SMP-enabled variant fails this test, _WRS_WIND_VARS_ALIGN must be
* increased. Since this limit also applies to any subsequent arch-only
* release against the same generic binary release, it may be desirable to
* allow for growth.
*/
# if (_CPU_CACHE_ALIGN_SIZE > _WRS_WIND_VARS_ALIGN)
#error Must increase "_WRS_WIND_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
# endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_WIND_VARS_ALIGN */
/*
* Sanity check on _PPC_ATOMIC_OPS_SEPARATION
*
* A miss here generates a warning instead of an error, since it is merely
* likely (not inevitable) that the lwarx/stwcx. granularity matches the
* cache line size; also the performance penalty is less. (Two instances of
* vxKernelVars within the same cache line will cause continual interference,
* but two atoms within the same reservation granule will only occasionally
* cause additional trips around the lwarx/stwcx. loop due to loss of the
* reservation to an unrelated store.)
*/
# if (_CPU_CACHE_ALIGN_SIZE > _PPC_ATOMIC_OPS_SEPARATION)
#warning Check "_PPC_ATOMIC_OPS_SEPARATION" setting; it likely should be at least _CPU_CACHE_ALIGN_SIZE
# endif /* _CPU_CACHE_ALIGN_SIZE > _PPC_ATOMIC_OPS_SEPARATION */
# endif /* _CPU_CACHE_ALIGN_SIZE */
/*
* Just call the (assembly) function for now, but to optimize
* performance this should eventually become a C-callable
* _WRS_ASM construct (whose syntax varies depending on TOOL).
*/
#define _WRS_CPU_INDEX_GET() vxCpuIndexGet()
#else /* _WRS_CONFIG_SMP */
#define _WRS_CPU_INDEX_GET() 0
#endif /* _WRS_CONFIG_SMP */
#ifdef _ASMLANGUAGE
# ifdef _WRS_CONFIG_SMP
DATA_IMPORT(vxKernelVars);
/* NOTE: PCV stands for per-cpu variable */
/* get the index of current cpu */
#ifdef _WRS_CONFIG_WRHV_GUEST
#define VB_VCORE_ID_OFFSET 0x98
#define _PPC_CPU_INDEX_GET(r) lis r, HIADJ(wrhvVbConfig) ; \
lwz r, LO(wrhvVbConfig)(r) ; \
lwz r, VB_VCORE_ID_OFFSET(r)
#else /* _WRS_CONFIG_WRHV_GUEST */
# if (CPU == PPC476)
#define _PPC_CPU_INDEX_GET(r) mfspr r, SPRG8
# else /* !PPC476 */
#define _PPC_CPU_INDEX_GET(r) mfspr r, PIR
# endif /* PPC476 */
#endif /* _WRS_CONFIG_WRHV_GUEST */
/* offset into "label" from the start of the windVars structure */
#define _WRS_WIND_VARS_OFFSET(label) (_WRS_WIND_VARS_OFFSET_##label)
/* offset into "label" from "bLabel" */
#define _WRS_WIND_VARS_OFFSET_FROM_BASE(label, bLabel) \
(_WRS_WIND_VARS_OFFSET(label) - _WRS_WIND_VARS_OFFSET(bLabel))
/* address of the "label" per-cpu variable for cpu0 */
#define _WRS_CPU0_VAR_ADRS(label) (vxKernelVars+_WRS_WIND_VARS_OFFSET(label))
/* get the offset into the per-cpu variables for "cpuIx" */
#define _PPC_PER_CPU_VARS_CPU_OFFSET_GET_WITH_INDEX(offset, cpuIx) \
slwi offset, cpuIx, _WRS_WIND_VARS_ALIGN_SHIFT
/* get the offset into the per-cpu variables for current cpu */
#define _PPC_PER_CPU_VARS_CPU_OFFSET_GET(r) \
_PPC_CPU_INDEX_GET(r) ; \
_PPC_PER_CPU_VARS_CPU_OFFSET_GET_WITH_INDEX(r, r)
/*
* _CPU_OFFSET macros are mainly used to construct other _PPC_PER_CPU_ macros.
* Please be careful when using them in assembly code as they don't have
* the UP counterparts.
*/
/* get the address of the "label" variable with cpu offset */
#define _PPC_PER_CPU_ADRS_GET_WITH_CPU_OFFSET(ra, label, offset) \
addis ra, offset, HIADJ(_WRS_CPU0_VAR_ADRS(label)) ; \
addi ra, ra, LO(_WRS_CPU0_VAR_ADRS(label))
/* get the value of the "label" variable with cpu offset */
#define _PPC_PER_CPU_VALUE_GET_WITH_CPU_OFFSET(rv, label, offset) \
addis rv, offset, HIADJ(_WRS_CPU0_VAR_ADRS(label)) ; \
lwz rv, LO(_WRS_CPU0_VAR_ADRS(label))(rv)
/* set the value of the "label" variable with cpu offset */
#define _PPC_PER_CPU_VALUE_SET_WITH_CPU_OFFSET(v, sc, label, offset) \
addis sc, offset, HIADJ(_WRS_CPU0_VAR_ADRS(label)) ; \
stw v, LO(_WRS_CPU0_VAR_ADRS(label))(sc)
/* get the value and the address of the "label" variable with cpu offset */
#define _PPC_PER_CPU_VALUE_AND_ADRS_GET_WITH_CPU_OFFSET(rv, ra, label, offset) \
addis ra, offset, HIADJ(_WRS_CPU0_VAR_ADRS(label)) ; \
lwzu rv, LO(_WRS_CPU0_VAR_ADRS(label))(ra)
/* set the value and get the address of the "label" variable with cpu offset */
#define _PPC_PER_CPU_VALUE_SET_ADRS_GET_WITH_CPU_OFFSET(v, ra, label, offset) \
addis ra, offset, HIADJ(_WRS_CPU0_VAR_ADRS(label)) ; \
stwu v, LO(_WRS_CPU0_VAR_ADRS(label))(ra)
/*
* simple _GET/_SET macros should be used when only one PCV needs to be
* accessed or there's no register available to save base address.
*/
/* get the address of the "label" variable for current cpu */
#define _PPC_PER_CPU_ADRS_GET(r, label) \
_PPC_PER_CPU_VARS_CPU_OFFSET_GET(r) ; \
_PPC_PER_CPU_ADRS_GET_WITH_CPU_OFFSET(r, label, r)
/* get the value of the "label" variable for current cpu */
#define _PPC_PER_CPU_VALUE_GET(r, label) \
_PPC_PER_CPU_VARS_CPU_OFFSET_GET(r) ; \
_PPC_PER_CPU_VALUE_GET_WITH_CPU_OFFSET(r, label, r)
/* set the value of the "label" variable for current cpu */
#define _PPC_PER_CPU_VALUE_SET(v, sc, label) \
_PPC_PER_CPU_VARS_CPU_OFFSET_GET(sc) ; \
_PPC_PER_CPU_VALUE_SET_WITH_CPU_OFFSET(v, sc, label, sc)
/* get the value and the address of the "label" variable for current cpu */
#define _PPC_PER_CPU_VALUE_AND_ADRS_GET(rv, ra, label) \
_PPC_PER_CPU_VARS_CPU_OFFSET_GET(ra) ; \
_PPC_PER_CPU_VALUE_AND_ADRS_GET_WITH_CPU_OFFSET(rv, ra, label, ra)
/* set the value and get the address of the "label" variable for current cpu */
#define _PPC_PER_CPU_VALUE_SET_ADRS_GET(v, ra, label) \
_PPC_PER_CPU_VARS_CPU_OFFSET_GET(ra) ; \
_PPC_PER_CPU_VALUE_SET_ADRS_GET_WITH_CPU_OFFSET(v, ra, label, ra)
/*
* _VARS_BASE_GET/_WITH_BASE macros should be used when multiple PCVs need
* to be accessed and it is guaranteed that the current CPU will not change
* while accessing multiple PCVs (i.e. interrupt locked or kernel lock taken).
*/
/*
* get the address of the "label" variable as the base address of PCVs
* for current cpu
*/
#define _PPC_PER_CPU_VARS_BASE_GET(rb, label) \
_PPC_PER_CPU_ADRS_GET(rb, label)
/*
* get the address of the "label" variable as the base address of PCVs
* with cpu offset
*/
#define _PPC_PER_CPU_VARS_BASE_GET_WITH_CPU_OFFSET(rb, label, offset) \
_PPC_PER_CPU_ADRS_GET_WITH_CPU_OFFSET(rb, label, offset)
/*
* get the value and the address of the "label" variable
* and use the address as the base address of PCVs
* for current cpu
*/
#define _PPC_PER_CPU_VALUE_AND_VARS_BASE_GET(rv, rb, label) \
_PPC_PER_CPU_VALUE_AND_ADRS_GET(rv, rb, label)
/*
* set the value and get the address of the "label" variable
* and use the address as the base address of PCVs
* for current cpu
*/
#define _PPC_PER_CPU_VALUE_SET_VARS_BASE_GET(v, rb, label) \
_PPC_PER_CPU_VALUE_SET_ADRS_GET(v, rb, label)
/* get the address of the "label" variable with the base address of "bLabel" */
#define _PPC_PER_CPU_ADRS_GET_WITH_BASE(ra, label, b, bLabel) \
addi ra, b, _WRS_WIND_VARS_OFFSET_FROM_BASE(label, bLabel)
/* get the value of the "label" variable with the base address of "bLabel" */
#define _PPC_PER_CPU_VALUE_GET_WITH_BASE(rv, label, b, bLabel) \
lwz rv, _WRS_WIND_VARS_OFFSET_FROM_BASE(label, bLabel)(b)
/* set the value of the "label" variable with the base address of "bLabel" */
#define _PPC_PER_CPU_VALUE_SET_WITH_BASE(v, sc, label, b, bLabel) \
stw v, _WRS_WIND_VARS_OFFSET_FROM_BASE(label, bLabel)(b)
/*
* get the value and the address of the "label" variable
* with the base address of "bLabel"
*/
#define _PPC_PER_CPU_VALUE_AND_ADRS_GET_WITH_BASE(rv, ra, label, b, bLabel) \
_PPC_PER_CPU_VALUE_GET_WITH_BASE(rv, label, b, bLabel) ; \
_PPC_PER_CPU_ADRS_GET_WITH_BASE(ra, label, b, bLabel)
/*
* set the value and get the address of the "label" variable
* with the base address of "bLabel"
*/
#define _PPC_PER_CPU_VALUE_SET_ADRS_GET_WITH_BASE(v, ra, label, b, bLabel) \
_PPC_PER_CPU_VALUE_SET_WITH_BASE(v, label, b, bLabel) ; \
_PPC_PER_CPU_ADRS_GET_WITH_BASE(ra, label, b, bLabel)
/* _SDA is equivalent to non _SDA in SMP as vxKernelVars[] are not in SDA */
/* get the value of the "label" variable for current cpu (SDA base valid) */
#define _PPC_PER_CPU_VALUE_GET_SDA(rv, label) \
_PPC_PER_CPU_VALUE_GET(rv, label)
/* set the value of the "label" variable for current cpu (SDA base valid) */
#define _PPC_PER_CPU_VALUE_SET_SDA(v, sc, label) \
_PPC_PER_CPU_VALUE_SET(v, sc, label)
/*
* get the value and the address of the "label" variable
* and use the address as the base address of PCVs
* for current cpu (SDA base valid)
*/
#define _PPC_PER_CPU_VALUE_AND_VARS_BASE_GET_SDA(rv, rb, label) \
_PPC_PER_CPU_VALUE_AND_ADRS_GET(rv, rb, label)
/*
* set the value and get the address of the "label" variable
* and use the address as the base address of PCVs
* for current cpu (SDA base valid)
*/
#define _PPC_PER_CPU_VALUE_SET_VARS_BASE_GET_SDA(v, rb, label) \
_PPC_PER_CPU_VALUE_SET_ADRS_GET(v, rb, label)
/*
* get the value of the "label" variable with the base address of "bLabel"
* (SDA base valid)
*/
#define _PPC_PER_CPU_VALUE_GET_SDA_WITH_BASE(rv, label, b, bLabel) \
_PPC_PER_CPU_VALUE_GET_WITH_BASE(rv, label, b, bLabel)
/*
* set the value of the "label" variable with the base address of "bLabel"
* (SDA base valid)
*/
#define _PPC_PER_CPU_VALUE_SET_SDA_WITH_BASE(v, sc, label, b, bLabel) \
_PPC_PER_CPU_VALUE_SET_WITH_BASE(v, sc, label, b, bLabel)
/*
* Macros to support a minimal locking operation, using CR0 and one scratch
* register. A base register must also be provided unless the lock word is
* located within 32KB of address 0. The base register will not be altered,
* and unless using 0 (=> base address == 0) it must be preset. This is
* generalized from code originally written for mmu600ALib.s vn. 01v,10may06,to
*
* reg is a scratch register number in [1,31]
* offset is a 16-bit non-zero signed constant
* base is a base register number in [0,31]
* The lock word is located at offset(base), and is set to 0
* when the lock is not held, or offset when it is held.
*/
#define _PPC_MINIMAL_LOCK(reg, offset, base) \
10: lwz reg, offset(base) /* reg = key */ ; \
cmpwi reg, 0 ; \
bne- 10b /* spin until (lock == 0) */ ; \
li reg, offset ; \
lwarx reg, base, reg /* reg = lock (reserving) */ ; \
cmpwi reg, 0 ; \
bne- 10b /* spin until (reserved lock == 0) */ ; \
li reg, offset ; \
stwcx. reg, base, reg /* try store lock = offset */ ; \
bne- 10b /* retry if store failed */ ; \
isync
#define _PPC_MINIMAL_TRY_LOCK(reg, offset, base, label) \
li reg, offset ; \
lwarx reg, base, reg /* reg = lock (reserving) */ ; \
cmpwi reg, 0 ; \
bne label /* if (lock != 0) goto label */ ; \
li reg, offset ; \
stwcx. reg, base, reg /* try store lock = offset */ ; \
bne label /* goto label if failed */ ; \
isync
#define _PPC_MINIMAL_UNLOCK(reg, offset, base) \
sync ; \
li reg, 0 ; \
stw reg, offset(base)
/*
* ro = register to store kernel lock owner
* ri = register to store cpu index
*
* typedef struct vxKernelLock
* {
* atomic_t tkt_ctr; /@ ticket counter @/
* char pad[]; /@ force tkt_ctr to consume cache line @/
* int cpuIndex; /@ Owner cpu identifier @/
* atomic_t svc_ctr; /@ ticket currently being serviced @/
* int flags; /@ Reserved for system use @/
*/
#define _PPC_KERNEL_LOCK_OWNER_GET(ro) \
lis ro, HIADJ(kernelStateLock + _WRS_KERNEL_LOCK_OFFSET_cpuIndex); \
lwz ro, LO(kernelStateLock + _WRS_KERNEL_LOCK_OFFSET_cpuIndex)(ro)
#define _PPC_KERNEL_LOCK_OWNER_GET_SDA(ro) \
lwz ro, SDA21(kernelStateLock + _WRS_KERNEL_LOCK_OFFSET_cpuIndex)
#define _PPC_KERNEL_LOCK_OWNER_AND_INDEX_GET(ro, ri) \
_PPC_KERNEL_LOCK_OWNER_GET(ro) ; \
_PPC_CPU_INDEX_GET(ri)
# else /* _WRS_CONFIG_SMP */
/* Macro unconditionally returns 0 when built for UP */
#define _PPC_CPU_INDEX_GET(r) li r, 0
#define _PPC_PER_CPU_ADRS_GET(r, label) \
lis r, HIADJ(label) ; \
addi r, r, LO(label)
/*
* r2 and r13 could have the _SDA2_BASE_ and _SDA_BASE_ for RTP and it's not
* able to access through SDA. If it's certain it's not the case, it's
* recommended to use _PPC_PER_CPU_VALUE_GET_SDA()/_PPC_PER_CPU_VALUE_SET_SDA()
* to reduce the number of the instructions.
*/
#if (defined(_WRS_CONFIG_VM_MULTIPLE_CONTEXT) || !defined(_PPC_USE_SDA))
#define _PPC_PER_CPU_VALUE_GET(r, label) \
lis r, HIADJ(label) ; \
lwz r, LO(label)(r)
#else /* (_WRS_CONFIG_VM_MULTIPLE_CONTEXT || !_PPC_USE_SDA */
#define _PPC_PER_CPU_VALUE_GET(r, label) \
/* If RTP is not supported, use SDA any time. */ \
_PPC_PER_CPU_VALUE_GET_SDA(r, label)
#endif /* (_WRS_CONFIG_VM_MULTIPLE_CONTEXT || !_PPC_USE_SDA */
#if (defined(_WRS_CONFIG_VM_MULTIPLE_CONTEXT) || !defined(_PPC_USE_SDA))
#define _PPC_PER_CPU_VALUE_SET(v, sc, label) \
lis sc, HIADJ(label) ; \
stw v, LO(label)(sc)
#else /* (_WRS_CONFIG_VM_MULTIPLE_CONTEXT || !_PPC_USE_SDA */
#define _PPC_PER_CPU_VALUE_SET(v, sc, label) \
/* If RTP is not supported, use SDA any time. */ \
_PPC_PER_CPU_VALUE_SET_SDA(v, sc, label)
#endif /* (_WRS_CONFIG_VM_MULTIPLE_CONTEXT || !_PPC_USE_SDA */
#define _PPC_PER_CPU_VALUE_AND_ADRS_GET(rv, ra, label) \
lis ra, HIADJ(label) ; \
lwzu rv, LO(label)(ra)
#define _PPC_PER_CPU_VALUE_SET_ADRS_GET(v, ra, label) \
lis ra, HIADJ(label) ; \
stwu v, LO(label)(ra)
/* _VARS_BASE is ignored in UP */
#define _PPC_PER_CPU_VARS_BASE_GET(rb, label)
#define _PPC_PER_CPU_VALUE_AND_VARS_BASE_GET(rv, rb, label) \
_PPC_PER_CPU_VALUE_GET(rv, label)
#define _PPC_PER_CPU_VALUE_SET_VARS_BASE_GET(v, sc, label) \
_PPC_PER_CPU_VALUE_SET(v, sc, label)
#define _PPC_PER_CPU_ADRS_GET_WITH_BASE(ra, label, b, bLabel) \
_PPC_PER_CPU_ADRS_GET(ra, label)
#define _PPC_PER_CPU_VALUE_GET_WITH_BASE(rv, label, b, bLabel) \
_PPC_PER_CPU_VALUE_GET(rv, label)
#define _PPC_PER_CPU_VALUE_SET_WITH_BASE(v, sc, label, b, bLabel) \
_PPC_PER_CPU_VALUE_SET(v, sc, label)
#define _PPC_PER_CPU_VALUE_AND_ADRS_GET_WITH_BASE(rv, ra, label, b, bLabel) \
_PPC_PER_CPU_VALUE_AND_ADRS_GET(rv, ra, label)
#define _PPC_PER_CPU_VALUE_SET_ADRS_GET_WITH_BASE(v, ra, label, b, bLabel) \
_PPC_PER_CPU_VALUE_SET_ADRS_GET(v, ra, label)
#ifdef _PPC_USE_SDA
#define _PPC_PER_CPU_VALUE_GET_SDA(r, label) \
LOADVAR_SDA(r, label)
#define _PPC_PER_CPU_VALUE_SET_SDA(v, sc, label) \
STOREVAR_SDA(v, sc, label)
#else /* _PPC_USE_SDA */
#define _PPC_PER_CPU_VALUE_GET_SDA(r, label) \
_PPC_PER_CPU_VALUE_GET(r, label)
#define _PPC_PER_CPU_VALUE_SET_SDA(v, sc, label) \
_PPC_PER_CPU_VALUE_SET(v, sc, label)
#endif /* _PPC_USE_SDA */
#define _PPC_PER_CPU_VALUE_AND_VARS_BASE_GET_SDA(rv, rb, label) \
_PPC_PER_CPU_VALUE_GET_SDA(rv, label)
#define _PPC_PER_CPU_VALUE_SET_VARS_BASE_GET_SDA(v, sc, label) \
_PPC_PER_CPU_VALUE_SET_SDA(v, sc, label)
#define _PPC_PER_CPU_VALUE_GET_SDA_WITH_BASE(rv, label, b, bLabel) \
_PPC_PER_CPU_VALUE_GET_SDA(rv, label)
#define _PPC_PER_CPU_VALUE_SET_SDA_WITH_BASE(v, sc, label, b, bLabel) \
_PPC_PER_CPU_VALUE_SET_SDA(v, sc, label)
# endif /* _WRS_CONFIG_SMP */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCsmpPpcPh */
vxworks-6.9/target/h/arch/ppc/private/vxPortableArchP.h
+88
View File
@@ -0,0 +1,88 @@
/* vxPortableArchP.h - PowerPC portable library configuration */
/*
* Copyright (c) 2007-2008, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01m,20oct10,s_s renamed _WRS_PORTABLE_vxCpuIndexGet to _WRS_PORTABLE_vxCpuLib
(CQ:WIND00199670)
01l,29apr10,pad Moved extern C statement after include statements.
01k,10oct08,kk renamed _WRS_PORTABLE_spinlockIsrNdLib to
_WRS_PORTABLE_spinLockIsrNdLib
01j,27aug08,jpb Renamed VSB header file
01i,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01h,10jun08,to enabled optimized intContext for SMP
01g,18mar08,to enabled optimized taskIdSelf for SMP
01f,13feb08,to enabled optimized syscallDispatch
01e,16jan08,dlk Rename spinLockFastLib --> spinlockIsrNdLib.
01d,11dec07,dlk Add ppc-specific spinLockFastLib.
01c,22sep07,zl enabled optimized kernel lock library.
01b,11jul07,kk disabled optimized vxAtomicLib for UP
01a,04may07,zl created
*/
#ifndef __INCvxPortableArchPh
#define __INCvxPortableArchPh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <private/vxPortableP.h>. It may undefine
* portable library definitions in order to enable architecture specific
* implementation of a library or routine.
*/
/* the following can be overridden with PORTABLE */
#ifndef PORTABLE
#undef _WRS_PORTABLE_bLib
#undef _WRS_PORTABLE_ffsLib
#undef _WRS_PORTABLE_ffsTbl
#undef _WRS_PORTABLE_kernelLockLib
#undef _WRS_PORTABLE_swab
#undef _WRS_PORTABLE_spinLockIsrNdLib
#undef _WRS_PORTABLE_syscallDispatch
#ifdef _WRS_CONFIG_SMP
/*
* These functions' optimized implementations are only used for SMP,
* as portable implementations are already optimal for UP.
*/
#undef _WRS_PORTABLE_intContext
#undef _WRS_PORTABLE_taskIdSelf
#endif /* _WRS_CONFIG_SMP */
#endif /* PORTABLE */
/* the following cannot be overridden with PORTABLE */
#ifdef _WRS_CONFIG_SMP
/*
* UP can disable the cache, hence the optimized version that uses the
* lwarx/stwcx. can't be used
*/
#undef _WRS_PORTABLE_vxAtomicLib
#endif /* _WRS_CONFIG_SMP */
#undef _WRS_PORTABLE_vxCpuLib
#ifdef __cplusplus
}
#endif
#endif /* __INCvxPortableArchPh */
vxworks-6.9/target/h/arch/ppc/private/vxdbgPpcLibP.h
+106
View File
@@ -0,0 +1,106 @@
/* vxdbgPpcLibP.h - private PPC VxWorks debug library (VxDBG) header file */
/*
* Copyright (c) 2007-2008, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01g,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
SMP (CQ:WIND00253870).
01f,29apr10,pad Moved extern C statement after include statements.
01e,27aug08,jpb Renamed VSB header file
01d,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01c,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
01b,11oct07,rlp Added the VXDBG_INT_REGS_IS_LOCKED macro (CQ:WIND00107725).
01a,01jun07,jmp Written
*/
#ifndef __INCvxdbgPpcLibPh
#define __INCvxdbgPpcLibPh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This macro returns the <level> parameter modified with the interrupt lock
* level defined into the <value> parameter. The <level> parameter must be
* previously get with either intCpuLock() or intRegsLock() API.
*
* We have to define a dummy VXDBG_INT_LOCK_LEVEL_COMPUTE macro since
* _PPC_MSR_EE is not defined when we build the VxDBG code with CPU==PPC32.
*/
#ifdef _PPC_MSR_EE
#ifdef _PPC_MSR_CE
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~(_PPC_MSR_EE | _PPC_MSR_CE)) | \
(value & (_PPC_MSR_EE | _PPC_MSR_CE)))
#else /* _PPC_MSR_CE */
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~_PPC_MSR_EE) | (value & _PPC_MSR_EE))
#endif /* _PPC_MSR_CE */
#else /* _PPC_MSR_EE */
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) (level)
#endif /* _PPC_MSR_EE */
#ifdef _WRS_CONFIG_SMP
/*
* return TRUE if interrupts are locked in specified register set.
*
* We have to define a dummy VXDBG_INT_REGS_IS_LOCKED macro since _PPC_MSR_EE
* is not defined when we build the VxDBG code with CPU==PPC32.
*/
#ifdef _PPC_MSR_EE
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->msr & _PPC_MSR_EE) == \
_PPC_MSR_EE) ? FALSE : TRUE)
#else /* _PPC_MSR_EE */
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (FALSE)
#endif /* _PPC_MSR_EE */
/*
* _WRS_VXDBG_CPU_CTRL_VARS_ALIGN sets the alignment constraint for
* vxdbgCpuCtrlVars array.
* The value must be:
* a power of two no smaller than sizeof(vxdbgCpuCtrlVars), and
* a multiple of the cache line size on every PPC variant that supports SMP.
*/
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN 256
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT 8
#ifdef _CPU_CACHE_ALIGN_SIZE
/*
* Validate _WRS_VXDBG_CPU_CTRL_VARS_ALIGN vs current build's
* _CPU_CACHE_ALIGN_SIZE
*
* If any SMP-enabled variant fails this test, _WRS_VXDBG_CPU_CTRL_VARS_ALIGN
* must be increased. Since this limit also applies to any subsequent arch-only
* release against the same generic binary release, it may be desirable to
* allow for growth.
*/
#if (_CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN)
#error Must increase "_WRS_VXDBG_CPU_CTRL_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
#endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN */
#endif /* _CPU_CACHE_ALIGN_SIZE */
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxdbgLibPh */