original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,76 @@
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/* cavSdkDrvInclude.h - Define path to SDK for Wind River Cavium interface */
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/*
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* Copyright (c) 2010-2011, 2105 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
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||||
*/
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||||
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||||
/*
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modification history
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--------------------
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01c,12oct15,g_x select SDK path according to CPU (US67253)
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01b,14jun11,d_c Rename latest SDK directory in clearcase to OCTEON-SDK
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01a,20oct10,d_c written
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DESCRIPTION
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This header defines a macro to be used by the Wind River Cavium hardware
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interface API defined in h/arch/mips/cav*.h. In many cases, the API
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defines it's data types as aliases for native Cavium SDK data types.
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In these cases, the native SDK type is pulled in by including a header
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from the SDK.
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WARNING: The files included by the Wind River Cavium API have been
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reviewed and tested to be compatible with both the Diab and Gnu
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compilers, and verified to be backwards compatible to prior SDK
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versions. Many of the files in the Cavium SDK will not compile with
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Diab and are not suitable for directly including in our driver or BSP
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code. Do not use this macro directly in any driver or BSP module, or
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to include some other file that has not been verified.
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*/
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#ifndef __INCcavSdkDrvIncludeh
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#define __INCcavSdkDrvIncludeh
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#define CAV_SDK_STRINGIFY(x) #x
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/* Modules in target/src/vendor/octeon include .c and .h files direcly
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* from the SDK. They also include cav interface files
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* (arch/mips/cav*.h) for cav interface definitions. To avoid
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* including SDK files twice, these modules set CAV_INCLUDED_SDK to
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* indicate that the SDK has already been included. In that case, we
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* simply include this file, which essentially include nothing.
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*/
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#ifndef CAV_INCLUDED_SDK
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/* Here we define the path into the SDK directory. This is where the
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* selection of the SDK version to be used by drivers is selected. In
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* general, we always use the latest SDK we have tested and rely on it
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* to be backwards compatible with previous SDK versions.
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* For ARCH and SDK libraries building, we use 3.1.1 for CN78XX, and
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* 2.1.0 for others.
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*/
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#if ((OCTEON_BOARD == CAVIUM_BOARD_EBT3000) || (OCTEON_BOARD == CAVIUM_BOARD_EBH5020) || \
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(OCTEON_BOARD == CAVIUM_BOARD_EBH5600) || (OCTEON_BOARD == CAVIUM_BOARD_EVB5860) || \
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(OCTEON_BOARD == CAVIUM_BOARD_EVB6300) || (OCTEON_BOARD == CAVIUM_BOARD_EVB6800) || \
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defined (MIPSXX_cav_cn3xxx) || defined (MIPSXX_cav_cn5xxx) || defined (MIPSXX_cav_cn6xxx))
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#define CAV_SDK_DRV_INCLUDE(incF) \
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CAV_SDK_STRINGIFY(../src/hwif/fw/cavium_sdk/OCTEON-SDK/executive/incF)
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#else /* (OCTEON_MODEL=OCTEON_CN78XX) or non-defined, use new SDK */
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#define CAV_SDK_DRV_INCLUDE(incF) \
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CAV_SDK_STRINGIFY(../src/hwif/fw/cavium_sdk/OCTEON-SDK-3.1.1-p1-547/executive/incF)
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#endif
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#else /* CAV_INCLUDED_SDK */
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#define CAV_SDK_DRV_INCLUDE(incF) \
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CAV_SDK_STRINGIFY(arch/mips/private/cavSdkDrvInclude.h)
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#endif /* CAV_INCLUDED_SDK */
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#endif /* cavSdkDrvIncludeh */
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@@ -0,0 +1,69 @@
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/* dsmMipP.h - private assembler definitions header file for disassembler */
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/*
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* Copyright (c) 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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||||
* of an applicable Wind River license agreement.
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||||
*/
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/*
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modification history
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--------------------
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01a,28apr10,rlg written.
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*/
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#ifndef __INCdsmMipsPh
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#define __INCdsmMipsPh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <vsbConfig.h>
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#include <arch/mips/archMips.h>
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#include <arch/mips/regsMips.h>
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#include <arch/mips/mipsExcPage.h>
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#include <private/kernelLockLibP.h>
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#ifdef _ASMLANGUAGE
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#include <private/windLibP.h>
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#endif /* _ASMLANGUAGE */
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/*
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The CPU bits defined below can be used to identify instructions which
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are only valid on a particular set of CPU types. At some point in the
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future it might be valuable to add bits which identify CPU groups such
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as ISA, ISA2, etc. If you add any entry to this list, a corresponding
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entry needs to be made to the CPUMASK, defined in /target/src/arch/mips
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dsmLib.c.
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*/
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#define dsmANY (0)
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#define dsmMIPS1 (1 << 0)
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#define dsmMIPS2 (1 << 1) /* MIPSI2 */
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#define dsmMIPS3 (1 << 2) /* MIPSI3 */
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#define dsmMIPS4 (1 << 3)
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#define dsmMIPS32 (1 << 4) /* MIPSI32 */
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#define dsmMIPS64 (1 << 5) /* MIPSI64 */
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#define dsmMIPS32R2 (1 << 6) /* MIPSI32R2 */
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#define dsmMIPS64R2 (1 << 7) /* MIPSI64R2 */
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#define dsmCW4011 (1 << 8)
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#define dsmR4650 (1 << 9)
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#define dsmVR5400 (1 << 10)
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#define dsmRMI_XLX (1 << 11)
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#define dsmOCTEON (1 << 12)
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#define dsmOCTEONII (1 << 13)
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#define dsmUNKNOWN (1 << 31)
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UINT dsmMipsSupportISAs (void );
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCdsmMipsPh */
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@@ -0,0 +1,290 @@
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/* octeonBoard.h - Board configuration file */
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/*
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* Copyright (c) 2008-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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||||
* of an applicable Wind River license agreement.
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||||
*/
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/*
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modification history
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--------------------
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01j,20dec11,x_f Add CN68XX board type
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01i,05jan11,d_c Defect WIND00249323 Fix WIND00249325 - configure PCIe bus
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01h,09nov10,d_c Remove definition of OCTEON_CACHE_ALIGN_SIZE.
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It's redundant with respect to CVMX_CACHE_LINE_SIZE
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in octeonMips64.h
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01g,04sep10,d_c Change CFG_I2C_EEPROM_ADDR for 63xx
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01f,31aug10,rlg addition of cn63xx defines
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01e,26aug10,pgh Removed octeon-model.h
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01d,09mar09,j_z add macros for 56xx and normalize file header
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01c,24sep08,pgh Fix copyright.
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01b,12jul08,l_z add macros for 50xx and normalize file header
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01a,14may08,l_z add macros for 58xx and normalize file header
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DESCRIPTION
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*/
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#ifndef OCTEON_BOARD_H
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#define OCTEON_BOARD_H
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#define CONFIG_OCTEON 1
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#define CAVIUM_BOARD_EBH3010 1
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#define CAVIUM_BOARD_EBH3100 2
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#define CAVIUM_BOARD_EBT3000 3
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#define CAVIUM_BOARD_EBH50XX 4
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#define CAVIUM_BOARD_EBH5020 5
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#define CAVIUM_BOARD_EVB5860 6
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#define CAVIUM_BOARD_EBH5600 7
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#define CAVIUM_BOARD_EVB6300 8
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#define CAVIUM_BOARD_EVB6800 9
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#define CAVIUM_BOARD_EBB7800 10
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#define CPU_CLOCK_RATE (cavCpuClockRateGet())
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#if OCTEON_BOARD == CAVIUM_BOARD_EBT3000
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#define BOARD_REV_MAJOR 3
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#define BOARD_REV_MINOR 1
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#define DEFAULT_CPU_CLOCK_RATE 500000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x52
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBT3000 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH3010
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 500000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBH3010 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH3100
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 500000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBH3100 */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH50XX
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 400000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#endif /* OCTEON_MODEL == OCTEON_CN50XX */
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH5020
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#define BOARD_REV_MINOR 0
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#define BOARD_REV_MAJOR 1
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#define DEFAULT_CPU_CLOCK_RATE 400000000
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#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
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#define CFG_ATA_DATA_OFFSET 0x400
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#define CFG_ATA_REG_OFFSET 0
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
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#define PCI_IO_ADRS 0x00001000
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#define PCI_IO_SIZE 0x08000000
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#define PCI_IO16_SIZE 0x0
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|
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#define PCI_MEM_ADRS 0x80000000
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#define PCI_MEM_SIZE 0x40000000
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|
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#define OCTEON_PCI_LAT_TIMER 0xff
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|
||||
#define I2C_RTC_ADDR (0x68)
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|
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#endif /* OCTEON_BOARD == OCTEON_CN5020 */
|
||||
|
||||
|
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#if OCTEON_BOARD == CAVIUM_BOARD_EBH5600
|
||||
#define BOARD_REV_MAJOR 1
|
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#define BOARD_REV_MINOR 1
|
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|
||||
#define DEFAULT_CPU_CLOCK_RATE 800000000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
|
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#define CFG_ATA_DATA_OFFSET 0x400
|
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#define CFG_ATA_REG_OFFSET 0
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x56
|
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|
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#define PCIE0_IO_ADRS 0x00001000
|
||||
#define PCIE0_IO_SIZE 0x04000000
|
||||
#define PCIE0_MEM_ADRS 0x80000000
|
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#define PCIE0_MEM_SIZE 0x20000000
|
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|
||||
#define PCIE1_IO_ADRS (PCIE0_IO_ADRS + PCIE0_IO_SIZE)
|
||||
#define PCIE1_IO_SIZE PCIE0_IO_SIZE
|
||||
#define PCIE1_MEM_ADRS (PCIE0_MEM_ADRS + PCIE0_MEM_SIZE)
|
||||
#define PCIE1_MEM_SIZE PCIE0_MEM_SIZE
|
||||
|
||||
#define I2C_RTC_ADDR (0x68)
|
||||
|
||||
#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBH5600 */
|
||||
|
||||
|
||||
#if OCTEON_BOARD == CAVIUM_BOARD_EVB5860
|
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#define BOARD_REV_MAJOR 3
|
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#define BOARD_REV_MINOR 1
|
||||
|
||||
#define DEFAULT_CPU_CLOCK_RATE 800000000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
|
||||
#define CFG_ATA_DATA_OFFSET 0x400
|
||||
#define CFG_ATA_REG_OFFSET 0
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_I2C_EEPROM_ADDR 0x52
|
||||
|
||||
#define I2C_RTC_ADDR (0x68)
|
||||
|
||||
#endif /* OCTEON_BOARD == CAVIUM_BOARD_EVB5860 */
|
||||
|
||||
#if OCTEON_BOARD == CAVIUM_BOARD_EVB6300
|
||||
#define BOARD_REV_MAJOR 1
|
||||
#define BOARD_REV_MINOR 0
|
||||
|
||||
#define DEFAULT_CPU_CLOCK_RATE 800000000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
|
||||
#define CFG_ATA_DATA_OFFSET 0x400
|
||||
#define CFG_ATA_REG_OFFSET 0
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x56
|
||||
|
||||
#define PCIE0_IO_ADRS 0x00001000
|
||||
#define PCIE0_IO_SIZE 0x04000000 /* 64M */
|
||||
|
||||
#define PCIE0_MEM_ADRS 0x80000000
|
||||
#define PCIE0_MEM_SIZE 0x20000000 /* 512M */
|
||||
|
||||
#define PCIE1_IO_ADRS (PCIE0_IO_ADRS + PCIE0_IO_SIZE)
|
||||
#define PCIE1_IO_SIZE PCIE0_IO_SIZE
|
||||
|
||||
#define PCIE1_MEM_ADRS (PCIE0_MEM_ADRS + PCIE0_MEM_SIZE)
|
||||
#define PCIE1_MEM_SIZE PCIE0_MEM_SIZE
|
||||
|
||||
#define I2C_RTC_ADDR (0x68)
|
||||
|
||||
#endif /* OCTEON_BOARD == CAVIUM_BOARD_EVB6300 */
|
||||
|
||||
#if OCTEON_BOARD == CAVIUM_BOARD_EVB6800
|
||||
#define BOARD_REV_MAJOR 1
|
||||
#define BOARD_REV_MINOR 0
|
||||
|
||||
#define DEFAULT_CPU_CLOCK_RATE 800000000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR (OCTEON_CF_COMMON_BASE_ADDR + 0x800)
|
||||
#define CFG_ATA_DATA_OFFSET 0x400
|
||||
#define CFG_ATA_REG_OFFSET 0
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x56
|
||||
|
||||
#define I2C_RTC_ADDR (0x68)
|
||||
|
||||
#endif /* OCTEON_BOARD == CAVIUM_BOARD_EVB6800 */
|
||||
|
||||
#if OCTEON_BOARD == CAVIUM_BOARD_EBB7800
|
||||
#define BOARD_REV_MAJOR 1
|
||||
#define BOARD_REV_MINOR 0
|
||||
|
||||
#define DEFAULT_CPU_CLOCK_RATE 1600000000
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
#define PCIE0_IO_ADRS 0x00001000
|
||||
#define PCIE0_IO_SIZE 0x04000000 /* 64M */
|
||||
|
||||
#define PCIE0_MEM_ADRS 0x80000000
|
||||
#define PCIE0_MEM_SIZE 0x10000000 /* 256M */
|
||||
|
||||
#define PCIE1_IO_ADRS (PCIE0_IO_ADRS + PCIE0_IO_SIZE)
|
||||
#define PCIE1_IO_SIZE PCIE0_IO_SIZE
|
||||
|
||||
#define PCIE1_MEM_ADRS (PCIE0_MEM_ADRS + PCIE0_MEM_SIZE)
|
||||
#define PCIE1_MEM_SIZE PCIE0_MEM_SIZE
|
||||
|
||||
#define PCIE2_IO_ADRS (PCIE1_IO_ADRS + PCIE1_IO_SIZE)
|
||||
#define PCIE2_IO_SIZE PCIE1_IO_SIZE
|
||||
|
||||
#define PCIE2_MEM_ADRS (PCIE1_MEM_ADRS + PCIE1_MEM_SIZE)
|
||||
#define PCIE2_MEM_SIZE PCIE1_MEM_SIZE
|
||||
|
||||
#define PCIE3_IO_ADRS (PCIE2_IO_ADRS + PCIE2_IO_SIZE)
|
||||
#define PCIE3_IO_SIZE PCIE2_IO_SIZE
|
||||
|
||||
#define PCIE3_MEM_ADRS (PCIE2_MEM_ADRS + PCIE2_MEM_SIZE)
|
||||
#define PCIE3_MEM_SIZE PCIE2_MEM_SIZE
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x56
|
||||
|
||||
#endif /* OCTEON_BOARD == CAVIUM_BOARD_EBB7800 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xbf400000 /* Flash Bank #1 */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10)
|
||||
|
||||
#define CFG_INIT_SP_OFFSET 0x400000
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
#define CFG_FLASH_PROTECT_LEN 0x80000 /* protect low 512K */
|
||||
|
||||
#define CFG_FLASH_CFI 1
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
|
||||
|
||||
#endif /* OCTEON_BOARD_H */
|
||||
@@ -0,0 +1,364 @@
|
||||
/* octeon_mips64.h */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2008, 2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
modification history
|
||||
--------------------
|
||||
01e,11nov10,slk add configuration 4 reg
|
||||
01d,09nov10,d_c Add default definition of CVMX_CACHE_LINE_SIZE
|
||||
01c,01nov10,d_c Add scratch memory defines
|
||||
01b,14oct10,rlg addition of checks for assembler to keep from getting
|
||||
warnings is c code
|
||||
01a,24sep08,pgh Fix copyright.
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _OCTEON_MIPS64_H_
|
||||
#define _OCTEON_MIPS64_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "arch/mips/private/octeonBoard.h"
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
/*
|
||||
* MIPS Coprocessor 0 regs
|
||||
*/
|
||||
#ifdef C0_INDEX
|
||||
#undef C0_INDEX
|
||||
#endif /* C0_INDEX */
|
||||
#define C0_INDEX $0,0
|
||||
#ifdef C0_RANDOM
|
||||
#undef C0_RANDOM
|
||||
#endif /* C0_RANDOM */
|
||||
#define C0_RANDOM $1,0
|
||||
#ifdef C0_ENTRYLO0
|
||||
#undef C0_ENTRYLO0
|
||||
#endif /* C0_ENTRYLO0 */
|
||||
#define C0_ENTRYLO0 $2,0
|
||||
#ifdef C0_ENTRYLO1
|
||||
#undef C0_ENTRYLO1
|
||||
#endif /* C0_ENTRYLO1 */
|
||||
#define C0_ENTRYLO1 $3,0
|
||||
#ifdef C0_CONTEXT
|
||||
#undef C0_CONTEXT
|
||||
#endif /* C0_CONTEXT */
|
||||
#define C0_CONTEXT $4,0
|
||||
#ifdef C0_USERLOCAL
|
||||
#undef C0_USERLOCAL
|
||||
#endif /* C0_USERLOCAL */
|
||||
#ifdef C0_PAGEMASK
|
||||
#undef C0_PAGEMASK
|
||||
#endif /* C0_PAGEMASK */
|
||||
#define C0_PAGEMASK $5,0
|
||||
#ifdef C0_PAGEGRAIN
|
||||
#undef C0_PAGEGRAIN
|
||||
#endif /* C0_PAGEGRAIN */
|
||||
#define C0_PAGEGRAIN $5,1
|
||||
#ifdef C0_WIRED
|
||||
#undef C0_WIRED
|
||||
#endif /* C0_WIRED */
|
||||
#define C0_WIRED $6,0
|
||||
#ifdef C0_HWRENA
|
||||
#undef C0_HWRENA
|
||||
#endif/* C0_HWRENA */
|
||||
#define C0_HWRENA $7,0
|
||||
#ifdef C0_BADVADDR
|
||||
#undef C0_BADVADDR
|
||||
#endif /* C0_BADVADDR */
|
||||
#define C0_BADVADDR $8,0
|
||||
#ifdef C0_COUNT
|
||||
#undef C0_COUNT
|
||||
#endif /* C0_COUNT */
|
||||
#define C0_COUNT $9,0
|
||||
#ifdef C0_ENTRYHI
|
||||
#undef C0_ENTRYHI
|
||||
#endif /* C0_ENTRYHI */
|
||||
#define C0_ENTRYHI $10,0
|
||||
#ifdef C0_COMPARE
|
||||
#undef C0_COMPARE
|
||||
#endif /* C0_COMPARE */
|
||||
#define C0_COMPARE $11,0
|
||||
#ifdef C0_STATUS
|
||||
#undef C0_STATUS
|
||||
#endif /* C0_STATUS */
|
||||
#define C0_STATUS $12,0
|
||||
#ifdef C0_INTCTL
|
||||
#undef C0_INTCTL
|
||||
#endif /* C0_INTCTL */
|
||||
#define C0_INTCTL $12,1
|
||||
#ifdef C0_SRSCTL
|
||||
#undef C0_SRSCTL
|
||||
#endif /* C0_SRSCTL */
|
||||
#define C0_SRSCTL $12,1
|
||||
#ifdef C0_CAUSE
|
||||
#undef C0_CAUSE
|
||||
#endif /* C0_CAUSE */
|
||||
#define C0_CAUSE $13,0
|
||||
#ifdef C0_EPC
|
||||
#undef C0_EPC
|
||||
#endif /* C0_EPC */
|
||||
#define C0_EPC $14,0
|
||||
#ifdef C0_PRIID
|
||||
#undef C0_PRIID
|
||||
#endif /* C0_PRIID */
|
||||
#define C0_PRIID $15,0
|
||||
#ifdef C0_EBASE
|
||||
#undef C0_EBASE
|
||||
#endif /* C0_EBASE */
|
||||
#define C0_EBASE $15,1
|
||||
#ifdef C0_CONFIG
|
||||
#undef C0_CONFIG
|
||||
#endif /* C0_CONFIG */
|
||||
#define C0_CONFIG $16,0
|
||||
#ifdef C0_CONFIG1
|
||||
#undef C0_CONFIG1
|
||||
#endif /* C0_CONFIG1 */
|
||||
#define C0_CONFIG1 $16,1
|
||||
#ifdef C0_CONFIG2
|
||||
#undef C0_CONFIG2
|
||||
#endif /* C0_CONFIG2 */
|
||||
#define C0_CONFIG2 $16,2
|
||||
#ifdef C0_CONFIG3
|
||||
#undef C0_CONFIG3
|
||||
#endif /* C0_CONFIG3 */
|
||||
#define C0_CONFIG3 $16,3
|
||||
#ifdef C0_CONFIG4
|
||||
#undef C0_CONFIG4
|
||||
#endif /* C0_CONFIG4 */
|
||||
#define C0_CONFIG4 $16,4
|
||||
#ifdef C0_WATCHLO0
|
||||
#undef C0_WATCHLO0
|
||||
#endif /* C0_WATCHLO0 */
|
||||
#define C0_WATCHLO0 $18,0
|
||||
#ifdef C0_WATCHLO1
|
||||
#undef C0_WATCHLO1
|
||||
#endif /* C0_WATCHLO1 */
|
||||
#define C0_WATCHLO1 $18,1
|
||||
#ifdef C0_WATCHHI0
|
||||
#undef C0_WATCHHI0
|
||||
#endif /* C0_WATCHHI0 */
|
||||
#define C0_WATCHHI0 $19,0
|
||||
#ifdef C0_WATCHHI1
|
||||
#undef C0_WATCHHI1
|
||||
#endif /* C0_WATCHHI1 */
|
||||
#define C0_WATCHHI1 $19,1
|
||||
#ifdef C0_XCONTEXT
|
||||
#undef C0_XCONTEXT
|
||||
#endif /* C0_XCONTEXT */
|
||||
#define C0_XCONTEXT $20,0
|
||||
#ifdef C0_DEBUG
|
||||
#undef C0_DEBUG
|
||||
#endif /* C0_DEBUG */
|
||||
#define C0_DEBUG $23,0
|
||||
#ifdef C0_DEPC
|
||||
#undef C0_DEPC
|
||||
#endif /* C0_DEPC */
|
||||
#define C0_DEPC $24,0
|
||||
#ifdef C0_PERFCNT0
|
||||
#undef C0_PERFCNT0
|
||||
#endif /* C0_PERFCNT0 */
|
||||
#define C0_PERFCNT0 $25,1
|
||||
#ifdef C0_PERFCNT1
|
||||
#undef C0_PERFCNT1
|
||||
#endif /* C0_PERFCNT1 */
|
||||
#define C0_PERFCNT1 $25,3
|
||||
#ifdef C0_CACHEERR0
|
||||
#undef C0_CACHEERR0
|
||||
#endif /* C0_CACHEERR0 */
|
||||
#define C0_CACHEERR0 $27,0
|
||||
#ifdef C0_CACHEERR1
|
||||
#undef C0_CACHEERR1
|
||||
#endif /* C0_CACHEERR1 */
|
||||
#define C0_CACHEERR1 $27,1
|
||||
#ifdef C0_TAGLO
|
||||
#undef C0_TAGLO
|
||||
#endif /* C0_TAGLO */
|
||||
#define C0_TAGLO $28,2
|
||||
#ifdef C0_DATALO
|
||||
#undef C0_DATALO
|
||||
#endif /* C0_DATALO */
|
||||
#define C0_DATALO $28,3
|
||||
#ifdef C0_TAGHI
|
||||
#undef C0_TAGHI
|
||||
#endif /* C0_TAGHI */
|
||||
#define C0_TAGHI $29,2
|
||||
#ifdef C0_DATAHI
|
||||
#undef C0_DATAHI
|
||||
#endif /*C0_DATAHI */
|
||||
#define C0_DATAHI $29,3
|
||||
#ifdef C0_ERROREPC
|
||||
#undef C0_ERROREPC
|
||||
#endif /* C0_ERROREPC */
|
||||
#define C0_ERROREPC $30,0
|
||||
#ifdef C0_DESAVE
|
||||
#undef C0_DESAVE
|
||||
#endif /* C0_DESAVE */
|
||||
#define C0_DESAVE $31,0
|
||||
#ifdef C0_CVMCTL
|
||||
#undef C0_CVMCTL
|
||||
#endif /* C0_CVMCTL */
|
||||
#define C0_CVMCTL $9,7
|
||||
#ifdef C0_CVMMEMCTL
|
||||
#undef C0_CVMMEMCTL
|
||||
#endif /* C0_CVMMEMCTL */
|
||||
#define C0_CVMMEMCTL $11,7
|
||||
#ifdef C0_CVMCOUNT
|
||||
#undef C0_CVMCOUNT
|
||||
#endif /* C0_CVMCOUNT */
|
||||
#define C0_CVMCOUNT $9,6
|
||||
#ifdef C0_MULTICOREDEBEG
|
||||
#undef C0_MULTICOREDEBEG
|
||||
#endif /* C0_MULTICOREDEBEG */
|
||||
#define C0_MULTICOREDEBEG $22,0
|
||||
#ifdef C0_KSCRATCH1
|
||||
#undef C0_KSCRATCH1
|
||||
#endif /* C0_KSCRATCH1 */
|
||||
#define C0_KSCRATCH1 $31,3
|
||||
#ifdef C0_KSCRATCH2
|
||||
#undef C0_KSCRATCH2
|
||||
#endif /* C0_KSCRATCH2 */
|
||||
#define C0_KSCRATCH2 $31,3
|
||||
#ifdef C0_KSCRATCH3
|
||||
#undef C0_KSCRATCH3
|
||||
#endif /* C0_KSCRATCH3 */
|
||||
#define C0_KSCRATCH3 $31,4
|
||||
#ifdef C0_KSCRATCH4
|
||||
#undef C0_KSCRATCH4
|
||||
#endif /* C0_KSCRATCH4 */
|
||||
#define C0_KSCRATCH4 $31,5
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
/*
|
||||
* Other Octeon defines
|
||||
*/
|
||||
|
||||
|
||||
#define INT_VEC_BASE 0x40
|
||||
|
||||
#define IV_INTSW0_NUM (INT_VEC_BASE+0)
|
||||
#define IV_INTSW1_NUM (INT_VEC_BASE+1)
|
||||
#define IV_INT0_NUM (INT_VEC_BASE+2) /* INT 0 */
|
||||
#define IV_INT1_NUM (INT_VEC_BASE+3) /* INT 1 */
|
||||
#define IV_ETHER_NUM (INT_VEC_BASE+4) /* INT 2 */
|
||||
#define IV_AUXCLK_NUM (INT_VEC_BASE+5) /* INT 3 */
|
||||
#define IV_UART0_NUM (INT_VEC_BASE+6) /* INT 4 */
|
||||
#define IV_CLOCK_NUM (INT_VEC_BASE+7) /* INT 5 */
|
||||
#define IV_UART1_NUM (INT_VEC_BASE+8)
|
||||
|
||||
#if (OCTEON_BOARD == CAVIUM_BOARD_EBB7800)
|
||||
#define OCTEON_NUM_CORES 48
|
||||
#else
|
||||
#define OCTEON_NUM_CORES 16
|
||||
#endif /* (OCTEON_BOARD == CAVIUM_BOARD_EBB7800) */
|
||||
#define C0_EBASE_CORE_MASK 0xff
|
||||
|
||||
|
||||
/* Interrupts for clk, CIU0, CIU1 */
|
||||
/*
|
||||
* interrupt priority: 7=high----0=low
|
||||
*/
|
||||
#define INT_PRIO_MSB TRUE
|
||||
#define INTERRUPT_CLOCK SR_IBIT8
|
||||
#define INTERRUPT_CIU_0 SR_IBIT4
|
||||
#define INTERRUPT_CIU_1 SR_IBIT3
|
||||
|
||||
#if (OCTEON_BOARD == CAVIUM_BOARD_EBB7800)
|
||||
#define DEFAULT_SR (SR_CU2|SR_CU1|SR_CU0|SR_FR| \
|
||||
INTERRUPT_CLOCK|INTERRUPT_CIU_0|INTERRUPT_CIU_1| \
|
||||
SR_KX|SR_SX|SR_UX|SR_INT_ENABLE)
|
||||
#else
|
||||
#define DEFAULT_SR (SR_CU2|SR_CU0| \
|
||||
INTERRUPT_CLOCK|INTERRUPT_CIU_0|INTERRUPT_CIU_1| \
|
||||
SR_KX|SR_SX|SR_UX|SR_INT_ENABLE)
|
||||
#endif /* (OCTEON_BOARD == CAVIUM_BOARD_EBB7800) */
|
||||
|
||||
/* Debugger related defines */
|
||||
#define DEBUG_STACK_SIZE 1024 /* Size of the debugger stack */
|
||||
#if (OCTEON_BOARD == CAVIUM_BOARD_EBB7800)
|
||||
#define DEBUG_NUMREGS 512 /* Total number of (64 bit)registers stored. Must match debug_handler.S */
|
||||
#else
|
||||
#define DEBUG_NUMREGS 64 /* Total number of (64 bit)registers stored. Must match debug_handler.S */
|
||||
#endif /* (OCTEON_BOARD == CAVIUM_BOARD_EBB7800) */
|
||||
|
||||
#define EXCEPTION_BASE_BASE 0 /* must be 4k aligned */
|
||||
#define EXCEPTION_BASE_INCR (4*1024) /* Increment size for exception base addresses (4k minimum) */
|
||||
#define OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE (OCTEON_NUM_CORES*EXCEPTION_BASE_INCR) /* 16 4k blocks */
|
||||
|
||||
/* Bootloader debugger stub register save area follows exception vector space */
|
||||
#define BOOTLOADER_DEBUG_REG_SAVE_BASE (EXCEPTION_BASE_BASE + OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE)
|
||||
#define BOOTLOADER_DEBUG_REG_SAVE_SIZE (OCTEON_NUM_CORES * DEBUG_NUMREGS * 8)
|
||||
|
||||
/* debugger stack follows reg save area */
|
||||
#define BOOTLOADER_DEBUG_STACK_BASE (BOOTLOADER_DEBUG_REG_SAVE_BASE + BOOTLOADER_DEBUG_REG_SAVE_SIZE)
|
||||
#define BOOTLOADER_DEBUG_STACK_SIZE (OCTEON_NUM_CORES * DEBUG_STACK_SIZE)
|
||||
#define BOOTLOADER_END_RESERVED_SPACE (BOOTLOADER_DEBUG_STACK_BASE + BOOTLOADER_DEBUG_STACK_SIZE)
|
||||
|
||||
#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800)
|
||||
#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE)
|
||||
#define BOOTLOADER_DEBUG_TRAMPOLINE (BOOTLOADER_BOOT_VECTOR + BOOT_VECTOR_SIZE) /* WORD */
|
||||
#define BOOTLOADER_DEBUG_GP_REG (BOOTLOADER_DEBUG_TRAMPOLINE + 4) /* WORD */
|
||||
#define BOOTLOADER_DEBUG_FLAGS_BASE (BOOTLOADER_DEBUG_GP_REG + 4) /* WORD * NUM_CORES */
|
||||
#define BOOTLOADER_NEXT_AVAIL_ADDR (BOOTLOADER_DEBUG_FLAGS_BASE + 4*OCTEON_NUM_CORES)
|
||||
|
||||
/* Address used for boot vectors for non-zero cores */
|
||||
#define BOOT_VECTOR_BASE (0x80000000 | BOOTLOADER_BOOT_VECTOR)
|
||||
#define BOOT_VECTOR_NUM_WORDS (8)
|
||||
#define BOOT_VECTOR_SIZE ((OCTEON_NUM_CORES*4)*BOOT_VECTOR_NUM_WORDS)
|
||||
|
||||
/* Addresses used to pass parameters to secondary cores at startup */
|
||||
#define BOOT_REGION_STORE_START 0x80000600
|
||||
#define BOOT_REGION_STORE_ENTRY (BOOT_REGION_STORE_START+0x00)
|
||||
#define BOOT_REGION_STORE_PARAMETER (BOOT_REGION_STORE_START+0x08)
|
||||
#define BOOT_REGION_STORE_SP (BOOT_REGION_STORE_START+0x10)
|
||||
#define BOOT_REGION_STORE_GP (BOOT_REGION_STORE_START+0x18)
|
||||
#define BOOT_REGION_WAIT_CHANNEL BOOT_REGION_STORE_ENTRY
|
||||
|
||||
/* Scratch memory used by early boot code */
|
||||
|
||||
#define SCRATCH_MEM_ADRS 0xffff9B00
|
||||
#define SCRATCH_MEM_SIZE 0x1B00
|
||||
|
||||
/* Flag to track whether DDR clock has been initialized */
|
||||
#define SCRATCH_MEM_DDR_CLOCK_INIT_ADRS (SCRATCH_MEM_ADRS - 0x08)
|
||||
|
||||
/* Flag to track whether cpu clock rate been initialized */
|
||||
#define SCRATCH_MEM_CPU_CLOCK_RATE_ADRS (SCRATCH_MEM_ADRS - 0x10)
|
||||
|
||||
/* Top of stack */
|
||||
#define SCRATCH_MEM_STACK_ADRS (SCRATCH_MEM_ADRS - 0x18)
|
||||
|
||||
/* Warning - this is copied from the SDK */
|
||||
|
||||
#ifndef CVMX_CACHE_LINE_SIZE
|
||||
#define CVMX_CACHE_LINE_SIZE 128
|
||||
#elif CVMX_CACHE_LINE_SIZE != 128
|
||||
#warning CVMX_CACHE_LINE_SIZE is not consistent between Cavium SDK and \
|
||||
vxWorks arch. See target/src/hwif/fw/cavium_sdk for conflicting definition.
|
||||
#endif
|
||||
|
||||
#ifndef CVMX_CACHE_LINE_ALIGNED
|
||||
#define CVMX_CACHE_LINE_ALIGNED \
|
||||
__attribute__ ((aligned (CVMX_CACHE_LINE_SIZE)))
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _OCTEON_MIPS64_H_ */
|
||||
@@ -0,0 +1,618 @@
|
||||
/* smpMipsP.h - private assembler definitions header file for SMP */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006-2012 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
02n,08mar12,h_k removed _WRS_ARCH_REQUIRES_TLB_SYNC_CPC. (WIND00320752)
|
||||
02m,23dec11,l_z Move _WRS_MIPS_SMP_VARIANT to Makefile for XLR/XLP CPU
|
||||
02l,17may11,slk Add 64bit register read and set interface
|
||||
02k,19nov10,rlg find WIND00242201 - compiler warnings
|
||||
02j,27may10,d_c Rename CAVIUM_CNMIPS_* to _WRS_CAVIUM_CNMIPS_* and define in
|
||||
arch Makefile
|
||||
02l,09jun10,kab Add _WRS_ARCH_HAS_OBJ_SAFE
|
||||
02k,29apr10,pad Moved extern C statement after include statements.
|
||||
02i,31mar10,d_c Add cav_cn5xxx and cav_cn6xxx variants
|
||||
02j,11jan10,slk add cavium to variants that support index on -1 page
|
||||
02i,13nov09,slk update and add macros for SMP M-N support
|
||||
02h,23sep09,s_s changed INT_CPU_LOCK() and INT_CPU_UNLOCK() to
|
||||
INT_CPU_MICRO_LOCK() and INT_CPU_MICRO_UNLOCK()
|
||||
(WIND00181479)
|
||||
02g,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
|
||||
02f,24feb09,slk fix zero register references
|
||||
02e,14feb09,slk move archVars to -1 page
|
||||
02d,18sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
|
||||
02c,27aug08,jpb Renamed VSB header file
|
||||
02b,24jun08,jpb Added include path for kernel configurations options set in
|
||||
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
|
||||
02a,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
|
||||
01z,03apr08,slk add global var access macros that don't call
|
||||
_MIPS_CPU_INDEX_GET (cpuindex supplied)
|
||||
01z,27may08,slk define _WRS_MIPS_SMP_VARIANT if _mti24kx variant
|
||||
01y,10jan08,gls added VX_INSTR_BARRIER()
|
||||
01x,05dec07,d_c add _MIPS_CPU_ID_GET() macro for Raza. Continue to default
|
||||
to _MIPS_CPU_INDEX_GET() for other variants.
|
||||
01w,25sep07,d_c Add extended interrupts for RMI _xlr variant (rebased on 02nov07)
|
||||
01x,07may08,slk add _mipsIpiMailbox and WRS ARCH macros
|
||||
01w,12oct07,pes Remove reference to _mipsEsfTailTbl.
|
||||
01v,09aug07,rlg Changes for the MIPS Library restructuring
|
||||
01u,01aug07,pes Disable cache lock for SMP
|
||||
01u,01aug07,l_z add limitation when define _MIPS_CPU_INDEX_GET
|
||||
01t,17jul07,pes Rename .kseg0data to .kseg0bss.
|
||||
01s,22jun07,slk add zero return to _MIPS_CPU_INDEX_GET for UP arch builds
|
||||
01r,18jun07,pes Move references to _WRS_VX_SMP out of public header file.
|
||||
01q,05jun07,agf remove octeon5xxx reference
|
||||
01q,30may07,pes Add defines for Raza CPU variant.
|
||||
01p,17apr07,kk move VX_MAX_SMP_CPUS to archMips.h
|
||||
01p,30mar07,pes Add CPU index get code for MIPS64R2 cores.
|
||||
01o,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
|
||||
01n,30nov06,pes Complete changes from 01m.
|
||||
01m,29nov06,pes Remove local definition of _WRS_WIND_VARS_OFFSET_archVars.
|
||||
01l,05oct06,pes Remove padding from windArchVars structure. Removed
|
||||
obsolete macro definitions. Change _MIPS_CPU_INDEX_GET
|
||||
macro to return core number instead of word index.
|
||||
01k,29sep06,pes Add _MIPS_KERNEL_LOCK_OWNER_AND_INDEX_GET.
|
||||
01j,20sep06,pes Provide default macros if _WRS_MIPS_SMP_VARIANT is not
|
||||
defined. Add definitions used in kernelCpuEnable. Define
|
||||
VX_KERNEL_VARS.
|
||||
01i,06sep06,gls added definition of MIPS specific vxKernelVars[] offsets
|
||||
01h,12sep06,pes Move _WRS_CPU_INDEX_GET macro out of assembly portion of the
|
||||
file.
|
||||
01g,12sep06,pes Add macro definition for _WRS_CPU_INDEX_GET().
|
||||
01f,22aug06,pes Correct use of WRS_KERNEL_VARS to VX_KERNEL_VARS.
|
||||
01e,16aug06,pes Change #if FALSE to #ifdef VX_KERNEL_VARS.
|
||||
01d,13aug06,pes Correct definition of _WRS_WIND_VARS_ARCH.
|
||||
01c,12aug06,pes Provide MIPS-specific definition of VX_MAX_SMP_CPUS.
|
||||
01b,26jul06,pes Include archMips.h. Add _WRS_WIND_VARS* definitions.
|
||||
Change name of CPU_INDEX macro to _MIPS_CPU_INDEX_GET.
|
||||
Replace individual global access macros with generic
|
||||
ones that automatically handle new globals as needed.
|
||||
01a,20jul06,pes written.
|
||||
*/
|
||||
|
||||
#ifndef __INCsmpMipsPh
|
||||
#define __INCsmpMipsPh
|
||||
|
||||
#include <vsbConfig.h>
|
||||
#include <arch/mips/archMips.h>
|
||||
#include <arch/mips/regsMips.h>
|
||||
#include <arch/mips/mipsExcPage.h>
|
||||
#include <private/kernelLockLibP.h>
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
#include <private/intMicroLibP.h>
|
||||
#endif
|
||||
#ifdef _ASMLANGUAGE
|
||||
#include <private/windLibP.h>
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* SMP support */
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/*
|
||||
* MIPS has been adapted to use the new object safe count feature for SMP.
|
||||
* When all architectures have been adapted this can be removed from
|
||||
* the code.
|
||||
*/
|
||||
|
||||
#define _WRS_ARCH_HAS_OBJ_SAFE
|
||||
|
||||
/* Trigger software cacheTextUpdate CPC */
|
||||
|
||||
#define _WRS_ARCH_REQUIRES_CACHE_TEXT_UPDATE_CPC
|
||||
|
||||
/* Disable cache locking */
|
||||
#undef _WRS_SUPPORT_CACHE_LOCK /* cache lock feature */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define _WRS_VX_KERNEL_VARS_SECTION_ATTR \
|
||||
__attribute__ ((__section__ (".kseg0bss")))
|
||||
|
||||
/*
|
||||
* This macro defines the alignment requirement for the WIND_VARS structure.
|
||||
*
|
||||
* There are 3 factors involved in selection of this value.
|
||||
*
|
||||
* 1. It's definition is no LESS than the maximum value of
|
||||
* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
|
||||
* cache line length growth.
|
||||
* 2. It must be at least as large as the WIND_VARS structure.
|
||||
* 3. It must be a power of 2.
|
||||
*
|
||||
* For example:
|
||||
* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
|
||||
* (rule 1).
|
||||
* if WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
|
||||
* (rules 2 and 3).
|
||||
*/
|
||||
#define _WRS_WIND_VARS_ALIGN 128
|
||||
#define _WRS_WIND_VARS_ALIGN_SHIFT 7
|
||||
|
||||
/*
|
||||
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
|
||||
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
|
||||
* XSCALE, etc), representing the maximum cache line size of the variants of
|
||||
* the respective arch.
|
||||
*
|
||||
* For MIPS this is 128 bytes.
|
||||
*/
|
||||
|
||||
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
|
||||
|
||||
/* add logical CPU index saved to -1 page support. the
|
||||
* _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED define is temporary and will
|
||||
* be removed before 6.8.1 is released
|
||||
* SLK - TO DO remove _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
*/
|
||||
|
||||
#if defined (_WRS_MIPS_NETLOGIC_CPU) \
|
||||
|| defined(_WRS_CAVIUM_CNMIPS_CORE) \
|
||||
|| defined(_WRS_CAVIUM_CNMIPS_II_CORE)
|
||||
#define _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
#else /* defined (_WRS_MIPS_NETLOGIC_CPU) || defined (_WRS_CAVIUM_CNMIPS[_II]_CORE) */
|
||||
#undef _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
#endif /* defined (_WRS_MIPS_NETLOGIC_CPU) || defined (_WRS_CAVIUM_CNMIPS[_II]_CORE) */
|
||||
|
||||
#if defined(_WRS_MIPS_NETLOGIC_CPU)
|
||||
/*
|
||||
* Note: The format of mipsSrImask variable changes for _xlr varient and
|
||||
* possibly others. Rather than representing SR[15:8],it represents
|
||||
* a full 32-bit interrupt mask MR[31:0]. The mapping of SR[15:8]
|
||||
* to MR is variant-dependent. In _xlr, SR[15:8] == EIMR[7:0].
|
||||
*/
|
||||
#endif /* _WRS_MIPS_NETLOGIC_CPU */
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/* MIPS has no arch vxKernelVars */
|
||||
#undef _WRS_WIND_VARS_ARCH
|
||||
|
||||
#if defined (_WRS_CONFIG_SMP)
|
||||
|
||||
/* macro to access the arch-specific fields of the vxKernelVars struct */
|
||||
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
|
||||
*(int *)(EXCPAGE_ARCHVARS##glob)
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
|
||||
*(int *)(EXCPAGE_ARCHVARS##glob)=var
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
|
||||
*(int *)(EXCPAGE_ARCHVARS##glob)
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
|
||||
do \
|
||||
{ \
|
||||
int key=INT_CPU_MICRO_LOCK(); \
|
||||
*(int *)(EXCPAGE_ARCHVARS##glob)=var; \
|
||||
INT_CPU_MICRO_UNLOCK(key); \
|
||||
} while ((0))
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
|
||||
do \
|
||||
{ \
|
||||
var=*(int *)(EXCPAGE_ARCHVARS##glob); \
|
||||
} while ((0))
|
||||
|
||||
#define _WRS_WIND_VARS_INLINE_ASM_ARCH_ACCESS(reg,glob) \
|
||||
lw reg, %lo(EXCPAGE_ARCHVARS##glob)(zero)
|
||||
|
||||
/* macro to access the arch-specific fields of the vxKernelVars struct
|
||||
* for 64 bit width
|
||||
*/
|
||||
#define _WRS_WIND_VARS_ARCH_64_ACCESS(glob) \
|
||||
*(UINT64 *)(EXCPAGE_ARCHVARS##glob)
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_64_SET(cpuid,glob,var) \
|
||||
*(UINT64 *)(EXCPAGE_ARCHVARS##glob)=var
|
||||
|
||||
#define _WRS_WIND_VARS_ARCH_64_GET(cpuid,glob) \
|
||||
*(UINT64 *)(EXCPAGE_ARCHVARS##glob)
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_64_SET(glob, var) \
|
||||
do \
|
||||
{ \
|
||||
int key=INT_CPU_MICRO_LOCK(); \
|
||||
*(UINT64 *)(EXCPAGE_ARCHVARS##glob)=var; \
|
||||
INT_CPU_MICRO_UNLOCK(key); \
|
||||
} while ((0))
|
||||
|
||||
#define _WRS_ARCH_LOCKED_GLOBAL_64_GET(glob, var) \
|
||||
do \
|
||||
{ \
|
||||
var=*(UINT64 *)(EXCPAGE_ARCHVARS##glob); \
|
||||
} while ((0))
|
||||
|
||||
#define _WRS_WIND_VARS_INLINE_ASM_ARCH_64_ACCESS(reg,glob) \
|
||||
ld reg, %lo(EXCPAGE_ARCHVARS##glob)(zero)
|
||||
/*
|
||||
* _WRS_CPU_INDEX_GET():
|
||||
*
|
||||
* Just call the (assembly) function for now, but to optimize
|
||||
* performance this should eventually become a C-callable
|
||||
* _WRS_ASM construct (whose syntax varies depending on TOOL).
|
||||
*/
|
||||
|
||||
#define _WRS_CPU_INDEX_GET() vxCpuIndexGet()
|
||||
#else /* !_WRS_CONFIG_SMP */
|
||||
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) glob
|
||||
#define _WRS_WIND_VARS_INLINE_ASM_ARCH_ACCESS(reg,glob) \
|
||||
lw reg, glob
|
||||
#define _WRS_WIND_VARS_ARCH_64_ACCESS(glob) glob
|
||||
#define _WRS_WIND_VARS_INLINE_ASM_ARCH_64_ACCESS(reg,glob) \
|
||||
ld reg, glob
|
||||
#define _WRS_CPU_INDEX_GET() 0
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
|
||||
|
||||
#endif /* ! _ASMLANGUAGE */
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
|
||||
#undef _MIPS_CPU_ID_GET_DEFD
|
||||
|
||||
/* read logical CPU index from -1 page if configured */
|
||||
|
||||
#ifdef _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
#define _MIPS_CPU_INDEX_GET(reg) \
|
||||
lw reg, %lo(EXCPAGE_CPU_LOGICAL_INDEX)(zero);
|
||||
#endif /* _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED */
|
||||
|
||||
#if defined (MIPSXX_sb1) \
|
||||
|| defined(_WRS_CAVIUM_CNMIPS_CORE) \
|
||||
|| defined(_WRS_CAVIUM_CNMIPS_II_CORE) \
|
||||
|| defined(MIPSXX_mti24kx) \
|
||||
|| defined(_WRS_MIPS_NETLOGIC_CPU)
|
||||
#ifndef _WRS_MIPS_SMP_VARIANT
|
||||
#define _WRS_MIPS_SMP_VARIANT
|
||||
#endif /* _WRS_MIPS_SMP_VARIANT */
|
||||
#endif /* MIPSXX_sb1 || _WRS_CAVIUM_CNMIPS[_II]_CORE || MIPSXX_mti24kx ||
|
||||
_WRS_MIPS_NETLOGIC_CPU */
|
||||
|
||||
#if defined (_WRS_MIPS_NETLOGIC_CPU)
|
||||
/*
|
||||
* the Raza XLR core implements 8 per-core scratch registers. We will use the
|
||||
* last of these scratch registers to hold a CPU identification. This makes it
|
||||
* a very simple matter to quickly determine what core we're running on.
|
||||
*/
|
||||
#define C0_CPUNUM $22,7
|
||||
#ifndef _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
#define _MIPS_CPU_INDEX_GET(reg) \
|
||||
mfc0 reg,C0_CPUNUM; /* CPUNum register */
|
||||
#endif /* _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED */
|
||||
#define C0_CPUID $15,1
|
||||
#define CPUID_MASK 0x1f
|
||||
#define _MIPS_CPU_ID_GET_DEFD 1
|
||||
#define _MIPS_CPU_ID_GET(reg) \
|
||||
mfc0 reg, C0_CPUID; \
|
||||
and reg, CPUID_MASK
|
||||
|
||||
#endif /* _WRS_MIPS_NETLOGIC_CPU */
|
||||
|
||||
#ifdef _WRS_MIPS_ENABLE_R2_ISA
|
||||
|
||||
/*
|
||||
* the MIPS32/MIPS64 Release 2 instruction set includes the ability to
|
||||
* determine core by reading the CPUIndex register.
|
||||
*/
|
||||
|
||||
#ifndef _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
#define _MIPS_CPU_INDEX_GET(reg) \
|
||||
rdhwr reg, cpunum; /* CPUNum register */
|
||||
#endif /* _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED */
|
||||
/* add _MIPS_CPU_ID_GET for R2 CPUs */
|
||||
#define _MIPS_CPU_ID_GET_DEFD 1
|
||||
#define _MIPS_CPU_ID_GET(reg) \
|
||||
rdhwr reg, cpunum; /* CPUNum register */
|
||||
|
||||
#elif defined(_WRS_MIPS_SMP_VARIANT)
|
||||
#ifndef _MIPS_CPU_INDEX_GET
|
||||
|
||||
/*
|
||||
* provide the register, shift and mask defines for the default
|
||||
* standard MIPS case
|
||||
*/
|
||||
|
||||
#if !defined(_MIPS_CPU_INDEX_GET_REG)
|
||||
#define _MIPS_CPU_INDEX_GET_REG C0_PRID
|
||||
#endif
|
||||
#if !defined(_MIPS_CPU_INDEX_GET_SHIFT)
|
||||
#define _MIPS_CPU_INDEX_GET_SHIFT (25)
|
||||
#endif
|
||||
#if !defined(_MIPS_CPU_INDEX_GET_MASK)
|
||||
#define _MIPS_CPU_INDEX_GET_MASK (7)
|
||||
#endif
|
||||
|
||||
#ifndef _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED
|
||||
#define _MIPS_CPU_INDEX_GET(reg) \
|
||||
mfc0 reg, _MIPS_CPU_INDEX_GET_REG; /* get processor ID */ \
|
||||
srl reg, _MIPS_CPU_INDEX_GET_SHIFT; /* shift CPU into word */ \
|
||||
/* index position */ \
|
||||
and reg, _MIPS_CPU_INDEX_GET_MASK; /* apply mask */
|
||||
#endif /* _MIPS_CPU_INDEX_GET */
|
||||
#define _MIPS_CPU_ID_GET_DEFD 1
|
||||
#define _MIPS_CPU_ID_GET(reg) \
|
||||
mfc0 reg, _MIPS_CPU_INDEX_GET_REG; /* get processor ID */ \
|
||||
srl reg, _MIPS_CPU_INDEX_GET_SHIFT; /* shift CPU into word */ \
|
||||
/* index position */ \
|
||||
and reg, _MIPS_CPU_INDEX_GET_MASK; /* apply mask */
|
||||
#endif /* _WRS_MIPS_EXCPAGE_CPU_INDEX_SUPPORTED */
|
||||
#else /* UP variant */
|
||||
|
||||
#define _MIPS_CPU_INDEX_GET(reg) \
|
||||
move reg, zero; /* processor ID always zero */
|
||||
|
||||
#endif /* _WRS_MIPS_ENABLE_R2_ISA */
|
||||
|
||||
#ifndef _MIPS_CPU_ID_GET_DEFD
|
||||
#define _MIPS_CPU_ID_GET(reg) _MIPS_CPU_INDEX_GET(reg)
|
||||
#endif
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
/*
|
||||
* N.B.: The macros which follow may ONLY be used in sections of code in
|
||||
* which use of the AT register as a scratch register is permitted.
|
||||
* When using them in interrupt/exception entry/exit, make sure
|
||||
* that AT is properly saved/restored.
|
||||
*
|
||||
* N.B.: Access to the kernel globals structure assumes two things. First,
|
||||
* that they are in an address space in which there is identity mapping
|
||||
* between kseg2 and kseg0. This is currently required for kernel data
|
||||
* so we should be ok there. The other requirement is that kernel data
|
||||
* must be in either kseg2 or kseg0 (for mapped or unmapped kernels,
|
||||
* respectively). This is so that we can force addresses to kseg0
|
||||
* by clearing bit 30. (i.e., 0xcxxxxxxx & 0xbfffffff = 0x8xxxxxxx).
|
||||
*/
|
||||
|
||||
#define _WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
la AT,vxKernelVars; \
|
||||
add AT,_WRS_WIND_VARS_OFFSET_##label;
|
||||
#define _WRS_MIPS_VAR_ADRS(label) vxKernelVars+_WRS_WIND_VARS_OFFSET_##label
|
||||
#define _WRS_WIND_VARS_OFFSET(reg) sll reg,_WRS_WIND_VARS_ALIGN_SHIFT;
|
||||
|
||||
#define _MIPS_PER_CPU_ADRS_GET(reg,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_MIPS_CPU_INDEX_GET(reg) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
addu reg, AT ;/* add word index */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_ADRS_GET(reg,label) \
|
||||
la reg, EXCPAGE_ARCHVARS##label
|
||||
|
||||
/* _MIPS_PER_CPU_INDEX_ADRS_GET is the same as _MIPS_PER_CPU_ADRS_GET
|
||||
* but cpuindex is supplied (and overwritten by return value)
|
||||
*/
|
||||
|
||||
#define _MIPS_PER_CPU_INDEX_ADRS_GET(cpuindex,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_WRS_WIND_VARS_OFFSET(cpuindex) \
|
||||
addu cpuindex, AT ;/* add word index */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_REG_VALUE_GET(reg,label) \
|
||||
_MIPS_PER_CPU_VALUE_GET(reg,label)
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_GET(reg,label) \
|
||||
_MIPS_PER_CPU_ARCH_VALUE_GET(reg,label)
|
||||
|
||||
#define _MIPS_PER_CPU_REG64_VALUE_GET(reg,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_MIPS_CPU_INDEX_GET(reg) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
addu AT, reg ;/* add word index */ \
|
||||
ld reg, 0(AT) ;/* fetch value from array */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG64_VALUE_GET(reg,label) \
|
||||
ld reg, %lo(EXCPAGE_ARCHVARS##label)(zero)
|
||||
|
||||
#define _MIPS_PER_CPU_VALUE_GET(reg,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_MIPS_CPU_INDEX_GET(reg) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
addu AT, reg ;/* add word index */ \
|
||||
lw reg, 0(AT) ;/* fetch value from array */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_VALUE_GET(reg,label) \
|
||||
lw reg, %lo(EXCPAGE_ARCHVARS##label)(zero)
|
||||
|
||||
/* _MIPS_PER_CPU_INDEX_VALUE_GET is the same as _MIPS_PER_CPU_VALUE_GET
|
||||
* but cpuindex is supplied (and overwritten by return value)
|
||||
*/
|
||||
|
||||
#define _MIPS_PER_CPU_INDEX_VALUE_GET(cpuindex,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_WRS_WIND_VARS_OFFSET(cpuindex) \
|
||||
addu AT, cpuindex ;/* add word index */ \
|
||||
lw cpuindex, 0(AT) ;/* fetch value from array */ \
|
||||
.set at
|
||||
|
||||
#if defined(_WRS_MIPS_NETLOGIC_CPU)
|
||||
#define _MIPS_PER_CPU_REG_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_MIPS_CPU_INDEX_GET(rega) \
|
||||
_WRS_WIND_VARS_OFFSET(rega) \
|
||||
addu rega, AT ;/* add word index */ \
|
||||
lwu regv, 0(rega) ;/* fetch value from array */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
la rega, EXCPAGE_ARCHVARS##label ; \
|
||||
lwu regv, 0(rega)
|
||||
|
||||
#else /* ! _WRS_MIPS_NETLOGIC_CPU */
|
||||
#define _MIPS_PER_CPU_REG_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
_MIPS_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,label)
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
_MIPS_PER_CPU_ARCH_VALUE_AND_ADRS_GET(regv,rega,label)
|
||||
|
||||
#endif /* _WRS_MIPS_NETLOGIC_CPU */
|
||||
|
||||
#define _MIPS_PER_CPU_REG64_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_MIPS_CPU_INDEX_GET(rega) \
|
||||
_WRS_WIND_VARS_OFFSET(rega) \
|
||||
addu rega, AT ;/* add word index */ \
|
||||
ld regv, 0(rega) ;/* fetch value from array */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG64_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
la rega, EXCPAGE_ARCHVARS##label ; \
|
||||
ld regv, 0(rega)
|
||||
|
||||
#define _MIPS_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
.set noat ;/* forbid assembler use of AT */ \
|
||||
_WRS_LOAD_AT_WITH_VAR_BASE(label) \
|
||||
_MIPS_CPU_INDEX_GET(rega) \
|
||||
_WRS_WIND_VARS_OFFSET(rega) \
|
||||
addu rega, AT ;/* add word index */ \
|
||||
lw regv, 0(rega) ;/* fetch value from array */ \
|
||||
.set at
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
la rega, EXCPAGE_ARCHVARS##label ; \
|
||||
lw regv, 0(rega)
|
||||
|
||||
#ifndef _MIPS_ASM_EXTERN_KERNEL_GLOBALS
|
||||
#define _MIPS_ASM_EXTERN_KERNEL_GLOBALS
|
||||
#endif /* _MIPS_ASM_EXTERN_KERNEL_GLOBALS */
|
||||
|
||||
/*
|
||||
* _MIPS_KERNEL_LOCK_OWNER_AND_INDEX_GET(ro,ri)
|
||||
*
|
||||
* ro = register to store kernel lock owner
|
||||
* ri = register to store cpu index
|
||||
*
|
||||
* typedef struct smpLock
|
||||
* {
|
||||
* volatile int state; /@ state of lock (free/taken) @/
|
||||
* volatile int owner; /@ CPU which owns the lock @/
|
||||
* int count; /@ recursive ownership nesting count @/
|
||||
* int options; /@ options applicable to this lock @/
|
||||
*/
|
||||
|
||||
#define _MIPS_KERNEL_LOCK_OWNER_AND_INDEX_GET(ro,ri) \
|
||||
la ro,kernelStateLock /* point to lock */; \
|
||||
lw ro,_WRS_KERNEL_LOCK_OFFSET_cpuIndex(ro) /* get CPU index */; \
|
||||
_MIPS_CPU_INDEX_GET(ri)
|
||||
|
||||
#else /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define _WRS_MIPS_VAR_ADRS(label) label
|
||||
|
||||
#define _MIPS_PER_CPU_ADRS_GET(r,label) \
|
||||
la r, _WRS_MIPS_VAR_ADRS(label) /* get address of label */\
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_ADRS_GET(r,label) \
|
||||
_MIPS_PER_CPU_ADRS_GET(r,label)
|
||||
|
||||
#define _MIPS_PER_CPU_INDEX_ADRS_GET(r,label) \
|
||||
la r, _WRS_MIPS_VAR_ADRS(label) /* get address of label */\
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_INDEX_ADRS_GET(r,label) \
|
||||
_MIPS_PER_CPU_INDEX_ADRS_GET(r,label)
|
||||
|
||||
/* On Raza we need a macro to load a 32-bit per-cpu value into a
|
||||
* 64-bit register without sign-extending. We use this macro to retrieve
|
||||
* the lower 32-bits of the EIMR, then write the full 64-bit register
|
||||
* to the EIMR. We want the upper 32 bits to always be zero.
|
||||
*/
|
||||
#if defined(_WRS_MIPS_NETLOGIC_CPU)
|
||||
#define _MIPS_PER_CPU_REG_VALUE_GET(r,label) \
|
||||
lwu r, _WRS_MIPS_VAR_ADRS(label) /* get value at label */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_GET(r,label) \
|
||||
_MIPS_PER_CPU_REG_VALUE_GET(r,label)
|
||||
|
||||
#else /* ! _WRS_MIPS_NETLOGIC_CPU */
|
||||
#define _MIPS_PER_CPU_REG_VALUE_GET(r,label) \
|
||||
_MIPS_PER_CPU_VALUE_GET(r,label)
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_GET(r,label) \
|
||||
_MIPS_PER_CPU_VALUE_GET(r,label)
|
||||
#endif /* _WRS_MIPS_NETLOGIC_CPU */
|
||||
|
||||
#define _MIPS_PER_CPU_REG64_VALUE_GET(r,label) \
|
||||
ld r, _WRS_MIPS_VAR_ADRS(label) /* get value at label */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG64_VALUE_GET(r,label) \
|
||||
_MIPS_PER_CPU_REG64_VALUE_GET(r,label)
|
||||
|
||||
#define _MIPS_PER_CPU_VALUE_GET(r,label) \
|
||||
lw r, _WRS_MIPS_VAR_ADRS(label) /* get value at label */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_VALUE_GET(r,label) \
|
||||
_MIPS_PER_CPU_VALUE_GET(r,label)
|
||||
|
||||
#define _MIPS_PER_CPU_INDEX_VALUE_GET(r,label) \
|
||||
lw r, _WRS_MIPS_VAR_ADRS(label) /* get value at label */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_INDEX_VALUE_GET(r,label) \
|
||||
_MIPS_PER_CPU_INDEX_VALUE_GET(r,label)
|
||||
|
||||
#if defined(_WRS_MIPS_NETLOGIC_CPU)
|
||||
#define _MIPS_PER_CPU_REG_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
la ra, _WRS_MIPS_VAR_ADRS(label); /* get address of label */ \
|
||||
lwu rv, 0(ra) ;/* load value through pointer */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
_MIPS_PER_CPU_REG_VALUE_AND_ADRS_GET(rv,ra,label)
|
||||
|
||||
#else /* ! _WRS_MIPS_NETLOGIC_CPU */
|
||||
#define _MIPS_PER_CPU_REG_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
_MIPS_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label)
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
_MIPS_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label)
|
||||
|
||||
#endif /* _WRS_MIPS_NETLOGIC_CPU */
|
||||
|
||||
#define _MIPS_PER_CPU_REG64_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
la ra, _WRS_MIPS_VAR_ADRS(label); /* get address of label */ \
|
||||
ld rv, 0(ra) ;/* load value through pointer */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_REG64_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
_MIPS_PER_CPU_REG64_VALUE_AND_ADRS_GET(rv,ra,label)
|
||||
|
||||
#define _MIPS_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
la ra, _WRS_MIPS_VAR_ADRS(label); /* get address of label */ \
|
||||
lw rv, 0(ra) ;/* load value through pointer */
|
||||
|
||||
#define _MIPS_PER_CPU_ARCH_VALUE_AND_ADRS_GET(rv,ra,label) \
|
||||
_MIPS_PER_CPU_VALUE_AND_ADRS_GET(rv,ra,label)
|
||||
|
||||
#ifndef _MIPS_ASM_EXTERN_KERNEL_GLOBALS
|
||||
#define _MIPS_ASM_EXTERN_KERNEL_GLOBALS \
|
||||
.extern _mipsEsfTail
|
||||
#endif /* _MIPS_ASM_EXTERN_KERNEL_GLOBALS */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsmpMipsPh */
|
||||
@@ -0,0 +1,77 @@
|
||||
/* vxPortableArchP.h - MIPS portable library configuration */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2010 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01m,20oct10,s_s renamed _WRS_PORTABLE_vxCpuIndexGet to _WRS_PORTABLE_vxCpuLib
|
||||
(CQ:WIND00199670)
|
||||
01l,28apr09,slk enable optimized mutex semaphore code
|
||||
01k,04apr09,slk undefine _WRS_PORTABLE_semBLib and _WRS_PORTABLE_semCLib
|
||||
for UP
|
||||
01j,10oct08,kk renamed _WRS_PORTABLE_spinlockIsrNdLib to
|
||||
_WRS_PORTABLE_spinLockIsrNdLib
|
||||
01i,29aug08,slk undef _WRS_PORTABLE_schedLib for UP MIPS adding optimzed
|
||||
reschedule
|
||||
01h,17jun08,slk undefine _WRS_PORTABLE_syscallDispatch adding optimized MIPS
|
||||
syscallDispatch
|
||||
01g,11apr08,slk undef _WRS_PORTABLE_workQLib adding MIPS workQALib.s
|
||||
01f,25mar08,slk undef _WRS_PORTABLE_qPriBMapNext and
|
||||
_WRS_PORTABLE_qPriBMapLib
|
||||
01e,16jan08,dlk Rename spinLockFastLib --> spinlockIsrNdLib.
|
||||
01d,19dec07,dlk Enable mips-optimized fast spin locks.
|
||||
01c,06jul07,zl enabled optimized libraries
|
||||
01b,03jul07,pes Re-enable optimized bLib.
|
||||
01a,04may07,zl created
|
||||
*/
|
||||
|
||||
#ifndef __INCvxPortableArchPh
|
||||
#define __INCvxPortableArchPh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This file is included from <private/vxPortableP.h>. It may undefine
|
||||
* portable library definitions in order to enable architecture specific
|
||||
* implementation of a library or routine.
|
||||
*/
|
||||
|
||||
/* the following can be overridden with PORTABLE */
|
||||
|
||||
#ifndef PORTABLE
|
||||
|
||||
#undef _WRS_PORTABLE_bLib
|
||||
#undef _WRS_PORTABLE_ffsLib
|
||||
#undef _WRS_PORTABLE_spinLockIsrNdLib
|
||||
#undef _WRS_PORTABLE_qPriBMapNext
|
||||
#undef _WRS_PORTABLE_qPriBMapLib
|
||||
#undef _WRS_PORTABLE_workQLib
|
||||
#undef _WRS_PORTABLE_syscallDispatch
|
||||
#ifndef _WRS_CONFIG_SMP
|
||||
#undef _WRS_PORTABLE_schedLib
|
||||
#undef _WRS_PORTABLE_semBLib
|
||||
#undef _WRS_PORTABLE_semCLib
|
||||
#undef _WRS_PORTABLE_semMLib
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#endif /* PORTABLE */
|
||||
|
||||
/* the following cannot be overridden with PORTABLE */
|
||||
|
||||
#undef _WRS_PORTABLE_vxAtomicLib
|
||||
#undef _WRS_PORTABLE_vxCpuLib
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxPortableArchPh */
|
||||
@@ -0,0 +1,99 @@
|
||||
/* vxdbgMipsLibP.h - private MIPS VxWorks debug library (VxDBG) header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2008, 2010-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this
|
||||
* software may be licensed only pursuant to the terms of an applicable Wind
|
||||
* River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01h,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
|
||||
SMP (CQ:WIND00253870).
|
||||
01g,29apr10,pad Moved extern C statement after include statements.
|
||||
01f,03sep08,jpb Renamed VSB header file
|
||||
01e,27aug08,slk change extern excIntStub_xxxx for SDA support
|
||||
01d,24jun08,jpb Added include path for kernel configurations options set in
|
||||
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
|
||||
01c,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
|
||||
01b,11oct07,rlp Added the VXDBG_INT_REGS_IS_LOCKED macro (CQ:WIND00107725).
|
||||
01a,01jun07,jmp Written
|
||||
*/
|
||||
|
||||
#ifndef __INCvxdbgMipsLibPh
|
||||
#define __INCvxdbgMipsLibPh
|
||||
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro returns the <level> parameter modified with the interrupt lock
|
||||
* level defined into the <value> parameter. The <level> parameter must be
|
||||
* previously get with either intCpuLock() or intRegsLock() API.
|
||||
*/
|
||||
|
||||
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
|
||||
((level & ~SR_INT_ENABLE) | (value & SR_INT_ENABLE))
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/* defines */
|
||||
|
||||
/* return TRUE if interrupts are locked in specified register set. */
|
||||
|
||||
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->sr & SR_INT_ENABLE) == \
|
||||
SR_INT_ENABLE) ? FALSE : TRUE)
|
||||
|
||||
/*
|
||||
* _WRS_VXDBG_CPU_CTRL_VARS_ALIGN sets the alignment constraint for
|
||||
* vxdbgCpuCtrlVars array.
|
||||
* The value must be:
|
||||
* a power of two no smaller than sizeof(vxdbgCpuCtrlVars), and
|
||||
* a multiple of the cache line size on every MIPS variant that supports SMP.
|
||||
*/
|
||||
|
||||
#if _WRS_MIPS_32BIT_CPU
|
||||
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN 256
|
||||
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT 8
|
||||
#else /* _WRS_MIPS_32BIT_CPU */
|
||||
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN 512
|
||||
#define _WRS_VXDBG_CPU_CTRL_VARS_ALIGN_SHIFT 9
|
||||
#endif /* _WRS_MIPS_32BIT_CPU */
|
||||
|
||||
#ifdef _CPU_CACHE_ALIGN_SIZE
|
||||
/*
|
||||
* Validate _WRS_VXDBG_CPU_CTRL_VARS_ALIGN vs current build's
|
||||
* _CPU_CACHE_ALIGN_SIZE
|
||||
*
|
||||
* If any SMP-enabled variant fails this test, _WRS_VXDBG_CPU_CTRL_VARS_ALIGN
|
||||
* must be increased. Since this limit also applies to any subsequent arch-only
|
||||
* release against the same generic binary release, it may be desirable to
|
||||
* allow for growth.
|
||||
*/
|
||||
|
||||
#if (_CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN)
|
||||
#error Must increase "_WRS_VXDBG_CPU_CTRL_VARS_ALIGN" to at least _CPU_CACHE_ALIGN_SIZE
|
||||
#endif /* _CPU_CACHE_ALIGN_SIZE > _WRS_VXDBG_CPU_CTRL_VARS_ALIGN */
|
||||
#endif /* _CPU_CACHE_ALIGN_SIZE */
|
||||
|
||||
/* externals */
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
extern void excIntStub_intExitOpAddr ();
|
||||
extern void excIntStub_intVxdbgCpuRegsGetOpAddr ();
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxdbgMipsLibPh */
|
||||
Reference in New Issue
Block a user