original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,64 @@
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/* adrSpaceArchLibP.h - address space header file for x86_64 */
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/*
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* Copyright (c) 2009-2010, 2018 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01d,18jul18,r_h Add kernel page table isolation support (F10571)
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01c,14apr10,zl changed RTP private region base to 2M
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01b,23dec09,zl fixed shared region base address.
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01a,24aug09,zl created with 64-bit region definitions.
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*/
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#ifndef __INCadrSpaceArchLibPh
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#define __INCadrSpaceArchLibPh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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#define __UL_CONST(x) x
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#else
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#define __UL_CONST(x) x##UL
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#endif
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/* virtual memory region definitions */
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#define RTP_PRIVATE_RGN_BASE __UL_CONST(0x0000000000200000)
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#define RTP_PRIVATE_RGN_SIZE __UL_CONST(0x000007ffffe00000)
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#define SHARED_RGN_BASE __UL_CONST(0x0000780000000000)
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#define SHARED_RGN_SIZE __UL_CONST(0x0000080000000000)
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#define KERNEL_VIRT_POOL_RGN_BASE __UL_CONST(0xffff800000000000)
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#define KERNEL_VIRT_POOL_RGN_SIZE __UL_CONST(0x0000080000000000)
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#define KERNEL_SYS_MEM_RGN_BASE __UL_CONST(0xffffffff80000000)
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#define KERNEL_SYS_MEM_RGN_SIZE __UL_CONST(0x0000000080000000)
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#define KERNEL_DIRECT_MAP_RGN_BASE __UL_CONST(0xfffff00000000000)
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#define KERNEL_DIRECT_MAP_RGN_SIZE __UL_CONST(0x0000080000000000)
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#ifdef _WRS_CONFIG_KPTI
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/*
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* RTP region for supervisor mode access; size is 512GB, the size
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* described by one PLM4 entry (L1 table entry)
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*/
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#define KERNEL_RTP_SUP_RGN_BASE __UL_CONST(0xfffff80000000000)
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#define KERNEL_RTP_SUP_RGN_SIZE __UL_CONST(0x0000008000000000)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCadrSpaceArchLibPh */
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@@ -0,0 +1,331 @@
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/* smpX86_64P.h - x86_64 private SMP assembler definitions header file */
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/*
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* Copyright (c) 2009-2013, 2018 Wind River Systems, Inc.
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*
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||||
* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
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||||
*/
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||||
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/*
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modification history
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||||
--------------------
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01s,18jul18,r_h Add kernel page table isolation support (F10571)
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01r,09jan13,scm WIND00229494 - SMP dedicated segment register
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01q,11sep12,cwl Correct the macro _WRS_WIND_VARS_ARCH_GET for UP.
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(WIND00375599)
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01p,21feb12,scm WIND00326315 - live lock osm & cpc issue...
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01o,14aug11,j_l added vxCpuIdLib.h include.
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01n,10aug11,zl added _WRS_CPU_SMTSET_GET().
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01m,06jan11,scm WIND00240019: add _X86_64_PER_CPU_VALUE_SET_INT macro for SMP support...
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01l,04jan11,scm WIND00248698 adjust vxIntStackEnabled to type BOOL...
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01k,27oct10,rbc WIND00204240 - Add support for objVerifiedSafe.
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01j,29jul10,pad Moved extern C statement after include statements.
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01i,22jun10,j_l Delete _X86_64_LOC_APIC_ID.
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01h,02jun10,scm modify for smp m to n...
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01g,16may10,scm SMP 64 bit macro clean up...
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01f,13may10,scm removal of unused vars...
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01e,29apr10,scm local apic register access adjustment...
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01d,22mar10,scm update for sysCr3...
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01c,18mar10,scm add Local CR3 cache to WIND_VARS_ARCH...
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01b,12feb09,jb Tuning for 64-bit
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01a,26jan09,jb Creating 64-bit version from 32-bit version 01x
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*/
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#ifndef __INCsmpX86_64Ph
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#define __INCsmpX86_64Ph
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/************************************************************/
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#include <vsbConfig.h>
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#include <arch/i86/x86_64/archX86_64.h>
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#include <regs.h>
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#include <private/kernelLockLibP.h>
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#include <hwif/cpu/arch/i86/vxCpuIdLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
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#define _X86_64_CPU_INDEX_SHIFT (0x18)
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#define _X86_64_CPU_INDEX_MASK (0xFF)
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#ifdef _WRS_CONFIG_SMP
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/*
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* IA has been adapted to use the new object safe count feature for SMP.
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* When all architectures have been adapted this can be removed from
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* the code.
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*/
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#define _WRS_ARCH_HAS_OBJ_SAFE
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/*
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* This macro defines the alignment requirement for the WIND_VARS structure.
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*
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* There are 3 factors involved in selection of this value.
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*
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* 1. It's definition is no LESS than the maximum value of
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* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
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* cache line length growth.
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* 2. It must be at least as large as the WIND_VARS structure.
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* 3. It must be a power of 2.
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*
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* For example:
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* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
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* (rule 1).
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* if WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
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* (rules 2 and 3).
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*
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* For KPTI configuration the alignment has to match WIND_RTP_VARS (512 bytes).
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*/
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#ifdef _WRS_CONFIG_KPTI
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# define _WRS_WIND_VARS_ALIGN _WRS_WIND_RTP_VARS_ALIGN
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# define _WRS_WIND_VARS_ALIGN_SHIFT _WRS_WIND_RTP_VARS_ALIGN_SHIFT
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#else
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# define _WRS_WIND_VARS_ALIGN 256
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# define _WRS_WIND_VARS_ALIGN_SHIFT 8
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#endif
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/*
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* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
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* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
|
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* XSCALE, etc), representing the maximum cache line size of the variants of
|
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* the respective arch.
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*
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* For x86 this is 128 bytes.
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*/
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||||
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#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
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#ifndef _ASMLANGUAGE
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/*
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* This macro is used to provide an instruction barrier. It is in this file
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* only until the semantics are solidified, at which point it should be
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* moved to vxAtomicArchLib.h.
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*
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* The current definition is a replication of the VX_MEM_BARRIER_R() macro. It
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* should be revisited when the semantics are finalized.
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*/
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#define VX_INSTR_BARRIER() _WRS_BARRIER("mfence")
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/* mpCpuIndexTable is used in vxCpuArchLib.c, this gloabal avoids
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* calling through vxbus and reduces overhead, table translations
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* are done everywhere, but once up this table should never change...
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*/
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extern UINT8 mpCpuIndexTable[];
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typedef struct wind_vars_arch
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{
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GDT *cpu_pSysGdt; /* 0x70: Global Descriptor Table */
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TSS *cpu_sysTssCurrent; /* 0x78: Task State Segmnet */
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TSS *cpu_excOSMTssCurrent; /* 0x80: OSM TSS */
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ULONG *cpu_excOSMStackCurrent; /* 0x88: OSM Stack */
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||||
ULONG cpu_vxIntStackPtr; /* 0x90: Interrupt Stack Pointer */
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BOOL cpu_vxIntStackEnabled; /* 0x98: Interrupt Stack Enabled */
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unsigned int cpu_cpuIndex; /* 0x9c: logical cpu used by GS ref. */
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ULONG cpu_sysCr3; /* 0xa0: Local CR3 cache */
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UINT32 cpu_intNest; /* 0xa8: Interrupt Nested Count */
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UINT32 cpu_sysOSMState; /* 0xac: OSM State Flag */
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} WIND_VARS_ARCH;
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#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
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/* macro to access the arch-specific fields of the vxKernelVars struct */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
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#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
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#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
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_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
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#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
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#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
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/*
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* _WRS_CPU_SMTSET_GET() is used by the SMP scheduler for Hyper-Threading
|
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* support.
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*/
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||||
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#define _WRS_CPU_SMTSET_GET(smtSet, cpuIx) \
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smtSet = sysCpuIdTopology.__smtSet[cpuIx]
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/* Fast retrieve of cpuIndex using GS Base register offset */
|
||||
|
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static __inline__ unsigned int _vxGsBaseCpuIndexGet_inline (void)
|
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{
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unsigned int cpu;
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__asm__ volatile ("mov %%gs:(0x9c), %%eax" \
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: "=a" (cpu) : /* no input */);
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||||
|
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return cpu;
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}
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#endif /* !_ASMLANGUAGE */
|
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#define _WRS_CPU_INDEX_GET() _vxGsBaseCpuIndexGet_inline ()
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#else /* _WRS_CONFIG_SMP */
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|
||||
#define _WRS_CPU_INDEX_GET() 0
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||||
/* macro to access the arch-specific fields */
|
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
|
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_WRS_KERNEL_GLOBAL_ACCESS (glob)
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#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
|
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_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
|
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|
||||
#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
|
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_WRS_KERNEL_CPU_GLOBAL_GET(ignored,glob)
|
||||
|
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#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
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||||
|
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#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
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||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef _ASMLANGUAGE
|
||||
|
||||
#include <private/windLibP.h>
|
||||
|
||||
#if defined(_WRS_CONFIG_SMP)
|
||||
|
||||
/* SMP support */
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET_pSysGdt (_WRS_WIND_VARS_OFFSET_archVars+0x0)
|
||||
#define _WRS_WIND_VARS_OFFSET_sysTssCurrent (_WRS_WIND_VARS_OFFSET_archVars+0x8)
|
||||
#define _WRS_WIND_VARS_OFFSET_excOSMTssCurrent (_WRS_WIND_VARS_OFFSET_archVars+0x10)
|
||||
#define _WRS_WIND_VARS_OFFSET_excOSMStackCurrent (_WRS_WIND_VARS_OFFSET_archVars+0x18)
|
||||
#define _WRS_WIND_VARS_OFFSET_vxIntStackPtr (_WRS_WIND_VARS_OFFSET_archVars+0x20)
|
||||
#define _WRS_WIND_VARS_OFFSET_vxIntStackEnabled (_WRS_WIND_VARS_OFFSET_archVars+0x28)
|
||||
#define _WRS_WIND_VARS_OFFSET_cpuIndex (_WRS_WIND_VARS_OFFSET_archVars+0x2c)
|
||||
#define _WRS_WIND_VARS_OFFSET_sysCr3 (_WRS_WIND_VARS_OFFSET_archVars+0x30)
|
||||
#define _WRS_WIND_VARS_OFFSET_intNest (_WRS_WIND_VARS_OFFSET_archVars+0x38)
|
||||
#define _WRS_WIND_VARS_OFFSET_sysOSMState (_WRS_WIND_VARS_OFFSET_archVars+0x3c)
|
||||
|
||||
#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
|
||||
lea FUNC(vxKernelVars),reg; \
|
||||
add $_WRS_WIND_VARS_OFFSET_##label,reg;
|
||||
|
||||
#define _WRS_WIND_VARS_OFFSET(reg) \
|
||||
rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
|
||||
|
||||
#define _X86_64_ASM_EXTERN_KERNEL_GLOBALS
|
||||
|
||||
/*
|
||||
* Obtain the address of vxKernelVars[cpuid] for the current
|
||||
* CPU in register 'reg', using 'scratch' as a scratch
|
||||
* variable.
|
||||
*/
|
||||
|
||||
#define _X86_64_CPU_ADRS_BASE_GET(reg,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
leaq FUNC(vxKernelVars)(reg), reg;
|
||||
|
||||
#define _X86_64_PER_CPU_ADRS_GET(reg,scratch,label) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addq reg,scratch; \
|
||||
leaq 0x0(scratch),reg;
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_GET_INT(reg,regv,scratch,label) \
|
||||
_WRS_WIND_VARS_OFFSET(regv) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
add regv,scratch; \
|
||||
movl 0x0(scratch),reg;
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_GET_LONG(reg,scratch,label) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addq reg,scratch; \
|
||||
movq 0x0(scratch),reg;
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_SET_INT(regv,scr1,scr2,label) \
|
||||
_WRS_WIND_VARS_OFFSET(scr1) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
|
||||
addq scr1,scr2; \
|
||||
movl regv,0x0(scr2);
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_SET_LONG(regv,scr1,scr2,label) \
|
||||
_WRS_WIND_VARS_OFFSET(scr1) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
|
||||
addq scr1,scr2; \
|
||||
movq regv,0x0(scr2);
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_AND_ADRS_GET_LONG(regv,rega,scratch,label) \
|
||||
_WRS_WIND_VARS_OFFSET(regv) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addq regv,scratch; \
|
||||
leaq 0x0(scratch),rega; \
|
||||
movq 0x0(scratch),regv;
|
||||
|
||||
#else /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define _WRS_X86_64_VAR_ADRS(label) FUNC(label)
|
||||
|
||||
#define _X86_64_ASM_EXTERN_KERNEL_GLOBALS \
|
||||
.globl FUNC(sysTssCurrent); /* OSM Tss task info */ \
|
||||
.globl FUNC(excOSMTssCurrent); /* OSM Tss */ \
|
||||
.globl FUNC(pSysGdt); /* Gdt */ \
|
||||
.globl FUNC(intNest); /* nested intr cnt */ \
|
||||
.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
|
||||
.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
|
||||
.globl FUNC(sysCr3); /* local CR3 cache */ \
|
||||
.globl FUNC(sysOSMState); /* OSM State Flag */
|
||||
|
||||
|
||||
#define _X86_64_PER_CPU_ADRS_GET(reg,scratch,label) \
|
||||
lea _WRS_X86_64_VAR_ADRS(label),reg; /* get address of label */
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_GET_INT(reg,scratch,label) \
|
||||
movl _WRS_X86_64_VAR_ADRS(label),reg; /* get value at label */
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_GET_LONG(reg,scratch,label) \
|
||||
movq _WRS_X86_64_VAR_ADRS(label),reg; /* get value at label */
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_SET_INT(regv,scr1,scr2,label) \
|
||||
movl regv,_WRS_X86_64_VAR_ADRS(label);
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_SET_LONG(regv,scr1,scr2,label) \
|
||||
movq regv,_WRS_X86_64_VAR_ADRS(label);
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_AND_ADRS_GET_INT(regv,rega,label) \
|
||||
leaq _WRS_X86_64_VAR_ADRS(label),rega; /* get address of label */ \
|
||||
leal 0x0(rega),regv; /* get value at label */
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_AND_ADRS_GET_LONG(regv,rega,label) \
|
||||
leaq _WRS_X86_64_VAR_ADRS(label),rega; /* get address of label */ \
|
||||
leaq 0x0(rega),regv; /* get value at label */
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_INC(reg,scratch,label) \
|
||||
incl _WRS_X86_64_VAR_ADRS(label);
|
||||
|
||||
#define _X86_64_PER_CPU_VALUE_DEC(reg,scratch,label) \
|
||||
decl _WRS_X86_64_VAR_ADRS(label);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCsmpX86_64Ph */
|
||||
@@ -0,0 +1,62 @@
|
||||
/* vxdbgX86_64LibP.h - private X86_64 VxDBG library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this
|
||||
* software may be licensed only pursuant to the terms of an applicable Wind
|
||||
* River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01e,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
|
||||
SMP (CQ:WIND00253870).
|
||||
01d,29apr10,pad Moved extern C statement after include statements.
|
||||
01c,06may09,rlp Added wdbDbgPreBreakpoint and wdbDbgPreTrace prototypes.
|
||||
01b,24feb09,jb Update register reference
|
||||
01a,18feb09,jb Created from 32-bit version 01d
|
||||
*/
|
||||
|
||||
#ifndef __INCvxdbgX86_64LibPh
|
||||
#define __INCvxdbgX86_64LibPh
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro returns the <level> parameter modified with the interrupt lock
|
||||
* level defined into the <value> parameter. The <level> parameter must be
|
||||
* previously get with either intCpuLock() or intRegsLock() API.
|
||||
*/
|
||||
|
||||
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
|
||||
((level & ~INT_FLAG) | (value & INT_FLAG))
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/* return TRUE if interrupts are locked in specified register set. */
|
||||
|
||||
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->rflags & INT_FLAG) == \
|
||||
INT_FLAG) ? FALSE : TRUE)
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
extern void wdbDbgPreBreakpoint (BREAK_ESF * info, long * regs, BOOL hardware);
|
||||
extern void wdbDbgPreTrace (BREAK_ESF * info, long * regs, BOOL hardware);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxdbgX86_64LibPh */
|
||||
Reference in New Issue
Block a user