original files of m241
This commit is contained in:
neelimap
@@ -0,0 +1,421 @@
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/* smpI86P.h - i80x86 private SMP assembler definitions header file */
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/*
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* Copyright (c) 2006-2013, 2018 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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02n,18jul18,r_h Add kernel page table isolation support (F10571)
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02m,16may13,scm WIND00417700 SMP diab macro correction...
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02l,09jan13,scm WIND00229494 - SMP dedicated segment register
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02k,20dec12,yjw clear warning when load symbol table.(WIND00380360)
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02j,11sep12,cwl Correct the macro _WRS_WIND_VARS_ARCH_GET for UP.
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(WIND00375599)
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02i,27jan12,scm WIND00326315 - live lock osm & cpc issue...
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02h,10aug11,zl added _WRS_CPU_SMTSET_GET()
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02g,04jan11,scm WIND00248698 adjust vxIntStackEnabled to type BOOL...
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02f,12nov10,pch CQ240922: exclude refs to OSM when small footprint selected
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02e,25oct10,rbc WIND00204240 - Add support for objVerifiedSafe.
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02d,29jul10,pad Moved extern C statement after include statements.
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02c,24may10,jb Mods for SMP M-N support
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02b,05may10,jl add support for SMP GuestOS
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02a,07may09,pee using generated offsets. Removing hardcoded offsets.
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01z,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
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01y,12feb09,sem Added sysCr3 to the WIND_VARS_ARCH struct
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Added sysCr3 access macros
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01x,18sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
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01w,27aug08,jpb Renamed VSB header file
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01v,30jul08,rbc Fix undefines for _IA32_LOC_APIC_ID...
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01u,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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01t,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
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01s,22apr08,zl ensure 32-bit _IA32_LOC_APIC_ID register access.
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01r,10jan08,gls added VX_INSTR_BARRIER()
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01q,01aug07,scm optimize _WRS_CPU_INDEX_GET()...
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01p,31may07,scm add _IA32_CPU_ADRS_BASE_GET macro...
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01o,04may07,scm correct _IA32_PER_CPU_VALUE_SET macro...
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01m,17apr07,kk move VX_MAX_SMP_CPUS to archI86.h
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01l,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
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01k,06dec06,scm correct macro for GNU compiler support...
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01j,28nov06,scm remove def for _WRS_WIND_VARS_OFFSET_archVars...
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01i,02nov06,scm rename pSysGdtCurrent for backward comp with P2/3/4...
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01h,26oct06,scm add per Cpu OSM Scratch memory space for GDT data manipulation
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01g,05oct06,scm add translation to _IA32_CPU_INDEX_GET...
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01f,03oct06,scm additional macro work...
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01e,15sep06,scm add specific vxKernelVars[] support...
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01d,30aug06,scm expand _WRS_WIND_VARS_ARCH...
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01c,21aug06,jb Combining smpI86P.h and vxCpuLibP.h
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01b,01aug06,scm more SMP work...
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01a,21jul06,scm created, added SMP Support Macros...
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*/
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#ifndef __INCasmI86Ph
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#define __INCasmI86Ph
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/************************************************************/
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#include <vsbConfig.h>
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#include <arch/i86/archI86.h>
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#include <arch/i86/regsI86.h>
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#include <private/kernelLockLibP.h>
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#include <hwif/cpu/arch/i86/vxCpuIdLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
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/*
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* 0xFEE00020 is the address of the local APIC ID Register.
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*/
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#define _IA32_LOC_APIC_ID 0xFEE00020
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#define _IA32_CPU_INDEX_SHIFT (0x18)
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#define _IA32_CPU_INDEX_MASK (0xFF)
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#ifdef _WRS_CONFIG_SMP
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/*
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* IA32 has been adapted to use the new object safe count feature for SMP.
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* When all architectures have been adapted this can be removed from
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* the code.
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*/
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#define _WRS_ARCH_HAS_OBJ_SAFE
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/*
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* This macro defines the alignment requirement for the WIND_VARS structure.
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*
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* There are 3 factors involved in selection of this value.
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*
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* 1. It's definition is no LESS than the maximum value of
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* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
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* cache line length growth.
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* 2. It must be at least as large as the WIND_VARS structure.
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* 3. It must be a power of 2.
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*
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* For example:
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* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
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* (rule 1).
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* If WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
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* (rules 2 and 3).
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*
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* For KPTI the alignment has to match WIND_RTP_VARS_ARCH; for that, we need
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* _WRS_WIND_RTP_VARS_ALIGN bytes.
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*/
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#ifdef _WRS_CONFIG_KPTI
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#define _WRS_WIND_VARS_ALIGN _WRS_WIND_RTP_VARS_ALIGN
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#define _WRS_WIND_VARS_ALIGN_SHIFT _WRS_WIND_RTP_VARS_ALIGN_SHIFT
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#else
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#define _WRS_WIND_VARS_ALIGN 128
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#define _WRS_WIND_VARS_ALIGN_SHIFT 7
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#endif
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/*
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* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
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* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
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* XSCALE, etc), representing the maximum cache line size of the variants of
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* the respective arch.
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*
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* For x86 this is 128 bytes.
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*/
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#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
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#ifndef _ASMLANGUAGE
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#ifdef _WRS_CONFIG_WRHV_GUEST
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/*
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* wrhvVbCpuId is used to store the address of the virtual-core's cpuId.
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* This global contains the virtual address for the core configuration
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* and avoids making a VBI function call to get the wrhvVbConfig address
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* and calculate the offset to the core id..
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*/
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extern UINT32 *wrhvVbCpuId;
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#endif /* WRS_CONFIG_WRHV_GUEST */
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/* mpCpuIndexTable is used in vxCpuArchLib.c, this gloabal avoids
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* calling through vxbus and reduces overhead, table translations
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* are done everywhere, but once up this table should never change...
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*/
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extern UINT8 mpCpuIndexTable[];
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typedef struct wind_vars_arch
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{
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GDT *cpu_pSysGdt; /* 0x4c: Global Descriptor Table */
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TSS *cpu_sysTssCurrent; /* 0x50: Task State Segmnet */
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TSS *cpu_excOSMTssCurrent; /* 0x54: OSM TSS */
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SEGDESC *cpu_sysOSMLdtCurrent; /* 0x58: Local Descriptor Table */
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UINT32 *cpu_excOSMStackCurrent; /* 0x5c: OSM Stack */
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UINT32 *cpu_sysOSMGdtScratchCurrent; /* 0x60: OSM Scratch memory */
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UINT32 cpu_vxIntStackPtr; /* 0x64: Interrupt Stack Pointer */
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BOOL cpu_vxIntStackEnabled; /* 0x68: Interrupt Stack Enabled */
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unsigned int cpu_cpuIndex; /* 0x6c: logical cpu used by GS */
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UINT32 cpu_cpuGsBaseCurrent; /* 0x70: &vxKernelVars in gsbase */
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UINT32 cpu_intNest; /* 0x74: Interrupt Nested Count */
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UINT32 cpu_sysCr3; /* 0x78: Local CR3 cache */
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UINT32 cpu_sysOSMState; /* 0x7c: OSM State Flag */
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} WIND_VARS_ARCH;
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#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
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/* macro to access the arch-specific fields of the vxKernelVars struct */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
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#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
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#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
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_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
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#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
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#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
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/*
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* _WRS_CPU_SMTSET_GET() is used by the SMP scheduler for Hyper-Threading
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* support.
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*/
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#define _WRS_CPU_SMTSET_GET(smtSet, cpuIx) \
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smtSet = sysCpuIdTopology.__smtSet[cpuIx]
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/* Fast retrieve of cpuIndex using GS Base register offset */
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#if defined (__DCC__)
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__asm volatile unsigned int _vxGsBaseCpuIndexGet_inline (void)
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{
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! "ax" /* ax is clobbered */
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mov %gs:(0x6c), %eax
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}
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#else /* if defined (__GNUC__) */
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static __inline__ unsigned int _vxGsBaseCpuIndexGet_inline (void)
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{
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unsigned int cpu;
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__asm__ volatile ("mov %%gs:(0x6c), %%eax" \
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: "=a" (cpu) : /* no input */);
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return cpu;
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}
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#endif /* __DCC__ */
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#endif /* !_ASMLANGUAGE */
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#ifdef _WRS_CONFIG_WRHV_GUEST
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#define _WRS_CPU_INDEX_GET() \
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(*(volatile UINT32 *)wrhvVbCpuId)
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#else /* _WRS_CONFIG_WRHV_GUEST */
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#define _WRS_CPU_INDEX_GET() _vxGsBaseCpuIndexGet_inline ()
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#endif /* _WRS_CONFIG_WRHV_GUEST */
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#else /* _WRS_CONFIG_SMP */
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#define _WRS_CPU_INDEX_GET() 0
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/* macro to access the arch-specific fields */
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#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
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_WRS_KERNEL_GLOBAL_ACCESS (glob)
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#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
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_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
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#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
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_WRS_KERNEL_CPU_GLOBAL_GET(ignored,glob)
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#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
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#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
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_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
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#endif /* _WRS_CONFIG_SMP */
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|
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#ifdef _ASMLANGUAGE
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|
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#include <private/windLibP.h>
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|
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#if defined(_WRS_CONFIG_SMP)
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|
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/* generated macro values required by assembly macros below */
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#include <private/offsetMacrosP.h>
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|
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/* SMP support */
|
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|
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#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
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leal FUNC(vxKernelVars),reg; \
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addl $_WIND_VARS_cpu_##label##_OFFSET,reg;
|
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|
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#define _WRS_WIND_VARS_OFFSET(reg) \
|
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rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
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|
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#define _IA32_ASM_EXTERN_KERNEL_GLOBALS
|
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|
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#ifdef _WRS_CONFIG_WRHV_GUEST
|
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#define _IA32_CPU_INDEX_GET(reg,scratch) \
|
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movl wrhvVbCpuId,reg; \
|
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movl 0x0(reg),reg;
|
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#else /* _WRS_CONFIG_WRHV_GUEST */
|
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#define _IA32_CPU_INDEX_GET(reg,scratch) \
|
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movl $_IA32_LOC_APIC_ID,reg; \
|
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movl 0x0(reg),reg; \
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ror $_IA32_CPU_INDEX_SHIFT,reg; \
|
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andl $_IA32_CPU_INDEX_MASK,reg; \
|
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leal FUNC(mpCpuIndexTable)(reg),scratch; \
|
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mov 0x0(scratch),reg; \
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andl $_IA32_CPU_INDEX_MASK,reg; \
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subl FUNC(vxBaseCpuPhysIndex), reg;
|
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#endif /* _WRS_CONFIG_WRHV_GUEST */
|
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|
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/*
|
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* Obtain the address of vxKernelVars[cpuid] for the current
|
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* CPU in register 'reg', using 'scratch' as a scratch
|
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* variable.
|
||||
*/
|
||||
|
||||
#define _IA32_CPU_ADRS_BASE_GET(reg,scratch) \
|
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_IA32_CPU_INDEX_GET(reg,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
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leal FUNC(vxKernelVars)(reg), reg;
|
||||
|
||||
#define _IA32_PER_CPU_ADRS_GET(reg,scratch,label) \
|
||||
_IA32_CPU_INDEX_GET(reg,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
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_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addl reg,scratch; \
|
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leal 0x0(scratch),reg;
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_GET(reg,scratch,label) \
|
||||
_IA32_CPU_INDEX_GET(reg,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
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addl reg,scratch; \
|
||||
movl 0x0(scratch),reg;
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_SET(regv,scr1,scr2,label) \
|
||||
_IA32_CPU_INDEX_GET(scr1,scr2) \
|
||||
_WRS_WIND_VARS_OFFSET(scr1) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
|
||||
addl scr1,scr2; \
|
||||
movl regv,0x0(scr2);
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,scratch,label) \
|
||||
_IA32_CPU_INDEX_GET(regv,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(regv) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addl regv,scratch; \
|
||||
leal 0x0(scratch),rega; \
|
||||
movl 0x0(scratch),regv;
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_INC(reg,scratch,label) \
|
||||
_IA32_CPU_INDEX_GET(reg,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addl reg,scratch; \
|
||||
movl 0x0(scratch),reg; \
|
||||
incl reg; \
|
||||
movl reg,0x0(scratch);
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_DEC(reg,scratch,label) \
|
||||
_IA32_CPU_INDEX_GET(reg,scratch) \
|
||||
_WRS_WIND_VARS_OFFSET(reg) \
|
||||
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
|
||||
addl reg,scratch; \
|
||||
movl 0x0(scratch),reg; \
|
||||
decl reg; \
|
||||
movl reg,0x0(scratch);
|
||||
|
||||
/*
|
||||
* rega = register to store kernel lock owner
|
||||
* regb = register to store cpu index
|
||||
*
|
||||
* typedef struct smpLock
|
||||
* {
|
||||
* volatile int state; /@ state of lock (free/taken) @/
|
||||
* volatile int owner; /@ CPU which owns the lock @/
|
||||
* int count; /@ recursive ownership nesting count @/
|
||||
* int options; /@ options applicable to this lock @/
|
||||
*/
|
||||
#define _IA32_KERNEL_LOCK_OWNER_AND_INDEX_GET(rega, regb) \
|
||||
_IA32_CPU_INDEX_GET(regb,rega) \
|
||||
leal FUNC(kernelStateLock),rega; \
|
||||
movl VX_KERNEL_LOCK_cpuIndex_OFFSET(rega),rega;
|
||||
/* kernel spin lock owner */
|
||||
|
||||
#else /* _WRS_CONFIG_SMP */
|
||||
|
||||
#define _WRS_IA32_VAR_ADRS(label) FUNC(label)
|
||||
|
||||
#ifdef _WRS_CONFIG_MEM_ALLOT
|
||||
|
||||
/* exclude OSM references, because OSM requires malloc() */
|
||||
|
||||
#define _IA32_ASM_EXTERN_KERNEL_GLOBALS \
|
||||
.globl FUNC(pSysGdt); /* Gdt */ \
|
||||
.globl FUNC(intNest); /* nested intr cnt */ \
|
||||
.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
|
||||
.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
|
||||
.globl FUNC(sysCr3); /* local CR3 cache */
|
||||
|
||||
#else /* _WRS_CONFIG_MEM_ALLOT */
|
||||
|
||||
#define _IA32_ASM_EXTERN_KERNEL_GLOBALS \
|
||||
.globl FUNC(sysTssCurrent); /* OSM Tss task info */ \
|
||||
.globl FUNC(excOSMTssCurrent); /* OSM Tss */ \
|
||||
.globl FUNC(sysOSMGdtScratchCurrent); /* OSM Scratch memory */ \
|
||||
.globl FUNC(sysOSMState); /* OSM State Flag */ \
|
||||
.globl FUNC(pSysGdt); /* Gdt */ \
|
||||
.globl FUNC(intNest); /* nested intr cnt */ \
|
||||
.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
|
||||
.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
|
||||
.globl FUNC(sysCr3); /* local CR3 cache */
|
||||
|
||||
#endif /* _WRS_CONFIG_MEM_ALLOT */
|
||||
|
||||
#define _IA32_PER_CPU_ADRS_GET(reg,scratch,label) \
|
||||
leal _WRS_IA32_VAR_ADRS(label),reg; /* get address of label */
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_GET(reg,scratch,label) \
|
||||
movl _WRS_IA32_VAR_ADRS(label),reg; /* get value at label */
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_SET(regv,scr1,scr2,label) \
|
||||
movl regv,_WRS_IA32_VAR_ADRS(label);
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,label) \
|
||||
leal _WRS_IA32_VAR_ADRS(label),rega; /* get address of label */ \
|
||||
leal 0x0(rega),regv; /* get value at label */
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_INC(reg,scratch,label) \
|
||||
incl _WRS_IA32_VAR_ADRS(label);
|
||||
|
||||
#define _IA32_PER_CPU_VALUE_DEC(reg,scratch,label) \
|
||||
decl _WRS_IA32_VAR_ADRS(label);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCasmI86Ph */
|
||||
@@ -0,0 +1,102 @@
|
||||
/* vxPortableArchP.h - x86/x86_64 portable library configuration */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01w,20jan11,scm WIND00251661 - PORTABLE macro should not be defined by
|
||||
default.
|
||||
01v,20oct10,s_s renamed _WRS_PORTABLE_vxCpuIndexGet to _WRS_PORTABLE_vxCpuLib
|
||||
(CQ:WIND00199670)
|
||||
01u,26may10,scm enable optimized syscallDispatcher...
|
||||
01t,23mar10,scm enable _WRS_PORTABLE_vxAtomicLib for 64 bit...
|
||||
01s,18mar10,scm enable _WRS_PORTABLE_kernelLockLib and
|
||||
_WRS_PORTABLE_spinLockIsrNdLib
|
||||
01r,04feb10,scm add ffs 64 bit flag...
|
||||
01q,20jan10,scm enable qPriBMapLib & qPriBMapNext...
|
||||
01p,07jan10,scm enable optimized libs for bLib, workQLib, dllLib, sllLib,
|
||||
and ffsLib.
|
||||
01o,09dec09,cww 64-bit ffsLib update
|
||||
01n,27jul09,jb Make vxAtomic portable for LP64
|
||||
01m,19jun09,mze replacing PAD64
|
||||
01l,20apr09,cww Temp enabling of portable vxAtomicLib for LP64
|
||||
01k,16oct08,jb 64bit - Enabling PORTABLE - To be disabled as optimized
|
||||
routines are ported
|
||||
01j,10oct08,kk renamed _WRS_PORTABLE_spinlockIsrNdLib to
|
||||
_WRS_PORTABLE_spinLockIsrNdLib
|
||||
01i,24mar08,scm enable optimized workQ routines...
|
||||
01h,16mar08,scm enable optimized qPriBMapNext...
|
||||
01g,13mar08,scm enabled optimized syscallDispatch...
|
||||
01f,16jan08,dlk Rename spinLockFastLib --> spinlockIsrNdLib.
|
||||
01e,10dec07,dlk Enabled i86-optimized fast spin locks.
|
||||
01d,22sep07,zl enabled optimized kernel lock library.
|
||||
01c,04jun07,scm update to support optimized implementations...
|
||||
01b,15may07,scm restore settings
|
||||
01a,04may07,zl created
|
||||
*/
|
||||
|
||||
#ifndef __INCvxPortableArchPh
|
||||
#define __INCvxPortableArchPh
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This file is included from <private/vxPortableP.h>. It may undefine
|
||||
* portable library definitions in order to enable architecture specific
|
||||
* implementation of a library or routine.
|
||||
*/
|
||||
|
||||
/* the following can be overridden with PORTABLE */
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
#ifndef PORTABLE
|
||||
#undef _WRS_PORTABLE_kernelLockLib
|
||||
#undef _WRS_PORTABLE_spinLockIsrNdLib
|
||||
#undef _WRS_PORTABLE_vxAtomicLib
|
||||
#undef _WRS_PORTABLE_bLib
|
||||
#undef _WRS_PORTABLE_workQLib
|
||||
#undef _WRS_PORTABLE_dllLib
|
||||
#undef _WRS_PORTABLE_sllLib
|
||||
#undef _WRS_PORTABLE_ffsLib
|
||||
#undef _WRS_PORTABLE_ffs64Lib
|
||||
#undef _WRS_PORTABLE_qPriBMapLib
|
||||
#undef _WRS_PORTABLE_qPriBMapNext
|
||||
#undef _WRS_PORTABLE_syscallDispatch
|
||||
#endif
|
||||
|
||||
#else /* (LP64) */
|
||||
|
||||
#ifndef PORTABLE
|
||||
#undef _WRS_PORTABLE_bLib
|
||||
#undef _WRS_PORTABLE_dllLib
|
||||
#undef _WRS_PORTABLE_ffsLib
|
||||
#define _WRS_PORTABLE_ffs64Lib
|
||||
#undef _WRS_PORTABLE_kernelLockLib
|
||||
#undef _WRS_PORTABLE_sllLib
|
||||
#undef _WRS_PORTABLE_spinLockIsrNdLib
|
||||
#undef _WRS_PORTABLE_syscallDispatch
|
||||
#undef _WRS_PORTABLE_qPriBMapLib
|
||||
#undef _WRS_PORTABLE_qPriBMapNext
|
||||
#undef _WRS_PORTABLE_workQLib
|
||||
#undef _WRS_PORTABLE_vxAtomicLib
|
||||
#endif
|
||||
#endif /* (LP64) */
|
||||
|
||||
/* the following cannot be overridden with PORTABLE */
|
||||
|
||||
#undef _WRS_PORTABLE_vxCpuLib
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxPortableArchPh */
|
||||
@@ -0,0 +1,55 @@
|
||||
/* vxdbgI86LibP.h - private I86 VxDBG library header file */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2008, 2010-2011 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use of this
|
||||
* software may be licensed only pursuant to the terms of an applicable Wind
|
||||
* River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01f,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
|
||||
SMP (CQ:WIND00253870).
|
||||
01e,29apr10,pad Moved extern C statement after include statements.
|
||||
01d,27aug08,jpb Renamed VSB header file
|
||||
01c,24jun08,jpb Added include path for kernel configurations options set in
|
||||
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
|
||||
01b,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
|
||||
01a,11oct07,rlp Written
|
||||
*/
|
||||
|
||||
#ifndef __INCvxdbgI86LibPh
|
||||
#define __INCvxdbgI86LibPh
|
||||
|
||||
#include <vsbConfig.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro returns the <level> parameter modified with the interrupt lock
|
||||
* level defined into the <value> parameter. The <level> parameter must be
|
||||
* previously get with either intCpuLock() or intRegsLock() API.
|
||||
*/
|
||||
|
||||
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
|
||||
((level & ~INT_FLAG) | (value & INT_FLAG))
|
||||
|
||||
#ifdef _WRS_CONFIG_SMP
|
||||
|
||||
/* return TRUE if interrupts are locked in specified register set. */
|
||||
|
||||
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->eflags & INT_FLAG) == \
|
||||
INT_FLAG) ? FALSE : TRUE)
|
||||
|
||||
#endif /* _WRS_CONFIG_SMP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCvxdbgI86LibPh */
|
||||
@@ -0,0 +1,122 @@
|
||||
/* windArchLibP.h - private WIND header file for i86 */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2018 Wind River Systems, Inc.
|
||||
*
|
||||
* The right to copy, distribute, modify or otherwise make use
|
||||
* of this software may be licensed only pursuant to the terms
|
||||
* of an applicable Wind River license agreement.
|
||||
*/
|
||||
|
||||
/*
|
||||
modification history
|
||||
--------------------
|
||||
01a,18jul18,r_h created for kernel page table isolation support (F10571)
|
||||
*/
|
||||
|
||||
#ifndef __INCwindArchLibPh
|
||||
#define __INCwindArchLibPh
|
||||
|
||||
|
||||
#include <vsbConfig.h>
|
||||
#include <private/adrSpaceLibP.h>
|
||||
#ifdef _ASMLANGUAGE
|
||||
#include <private/offsetMacrosP.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef _WRS_CONFIG_KPTI
|
||||
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
#define _WRS_WIND_RTP_VARS_ALIGN 512
|
||||
#define _WRS_WIND_RTP_VARS_ALIGN_SHIFT 9
|
||||
#define RTP_TRAMPOLINE_STACK_SIZE 192
|
||||
#define TSS_MAX_COUNT 1
|
||||
#else
|
||||
#define _WRS_WIND_RTP_VARS_ALIGN 1024
|
||||
#define _WRS_WIND_RTP_VARS_ALIGN_SHIFT 10
|
||||
#define RTP_TRAMPOLINE_STACK_SIZE 96
|
||||
#define TSS_MAX_COUNT 2
|
||||
#endif
|
||||
|
||||
#define GDT_MAX_COUNT 12
|
||||
|
||||
/* RTP region for 32-bit supervisor mode access */
|
||||
|
||||
#ifndef _WRS_CONFIG_LP64
|
||||
#ifndef _ASMLANGUAGE
|
||||
IMPORT char *trampolineBaseAddr;
|
||||
#endif /* _ASMLANGUAGE */
|
||||
#define KERNEL_RTP_SUP_RGN_BASE trampolineBaseAddr
|
||||
#define KERNEL_RTP_SUP_RGN_SIZE 0x00400000
|
||||
#endif
|
||||
|
||||
#define RTP_SUP_RGN_CODE_ADDR (KERNEL_RTP_SUP_RGN_BASE + 0x000000)
|
||||
#define RTP_SUP_RGN_CODE_SIZE 0x2000
|
||||
#define RTP_SUP_RGN_DATA_ADDR (KERNEL_RTP_SUP_RGN_BASE + RTP_SUP_RGN_CODE_SIZE)
|
||||
#define RTP_SUP_RGN_DATA_SIZE (RTP_SUP_RGN_IDT_SIZE + RTP_SUP_RGN_VARS_SIZE)
|
||||
|
||||
/* space for 256 IDT entries, each entry is 16 bytes (4k total) */
|
||||
|
||||
#define RTP_SUP_RGN_IDT_ADDRESS (RTP_SUP_RGN_DATA_ADDR)
|
||||
#define RTP_SUP_RGN_IDT_SIZE ((HIGH_VEC + 1) * 16)
|
||||
|
||||
/* 256 bytes for each CPU for WIND_RTP_VARS (up to 16k) */
|
||||
|
||||
#define RTP_SUP_RGN_VARS_ADDR (RTP_SUP_RGN_DATA_ADDR + RTP_SUP_RGN_IDT_SIZE)
|
||||
#define RTP_SUP_RGN_VARS_SIZE (_WRS_WIND_RTP_VARS_ALIGN * VX_MAX_SMP_CPUS)
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
/*
|
||||
* per-CPU arch specific data accessible using the user-mode page table.
|
||||
* For x86 the total size (including the arch-independent part) is 512
|
||||
* bytes(64-bit mode) or 1024 bytes(32-bit mode), see
|
||||
* _WRS_WIND_RTP_VARS_ALIGN / _WRS_WIND_VARS_ALIGN.
|
||||
*
|
||||
* Note: unlike the windVarsArch, this is used for UP as well.
|
||||
*/
|
||||
|
||||
typedef struct windRtpVarsArch
|
||||
{
|
||||
TSS tss[TSS_MAX_COUNT]; /* 0x010 / 0x020: TSS */
|
||||
#ifndef _WRS_CONFIG_LP64
|
||||
ULONG tss_pad; /* ----- / : for future use */
|
||||
#endif
|
||||
ULONG cr3Offset; /* 0x22c / 0x088: offset to user mode CR3 */
|
||||
GDT gdt[GDT_MAX_COUNT]; /* 0x230 / 0x090: GDT */
|
||||
#ifdef _WRS_CONFIG_LP64
|
||||
ULONG reserved[2]; /* ----- / 0x0f0: for future use */
|
||||
#endif
|
||||
char trampolineStack[RTP_TRAMPOLINE_STACK_SIZE];
|
||||
/* 0x290 / 0x100: trampoline stack */
|
||||
} WIND_RTP_VARS_ARCH;
|
||||
|
||||
#define _WRS_WIND_RTP_VARS_ARCH WIND_RTP_VARS_ARCH cpu_archVars
|
||||
|
||||
#define _WRS_WIND_RTP_VARS_ARCH_ACCESS(ix, var) \
|
||||
_WRS_WIND_RTP_VARS_ACCESS (ix, archVars.var)
|
||||
|
||||
#define RTP_SUP_RGN_GDT_ADDRESS(cpu) \
|
||||
(&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, gdt[0]))
|
||||
#define RTP_SUP_RGN_TSS_ADDRESS(cpu) \
|
||||
(&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, tss[0]))
|
||||
|
||||
#ifndef _WRS_CONFIG_LP64
|
||||
#define RTP_SUP_RGN_OSMTSS_ADDRESS(cpu) \
|
||||
(&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, tss[1]))
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* _WRS_CONFIG_KPTI */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCwindArchLibPh */
|
||||
Reference in New Issue
Block a user