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/* mmuI86Lib.h - mmuI86Lib header for i86. */
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/* Copyright 1984-2003 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01g,24jun04,zmm Ported from mmuPro32Lib.h version 01f to P5 MMU.
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01f,12jun02,hdn added arch specific VM library APIs' prototype
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01e,22aug01,hdn moved GDT and GDT_ENTRIES to regsI86.h
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01d,13may98,hdn added PAGE_SIZE_XXX and _ASMLANGUAGE macros.
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01c,07jan95,hdn added GDT and GDT_ENTRIES.
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01b,01nov94,hdn added MMU_STATE_CACHEABLE_WT for Pentium.
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01a,26jul93,hdn written based on mc68k's version.
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*/
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#ifndef __INCmmuI86Libh
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#define __INCmmuI86Libh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PAGE_SIZE 0x1000
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#define PAGE_BLOCK_SIZE 0x400000
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#define PAGE_SIZE_4KB 0x1000
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#define PAGE_SIZE_4MB 0x400000
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#define N_PTES 1024
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#define N_PDES 1024
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#define DIRECTORY_BITS 0xffc00000
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#define TABLE_BITS 0x003ff000
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#define OFFSET_BITS_4KB 0x00000fff
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#define DIRECTORY_INDEX 22
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#define TABLE_INDEX 12
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#define PTE_TO_ADDR_4KB 0xfffff000
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#define PTE_INVALID PTE_TO_ADDR_4KB
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#define PDE_INVALID PTE_INVALID
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#define ADDR_TO_PAGE 12
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#define ADDR_TO_PAGEBASE 0xffc00000
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#ifndef _ASMLANGUAGE
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typedef struct
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{
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unsigned present:1;
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unsigned rw:1;
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unsigned us:1;
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unsigned pwt:1;
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unsigned pcd:1;
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unsigned access:1;
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unsigned dirty:1;
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unsigned zero:2;
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unsigned avail:3;
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unsigned page:20;
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} PTE_FIELD;
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typedef union pte
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{
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PTE_FIELD field;
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unsigned int bits;
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} PTE;
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typedef struct mmuTransTblStruct
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{
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PTE *pDirectoryTable;
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INT32 pageSize; /* Fixed size 4K or 4M if !mixed */
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BOOL mixed; /* TRUE if mixed size pages */
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} MMU_TRANS_TBL;
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#define MMU_STATE_MASK_VALID 0x001
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#define MMU_STATE_MASK_WRITABLE 0x002
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#define MMU_STATE_MASK_USER 0x004
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#define MMU_STATE_MASK_PROTECTION 0x006
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#define MMU_STATE_MASK_WRITETHROUGH 0x008
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#define MMU_STATE_MASK_WBACK 0x008
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#define MMU_STATE_MASK_CACHEABLE 0x018 /* 0x018 was 0x10 in AE version */
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#define MMU_STATE_MASK_GLOBAL 0x100
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#define MMU_STATE_MASK_STATE 0x11f
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#define MMU_STATE_VALID 0x001
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#define MMU_STATE_VALID_NOT 0x000
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#define MMU_STATE_WRITABLE 0x002
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#define MMU_STATE_WRITABLE_NOT 0x000
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#define MMU_STATE_USER 0x004
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#define MMU_STATE_USER_NOT 0x000
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#define MMU_STATE_WRITETHROUGH 0x008
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#define MMU_STATE_WBACK 0x000
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#define MMU_STATE_COPYBACK 0x000
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#define MMU_STATE_CACHEABLE_NOT 0x018 /* 0x18 was 0x10 in AE version */
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#define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT
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#define MMU_STATE_CACHEABLE 0x000
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#define MMU_STATE_GLOBAL 0x100
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#define MMU_STATE_GLOBAL_NOT 0x000
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#define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT) /* 0x0 */
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#define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT) /* 0x4 */
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#define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE) /* 0x2 */
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#define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE) /* 0x6 */
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/* wpOff is used to temporarily override supervisor write-protection.
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* When using wpOff, interrupts should
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* be locked because this disables write-protection system wide!
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* Before unlocking interrupts, be sure to do a wpOn().
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*/
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#define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff)
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#define wpOn() vxCr0Set (vxCr0Get() | 0x00010000)
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS mmuI86LibInit (int pageSize);
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extern STATUS mmuI86Enable (BOOL enable);
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extern void mmuI86On ();
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extern void mmuI86Off ();
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extern void mmuI86TLBFlush ();
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extern void mmuI86PdbrSet (MMU_TRANS_TBL *transTbl);
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extern void mmuI86Show (MMU_TRANS_TBL *transTbl, void * vaddr);
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extern MMU_TRANS_TBL *mmuI86PdbrGet ();
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#else /* __STDC__ */
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extern STATUS mmuI86LibInit ();
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extern STATUS mmuI86Enable ();
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extern void mmuI86On ();
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extern void mmuI86Off ();
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extern void mmuI86TLBFlush ();
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extern void mmuI86PdbrSet ();
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extern void mmuI86Show ();
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extern MMU_TRANS_TBL *mmuI86PdbrGet ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmmuI86Libh */
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