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neelimap
2026-07-30 11:19:44 +05:30
parent 170c2b3f3a
commit afc7070c1f
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vxworks-6.9/target/h/arch/i86/archI86.h
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/* archI86.h - Intel 80X86 specific header */
/*
* Copyright (c) 1993,1999,2001-2008,2010,2011,2013 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
03b,20jun13,scm WIND00420874 - correct workQAdd indexing for more than 8
core...
03a,14aug11,j_l Move _WRS_ARCH_HAS_CPU_PWR_MGMT outside of power management
ifdef.
02z,12aug11,rbc WIND00238999 - Fix conditional for CPU==NEHALEM
02y,11aug11,rbc WIND00238999 - Fix build errors
02x,09aug11,rbc WIND00238999 - Fix build error for windPwrDown()
02w,18may11,jb Requirement WIND00189850 - Increase VX_MAX_SMP_CPUS for HT/SMT support
02v,19jan11,jb Fix for WIND00185635 - mmu deoptimize locks do not work
02u,05nov10,gls modified _ALLOC_ALIGN_SIZE
02t,20oct10,zl defined _WRS_ARCH_DEFERS_KERNEL_UNLOCK and
_WRS_ARCH_HAS_TASK_MMU_CURRENT_SET.
02t,30sep10,sem Add new IA cpus. Remove pentium2/3
02s,16sep10,gls added VX_OBJ_ALIGN_SIZE
02r,29jul10,pad Moved extern C statement after include statements.
02q,10oct08,rbc WIND00132719. Add defines for _STACK_ALIGN_SIZE and
_ALLOC_ALIGN_SIZE.
02p,27aug08,jpb Renamed VSB header file
02o,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
02n,13mar08,rlp Removed obsolete _WRS_ARCH_HAS_DBG_IPI macro.
02m,24sep07,scm WIND00105635, enable _WRS_MMU_HAS_MAP_STATE_API.
02l,15aug07,mmi Added _WRS_ARCh_HAS_CPU_PWR_MGMT
02k,25jul07,scm WIND00099103...
02j,13jul07,rlp Added the _WRS_ARCH_HAS_DBG_IPI support.
02i,09jul07,tor revert 02h
02h,02jul07,tor temp macro for vxIpiLib and cpcLib
02g,04may07,zl updated portable library build configuration.
02f,17apr07,kk move VX_MAX_SMP_CPUS from smpI86P.h to here
02e,21feb07,jmg Added include vxPortablLibP.h
02d,11dec06,kk removed references to _WRS_BASE6_SCHEDULER and
_WRS_ARCH_HAS_RESCHEDULE_STACK, no longer needed
02c,06dec06,scm only Pentium4 is SMP safe...
02b,02nov06,scm define _WRS_ARCH_HAS_IDLE_TASK, undef
_WRS_ARCH_HAS_RESCHEDULE_STACK
02a,25sep06,scm added _WRS_ARCH_HAS_NEW_KERNEL_LOCK
01z,30aug06,scm Add definition _WRS_VX_NO_GLOBAL_ERRNO
01y,15jun06,scm Add definition of _WRS_ARCH_HAS_RESCHEDULE_STACK.
01y,30jun06,agf enable optimized version of bLib (CQ:WIND00044910)
01x,28apr05,scm scm add _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
01w,12apr05,kk remove _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
01v,04nov04,scm add _WRS_OSM_INIT for new OSM API...
01u,01sep04,jb Adding _WRS_OBJLIB_SUPPORT_VERIFY_TRAP for objVerify support
01t,14jul04,jb Enable Portable for all functions
01s,17may04,jb Switch to PORTABLE scheduler.
Fix debug register clear on load and go problem
01r,05may04,zmm Fix diab compiler warnings.
01s,13may04,zl fixed _WRS_FRAMEP_FROM_JMP_BUF().
01r,27apr04,cjj Defined workQLib_PORTABLE
01q,27apr04,jmp moved INSTR definition to archI86Common.h. added macros for
getting frame and return PC from a jmp_buf.
01p,03dec03,md changed to use portable scheduler
01o,25nov03,pes Move setting of _BYTE_ORDER macro into archI86Common.h.
01n,14nov03,job Moved some blib stuff to archI86Common.h
01m,13nov03,pes Add include of archI86Common.h
01l,27aug03,to added defines for semLib.
01k,07may03,pes PAL conditional compilation cleanup. Phase 2.
01j,28apr03,pes PAL conditional compilation cleanup.
01i,12nov02,hdn made CR4 initialization only for P5 or later (spr 83992)
01h,29oct02,hdn assigned reserved1 to (FP_CONTEXT *) (spr 70252)
01g,07oct02,hdn added the architecture extension of the TCB
01f,13mar01,sn SPR 73723 - define supported toolchains
01e,04oct01,hdn enclosed ARCH_REGS_INIT macro with _ASMLANGUAGE
01d,21aug01,hdn added PENTIUM4's _CACHE_ALIGN_SIZE, ARCH_REGS_INIT
01c,10aug01,hdn added PENTIUM2/3/4 support
01b,25feb99,hdn added _CACHE_ALIGN_SIZE for Pentium and PentiumPro
01a,07jun93,hdn written based on arch68k.h
*/
#ifndef __INCarchI86h
#define __INCarchI86h
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
#if (CPU==PENTIUM) && defined(_WRS_CONFIG_SMP)
#error "PENTIUM IS NOT SMP SAFE !!!"
#endif
#define _ARCH_SUPPORTS_GCC
/* temporary macro to indicate i86 uses the idle task stack */
#define _WRS_ARCH_HAS_IDLE_TASK
/* temporary macro to indicate i86 uses the type II kernel lock */
#define _WRS_ARCH_HAS_NEW_KERNEL_LOCK
#define _WRS_VX_NO_GLOBAL_ERRNO
/* arch supports new MMU API... */
#define _WRS_MMU_HAS_MAP_STATE_API
/* this cpu family supports power management framework */
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
#if (CPU==_VX_NEHALEM) || defined(_WRS_CONFIG_WRHV_GUEST)
#define _WRS_ARCH_HAS_WIND_PWR_DOWN
#define WIND_PWR_DOWN() windPwrDown()
/* support for device power management */
#if !defined(_WRS_CONFIG_WRHV_GUEST)
#define _WRS_ARCH_HAS_DEV_PWR_MGMT
#endif /* !defined(_WRS_CONFIG_WRHV_GUEST) */
#endif /* (CPU==_VX_NEHALEM) || defined(_WRS_CONFIG_WRHV_GUEST) */
/* arch needs deferred kernel unlock */
#define _WRS_ARCH_DEFERS_KERNEL_UNLOCK
/* arch provides taskMmuCurrentSet() */
#define _WRS_ARCH_HAS_TASK_MMU_CURRENT_SET
/* arch allows semaphore protection for vmStateSet */
#define _WRS_MMU_DEOPTIMIZE_LOCK_CTX_SEM
#undef VX_MAX_SMP_CPUS
#if CPU!=PENTIUM
#if CPU==_VX_ATOM
#define VX_MAX_SMP_CPUS 8 /* maximum processors in SMP configuration */
#define VX_MAX_SMP_CPU_SHIFT 3 /* allow workQ to calculate with Max CPUs */
#elif CPU==PENTIUM4 || CPU==_VX_CORE
#define VX_MAX_SMP_CPUS 16 /* maximum processors in SMP configuration */
#define VX_MAX_SMP_CPU_SHIFT 4 /* allow workQ to calculate with Max CPUs */
#else
#define VX_MAX_SMP_CPUS 32 /* maximum processors in SMP configuration */
#define VX_MAX_SMP_CPU_SHIFT 5 /* allow workQ to calculate with Max CPUs */
#endif /* CPU==_VX_ATOM */
#endif /* CPU!=PENTIUM */
#define _DYNAMIC_BUS_SIZING FALSE /* required alignment for swap */
/* required stack alignment for sse and sse2 instructions is 16 bytes */
#define _STACK_ALIGN_SIZE 16
/* allocated objects require an 8 byte aligment */
#define _ALLOC_ALIGN_SIZE 8
/*
* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
* This is used for both statically and dynamically allocated objects.
*
* NOTE:
*
* For the INTEL architecture VxWorks objects must be aligned to a 64-bit
* boundary for ILP32 and a 128-bit boundary for LP64. This is to allow
* the objVerifiedSafe() routine to be implemented using an atomic CAS of
* the 'safe' count and 'magic' value in an object handle.
*/
#define VX_OBJ_ALIGN_SIZE 8
#if (CPU==PENTIUM)
#define _CACHE_ALIGN_SIZE 32
#else
#define _CACHE_ALIGN_SIZE 64
#endif /* CPU==PENTIUM */
#ifdef _ASMLANGUAGE
/*
* system startup macros used by sysInit(sysALib.s) and romInit(romInnit.s).
* - no function calls to outside of BSP is allowed.
* - no references to the data segment is allowed.
* the CR4 is introduced in the Pentium processor.
*/
#define ARCH_REGS_INIT \
xorl %eax, %eax; /* zero EAX */ \
movl %cr0, %edx; /* get CR0 */ \
andl $0x7ffafff1, %edx; /* clear PG, AM, WP, TS, EM, MP */ \
movl %edx, %cr0; /* set CR0 */ \
\
pushl %eax; /* initialize EFLAGS */ \
popfl;
#define ARCH_CR4_INIT \
xorl %eax, %eax; /* zero EAX */ \
movl %eax, %cr4; /* initialize CR4 */
#else
/* architecture extension of the TCB (pTcb->reserved2) */
typedef struct x86Ext /* architecture specific TCB extension */
{
unsigned int reserved0; /* (DS_CONFIG *) */
unsigned int reserved1; /* (FP_CONTEXT *) for FPU exception */
unsigned int reserved2;
unsigned int reserved3;
unsigned int reserved4;
unsigned int reserved5;
unsigned int reserved6;
unsigned int reserved7;
} X86_EXT;
/* no function declarations for makeSymTlb/symTbl.c */
/* macros for getting frame and return PC from a jmp_buf */
#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_fp)
#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
#endif /* _ASMLANGUAGE */
/* PAL additions */
/* architecture-specific overrides for fppSave and fppRestore in fppLib.c */
#define FPP_SAVE(p) (*_func_fppSaveRtn)(p)
#define FPP_RESTORE(p) (*_func_fppRestoreRtn)(p)
/* from h/usb/target/usbIsaLib.h */
/* DMA controller selection */
#define _WRS_DMA_I8237
/* trigger signed IO arguments in sysLib.h */
#define _WRS_SIGNED_IO_ARGS
#define _WRS_SYS_IO
/* override _WRS_SR_SIZE in taskArchLib.h */
#define _WRS_SR_SIZE UINT
/*
* trigger definition of portWorkQAdd1 in trgLib.c and
* rBuffLib.c
*/
#define _WRS_PORT_WORK_Q_ADD1
/* used in cacheLib.c:cacheFuncsSet() */
#define _WRS_EXTERN_WRITEBACK
/* used in fppLib.c to align FP_CONTEXT */
/* dummy context must be in data section for now */
#define _WRS_ALIGN_FP_CONTEXT
#define _WRS_FPP_DUMMY_CONTEXT \
_WRS_DATA_ALIGN_BYTES(_CACHE_ALIGN_SIZE) fppDummyContext = {{{0}}}
/* architecture-specific overrides for fppSave and fppRestore in dbgLib.c */
#define _WRS_SHOW_SSE_REGS
#define FPP_DBG_SAVE(p) (*_func_fppSaveRtn)(p)
#define FPP_DBG_RESTORE(p) (*_func_fppRestoreRtn)(p)
/* from loadElfLib.c */
#define _WRS_USE_ELF_LOAD_FORMAT
/* from xdr_float.c */
#define FLOAT_NORM
/* from vmShow.c */
#define _WRS_SHOW_WBACK_STATE
#define _WRS_SHOW_GLOBAL_STATE
/* from taskShow.c */
#define _WRS_SHOW_SSE_REGS
/* from rBuffLib.c */
#define _WRS_PORT_WORK_Q_ADD1
/* from wdbFpLib.c */
#define _WRS_ALIGN_REG_SET
/* from schedLib.c */
#define _WRS_ENABLE_IDLE_INTS {intUnlock (-1);}
/* from sysOsmLib.c */
#define _WRS_OSM_INIT
/* Interrupt stack protection, used in usrDepend.c and usrKernelStack.c */
#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
/* if OSM support not available for stack protection,
* * then support can not be available for interrupt
* * stack protection.
* */
#if !defined(_WRS_OSM_INIT)
#undef _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
#endif
#ifdef __cplusplus
}
#endif
#include <arch/i86/archI86Common.h>
/* end of PAL additions */
#endif /* __INCarchI86h */
vxworks-6.9/target/h/arch/i86/archI86Common.h
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/* archI86Common.h - common I86 architecture specific header */
/*
* Copyright (c) 2003-2004, 2006-2007, 2009, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01l,22mar12,jpb Updated for POSIX namespace isolation conformance (part of
defect Defect WIND000307800).
01k,15dec09,scm remove SYSCALL64 var...
01j,10dec09,scm create 64bit syscall constants...
01i,04may07,zl updated portable library build configuration.
01h,02feb06,mil Updated for POSIX namespace conformance.
01g,13may04,zl enabled user trcLib support.
01f,27apr04,jmp added support for portable trcLib. moved INSTR definition
form archI86.h.
01e,13apr04,zmm Add coprocessor support for Pentium.
01d,25nov03,pes Move setting of _BYTE_ORDER macro into archI86Common.h
01c,17nov03,jb Adding defines for syscalls
01b,12nov03,job Moved some blib stuff from archI86.h
01a,11nov03,pes written.
*/
#ifndef __INCarchI86Commonh
#define __INCarchI86Commonh
#ifdef __cplusplus
extern "C" {
#endif
#define _BYTE_ORDER _LITTLE_ENDIAN
#ifndef _ASMLANGUAGE
typedef unsigned char _Vx_INSTR; /* char instructions */
#endif /* !_ASMLANGUAGE */
#if !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE) && \
!defined(_POSIX_AEP_RT_CONTROLLER_C_SOURCE)
/* Common syscall defines */
#define SYSCALL_SEGMENT 8
#define SYSCALL_GATE_OFFSET 0x43 /* (SYSCALL_SEGMENT * sizeof(GDT) | (DPL3 > 13) ) */
/* from bLib.c */
#define _WRS_BLIB_ALIGNMENT 1 /* 2 byte alignment mask */
#define _WRS_PAL_COPROC_LIB /* enable coprocessor abstraction */
#define _WRS_TRC_ARGS_COUNT 5 /* number of arguments to print in */
/* stack trace */
#ifndef _ASMLANGUAGE
typedef _Vx_INSTR INSTR;
#endif /* !_ASMLANGUAGE */
#endif /* !_POSIX_xxx_SOURCE */
#ifdef __cplusplus
}
#endif
#endif /* __INCarchI86Commonh */
vxworks-6.9/target/h/arch/i86/asmI86.h
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/* asmI86.h - i80x86 assembler definitions header file */
/*
* Copyright (c) 1992,1993.1998,2001,2003,2006,2008
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01o,26mar08,dbt Added FUNC_BEGIN & FUNC_END macros (Defect WIND00066731)
01n,21jul06,scm Move SMP macros to private header.
01m,13jul06,scm correct for UNI mode RTP/OSM support...
01l,07jul06,scm update macros for smp/uni...
01k,28jun06,scm SMP GDT support macros added.
01j,06jun06,scm Add SMP support.
01i,17nov05,zmm Use .type directive to declare assembly language symbols that
weren't typed properly by GNU assembler. SPR 114490.
01h,04may04,dbt Added ARG8-12 and SP_ARG8-12.
01g,17nov03,jb Adding additional ARG defines
01f,01nov01,hdn added ARG8 and SP_ARG8
01e,01oct01,pad Turn off the underscore prepending to assembly routines.
01d,14aug01,hdn imported FUNC/FUNC_LABEL GTEXT/GDATA macros from T31 ver 01i
01c,28aug98,hdn added INT_CONNECT_CODE29 for intEnt().
01b,07jun93,hdn added support for c++
01a,28feb92,hdn written based on TRON, 68k version.
*/
#ifndef __INCasmI86h
#define __INCasmI86h
/************************************************************/
/*
* The following definitions are used for symbol name compatibility.
*
* When #if 1, sources are assembled assuming the compiler
* you are using does not generate global symbols prefixed by "_".
* (e.g. elf/dwarf)
*
* When #if 0, sources are assembled assuming the compiler
* you are using generates global symbols prefixed by "_".
* (e.g. coff/stabs)
*/
#if TRUE
#define FUNC(sym) sym
#define FUNC_LABEL(sym) sym:
#else
#define FUNC(sym) _##sym
#define FUNC_LABEL(sym) _##sym:
#endif
#define VAR(sym) FUNC(sym)
/*
* These macros are used to declare assembly language symbols that need
* to be typed properly(func or data) to be visible to the OMF tool.
* So that the build tool could mark them as an entry point to be linked
* correctly. This is an elfism. Use #if 0 for a.out.
*/
#if TRUE
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@function
#define GDATA(sym) FUNC(sym) ; .type FUNC(sym),@object
#else
#define GTEXT(sym) FUNC(sym)
#define GDATA(sym) FUNC(sym)
#endif
/* Introduced to abstract assembler idiosyncrasies */
#define FUNC_BEGIN(func) FUNC_LABEL(func)
#define FUNC_END(func) .size FUNC(func), . - FUNC(func)
/************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/* fp offsets to arguments */
#define ARG1 8
#define ARG1W 10
#define ARG2 12
#define ARG2W 14
#define ARG3 16
#define ARG3W 18
#define ARG4 20
#define ARG5 24
#define ARG6 28
#define ARG7 32
#define ARG8 36
#define ARG9 40
#define ARG10 44
#define ARG11 48
#define ARG12 52
#define DARG1 8 /* double arguments */
#define DARG1L 12
#define DARG2 16
#define DARG2L 20
#define DARG3 24
#define DARG3L 28
#define DARG4 32
#define DARG4L 36
/* sp offsets to arguments */
#define SP_ARG0 0
#define SP_ARG1 4
#define SP_ARG1W 6
#define SP_ARG2 8
#define SP_ARG2W 10
#define SP_ARG3 12
#define SP_ARG3W 14
#define SP_ARG4 16
#define SP_ARG5 20
#define SP_ARG6 24
#define SP_ARG7 28
#define SP_ARG8 32
#define SP_ARG9 36
#define SP_ARG10 40
#define SP_ARG11 44
#define SP_ARG12 48
/* offset to the IRQ number in the intConnectCode[] */
#define INT_CONNECT_CODE29 24 /* from the return address of intEnt() */
#ifdef __cplusplus
}
#endif
#endif /* __INCasmI86h */
vxworks-6.9/target/h/arch/i86/cacheI86Lib.h
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/* cacheI86Lib.h - I80486 cache library header file */
/* Copyright 1984-2002, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01g,29apr10,pad Moved extern C statement after include statements.
01f,04jun04,mil Removed cacheArchXXX routines.
01e,07mar02,hdn added CLFLUSH related macros (spr 73360)
01d,04dec01,hdn added CACHE_TYPE parameter to cachePen4Flush/Clear
01c,23aug01,hdn renamed cache486XXX to cacheI86XXX
added PENTIUM4 support
01b,29may94,hdn deleted I80486 macro.
01a,15jun93,hdn created.
*/
#ifndef __INCcacheI86Libh
#define __INCcacheI86Libh
#include "vxWorks.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CLFLUSH_DEF_BYTES 64 /* def bytes flushed by CLFLUSH */
#define CLFLUSH_MAX_BYTES 255 /* max bytes flushed with CLFLUSH */
#ifndef _ASMLANGUAGE
#if defined(__STDC__) || defined(__cplusplus)
extern void cacheI86Reset (void);
extern void cacheI86Enable (void);
extern void cacheI86Disable (void);
extern void cacheI86Lock (void);
extern void cacheI86Unlock (void);
extern void cacheI86Clear (void);
extern void cacheI86Flush (void);
extern void cachePen4Clear (CACHE_TYPE cache, void * address, size_t bytes);
extern void cachePen4Flush (CACHE_TYPE cache, void * address, size_t bytes);
#else
extern void cacheI86Reset ();
extern void cacheI86Enable ();
extern void cacheI86Disable ();
extern void cacheI86Lock ();
extern void cacheI86Unlock ();
extern void cacheI86Clear ();
extern void cacheI86Flush ();
extern void cachePen4Clear ();
extern void cachePen4Flush ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheI86Libh */
vxworks-6.9/target/h/arch/i86/coprocI86.h
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/* coprocI86.h - coprocessor management library header */
/*
* Copyright 2003-2004, 2010, 2012 Wind River Systems, Inc.
* The right to copy, distribute, modify, or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01c,15may12,jmp CQID: Fix WIND00309977 : Added VX_COPROCS_ALL_TASK
definition.
01b,28apr10,pad Moved extern C statement after include statements.
01a,13apr04,zmm written based on coprocPpc.h 01c.
*/
#ifndef __INCcoprocI86h
#define __INCcoprocI86h
/* includes */
#include "taskLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define VX_FP_TASK VX_COPROC1_TASK
#define VX_COPROCS_ALL_TASK VX_FP_TASK
#ifdef __cplusplus
}
#endif
#endif /* __INCcoprocI86h */
vxworks-6.9/target/h/arch/i86/cpuPwrArchI86Lib.h
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/* cpuPwrArchI86Lib.h - CPU Power Mgmt. H/W library specific header */
/*
* Copyright (c) 2011, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01j,27aug12,c_t WIND00350715 - Add cpuPwrArchTurboUnSet
01i,23aug11,sem WIND00294323, undef P-state and C-State propagation
01h,18aug11,sem WIND00294323, fix default P-state values
01g,02aug11,scm WIND00255355, allow for propagation of CPU C-States...
01f,22jul11,scm WIND00255355, allow for propagation of CPU[0] P-States...
01e,18jul11,jlv WIND00255352, add cpuPwrArchPStateGetByCpu
01d,06jul11,rdl move common APIs to the common header file
01c,05jul11,scm WIND00255355, adjust inclusion wrapper...
01b,28jun11,scm WIND00255255, add pwr mgmt arch abstraction...
01a,31may11,scm WIND00255355, CPU Power State Device Management...
*/
#ifndef __INCcpuPwrArchI86Libh
#define __INCcpuPwrArchI86Libh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/* allow for duplication of CPU[0] P-States */
#undef ACPI_PWR_CPU_ARCH_PROPAGATE_CPU_PERF_0
/* allow for duplication of CPU[0] C-States */
#undef ACPI_PWR_CPU_ARCH_PROPAGATE_CPU_C_STATE
/* Power Management support definitions */
#define PM_CPUID_KEY 0x06
#define MSR_IA32_MPERF 0x00E7
#define MSR_IA32_APERF 0x00E8
#define MSR_IA32_PERF_STAT 0x0198
#define MSR_IA32_PERF_CTL 0x0199
#define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_IA32_ENERGY_PERF_BIAS 0x01B0
#define PM_EAX_MSK 0x00000077
#define PM_EBX_MSK 0x0000000F
#define PM_ECX_MSK 0x00000009
#define PM_DTS 0x00000001
#define PM_TBT 0x00000002
#define PM_ARAT 0x00000004
#define PM_PLN 0x00000010
#define PM_ECMD 0x00000020
#define PM_PTM 0x00000040
#define PM_HCFC 0x00000001
#define PM_OPPO 0x00000040
#define PM_PEB 0x00000004
#define PM_PEBH_MSK1 0x0000000F
#define PM_PEBH_MSK2 0xFFFFFFF0
#define TM_DISENGAGE_BIT 0x00000001
#define TM_DISENGAGE_MSK 0xFFFFFFFE
#define TM_EIST_TRG_MSK 0x0000ffff
#ifdef _WRS_CONFIG_LP64
#define cpuPwrArchPMSup1_Offset 0x70
#define cpuPwrArchPMSup2_Offset 0x74
#define cpuPwrArchPMIntThrsh_Offset 0x78
#else
#define cpuPwrArchPMSup1_Offset 0x50
#define cpuPwrArchPMSup2_Offset 0x54
#define cpuPwrArchPMIntThrsh_Offset 0x58
#endif /* _WRS_CONFIG_LP64 */
/* Thermal Management support definitions */
#define TM_CPUID_KEY 0x01
#define MSR_THERM2_CTL 0x019D
#define MSR_IA32_CLOCK_MODULATION 0x019A
#define MSR_IA32_THERM_INTERRUPT 0x019B
#define MSR_IA32_THERM_STATUS 0x019C
#define MSR_IA32_PACKAGE_THERM_STATUS 0x01B1
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x01B2
#define TM_ECX_MSK 0x00000180
#define TM_EDX_MSK 0x20400000
#define TM_TM2_TRANS_TRG_MSK 0x0000FFFF
#define TM_TM2_SELECT 0x00010000
#define TM_ENABLE 0x00000008
#define TM_TM2 0x00000100
#define TM_EST 0x00000080
#define TM_TURBO_EN_BIT 0x00000040
#define TM_TURBO_EN_MSK 0xFFFFFFBF
#define TM_TM1 0x20000000
#define TM_ACPI 0x00400000
/* ODCM - On-Demand Clock Modulation */
#define TM_ODCM_RES 0x0000 /* Duty Cycle Reserved */
#define TM_ODCM_06_25 0x0001 /* Extended Duty Cycle 06.25% */
#define TM_ODCM_12_50 0x0002 /* Duty Cycle 12.50% -default */
#define TM_ODCM_18_75 0x0003 /* Extended Duty Cycle 18.75% */
#define TM_ODCM_25_00 0x0004 /* Duty Cycle 25.00% */
#define TM_ODCM_31_25 0x0005 /* Extended Duty Cycle 31.25% */
#define TM_ODCM_37_50 0x0006 /* Duty Cycle 37.50% */
#define TM_ODCM_43_75 0x0007 /* Extended Duty Cycle 43.75% */
#define TM_ODCM_50_00 0x0008 /* Duty Cycle 50.00% */
#define TM_ODCM_56_25 0x0009 /* Extended Duty Cycle 56.25% */
#define TM_ODCM_63_50 0x000A /* Duty Cycle 63.50% */
#define TM_ODCM_69_75 0x000B /* Extended Duty Cycle 69.75% */
#define TM_ODCM_75_00 0x000C /* Duty Cycle 75.00% */
#define TM_ODCM_81_25 0x000D /* Extended Duty Cycle 81.25% */
#define TM_ODCM_87_50 0x000E /* Duty Cycle 87.50% */
#define TM_ODCM_93_75 0x000F /* Extended Duty Cycle 93.75% */
#define TM_ODCM_ENABLE 0x00000010
#define TM_ODCM_ENABLE_MSK 0xFFFFFFEF
#define TM_ODCM_MSK 0xFFFFFFF1
#define TM_ODCM_EXT_MSK 0xFFFFFFF0
#define TM_ODCM_DC_MSK1 0x0000000E
#define TM_ODCM_DC_MSK2 0xFFFFFFF1
#define TM_ODCM_DC_EXT_MSK1 0x0000000F
#define TM_ODCM_DC_EXT_MSK2 0xFFFFFFF0
/* IA32_THERM_STATUS Register */
#define TM_STATUS_REG_MSK 0xF87F0FFF
#define TM_STAT_READ_VALID 0x80000000
#define TM_STAT_RES_CELS_MSK 0x71000000
#define TM_STAT_RES_CELS_SHFT 0x19
#define TM_STAT_DIG_READ_MSK 0x007F0000
#define TM_STAT_DIG_READ_SHFT 0x10
#define TM_STAT_PLN_LOG 0x00000800
#define TM_STAT_PLN_LOG_MSK 0xFFFFF7FF
#define TM_STAT_PLN_STAT 0x00000400
#define TM_STAT_THRSH2_LOG 0x00000200
#define TM_STAT_THRSH2_LOG_MSK 0xFFFFFDFF
#define TM_STAT_THRSH2_STAT 0x00000100
#define TM_STAT_THRSH1_LOG 0x00000080
#define TM_STAT_THRSH1_LOG_MSK 0xFFFFFF7F
#define TM_STAT_THRSH1_STAT 0x00000040
#define TM_STAT_CTEMP_LOG 0x00000020
#define TM_STAT_CTEMP_LOG_MSK 0xFFFFFFDF
#define TM_STAT_CTEMP_STAT 0x00000010
#define TM_STAT_PF_LOG 0x00000008
#define TM_STAT_PF_LOG_MSK 0xFFFFFFF7
#define TM_STAT_PF_STAT 0x00000004
#define TM_STATUS_LOG 0x00000002
#define TM_STATUS_LOG_MSK 0xFFFFFFFD
#define TM_STATUS 0x00000001
/* IA32_THERM_INTERRUPT Register */
#define TM_INTERRUPT_REG_MSK 0x01FFFF1F
#define TM_INT_PLN_EN 0x01000000
#define TM_INT_PLN_EN_MSK 0xFEFFFFFF
#define TM_INT_THRSH2_EN 0x00800000
#define TM_INT_THRSH2_EN_MSK 0xFF7FFFFF
#define TM_INT_THRSH2_VAL_MSK1 0x007F0000
#define TM_INT_THRSH2_VAL_MSK2 0xFF80FFFF
#define TM_INT_THRSH2_VAL_SHFT 0x10
#define TM_INT_THRSH1_EN 0x00008000
#define TM_INT_THRSH1_EN_MSK 0xFFFF7FFF
#define TM_INT_THRSH1_VAL_MSK1 0x00007F00
#define TM_INT_THRSH1_VAL_MSK2 0xFFFF80FF
#define TM_INT_THRSH1_VAL_SHFT 0x08
#define TM_INT_OH_EN 0x00000010
#define TM_INT_OH_EN_MSK 0xFFFFFFEF
#define TM_INT_FORCEPR_EN 0x00000008
#define TM_INT_FORCEPR_EN_MSK 0xFFFFFFF7
#define TM_INT_PROCHOT_EN 0x00000004
#define TM_INT_PROCHOT_EN_MSK 0xFFFFFFFB
#define TM_INT_LTEMP_EN 0x00000002
#define TM_INT_LTEMP_EN_MSK 0xFFFFFFFD
#define TM_INT_HTEMP_EN 0x00000001
#define TM_INT_HTEMP_EN_MSK 0xFFFFFFFE
#ifdef _WRS_CONFIG_LP64
#define cpuPwrArchTMSup1_Offset 0x7C
#define cpuPwrArchTMSup2_Offset 0x80
#else
#define cpuPwrArchTMSup1_Offset 0x5C
#define cpuPwrArchTMSup2_Offset 0x60
#endif /* _WRS_CONFIG_LP64 */
/* thermal zone cooling policy */
#define CPU_PWR_ARCH_COOLING_NONE 0 /* let things cook until hardware limits */
#define CPU_PWR_ARCH_COOLING_ACTIVE 1 /* use fans etc */
#define CPU_PWR_ARCH_COOLING_PASSIVE 2 /* throttle cpu and device utilization */
#ifndef _ASMLANGUAGE
#include <base/b_cpuset_t.h>
#if defined (ACPI_PWR_CPU_ARCH_PROPAGATE_CPU_PERF_0)
/* default Performance options when table missing (based on Emerson) */
#define CPU_PWR_ARCH_DOMAIN_ID 0x00
#define CPU_PWR_ARCH_COOR_TYPE 0xFC
#define CPU_PWR_ARCH_NUM_CPUS_IN_DOMAIN 0x01
#define CPU_PWR_ARCH_NUM_PERF 13
#define CPU_PWR_ARCH_NUM_PERF_NOT_SUP 0
#define CPU_PWR_ARCH_NUM_P_STATES CPU_PWR_ARCH_NUM_PERF
#define CPU_PWR_ARCH_PERF_CONTROL 0x00000199
#define CPU_PWR_ARCH_PERF_STATUS 0x00000198
#define CPU_PWR_ARCH_PERF_DFLT_1_CORE_FREQ 2667
#define CPU_PWR_ARCH_PERF_DFLT_1_POWER 25000
#define CPU_PWR_ARCH_PERF_DFLT_1_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_1_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_1_CTRL_REG_VAL 0x0015
#define CPU_PWR_ARCH_PERF_DFLT_1_STAT_REG_VAL 0x0015
#define CPU_PWR_ARCH_PERF_DFLT_2_CORE_FREQ 2666
#define CPU_PWR_ARCH_PERF_DFLT_2_POWER 25000
#define CPU_PWR_ARCH_PERF_DFLT_2_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_2_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_2_CTRL_REG_VAL 0x0014
#define CPU_PWR_ARCH_PERF_DFLT_2_STAT_REG_VAL 0x0014
#define CPU_PWR_ARCH_PERF_DFLT_3_CORE_FREQ 2533
#define CPU_PWR_ARCH_PERF_DFLT_3_POWER 23465
#define CPU_PWR_ARCH_PERF_DFLT_3_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_3_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_3_CTRL_REG_VAL 0x0013
#define CPU_PWR_ARCH_PERF_DFLT_3_STAT_REG_VAL 0x0013
#define CPU_PWR_ARCH_PERF_DFLT_4_CORE_FREQ 2399
#define CPU_PWR_ARCH_PERF_DFLT_4_POWER 21982
#define CPU_PWR_ARCH_PERF_DFLT_4_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_4_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_4_CTRL_REG_VAL 0x0012
#define CPU_PWR_ARCH_PERF_DFLT_4_STAT_REG_VAL 0x0012
#define CPU_PWR_ARCH_PERF_DFLT_5_CORE_FREQ 2266
#define CPU_PWR_ARCH_PERF_DFLT_5_POWER 20527
#define CPU_PWR_ARCH_PERF_DFLT_5_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_5_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_5_CTRL_REG_VAL 0x0011
#define CPU_PWR_ARCH_PERF_DFLT_5_STAT_REG_VAL 0x0011
#define CPU_PWR_ARCH_PERF_DFLT_6_CORE_FREQ 2133
#define CPU_PWR_ARCH_PERF_DFLT_6_POWER 19080
#define CPU_PWR_ARCH_PERF_DFLT_6_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_6_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_6_CTRL_REG_VAL 0x0010
#define CPU_PWR_ARCH_PERF_DFLT_6_STAT_REG_VAL 0x0010
#define CPU_PWR_ARCH_PERF_DFLT_7_CORE_FREQ 1999
#define CPU_PWR_ARCH_PERF_DFLT_7_POWER 17681
#define CPU_PWR_ARCH_PERF_DFLT_7_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_7_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_7_CTRL_REG_VAL 0x000F
#define CPU_PWR_ARCH_PERF_DFLT_7_STAT_REG_VAL 0x000F
#define CPU_PWR_ARCH_PERF_DFLT_8_CORE_FREQ 1866
#define CPU_PWR_ARCH_PERF_DFLT_8_POWER 16310
#define CPU_PWR_ARCH_PERF_DFLT_8_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_8_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_8_CTRL_REG_VAL 0x000E
#define CPU_PWR_ARCH_PERF_DFLT_8_STAT_REG_VAL 0x000E
#define CPU_PWR_ARCH_PERF_DFLT_9_CORE_FREQ 1733
#define CPU_PWR_ARCH_PERF_DFLT_9_POWER 14966
#define CPU_PWR_ARCH_PERF_DFLT_9_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_9_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_9_CTRL_REG_VAL 0x000D
#define CPU_PWR_ARCH_PERF_DFLT_9_STAT_REG_VAL 0x000D
#define CPU_PWR_ARCH_PERF_DFLT_10_CORE_FREQ 1599
#define CPU_PWR_ARCH_PERF_DFLT_10_POWER 13665
#define CPU_PWR_ARCH_PERF_DFLT_10_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_10_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_10_CTRL_REG_VAL 0x000C
#define CPU_PWR_ARCH_PERF_DFLT_10_STAT_REG_VAL 0x000C
#define CPU_PWR_ARCH_PERF_DFLT_11_CORE_FREQ 1466
#define CPU_PWR_ARCH_PERF_DFLT_11_POWER 12375
#define CPU_PWR_ARCH_PERF_DFLT_11_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_11_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_11_CTRL_REG_VAL 0x000B
#define CPU_PWR_ARCH_PERF_DFLT_11_STAT_REG_VAL 0x000B
#define CPU_PWR_ARCH_PERF_DFLT_12_CORE_FREQ 1333
#define CPU_PWR_ARCH_PERF_DFLT_12_POWER 11112
#define CPU_PWR_ARCH_PERF_DFLT_12_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_12_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_12_CTRL_REG_VAL 0x000A
#define CPU_PWR_ARCH_PERF_DFLT_12_STAT_REG_VAL 0x000A
#define CPU_PWR_ARCH_PERF_DFLT_13_CORE_FREQ 1199
#define CPU_PWR_ARCH_PERF_DFLT_13_POWER 9877
#define CPU_PWR_ARCH_PERF_DFLT_13_TRANSITION 10
#define CPU_PWR_ARCH_PERF_DFLT_13_BUS_MASTER 10
#define CPU_PWR_ARCH_PERF_DFLT_13_CTRL_REG_VAL 0x0009
#define CPU_PWR_ARCH_PERF_DFLT_13_STAT_REG_VAL 0x0009
#endif /* ACPI_PWR_CPU_ARCH_PROPAGATE_CPU_PERF_0 */
#if defined (ACPI_PWR_CPU_ARCH_PROPAGATE_CPU_C_STATE)
/* default C-State options when table missing (based on Emerson) */
#define CPU_PWR_ARCH_C_STATE_DFLT_COUNT 0x3
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_1_ADDRESS 0x00000000
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_1_TYPE 0x01
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_1_LATENCY 0x03
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_1_POWER 0x3E8
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_2_ADDRESS 0x00000414
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_2_TYPE 0x02
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_2_LATENCY 0xCD
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_2_POWER 0x1F4
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_3_ADDRESS 0x00000415
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_3_TYPE 0x03
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_3_LATENCY 0xF5
#define CPU_PWR_ARCH_C_STATE_SUB_DFLT_3_POWER 0x15E
#endif /* ACPI_PWR_CPU_ARCH_PROPAGATE_CPU_C_STATE */
/*
* This structure defines an HPET descriptor table entries. See section
* 3.2.4 in the IA-PC HPET Specification for detailsi.
*/
typedef struct cpuPwrArchHpetStruct
{
UINT32 Id; /* Hardware Id of Event Timer Block */
UINT64 Address; /* Address of Event Timer Block */
UINT8 AddrSpaceId; /* 0 = System memory, 1 = System I/O */
UINT8 Sequence; /* HPET sequence number */
UINT16 MinimumTick; /* Main counter min tick, periodic mode */
UINT8 Flags; /* attribute specific */
UINT8 pad_1; /* padding for alignment */
UINT16 pad_2;
} CPU_PWR_ARCH_HPET;
/*
* This structure represents a defined thermal zone.
*/
typedef struct cpuPwrArchThermalZoneStruct
{
void *handle; /* HANDLE */
void *context; /* THERMAL_ZONE [0..n-1] */
UINT32 DomainId; /* domain number */
UINT32 activeCoolingThresh; /* active cooling threshold (degK/10) */
UINT32 criticalTrip; /* hardware shutdown trip (degK/10) */
UINT32 hotTemp; /* software shutdown trip (degK/10) */
UINT32 passiveTrip; /* software passive cool trip (degK/10) */
UINT32 currentTemp; /* current zone temperature (degK/10) */
UINT32 currentAccuracy; /* see ACPI spec 11.4.7 (_NTT) */
UINT32 coolingPolicy; /* thermal zone cooling policy */
} CPU_PWR_ARCH_THERMAL_ZONE;
/*
* This structure defines the supported performance states.
*/
typedef struct cpuPwrArchPerfStruct
{
UINT32 coreFreq; /* core frequency (MHZ) */
UINT32 power; /* max power consumption (mw) */
UINT32 transitionLatency; /* us */
UINT32 busMasterLatency; /* us */
UINT32 control; /* performance control register value */
UINT32 status; /* expected control status value */
} CPU_PWR_ARCH_PERFORMANCE;
/*
* This structure defines the supported throttling states.
*/
typedef struct cpuPwrArchThrottleStruct
{
UINT32 percentage; /* percentage of clock rate (1%..100%) */
UINT32 power; /* power consumption (mw) */
UINT32 transitionLatency; /* us */
UINT32 control; /* throttle control register value */
UINT32 status; /* expected control status value */
} CPU_PWR_ARCH_THROTTLE;
/*
* This structure defines declare the supported processor power
* states (C States).
*/
typedef struct cpuPwrArchCStateSubStruct
{
UINT64 address; /* address of reg to read to set C State */
UINT32 type; /* C State type (1=C1, 2=C2 3=C3, etc.) */
UINT32 latency; /* worst case latency, in microseconds */
UINT32 power; /* average power consumption milliwatts */
} CPU_PWR_ARCH_C_STATE_SUB;
typedef struct cpuPwrArchCStateStruct
{
UINT32 count; /* number of C State sub-packages */
CPU_PWR_ARCH_C_STATE_SUB *pCStateSub; /* pointer to C State record */
} CPU_PWR_ARCH_C_STATE;
/*
* This structure holds information reported by Power and Thermal
* Management for one CPU.
*/
typedef struct cpuPwrArchStruct
{
void *handle; /* HANDLE */
void *context; /* CPU [0..n-1] */
UINT32 procId; /* not necessarilly 0..n-1 */
UINT32 coordType; /* see P-state dependency definitions */
UINT32 cpuPState; /* current cpu P-state (0..numPerfSup)*/
UINT32 DomainId; /* dependency domain number (see _PSD) */
UINT32 numCpusInDomain; /* number of CPUs in domain */
UINT32 numThrottle; /* number of throttle states defined */
UINT32 numThrottleNotSup; /* number of T-states not supported */
UINT32 numPerf; /* number of performance states defined */
UINT32 numPerfNotSup; /* number of P-states not supported */
UINT32 numPstates; /* number of supported P-states */
UINT32 *pThControl; /* throttle control register address */
UINT32 *pThStatus; /* throttle status address */
UINT32 *pPerfControl; /* peformance control register address */
UINT32 *pPerfStatus; /* performance status address */
CPU_PWR_ARCH_THROTTLE *pThrottle; /* pointer to throttle record */
CPU_PWR_ARCH_PERFORMANCE *pPerf; /* pointer to performance record */
char nodeName[5]; /* CPU name */
char fill[3];
UINT32 cpuPwrArchPMSup1; /* Power Management capabilities */
UINT32 cpuPwrArchPMSup2; /* Power Management capabilities */
UINT32 cpuPwrArchPMIntThrsh; /* Power Management capabilities */
UINT32 cpuPwrArchTMSup1; /* Thermal Management capabilities */
UINT32 cpuPwrArchTMSup2; /* Thermal Management capabilities */
CPU_PWR_ARCH_C_STATE cpuCState; /* optional variable C State record */
cpuset_t pStates; /* bit map of supported P States for cpu */
cpuset_t tStates; /* bit map of supported T States for cpu */
cpuset_t cStates; /* bit map of supported C States for cpu */
} CPU_PWR_ARCH;
/*
* This structure represents information that describes the target board.
*/
typedef struct cpuPwrArchBoardStruct
{
UINT32 cpuPwrArchNumCpus;
CPU_PWR_ARCH *pCpuPwrArch;
UINT32 cpuPwrArchValHpet;
CPU_PWR_ARCH_HPET *pHpet;
UINT32 cpuPwrArchNumThermZones;
CPU_PWR_ARCH_THERMAL_ZONE *pThermalZone;
} CPU_PWR_ARCH_BOARD_INFO;
IMPORT CPU_PWR_ARCH_BOARD_INFO sysCpuPwrArchBoardInfo, *pSysCpuPwrArchBoardInfo;
/* function declarations */
#if defined (__STDC__) || defined (__cplusplus)
IMPORT CPU_PWR_ARCH * cpuPwrArchGetCpuInfo (int cpuIndex);
IMPORT cpuset_t cpuPwrArchPStates (int cpuIndex);
IMPORT cpuset_t cpuPwrArchTStates (int cpuIndex);
IMPORT cpuset_t cpuPwrArchCStates (int cpuIndex);
IMPORT UINT32 cpuPwrArchPStateGetByCpu (int cpuIndex);
IMPORT void cpuPwrArchCStateSet (UINT8 cStateHint);
#if ((CPU_FAMILY==I80X86) && (CPU != PENTIUM))
IMPORT STATUS cpuPwrArchTurboSet (void);
IMPORT STATUS cpuPwrArchTurboUnSet (void);
#endif /* (CPU_FAMILY==I80X86) && (CPU != PENTIUM) */
IMPORT void cpuPwrArchGetCapabilities (CPU_PWR_ARCH *pCpu);
IMPORT STATUS cpuPwrArchShowCapabilities (void);
IMPORT STATUS cpuPwrArchBoardShow (void);
#ifdef _WRS_CONFIG_LP64
IMPORT void cpuPwrArchMperfGet (long *pData);
IMPORT void cpuPwrArchMperfSet (long *pData);
IMPORT void cpuPwrArchAperfGet (long *pData);
IMPORT void cpuPwrArchAperfSet (long *pData);
IMPORT BOOL cpuPwrArchOPP (void);
IMPORT void cpuPwrArchOPPEnable (void);
IMPORT void cpuPwrArchOPPDisable (void);
IMPORT UINT8 cpuPwrArchPEBHGet (void);
IMPORT void cpuPwrArchPEBHSet (UINT8 pebHint);
#else
IMPORT void cpuPwrArchMperfGet (long long int *pData);
IMPORT void cpuPwrArchMperfSet (long long int *pData);
IMPORT void cpuPwrArchAperfGet (long long int *pData);
IMPORT void cpuPwrArchAperfSet (long long int *pData);
#endif /* _WRS_CONFIG_LP64 */
IMPORT BOOL cpuPwrArchODCM (void);
IMPORT void cpuPwrArchODCM_Enable (void);
IMPORT void cpuPwrArchODCM_Disable (void);
IMPORT UINT8 cpuPwrArchODCM_DCGet (void);
IMPORT void cpuPwrArchODCM_DCSet (UINT8 dutyCycle);
IMPORT UINT8 cpuPwrArchODCM_DCExtGet (void);
IMPORT void cpuPwrArchODCM_DCExtSet (UINT8 dutyCycle);
#ifdef _WRS_CONFIG_LP64
IMPORT void cpuPwrArchTM_StatRegGet (long *pData);
IMPORT void cpuPwrArchTM_StatRegSet (long *pData);
#else
IMPORT void cpuPwrArchTM_StatRegGet (long long int *pData);
IMPORT void cpuPwrArchTM_StatRegSet (long long int *pData);
#endif /* _WRS_CONFIG_LP64 */
IMPORT BOOL cpuPwrArchTM_Status (void);
IMPORT BOOL cpuPwrArchTM_StatLog (void);
IMPORT void cpuPwrArchTM_StatLogClr (void);
IMPORT BOOL cpuPwrArchTM_PFEvent (void);
IMPORT BOOL cpuPwrArchTM_PFEventLog (void);
IMPORT void cpuPwrArchTM_PFEventLogClr (void);
IMPORT BOOL cpuPwrArchTM_CTempStat (void);
IMPORT BOOL cpuPwrArchTM_CTempLog (void);
IMPORT void cpuPwrArchTM_CTempLogClr (void);
IMPORT BOOL cpuPwrArchTM_Thrsh1Stat (void);
IMPORT BOOL cpuPwrArchTM_Thrsh1Log (void);
IMPORT void cpuPwrArchTM_Thrsh1LogClr (void);
IMPORT BOOL cpuPwrArchTM_Thrsh2Stat (void);
IMPORT BOOL cpuPwrArchTM_Thrsh2Log (void);
IMPORT void cpuPwrArchTM_Thrsh2LogClr (void);
IMPORT BOOL cpuPwrArchTM_PLNStat (void);
IMPORT BOOL cpuPwrArchTM_PLNLog (void);
IMPORT void cpuPwrArchTM_PLNLogClr (void);
IMPORT UINT8 cpuPwrArchTM_DigReadOut (void);
IMPORT UINT8 cpuPwrArchTM_ResCelsius (void);
IMPORT BOOL cpuPwrArchTM_DigReadOutValid (void);
#ifdef _WRS_CONFIG_LP64
IMPORT void cpuPwrArchTM_pkgStatRegGet (long *pData);
IMPORT void cpuPwrArchTM_pkgStatRegSet (long *pData);
#else
IMPORT void cpuPwrArchTM_pkgStatRegGet (long long int *pData);
IMPORT void cpuPwrArchTM_pkgStatRegSet (long long int *pData);
#endif /* _WRS_CONFIG_LP64 */
IMPORT BOOL cpuPwrArchTM_pkgStatus (void);
IMPORT BOOL cpuPwrArchTM_pkgStatLog (void);
IMPORT void cpuPwrArchTM_pkgStatLogClr (void);
IMPORT BOOL cpuPwrArchTM_pkgPFEvent (void);
IMPORT BOOL cpuPwrArchTM_pkgPFEventLog (void);
IMPORT void cpuPwrArchTM_pkgPFEventLogClr (void);
IMPORT BOOL cpuPwrArchTM_pkgCTempStat (void);
IMPORT BOOL cpuPwrArchTM_pkgCTempLog (void);
IMPORT void cpuPwrArchTM_pkgCTempLogClr (void);
IMPORT BOOL cpuPwrArchTM_pkgThrsh1Stat (void);
IMPORT BOOL cpuPwrArchTM_pkgThrsh1Log (void);
IMPORT void cpuPwrArchTM_pkgThrsh1LogClr (void);
IMPORT BOOL cpuPwrArchTM_pkgThrsh2Stat (void);
IMPORT BOOL cpuPwrArchTM_pkgThrsh2Log (void);
IMPORT void cpuPwrArchTM_pkgThrsh2LogClr (void);
IMPORT BOOL cpuPwrArchTM_pkgPLNStat (void);
IMPORT BOOL cpuPwrArchTM_pkgPLNLog (void);
IMPORT void cpuPwrArchTM_pkgPLNLogClr (void);
IMPORT UINT8 cpuPwrArchTM_pkgDigReadOut (void);
#ifdef _WRS_CONFIG_LP64
IMPORT void cpuPwrArchTM_intRegGet (long *pData);
IMPORT void cpuPwrArchTM_intRegSet (long *pData);
#else
IMPORT void cpuPwrArchTM_intRegGet (long long int *pData);
IMPORT void cpuPwrArchTM_intRegSet (long long int *pData);
#endif /* _WRS_CONFIG_LP64 */
IMPORT BOOL cpuPwrArchTM_intHT (void);
IMPORT void cpuPwrArchTM_intHTEn (void);
IMPORT void cpuPwrArchTM_intHTDis (void);
IMPORT BOOL cpuPwrArchTM_intLT (void);
IMPORT void cpuPwrArchTM_intLTEn (void);
IMPORT void cpuPwrArchTM_intLTDis (void);
IMPORT BOOL cpuPwrArchTM_intPROCHOT (void);
IMPORT void cpuPwrArchTM_intPROCHOTEn (void);
IMPORT void cpuPwrArchTM_intPROCHOTDis (void);
IMPORT BOOL cpuPwrArchTM_intFORCEPR (void);
IMPORT void cpuPwrArchTM_intFORCEPREn (void);
IMPORT void cpuPwrArchTM_intFORCEPRDis (void);
IMPORT BOOL cpuPwrArchTM_intOHeat (void);
IMPORT void cpuPwrArchTM_intOHeatEn (void);
IMPORT void cpuPwrArchTM_intOHeatDis (void);
IMPORT UINT8 cpuPwrArchTM_intThrsh1Get (void);
IMPORT void cpuPwrArchTM_intThrsh1Set (UINT8 thrsh1Val);
IMPORT BOOL cpuPwrArchTM_intThrsh1 (void);
IMPORT void cpuPwrArchTM_intThrsh1En (void);
IMPORT void cpuPwrArchTM_intThrsh1Dis (void);
IMPORT UINT8 cpuPwrArchTM_intThrsh2Get (void);
IMPORT void cpuPwrArchTM_intThrsh2Set (UINT8 thrsh2Val);
IMPORT BOOL cpuPwrArchTM_intThrsh2 (void);
IMPORT void cpuPwrArchTM_intThrsh2En (void);
IMPORT void cpuPwrArchTM_intThrsh2Dis (void);
IMPORT BOOL cpuPwrArchTM_intPLN (void);
IMPORT void cpuPwrArchTM_intPLNEn (void);
IMPORT void cpuPwrArchTM_intPLNDis (void);
#ifdef _WRS_CONFIG_LP64
IMPORT void cpuPwrArchTM_pkgIntRegGet (long *pData);
IMPORT void cpuPwrArchTM_pkgIntRegSet (long *pData);
#else
IMPORT void cpuPwrArchTM_pkgIntRegGet (long long int *pData);
IMPORT void cpuPwrArchTM_pkgIntRegSet (long long int *pData);
#endif /* _WRS_CONFIG_LP64 */
IMPORT BOOL cpuPwrArchTM_pkgIntHT (void);
IMPORT void cpuPwrArchTM_pkgIntHTEn (void);
IMPORT void cpuPwrArchTM_pkgIntHTDis (void);
IMPORT BOOL cpuPwrArchTM_pkgIntLT (void);
IMPORT void cpuPwrArchTM_pkgIntLTEn (void);
IMPORT void cpuPwrArchTM_pkgIntLTDis (void);
IMPORT BOOL cpuPwrArchTM_pkgIntPROCHOT (void);
IMPORT void cpuPwrArchTM_pkgIntPROCHOTEn (void);
IMPORT void cpuPwrArchTM_pkgIntPROCHOTDis (void);
IMPORT BOOL cpuPwrArchTM_pkgIntFORCEPR (void);
IMPORT void cpuPwrArchTM_pkgIntFORCEPREn (void);
IMPORT void cpuPwrArchTM_pkgIntFORCEPRDis (void);
IMPORT BOOL cpuPwrArchTM_pkgIntOHeat (void);
IMPORT void cpuPwrArchTM_pkgIntOHeatEn (void);
IMPORT void cpuPwrArchTM_pkgIntOHeatDis (void);
IMPORT UINT8 cpuPwrArchTM_pkgIntThrsh1Get (void);
IMPORT void cpuPwrArchTM_pkgIntThrsh1Set (UINT8 thrsh1Val);
IMPORT BOOL cpuPwrArchTM_pkgIntThrsh1 (void);
IMPORT void cpuPwrArchTM_pkgIntThrsh1En (void);
IMPORT void cpuPwrArchTM_pkgIntThrsh1Dis (void);
IMPORT UINT8 cpuPwrArchTM_pkgIntThrsh2Get (void);
IMPORT void cpuPwrArchTM_pkgIntThrsh2Set (UINT8 thrsh2Val);
IMPORT BOOL cpuPwrArchTM_pkgIntThrsh2 (void);
IMPORT void cpuPwrArchTM_pkgIntThrsh2En (void);
IMPORT void cpuPwrArchTM_pkgIntThrsh2Dis (void);
IMPORT BOOL cpuPwrArchTM_pkgIntPLN (void);
IMPORT void cpuPwrArchTM_pkgIntPLNEn (void);
IMPORT void cpuPwrArchTM_pkgIntPLNDis (void);
IMPORT BOOL cpuPwrArchODCM (void);
IMPORT void cpuPwrArchODCM_Enable (void);
IMPORT void cpuPwrArchODCM_Disable (void);
IMPORT UINT8 cpuPwrArchODCM_DCGet (void);
IMPORT void cpuPwrArchODCM_DCSet (UINT8 dutyCycle);
IMPORT UINT8 cpuPwrArchODCM_DCExtGet (void);
IMPORT void cpuPwrArchODCM_DCExtSet (UINT8 dutyCycle);
#else
IMPORT STATUS cpuPwrArchLibInit ();
IMPORT STATUS cpuPwrArchEnable ();
IMPORT STATUS cpuPwrArchDisable ();
IMPORT CPU_PWR_ARCH * cpuPwrArchGetCpuInfo ();
IMPORT UINT32 cpuPwrArchPStateSet ();
IMPORT UINT32 cpuPwrArchPStateGet ();
IMPORT cpuset_t cpuPwrArchPStates ();
IMPORT cpuset_t cpuPwrArchTStates ();
IMPORT cpuset_t cpuPwrArchCStates ();
IMPORT void vxC1StateSet ();
IMPORT void cpuPwrArchCStateSet ();
#if ((CPU_FAMILY==I80X86) && (CPU != PENTIUM))
IMPORT STATUS cpuPwrArchTurboSet ();
IMPORT STATUS cpuPwrArchTurboUnSet ();
#endif /* (CPU_FAMILY==I80X86) && (CPU != PENTIUM) */
IMPORT void cpuPwrArchGetCapabilities ();
IMPORT STATUS cpuPwrArchShowCapabilities ();
IMPORT STATUS cpuPwrArchBoardShow ();
IMPORT void cpuPwrArchMperfGet ();
IMPORT void cpuPwrArchMperfSet ();
IMPORT void cpuPwrArchAperfGet ();
IMPORT void cpuPwrArchAperfSet ();
#ifdef _WRS_CONFIG_LP64
IMPORT BOOL cpuPwrArchOPP ();
IMPORT void cpuPwrArchOPPEnable ();
IMPORT void cpuPwrArchOPPDisable ();
IMPORT UINT8 cpuPwrArchPEBHGet ();
IMPORT void cpuPwrArchPEBHSet ();
#endif /* _WRS_CONFIG_LP64 */
IMPORT BOOL cpuPwrArchODCM ();
IMPORT void cpuPwrArchODCM_Enable ();
IMPORT void cpuPwrArchODCM_Disable ();
IMPORT UINT8 cpuPwrArchODCM_DCGet ();
IMPORT void cpuPwrArchODCM_DCSet ();
IMPORT UINT8 cpuPwrArchODCM_DCExtGet ();
IMPORT void cpuPwrArchODCM_DCExtSet ();
/* IA32 Thermal Status Register */
IMPORT void cpuPwrArchTM_StatRegGet ();
IMPORT void cpuPwrArchTM_StatRegSet ();
IMPORT BOOL cpuPwrArchTM_Status ();
IMPORT BOOL cpuPwrArchTM_StatLog ();
IMPORT void cpuPwrArchTM_StatLogClr ();
IMPORT BOOL cpuPwrArchTM_PFEvent ();
IMPORT BOOL cpuPwrArchTM_PFEventLog ();
IMPORT void cpuPwrArchTM_PFEventLogClr ();
IMPORT BOOL cpuPwrArchTM_CTempStat ();
IMPORT BOOL cpuPwrArchTM_CTempLog ();
IMPORT void cpuPwrArchTM_CTempLogClr ();
IMPORT BOOL cpuPwrArchTM_Thrsh1Stat ();
IMPORT BOOL cpuPwrArchTM_Thrsh1Log ();
IMPORT void cpuPwrArchTM_Thrsh1LogClr ();
IMPORT BOOL cpuPwrArchTM_Thrsh2Stat ();
IMPORT BOOL cpuPwrArchTM_Thrsh2Log ();
IMPORT void cpuPwrArchTM_Thrsh2LogClr ();
IMPORT BOOL cpuPwrArchTM_PLNStat ();
IMPORT BOOL cpuPwrArchTM_PLNLog ();
IMPORT void cpuPwrArchTM_PLNLogClr ();
IMPORT UINT8 cpuPwrArchTM_DigReadOut ();
IMPORT UINT8 cpuPwrArchTM_ResCelsius ();
IMPORT BOOL cpuPwrArchTM_DigReadOutValid ();
/* IA32 Package Thermal Status Register */
IMPORT void cpuPwrArchTM_pkgStatRegGet ();
IMPORT void cpuPwrArchTM_pkgStatRegSet ();
IMPORT BOOL cpuPwrArchTM_pkgStatus ();
IMPORT BOOL cpuPwrArchTM_pkgStatLog ();
IMPORT void cpuPwrArchTM_pkgStatLogClr ();
IMPORT BOOL cpuPwrArchTM_pkgPFEvent ();
IMPORT BOOL cpuPwrArchTM_pkgPFEventLog ();
IMPORT void cpuPwrArchTM_pkgPFEventLogClr ();
IMPORT BOOL cpuPwrArchTM_pkgCTempStat ();
IMPORT BOOL cpuPwrArchTM_pkgCTempLog ();
IMPORT void cpuPwrArchTM_pkgCTempLogClr ();
IMPORT BOOL cpuPwrArchTM_pkgThrsh1Stat ();
IMPORT BOOL cpuPwrArchTM_pkgThrsh1Log ();
IMPORT void cpuPwrArchTM_pkgThrsh1LogClr ();
IMPORT BOOL cpuPwrArchTM_pkgThrsh2Stat ();
IMPORT BOOL cpuPwrArchTM_pkgThrsh2Log ();
IMPORT void cpuPwrArchTM_pkgThrsh2LogClr ();
IMPORT BOOL cpuPwrArchTM_pkgPLNStat ();
IMPORT BOOL cpuPwrArchTM_pkgPLNLog ();
IMPORT void cpuPwrArchTM_pkgPLNLogClr ();
IMPORT UINT8 cpuPwrArchTM_pkgDigReadOut ();
/* IA32 Thermal Interrupt Register */
IMPORT void cpuPwrArchTM_intRegGet ();
IMPORT void cpuPwrArchTM_intRegSet ();
IMPORT BOOL cpuPwrArchTM_intHT ();
IMPORT void cpuPwrArchTM_intHTEn ();
IMPORT void cpuPwrArchTM_intHTDis ();
IMPORT BOOL cpuPwrArchTM_intLT ();
IMPORT void cpuPwrArchTM_intLTEn ();
IMPORT void cpuPwrArchTM_intLTDis ();
IMPORT BOOL cpuPwrArchTM_intPROCHOT ();
IMPORT void cpuPwrArchTM_intPROCHOTEn ();
IMPORT void cpuPwrArchTM_intPROCHOTtDis ();
IMPORT BOOL cpuPwrArchTM_intFORCEPR ();
IMPORT void cpuPwrArchTM_intFORCEPREn ();
IMPORT void cpuPwrArchTM_intFORCEPRDis ();
IMPORT BOOL cpuPwrArchTM_intOHeat ();
IMPORT void cpuPwrArchTM_intOHeatEn ();
IMPORT void cpuPwrArchTM_intOHeatDis ();
IMPORT UINT8 cpuPwrArchTM_intThrsh1Get ();
IMPORT void cpuPwrArchTM_intThrsh1Set ();
IMPORT BOOL cpuPwrArchTM_intThrsh1 ();
IMPORT void cpuPwrArchTM_intThrsh1En ();
IMPORT void cpuPwrArchTM_intThrsh1Dis ();
IMPORT UINT8 cpuPwrArchTM_intThrsh2Get ();
IMPORT void cpuPwrArchTM_intThrsh2Set ();
IMPORT BOOL cpuPwrArchTM_intThrsh2 ();
IMPORT void cpuPwrArchTM_intThrsh2En ();
IMPORT void cpuPwrArchTM_intThrsh2Dis ();
IMPORT BOOL cpuPwrArchTM_intPLN ();
IMPORT void cpuPwrArchTM_intPLNEn ();
IMPORT void cpuPwrArchTM_intPLNDis ();
/* IA32 Package Thermal Interrupt Register */
IMPORT void cpuPwrArchTM_pkgIntRegGet ();
IMPORT void cpuPwrArchTM_pkgIntRegSet ();
IMPORT BOOL cpuPwrArchTM_pkgIntHT ();
IMPORT void cpuPwrArchTM_pkgIntHTEn ();
IMPORT void cpuPwrArchTM_pkgIntHTDis ();
IMPORT BOOL cpuPwrArchTM_pkgIntLT ();
IMPORT void cpuPwrArchTM_pkgIntLTEn ();
IMPORT void cpuPwrArchTM_pkgIntLTDis ();
IMPORT BOOL cpuPwrArchTM_pkgIntPROCHOT ();
IMPORT void cpuPwrArchTM_pkgIntPROCHOTEn ();
IMPORT void cpuPwrArchTM_pkgIntPROCHOTDis ();
IMPORT BOOL cpuPwrArchTM_pkgIntFORCEPR ();
IMPORT void cpuPwrArchTM_pkgIntFORCEPREn ();
IMPORT void cpuPwrArchTM_pkgIntFORCEPRDis ();
IMPORT BOOL cpuPwrArchTM_pkgIntOHeat ();
IMPORT void cpuPwrArchTM_pkgIntOHeatEn ();
IMPORT void cpuPwrArchTM_pkgIntOHeatDis ();
IMPORT UINT8 cpuPwrArchTM_pkgIntThrsh1Get ();
IMPORT void cpuPwrArchTM_pkgIntThrsh1Set ();
IMPORT BOOL cpuPwrArchTM_pkgIntThrsh1 ();
IMPORT void cpuPwrArchTM_pkgIntThrsh1En ();
IMPORT void cpuPwrArchTM_pkgIntThrsh1Dis ();
IMPORT UINT8 cpuPwrArchTM_pkgIntThrsh2Get ();
IMPORT void cpuPwrArchTM_pkgIntThrsh2Set ();
IMPORT BOOL cpuPwrArchTM_pkgIntThrsh2 ();
IMPORT void cpuPwrArchTM_pkgIntThrsh2En ();
IMPORT void cpuPwrArchTM_pkgIntThrsh2Dis ();
IMPORT BOOL cpuPwrArchTM_pkgIntPLN ();
IMPORT void cpuPwrArchTM_pkgIntPLNEn ();
IMPORT void cpuPwrArchTM_pkgIntPLNDis ();
#endif /* __STDC__ || __cplusplus */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcpuPwrArchI86Libh */
vxworks-6.9/target/h/arch/i86/dbgI86Lib.h
+155
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/* dbgI86Lib.h - header file for arch dependent portion of debugger */
/*
* Copyright (c) 1991,1993,1997-1998,2002-2005,2009-2010,2012,2016
* Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01v,20may16,jmp Imported from vxWorks 7 for WB4 debug support:
Added 8 bytes hardware breakpoint support (US11680).
Added VXDBG_HAS_HW_BP_SUPPORT_CHECK as VxDBG provides support
to dynamically detect if HW BP support is enabled on this
architecture (US39045).
01u,16oct12,scm WIND00376020 - fast system call support...
01t,22oct10,jmp Removed obsolete DSM() macro - Replaced by VXDBG_INSTR_CMP().
01s,29jul10,pad Moved extern C statement after include statements.
01r,19jun09,mze replacing PAD64
01q,20mar09,jmp removed DBG_INST_ALIGN definition (Use the default one).
01p,10feb09,jb Adding 64-bit Support
01p,31mar09,dbt Disable hardware breakpoint support for Hypervisor
Guest OS (CQ:WIND00161733).
01o,16feb05,aeg changed wdbDbgCtxXXX() prototypes (SPR #106381).
01n,14oct04,elg Rename wdbDbgCtxXXX() in wdbCtxXXX().
01m,01sep04,elg Define context load/save for WDB.
01l,19aug04,jb Fix for SPRs 100660, 100729, and 100748
01k,25jun04,elg Undefine WDB_CTX_LOAD() to use standard definition
(SPR #98730).
01j,27apr04,jmp adapted to share trcArchLib between VxSim/i86 and i86 arches.
01i,02mar04,jb Adding StepOverSyscall support
01h,17jul03,c_c Fixed build.
01g,16sep02,pai Updated with commonly used manifest constants.
01f,30may02,hdn added WDB_CTX_LOAD() define (spr 75694)
01e,11mar98,dbt corrected problems introduced by the SENS merge
added Copyright.
01d,13feb98,hdn fixed BRK_DATAxx macros.
01d,30dec97,dbt modified and added some defines for new breakpoint scheme.
01c,29nov93,hdn added a definition EDI - EFLAGS.
01b,27aug93,hdn added support for c++
01a,11sep91,hdn written based on TRON version.
*/
#ifndef __INCI86dbgh
#define __INCI86dbgh
#ifdef _WRS_CONFIG_LP64
#include "arch/i86/x86_64/dbgX86_64Lib.h"
#else
/* includes */
#include "arch/i86/esfI86.h"
#include "arch/i86/regsI86.h"
#include "arch/i86/instrI86.h"
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define BRK_INST (0x00) /* instruction hardware breakpoint */
#define BRK_DATAW1 (0x01) /* data write 1 byte breakpoint */
#define BRK_DATAW2 (0x05) /* data write 2 byte breakpoint */
#define BRK_DATAW4 (0x0d) /* data write 4 byte breakpoint */
#define BRK_DATAW8 (0x09) /* data write 8 byte breakpoint */
#define BRK_DATARW1 (0x03) /* data read-write 1 byte breakpoint */
#define BRK_DATARW2 (0x07) /* data read-write 2 byte breakpoint */
#define BRK_DATARW4 (0x0f) /* data read-write 4 byte breakpoint */
#define BRK_DATARW8 (0x0b) /* data read-write 8 byte breakpoint */
#define DEFAULT_HW_BP (BRK_DATARW1) /* default hardware breakpoint */
#define BRK_HARDWARE (0x10) /* hardware breakpoint bit */
#define BRK_HARDMASK (0x0f) /* hardware breakpoint mask */
#define SAVED_DBGREGS (0x18) /* 6 debug registers */
#define SAVED_REGS (0x38) /* 8 + 6 registers */
#define TRACE_FLAG (0x0100) /* TF in EFLAGS */
#define INT_FLAG (0x0200) /* IF in EFLAGS */
#define DBG_HARDWARE_BP 1 /* hardware breakpoint support */
#define VXDBG_HAS_HW_BP_SUPPORT_CHECK 1
/* VxDBG provides HW BP support detection */
#ifndef _ASMLANGUAGE
#define DBG_BREAK_INST (0xcc) /* int 3 */
#if (CPU != PENTIUM)
#define DBG_SYSCALL_SIZE 2
#define DBG_SYSCALL_INST 0x5a5d340f
#define DBG_SYSCALL_INST_MASK 0xffffffff
#else
#define DBG_SYSCALL_SIZE 7
#define DBG_SYSCALL_INST 0x0000009A
#endif /* (CPU != PENTIUM) */
/* offsets to register fields in type REG_SET */
#define EDI (0)
#define ESI (1)
#define EBP (2)
#define ESP (3)
#define EBX (4)
#define EDX (5)
#define ECX (6)
#define EAX (7)
#define EFLAGS (8)
/* context save/load for WDB */
#define WDB_CTX_SAVE(pRegs) (_wdbCtxSave (pRegs))
#define WDB_CTX_LOAD(pRegs) (_wdbCtxLoad (pRegs))
/* typedefs */
/* aliases for type <ESF0> */
typedef ESF0 BREAK_ESF;
typedef ESF0 TRACE_ESF;
/* hardware breakpoint registers */
typedef struct /* DBG_REGS */
{
unsigned int db0; /* debug register 0 */
unsigned int db1; /* debug register 1 */
unsigned int db2; /* debug register 2 */
unsigned int db3; /* debug register 3 */
unsigned int db6; /* debug register 6 */
unsigned int db7; /* debug register 7 */
} DBG_REGS;
/* function declarations */
extern void _wdbCtxLoad (const REG_SET *);
extern int _wdbCtxSave (const REG_SET *);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* _WRS_CONFIG_LP64 */
#endif /* __INCI86dbgh */
vxworks-6.9/target/h/arch/i86/dbgStrLib.h
+357
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/* dbgStrLib.h - Debug Store mechanism definitions header file */
/* Copyright 2001-2002, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01b,29apr10,pad Moved extern C statement after include statements.
01a,23jul01,hdn written
*/
#ifndef __INCdbgStrLibh
#define __INCdbgStrLibh
#include "arch/i86/regsP7.h"
#ifdef __cplusplus
extern "C" {
#endif
/* DS buffer : BTS/PEBS minimum/default/threshold size */
#define BTS_NBYTES_MIN 0x1000 /* 4KB minimum BTS buffer */
#define BTS_NBYTES_DEF 0x4000 /* 16KB default BTS buffer */
#define BTS_NBYTES_OFF 0x200 /* .5KB (max - threshold) BTS */
#define PEBS_NBYTES_MIN 0x1000 /* 4KB minimum PEBS buffer */
#define PEBS_NBYTES_DEF 0x4000 /* 16KB default PEBS buffer */
#define PEBS_NBYTES_OFF 0x200 /* .5KB (max - threshold) PEBS */
#define PEBS_DEF_RESET -1LL /* default reset counter value */
/* BTS : record bit */
#define BTS_PREDICTED 0x00000010 /* bit4: Branch Predicted */
/* PEBS : events */
#define PEBS_FRONT_END 0x01
#define PEBS_EXECUTION 0x02
#define PEBS_REPLAY 0x03
/* PEBS : metrics (Front End Event) */
#define PEBS_MEMORY_LOADS 0x01
#define PEBS_MEMORY_STORES 0x02
/* PEBS : metrics (Execution Event) */
#define PEBS_PACKED_SP 0x03
#define PEBS_PACKED_DP 0x04
#define PEBS_SCALAR_SP 0x05
#define PEBS_SCALAR_DP 0x06
#define PEBS_128BIT_MMX 0x07
#define PEBS_64BIT_MMX 0x08
#define PEBS_X87_FP 0x09
#define PEBS_X87_SIMD_MOVES 0x0a
/* PEBS : metrics (Replay Event) */
#define PEBS_1STL_CACHE_LOAD_MISS 0x0b
#define PEBS_2NDL_CACHE_LOAD_MISS 0x0c
#define PEBS_DTLB_LOAD_MISS 0x0d
#define PEBS_DTLB_STORE_MISS 0x0e
#define PEBS_DTLB_ALL_MISS 0x0f
#define PEBS_MOB_LOAD_REPLAY 0x10
#define PEBS_SPLIT_LOAD 0x11
#define PEBS_SPLIT_STORE 0x12
/* PEBS : ESCR, CCCR definitions (Front End Event) */
#define ESCR_FRONT_END \
(((0x08 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define CCCR_FRONT_END \
(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
CCCR_RSVD)
#define ESCR_MEMORY_LOADS \
(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define ESCR_MEMORY_STORES \
(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_2 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
/* PEBS : ESCR, CCCR definitions (Execution Event) */
#define ESCR_EXECUTION \
(((0x0c << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_0 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define CCCR_EXECUTION \
(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
CCCR_RSVD)
#define ESCR_PACKED_SP \
(((0x08 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_PACKED_DP \
(((0x0c << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_SCALAR_SP \
(((0x0a << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_SCALAR_DP \
(((0x0e << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_64BIT_MMX \
(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_128BIT_MMX \
(((0x1a << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_X87_FP \
(((0x04 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_X87_SIMD_MOVES \
(((0x2e << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
(((DS_BIT_3 | DS_BIT_4) << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
/* PEBS : ESCR, CCCR definitions (Replay Event) */
#define ESCR_REPLAY \
(((0x09 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_0 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define CCCR_REPLAY \
(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
CCCR_RSVD)
#define ESCR_MOB_LOAD_REPLAY \
(((0x03 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
(((DS_BIT_4 | DS_BIT_5) << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define ESCR_SPLIT_LOAD \
(((0x04 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define ESCR_SPLIT_STORE \
(((0x05 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
/* DS : MSR(ESCR) bit definition */
#define DS_BIT_0 0x00000001
#define DS_BIT_1 0x00000002
#define DS_BIT_2 0x00000004
#define DS_BIT_3 0x00000008
#define DS_BIT_4 0x00000010
#define DS_BIT_5 0x00000020
#define DS_BIT_6 0x00000040
#define DS_BIT_7 0x00000080
#define DS_BIT_8 0x00000100
#define DS_BIT_9 0x00000200
#define DS_BIT_10 0x00000400
#define DS_BIT_11 0x00000800
#define DS_BIT_12 0x00001000
#define DS_BIT_13 0x00002000
#define DS_BIT_14 0x00004000
#define DS_BIT_15 0x00008000
#define DS_BIT_16 0x00010000
#define DS_BIT_17 0x00020000
#define DS_BIT_18 0x00040000
#define DS_BIT_19 0x00080000
#define DS_BIT_20 0x00100000
#define DS_BIT_21 0x00200000
#define DS_BIT_22 0x00400000
#define DS_BIT_23 0x00800000
#define DS_BIT_24 0x01000000
#define DS_BIT_25 0x02000000
#define DS_BIT_26 0x04000000
#define DS_BIT_27 0x08000000
#define DS_BIT_28 0x10000000
#define DS_BIT_29 0x20000000
#define DS_BIT_30 0x40000000
#define DS_BIT_31 0x80000000
/* DS : MSR(ESCR, CCCR) shift count definition */
#define DS_SHIFT_1 1
#define DS_SHIFT_2 2
#define DS_SHIFT_3 3
#define DS_SHIFT_4 4
#define DS_SHIFT_5 5
#define DS_SHIFT_6 6
#define DS_SHIFT_7 7
#define DS_SHIFT_8 8
#define DS_SHIFT_9 9
#define DS_SHIFT_10 10
#define DS_SHIFT_11 11
#define DS_SHIFT_12 12
#define DS_SHIFT_13 13
#define DS_SHIFT_14 14
#define DS_SHIFT_15 15
#define DS_SHIFT_16 16
#define DS_SHIFT_17 17
#define DS_SHIFT_18 18
#define DS_SHIFT_19 19
#define DS_SHIFT_20 20
#define DS_SHIFT_21 21
#define DS_SHIFT_22 22
#define DS_SHIFT_23 23
#define DS_SHIFT_24 24
#define DS_SHIFT_25 25
#define DS_SHIFT_26 26
#define DS_SHIFT_27 27
#define DS_SHIFT_28 28
#define DS_SHIFT_29 29
#define DS_SHIFT_30 30
#define DS_SHIFT_31 31
#ifndef _ASMLANGUAGE
typedef struct btsRec /* BTS (Branch Trace Store) record */
{
UINT32 pcFm; /* Last Branch From */
UINT32 pcTo; /* Last Branch To */
UINT32 misc; /* bit4: Branch Predicted */
} BTS_REC;
typedef struct pebsRec /* PEBS (Precise Event Based Sampling) rec */
{
UINT32 eflags; /* EFLAGS */
UINT32 eip; /* Linear IP */
UINT32 eax; /* EAX */
UINT32 ebx; /* EBX */
UINT32 ecx; /* ECX */
UINT32 edx; /* EDX */
UINT32 esi; /* ESI */
UINT32 edi; /* EDI */
UINT32 ebp; /* EBP */
UINT32 esp; /* ESP */
} PEBS_REC;
typedef struct dsBufHeader /* DS (Debug Store) buffer management */
{
BTS_REC * btsBase; /* BTS buffer base */
BTS_REC * btsIndex; /* BTS index */
UINT32 btsMax; /* BTS absolute maximum */
UINT32 btsThreshold; /* BTS interrupt threshold */
PEBS_REC * pebsBase; /* PEBS buffer base */
PEBS_REC * pebsIndex; /* PEBS index */
UINT32 pebsMax; /* PEBS absolute maximum */
UINT32 pebsThreshold; /* PEBS interrupt threshold */
LL_INT pebsCtr; /* PEBS counter reset value */
UINT32 reserved[3]; /* reserved */
} DS_BUF_HEADER;
typedef struct dsConfig /* DS (Debug Store) configuration */
{
UINT32 btsNbytes; /* BTS buffer size */
BOOL btsAvailable; /* TRUE if BTS is available */
BOOL btsEnabled; /* TRUE if BTS is enabled */
BOOL btsIntMode; /* TRUE for interrupt mode */
BOOL btsBufMode; /* TRUE to store BTMs */
UINT32 pebsNbytes; /* PEBS buffer size */
BOOL pebsAvailable; /* TRUE if PEBS is available */
BOOL pebsEnabled; /* TRUE if PEBS is enabled */
INT32 pebsEvent; /* PEBS event */
INT32 pebsMetric; /* PEBS metric */
BOOL pebsOs; /* PEBS os */
LL_INT pebsCtr; /* PEBS counter */
DS_BUF_HEADER * pH; /* DS buffer header */
} DS_CONFIG;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS dbgStrLibInit (UINT32 nBytesBts, UINT32 nBytesPebs,
BOOL sysMode);
extern DS_BUF_HEADER * dbgStrBufInit (DS_BUF_HEADER * pH,
BTS_REC * btsBufAddr,
UINT32 btsMaxOffset,
UINT32 btsIntOffset,
PEBS_REC * pebsBufAddr,
UINT32 pebsMaxOffset,
UINT32 pebsIntOffset);
extern STATUS dbgStrBufAlloc (WIND_TCB * pTcb);
extern STATUS dbgStrBufFree (WIND_TCB * pTcb);
extern STATUS dbgStrConfig (WIND_TCB * pTcb,
BOOL btsEnable, BOOL pebsEnable,
BOOL btsIntMode, BOOL btsBufMode,
INT32 pebsEvent, INT32 pebsMetric,
BOOL pebsOs, LL_INT * pPebsValue);
extern STATUS dbgStrStart (WIND_TCB * pTcb);
extern STATUS dbgStrStop (WIND_TCB * pTcb);
extern STATUS dbgStrBtsModeSet (BOOL intMode, BOOL bufMode);
extern BOOL dbgStrBtsEnable (BOOL enable);
extern STATUS dbgStrPebsModeSet (INT32 event, INT32 metric, BOOL os,
LL_INT * pValue);
extern BOOL dbgStrPebsEnable (BOOL enable);
extern void dbgStrShowInit (void);
extern void dbgStrShow (WIND_TCB * pTcb, int type);
#else /* __STDC__ */
extern STATUS dbgStrLibInit ();
extern DS_BUF_HEADER * dbgStrBufInit ();
extern STATUS dbgStrBufAlloc ();
extern STATUS dbgStrBufFree ();
extern STATUS dbgStrConfig ();
extern STATUS dbgStrStart ();
extern STATUS dbgStrStop ();
extern STATUS dbgStrBtsModeSet ();
extern BOOL dbgStrBtsEnable ();
extern STATUS dbgStrPebsModeSet ();
extern BOOL dbgStrPebsEnable ();
extern void dbgStrShowInit ();
extern void dbgStrShow ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCdbgStrLibh */
vxworks-6.9/target/h/arch/i86/dsmI86Lib.h
+1086
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vxworks-6.9/target/h/arch/i86/elfI86.h
+120
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@@ -0,0 +1,120 @@
/* elfI86.h - i86-specific ELF loader header */
/*
* Copyright (c) 2001, 2004-2005, 2009 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software may be
* licensed only pursuant to the terms of an applicable Wind River license
* agreement.
*/
/*
modification history
--------------------
01e,14dec09,pgh Add EM_ARCH_MACHINE_x macro definition.
01d,05jun09,v_r Added ELF64 support (from Professional Services EMT64 Data
Access project).
01c,25jul05,v_r Updated copyright.
01b,27feb04,pad Renamed relocation type R_386_JUMP_SLOT as R_386_JMP_SLOT as
per ABI.
01a,12sep01,pad Backported from TAE 3.1 to T2.2 with necessary adaptations
(base version: elfI86.h@@/main/tor3_x/1).
*/
#ifndef __INCelfI86h
#define __INCelfI86h
#ifdef __cplusplus
extern "C" {
#endif
/*
* The following macros define the ELF machine type values that can be loaded
* into an i86 CPU.
*/
#define EM_ARCH_MACHINE_1 EM_386
#define EM_ARCH_MACHINE_2 EM_486
#define EM_ARCH_MACHINE_3 EM_X86_64
#ifdef _WRS_CONFIG_LP64
#define EM_ARCH_MACHINE EM_X86_64
#else /* _WRS_CONFIG_LP64 */
#define EM_ARCH_MACHINE EM_386
#define EM_ARCH_MACH_ALT EM_486 /* not used */
#endif /* !_WRS_CONFIG_LP64 */
/*
* Relocation Type Definitions
* The only ones that appear in vxWorks archives are "1" and "2"
*/
#define R_386_NONE 0 /* No reloc */
#define R_386_32 1 /* Direct 32 bit */
#define R_386_PC32 2 /* PC relative 32 bit */
#define R_386_GOT32 3 /* 32 bit GOT entry */
#define R_386_PLT32 4 /* 32 bit PLT address */
#define R_386_COPY 5 /* Copy symbol at runtime */
#define R_386_GLOB_DAT 6 /* Create GOT entry */
#define R_386_JMP_SLOT 7 /* Create PLT entry */
#define R_386_RELATIVE 8 /* Adjust by program base */
#define R_386_GOTOFF 9 /* 32 bit offset to GOT */
#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */
/* These 16-bit and 8-bit relocs should never show up */
#define R_386_16 20
#define R_386_PC16 21
#define R_386_8 22
#define R_386_PC8 23
#define R_386_max 24
/* These are GNU extensions to enable C++ vtable garbage collection. */
#define R_386_GNU_VTINHERIT 250
#define R_386_GNU_VTENTRY 251
/* AMD x86-64 relocations. */
#define R_X86_64_NONE 0 /* No reloc */
#define R_X86_64_64 1 /* Direct 64 bit */
#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
#define R_X86_64_PLT32 4 /* 32 bit PLT address */
#define R_X86_64_COPY 5 /* Copy symbol at runtime */
#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative
offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */
#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
#define R_X86_64_8 14 /* Direct 8 bit sign extended */
#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */
#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */
#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */
#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset
to two GOT entries for GD symbol */
#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset
to two GOT entries for LD symbol */
#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */
#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset
to GOT entry for IE symbol */
#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */
#define R_X86_64_PC64 24 /* PC-relative 64 bits */
#define R_X86_64_GOTOFF64 25
#define R_X86_64_GOTPC32 26
#define R_X86_64_SIZE32 32
#define R_X86_64_SIZE64 33
#define R_X86_64_GOTPC32_TLSDESC 34
#define R_X86_64_TLSDESC_CALL 35
#define R_X86_64_TLSDESC 36
#ifdef __cplusplus
}
#endif
#endif /* __INCelfI86h */
vxworks-6.9/target/h/arch/i86/esfI86.h
+110
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/* esfI86.h - I80x86 exception stack frames */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,31aug01,hdn added ESF[123] macros and its offset/size.
01b,08jun93,hdn added support for c++. updated to 5.1.
01a,28feb92,hdn written based on TRON, 68k version.
*/
#ifndef __INCesfI86h
#define __INCesfI86h
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/* Exception stack frames. Most of these can happen only for one
CPU or another, but they are all defined for all CPU's */
/* Format-0 - no privilege change, no error code */
typedef struct
{
INSTR * pc; /* 0x00 : PC */
unsigned short cs; /* 0x04 : code segment */
unsigned short pad0; /* 0x06 : padding */
unsigned long eflags; /* 0x08 : EFLAGS */
} ESF0; /* sizeof(ESF0) -> 0x0c */
/* Format-1 - no privilege change, error code */
typedef struct
{
unsigned long errCode; /* 0x00 : error code */
INSTR * pc; /* 0x04 : PC */
unsigned short cs; /* 0x08 : code segment */
unsigned short pad0; /* 0x0a : padding */
unsigned long eflags; /* 0x0c : EFLAGS */
} ESF1; /* sizeof(ESF1) -> 0x10 */
/* Format-2 - privilege change, no error code */
typedef struct
{
INSTR * pc; /* 0x00 : PC */
unsigned short cs; /* 0x04 : code segment */
unsigned short pad0; /* 0x06 : padding */
unsigned long eflags; /* 0x08 : EFLAGS */
unsigned long esp; /* 0x0c : ESP */
unsigned long ss; /* 0x10 : SS */
} ESF2; /* sizeof(ESF2) -> 0x14 */
/* Format-3 - privilege change, error code */
typedef struct
{
unsigned long errCode; /* 0x00 : error code */
INSTR * pc; /* 0x04 : PC */
unsigned short cs; /* 0x08 : code segment */
unsigned short pad0; /* 0x0a : padding */
unsigned long eflags; /* 0x0c : EFLAGS */
unsigned long esp; /* 0x10 : ESP */
unsigned long ss; /* 0x14 : SS */
} ESF3; /* sizeof(ESF3) -> 0x18 */
#endif /* _ASMLANGUAGE */
#define ESF0_EIP 0x00 /* 0x00 : PC */
#define ESF0_CS 0x04 /* 0x04 : CS */
#define ESF0_EFLAGS 0x08 /* 0x08 : EFLAGS */
#define ESF1_ERROR 0x00 /* 0x00 : ERROR */
#define ESF1_EIP 0x04 /* 0x04 : PC */
#define ESF1_CS 0x08 /* 0x08 : CS */
#define ESF1_EFLAGS 0x0c /* 0x0c : EFLAGS */
#define ESF2_EIP 0x00 /* 0x00 : PC */
#define ESF2_CS 0x04 /* 0x04 : CS */
#define ESF2_EFLAGS 0x08 /* 0x08 : EFLAGS */
#define ESF2_ESP 0x0c /* 0x0c : ESP */
#define ESF2_SS 0x10 /* 0x10 : SS */
#define ESF3_ERROR 0x00 /* 0x00 : ERROR */
#define ESF3_EIP 0x04 /* 0x04 : PC */
#define ESF3_CS 0x08 /* 0x08 : CS */
#define ESF3_EFLAGS 0x0c /* 0x0c : EFLAGS */
#define ESF3_ESP 0x10 /* 0x10 : ESP */
#define ESF3_SS 0x14 /* 0x14 : SS */
#define ESF0_NBYTES 0x0c /* sizeof(ESF0) */
#define ESF1_NBYTES 0x10 /* sizeof(ESF1) */
#define ESF2_NBYTES 0x14 /* sizeof(ESF2) */
#define ESF3_NBYTES 0x18 /* sizeof(ESF3) */
#define ESF0_NLONGS 0x03 /* sizeof(ESF0) / sizeof(int) */
#define ESF1_NLONGS 0x04 /* sizeof(ESF1) / sizeof(int) */
#define ESF2_NLONGS 0x05 /* sizeof(ESF2) / sizeof(int) */
#define ESF3_NLONGS 0x06 /* sizeof(ESF3) / sizeof(int) */
#ifdef __cplusplus
}
#endif
#endif /* __INCesfI86h */
vxworks-6.9/target/h/arch/i86/excI86Lib.h
+122
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@@ -0,0 +1,122 @@
/* excLib.h - exception library header */
/* Copyright 1984-2003,2008, 2011 Wind River Systems, Inc. */
/*
modification history
--------------------
01i,14nov11,yjw Add exception vector definitions.(WIND00310152)
01h,13oct08,rbc WIND00137483. Fix the _WRS_IS_SUPV_EXC macro.
01g,26nov03,pes Correct _WRS_IS_SUPV_EXC macro.
01f,18nov03,pes Add _WRS_IS_SUPV_EXC macro.
01e,22oct02,hdn added EXC_FP_CONTEXT for FPU exception (spr 70252)
01d,29aug01,hdn added _ASMLANGUAGE conditional macro
added esp0, cr2, cr3, esp0[07] to EXC_INFO.
01c,14nov93,hdn added excExcepHook.
01b,08jun93,hdn added support for c++. updated to 5.1.
01a,28feb92,hdn written based on TRON, 68k version.
*/
#ifndef __INCexcI86Libh
#define __INCexcI86Libh
#ifdef __cplusplus
extern "C" {
#endif
/* lowest and highest vector number to initialize */
#define LOW_VEC 0 /* lowest initialized vector */
#define HIGH_VEC 0xff /* highest initialized vector */
#ifndef _ASMLANGUAGE
typedef struct
{
UINT16 valid; /* indicators that following fields are valid */
UINT16 vecNum; /* vector number */
ULONG errCode; /* error code */
INSTR * pc; /* program counter */
ULONG eflags; /* eflags register */
UINT16 cs; /* code segment register */
UINT16 pad; /* pad to four byte boundary */
ULONG esp; /* stack pointer in the ESF */
ULONG ss; /* stack segment in the ESF */
ULONG esp0; /* supervisor (PL0) stack pointer */
ULONG cr2; /* CR2 */
ULONG cr3; /* CR3 */
ULONG esp00; /* content of the stack *(esp0 + 0) */
ULONG esp01; /* content of the stack *(esp0 + 1) */
ULONG esp02; /* content of the stack *(esp0 + 2) */
ULONG esp03; /* content of the stack *(esp0 + 3) */
ULONG esp04; /* content of the stack *(esp0 + 4) */
ULONG esp05; /* content of the stack *(esp0 + 5) */
ULONG esp06; /* content of the stack *(esp0 + 6) */
ULONG esp07; /* content of the stack *(esp0 + 7) */
ULONG reserved0; /* reserved 0 */
ULONG reserved1; /* reserved 1 */
ULONG reserved2; /* reserved 2 */
ULONG reserved3; /* reserved 3 */
} EXC_INFO;
#define _WRS_IS_SUPV_EXC() (((excInfo.cs & 0x3) == 0) ? TRUE : FALSE)
/* exception info valid bits */
#define EXC_VEC_NUM 0x01 /* vector number valid */
#define EXC_ERROR_CODE 0x02 /* error code valid */
#define EXC_ESP_SS 0x04 /* ESP and SS valid */
#define EXC_CR2 0x08 /* CR2 valid */
#define EXC_FP_CONTEXT 0x10 /* FP_CONTEXT valid */
#define EXC_INVALID_TYPE 0x80 /* special indicator: ESF type was bad;
* type is in funcCode field */
/* exception vector number */
#define EXC_DIVIDE_ERROR 0x00 /* divide error */
#define EXC_DEBUG 0x01 /* debug */
#define EXC_NMI 0x02 /* NMI */
#define EXC_INT3 0x03 /* breakpoint */
#define EXC_OVERFLOW 0x04 /* overflow */
#define EXC_BOUNDS_CHECK 0x05 /* bounds check */
#define EXC_INVALID_OPCODE 0x06 /* invalid opcode */
#define EXC_DEVICE_NOT_AVAILABLE 0x07 /* device not available */
#define EXC_DOUBLE_FAULT 0x08 /* double fault */
#define EXC_COPROC_OVERRUN 0x09 /* coprocessor segment overrun */
#define EXC_INVALID_TSS 0x0a /* invalid TSS */
#define EXC_SEGMENT_NOT_PRESENT 0x0b /* segment not present */
#define EXC_STACK_SEGMENT_FAULT 0x0c /* stack segment fault */
#define EXC_GENERAL_PROTECTION 0x0d /* general protection */
#define EXC_PAGE_FAULT 0x0e /* page fault */
#define EXC_RESERVED 0x0f /* Intel-reserved */
#define EXC_FP_ERROR 0x10 /* Floating-point error */
#define EXC_ALIGNMENT_CHECK 0x11 /* alignment check */
#define EXC_MACHINE_CHECK 0x12 /* machine check */
#define EXC_SIMD_ERROR 0x13 /* SIMD Float exception */
/* variable declarations */
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void excStub (void);
extern void excIntStub (void);
#else /* __STDC__ */
extern void excStub ();
extern void excIntStub ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCexcI86Libh */
vxworks-6.9/target/h/arch/i86/fppI86Lib.h
+307
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@@ -0,0 +1,307 @@
/* fppLib.h - floating-point coprocessor support library header */
/* Copyright 1992-1993,2001-2002,2008,2010-2011 Wind River Systems, Inc. */
/*
modification history
--------------------
01m,22dec11,jjk WIND00313302 - Fix display of FP/MMX registers
01l,27jul11,g_x add xmm[] and ymm[] to FPREG_SET (WIND00285122)
01k,22mar11,ggm WIND00262870 - Added fppArchCpuInit.
01j,19jan11,ggm XSave/XRestore implementation for extended state context
switch.
01i,29sep10,scm adjust offset for FPXREG_FPX for DOUBLEX_SSE structs...
01h,05mar08,scm WIND00116608.
01g,25mar02,hdn added two APIs to detect illegal FPU usage (spr 70187)
01f,21nov01,hdn derived xmm[] from the reserved res2[] in FPX_CONTEXT
01e,21aug01,hdn imported SSE support from T31 ver 01g
01d,02sep93,hdn deleted a macro FPX.
01c,08jun93,hdn added support for c++. updated to 5.1.
01b,29sep92,hdn changed UTINY to UCHAR.
01a,07apr92,hdn written based on TRON version.
*/
#ifndef __INCfppI86Libh
#define __INCfppI86Libh
#ifdef __cplusplus
extern "C" {
#endif
/* control register: defines for control word */
#define FPCR_IM 0x0001 /* IM exc-mask invalid operation */
#define FPCR_DM 0x0002 /* DM exc-mask denormalized operand */
#define FPCR_ZM 0x0004 /* ZM exc-mask zero divide */
#define FPCR_OM 0x0008 /* OM exc-mask overflow */
#define FPCR_UM 0x0010 /* UM exc-mask underflow */
#define FPCR_PM 0x0020 /* PM exc-mask precision */
#define FPCR_PC_SINGLE 0x0000 /* PC single precision(24 bits) */
#define FPCR_PC_DOUBLE 0x0200 /* PC double precision(53 bits) */
#define FPCR_PC_EXTENDED 0x0300 /* PC extended precision(64 bits) */
#define FPCR_PC_MASK 0xfcff /* PC extended precision(64 bits) */
#define FPCR_RC_NEAREST 0x0000 /* RC round to nearest */
#define FPCR_RC_DOWN 0x0400 /* RC round down */
#define FPCR_RC_UP 0x0800 /* RC round up */
#define FPCR_RC_ZERO 0x0c00 /* RC round to zero */
#define FPCR_RC_MASK 0xf3ff /* RC round bits mask */
#define FPCR_X 0x1000 /* X infinity control */
/* status register: defines for status word */
#define FPSR_IE 0x0001 /* IE exc-flag invalid operation */
#define FPSR_DE 0x0002 /* DE exc-flag denormalized operand */
#define FPSR_ZE 0x0004 /* ZE exc-flag zero divide */
#define FPSR_OE 0x0008 /* OE exc-flag overflow */
#define FPSR_UE 0x0010 /* UE exc-flag underflow */
#define FPSR_PE 0x0020 /* PE exc-flag precision */
#define FPSR_SF 0x0040 /* SF stack fault */
#define FPSR_ES 0x0080 /* ES error summary status */
#define FPSR_C0 0x0100 /* C0 condition code */
#define FPSR_C1 0x0200 /* C1 condition code */
#define FPSR_C2 0x0400 /* C2 condition code */
#define FPSR_TOP 0x3800 /* TOP top of stack pointer */
#define FPSR_C3 0x4000 /* C3 condition code */
#define FPSR_B 0x8000 /* FPU busy */
/* number of FP/MM and XMM registers on coprocessor */
#define FP_NUM_REGS 8 /* number of FP/MM registers */
#define XMM_NUM_REGS 8 /* number of XMM registers */
#define FP_NUM_RESERVED 14 /* reserved area in FPX_CONTEXT */
#define XSAVE_HEADER 64 /* Number of bytes in the XSAVE header */
/* maximum size of floating-point coprocessor state frame */
#define FPO_STATE_FRAME_SIZE 108 /* nBytes of FPO_CONTEXT */
#define FPX_STATE_FRAME_SIZE 512 /* nBytes of FPX_CONTEXT */
/* FPREG_SET structure offsets */
#define FPREG_FPCR 0x00 /* offset to FPCR in FPREG_SET */
#define FPREG_FPSR 0x04 /* offset to FPSR in FPREG_SET */
#define FPREG_FPTAG 0x08 /* offset to FPTAG in FPREG_SET */
#define FPREG_OP 0x0c /* offset to OP in FPREG_SET */
#define FPREG_IP 0x10 /* offset to IP in FPREG_SET */
#define FPREG_CS 0x14 /* offset to CS in FPREG_SET */
#define FPREG_DP 0x18 /* offset to DP in FPREG_SET */
#define FPREG_DS 0x1c /* offset to DS in FPREG_SET */
#define FPREG_FPX(n) (0x20 + (n)*sizeof(DOUBLEX)) /* offset to FPX(n) */
/* FPX_CONTEXT REG_SET - structure offsets for New FP context */
#define FPXREG_FPCR 0x00 /* offset to FPCR in FPREG_SET */
#define FPXREG_FPSR 0x02 /* offset to FPSR in FPREG_SET */
#define FPXREG_FPTAG 0x04 /* offset to FPTAG in FPREG_SET */
#define FPXREG_OP 0x06 /* offset to OP in FPREG_SET */
#define FPXREG_IP 0x08 /* offset to IP in FPREG_SET */
#define FPXREG_CS 0x0c /* offset to CS in FPREG_SET */
#define FPXREG_DP 0x10 /* offset to DP in FPREG_SET */
#define FPXREG_DS 0x14 /* offset to DS in FPREG_SET */
#define FPXREG_RSVD0 0x18 /* offset to RESERVED0 in FPREG_SET */
#define FPXREG_RSVD1 0x1c /* offset to RESERVED1 in FPREG_SET */
#define FPXREG_FPX(n) (0x20 + (n)*sizeof(DOUBLEX_SSE)) /* offset to FPX(n) */
#ifndef _ASMLANGUAGE
/* DOUBLEX - double extended precision */
typedef struct
{
UCHAR f[10]; /* ST[0-7] or MM[0-7] */
} DOUBLEX;
/* DOUBLEX_SSE - double extended precision used in FPX_CONTEXT for SSE */
typedef struct
{
UCHAR xmm[16]; /* for 128 bits XMM registers */
} DOUBLEX_SSE;
/* FPREGO_SET - FP register set that is different from FP_CONTEXT */
typedef struct fpregOSet
{
int fpcr; /* control word */
int fpsr; /* status word */
int fptag; /* tag word */
int op; /* last FP instruction op code */
int ip; /* instruction pointer */
int cs; /* instruction pointer selector */
int dp; /* data pointer */
int ds; /* data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* FR[0-7] non-TOS rel. order */
} FPREGO_SET;
/* FPREGX_SET - FP register set that is corresponding to FPX_CONTEXT*/
typedef struct fpregXSet
{
int fpcr; /* control word */
int fpsr; /* status word */
int fptag; /* tag word */
int op; /* last FP instruction op code */
int ip; /* instruction pointer */
int cs; /* instruction pointer selector */
int dp; /* data pointer */
int ds; /* data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 8*16 XMM[0-7] */
} FPREGX_SET;
/* FPREGX_EXT_SET - FP register set that is corresponding to FPX_EXT_CONTEXT */
typedef struct fpregX_ExtSet
{
int fpcr; /* control word */
int fpsr; /* status word */
int fptag; /* tag word */
int op; /* last FP instruction op code */
int ip; /* instruction pointer */
int cs; /* instruction pointer selector */
int dp; /* data pointer */
int ds; /* data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 8*16 XMM[0-7] */
DOUBLEX_SSE ymm[XMM_NUM_REGS]; /* 8*16 higher 128 bits of YMM[0-7] */
} FPREGX_EXT_SET;
/* FPREG_SET - Common FP register set */
typedef struct fpregSet
{
union n
{
FPREGO_SET o; /* old FPO_CONTEXT for fsave/frstor */
FPREGX_SET x; /* new FPX_CONTEXT for fxsave/fxrstor */
FPREGX_EXT_SET x_ext; /* FPX_EXT_CONTEXT for xsave/xrstor */
} n;
} FPREG_SET;
/* FPO_CONTEXT - Old FP context used by fsave/frstor instruction */
typedef struct fpOcontext
{
int fpcr; /* 4 control word */
int fpsr; /* 4 status word */
int fptag; /* 4 tag word */
int ip; /* 4 instruction pointer */
short cs; /* 2 instruction pointer selector */
short op; /* 2 last FP instruction op code */
int dp; /* 4 data pointer */
int ds; /* 4 data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* 8*10 FR[0-7] non-TOS rel. order */
} FPO_CONTEXT; /* 108 bytes total */
/* FPX_CONTEXT - New FP context used by fxsave/fxrstor instruction */
typedef struct fpXcontext
{
short fpcr; /* 2 control word */
short fpsr; /* 2 status word */
short fptag; /* 2 tag word */
short op; /* 2 last FP instruction op code */
int ip; /* 4 instruction pointer */
int cs; /* 4 instruction pointer selector */
int dp; /* 4 data pointer */
int ds; /* 4 data pointer selector */
int reserved0; /* 4 reserved */
int reserved1; /* 4 reserved */
DOUBLEX_SSE fpx[FP_NUM_REGS]; /* 8*16 FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 8*16 XMM[0-7] */
DOUBLEX_SSE res2[FP_NUM_RESERVED]; /* 14*16 reserved */
} FPX_CONTEXT; /* 512 bytes total */
/* FPX_EXT_CONTEXT - Extended FP context used by xsave/xrstor instruction */
typedef struct fpX_ExtContext
{
short fpcr; /* 2 control word */
short fpsr; /* 2 status word */
short fptag; /* 2 tag word */
short op; /* 2 last FP instruction op code */
int ip; /* 4 instruction pointer */
int cs; /* 4 instruction pointer selector */
int dp; /* 4 data pointer */
int ds; /* 4 data pointer selector */
int reserved0; /* 4 reserved */
int reserved1; /* 4 reserved */
DOUBLEX_SSE fpx[FP_NUM_REGS]; /* 8*16 FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 8*16 XMM[0-7] */
DOUBLEX_SSE res2[FP_NUM_RESERVED]; /* 14*16 reserved */
UCHAR xSaveHeader[XSAVE_HEADER]; /* 64 XSave header */
DOUBLEX_SSE ymm[XMM_NUM_REGS]; /* 8*16 higher 128 bits of YMM[0-7] */
} FPX_EXT_CONTEXT; /* 704 bytes total */
/* FP_CONTEXT - Common FP context */
typedef struct fpContext
{
union u
{
FPO_CONTEXT o; /* old FPO_CONTEXT for fsave/frstor */
FPX_CONTEXT x; /* new FPX_CONTEXT for fxsave/fxrstor */
FPX_EXT_CONTEXT x_ext; /* FPX_EXT_CONTEXT for xsave/xrstor */
} u;
} FP_CONTEXT;
/* variable declarations */
extern REG_INDEX fpRegName[]; /* f-point data register table */
extern REG_INDEX fpXregName[]; /* f-point data register table for FPX and FPX_EXT */
extern REG_INDEX fpCtlRegName[]; /* f-point control register table */
extern REG_INDEX fpXctlRegName[]; /* new f-point control register table */
extern WIND_TCB *pFppTaskIdPrevious; /* task id for deferred exceptions */
extern FUNCPTR fppCreateHookRtn; /* arch dependent create hook routine */
extern FUNCPTR fppDisplayHookRtn; /* arch dependent display routine */
extern VOIDFUNCPTR _func_fppSaveRtn; /* fppSave or fppXsave */
extern VOIDFUNCPTR _func_fppRestoreRtn; /* fppRestore or fppXrestore */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void fppArchCpuInit(void);
extern void fppArchInit (void);
extern void fppArchTaskCreateInit (FP_CONTEXT *pFpContext);
extern STATUS fppProbeSup (void);
extern void fppProbeTrap (void);
extern void fppDtoDx (DOUBLEX *pDx, double *pDouble);
extern void fppDxtoD (double *pDouble, DOUBLEX *pDx);
extern void fppXrestore (FP_CONTEXT *pFpContext);
extern void fppXsave (FP_CONTEXT *pFpContext);
extern void fppXregsToCtx (FPREG_SET *pFpRegSet, FP_CONTEXT *pFpContext);
extern void fppExtXregsToCtx (FPREG_SET *pFpRegSet, FP_CONTEXT *pFpContext);
extern void fppXctxToRegs (FP_CONTEXT *pFpContext, FPREG_SET *pFpRegSet);
extern void fppExtXctxToRegs (FP_CONTEXT *pFpContext, FPREG_SET *pFpRegSet);
extern void fppArchSwitchHook (WIND_TCB * pOldTcb, WIND_TCB * pNewTcb);
extern STATUS fppArchSwitchHookEnable (BOOL enable);
#else
extern void fppArchCpuInit();
extern void fppArchInit ();
extern void fppArchTaskCreateInit ();
extern STATUS fppProbeSup ();
extern void fppProbeTrap ();
extern void fppDtoDx ();
extern void fppDxtoD ();
extern void fppXrestore ();
extern void fppXsave ();
extern void fppXregsToCtx ();
extern void fppExtXregsToCtx ();
extern void fppXctxToRegs ();
extern void fppExtXctxToRegs ();
extern void fppArchSwitchHook ();
extern STATUS fppArchSwitchHookEnable ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCfppI86Libh */
vxworks-6.9/target/h/arch/i86/in_cksum.h
+176
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@@ -0,0 +1,176 @@
/* in_cksum.h - x86 version in_cksum header file */
/* Copyright 2001-2002 Wind River Systems, Inc. */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from tahoe: in_cksum.c 1.2 86/01/05
* from: @(#)in_cksum.c 1.3 (Berkeley) 1/19/91
* from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp
* $FreeBSD: src/sys/i386/include/in_cksum.h,v 1.7.2.1 2000/05/05 13:37:00 jlemon Exp $
*/
/*
modification history
--------------------
01f,25aug05,dlk Add section tags.
01e,24mar04,m_h Internet Checksum
01d,18mar04,m_h moved to arch/i86
01c,20nov03,niq Remove copyright_wrs.h file inclusion
01c,18nov03,rp updated header file path
01b,25jul02,rvr removed DCC specific code
01a,13sep01,hsh Created from BSD 4.3
*/
#ifndef _MACHINE_IN_CKSUM_H_
#define _MACHINE_IN_CKSUM_H_ 1
#include <sys/cdefs.h>
/*
* in_cksum_hdr - checksum on header only
*
* It is useful to have an Internet checksum routine which is inlineable
* and optimized specifically for the task of computing IP header checksums
* in the normal case (where there are no options and the header length is
* therefore always exactly five 32-bit words.
*/
static __inline u_int
in_cksum_hdr
(
const struct ip *ip
)
{
register u_int sum = 0;
int hlen = sizeof (struct ip);
register u_short *w = (u_short *) ip;
u_short remaining = 0;
while (hlen > 1)
{
sum += *w++;
hlen -= 2;
}
if (hlen == 1)
{
*(u_char *) (&remaining) = *(u_char *) w;
sum += remaining;
}
sum = (sum & 0xffff) + (sum >> 16);
if (sum > 0xffff)
sum -= 0xffff;
return ~sum & 0xffff;
}
/*
* in_cksum_update
*/
static __inline void
in_cksum_update
(
struct ip *ip
)
{
int __tmpsum;
__tmpsum = (int)ntohs(ip->ip_sum) + 256;
ip->ip_sum = htons(__tmpsum + (__tmpsum >> 16));
}
/*
* in_pseudo - pre-checksum parts of pseudo-header
*
* Compute significant parts of the IPv4 checksum pseudo-header * for use in a
* delayed TCP/UDP checksum calculation.
*
* Args:
*
* src Source IP address
* dst Destination IP address
* lenproto htons(proto-hdr-len + proto-number)
*/
static __inline u_int16_t in_pseudo
(
u_int32_t src,
u_int32_t dst,
u_int32_t lenproto
)
{
u_int32_t sum;
sum = lenproto +
(u_int16_t)(src >> 16) +
(u_int16_t)(src /*& 0xffff*/) +
(u_int16_t)(dst >> 16) +
(u_int16_t)(dst /*& 0xffff*/);
sum = (u_int16_t)(sum >> 16) + (u_int16_t)(sum /*& 0xffff*/);
if (sum > 0xffff)
sum -= 0xffff;
return (sum);
}
/*
* in_addword - Add two 16-bit workd
*
* Add the two 16-bit network-order values, carry, and return.
*/
static __inline u_int16_t in_addword
(
u_int16_t a,
u_int16_t b
)
{
u_int32_t sum = a + b;
if (sum > 0xffff)
sum -= 0xffff;
return (sum);
}
_WRS_FASTTEXT
u_short in_cksum_skip(struct mbuf *m, int len, int skip);
#endif /* _MACHINE_IN_CKSUM_H_ */
vxworks-6.9/target/h/arch/i86/instrI86.h
+86
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@@ -0,0 +1,86 @@
/* instrI86.h - header for I86 instruction fields */
/* Copyright 2004 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,26apr04,jmp created from target/h/dbgI86Lib.h
*/
/*
* WARNING: This file is shared between i86 and VxSim/i86 arches,
* and between Kernel and User sides.
* Please make sure that any modifications to this file
* does not break other arches.
*/
#ifndef __INCinstrI86h
#define __INCinstrI86h
/* defines */
#define ADDI08_0 (0x83)
#define ADDI08_1 (0xc4)
#define ADDI32_0 (0x81)
#define ADDI32_1 (0xc4)
#define LEAD08_0 (0x8d)
#define LEAD08_1 (0x64)
#define LEAD08_2 (0x24)
#define LEAD32_0 (0x8d)
#define LEAD32_1 (0xa4)
#define LEAD32_2 (0x24)
#define JMPD08 (0xeb)
#define JMPD32 (0xe9)
#define ENTER (0xc8)
#define PUSH_EBX (0x53)
#define PUSH_EBP (0x55)
#define PUSH_ESI (0x56)
#define MOV_ESP0 (0x89)
#define MOV_ESP1 (0xe5)
#define MOV_ESP_ESI (0xe689)
#define LEAVE (0xc9)
#define RET (0xc3)
#define RETADD (0xc2)
#define CALL_DIR (0xe8)
#define CALL_INDIR0 (0xff)
#define CALL_INDIR1 (0x10)
#define CALL_INDIR_REG_EAX (0xd0)
#define CALL_INDIR_REG_ECX (0xd1)
#define CALL_INDIR_REG_EDX (0xd2)
#define CALL_INDIR_REG_EBX (0xd3)
#define MOV_ECX (0x0d8b)
#define MOV_EDX (0x158b)
#define MOV_EBP_ESP (0xe589)
#define ADDI08_0_MASK (0xff)
#define ADDI08_1_MASK (0xff)
#define ADDI32_0_MASK (0xff)
#define ADDI32_1_MASK (0xff)
#define LEAD08_0_MASK (0xff)
#define LEAD08_1_MASK (0xff)
#define LEAD08_2_MASK (0xff)
#define LEAD32_0_MASK (0xff)
#define LEAD32_1_MASK (0xff)
#define LEAD32_2_MASK (0xff)
#define JMPD08_MASK (0xff)
#define JMPD32_MASK (0xff)
#define ENTER_MASK (0xff)
#define PUSH_EBX_MASK (0xff)
#define PUSH_EBP_MASK (0xff)
#define PUSH_ESI_MASK (0xff)
#define MOV_ESP0_MASK (0xff)
#define MOV_ESP1_MASK (0xff)
#define MOV_ESP_ESI_MASK (0xffff)
#define LEAVE_MASK (0xff)
#define RET_MASK (0xff)
#define RETADD_MASK (0xff)
#define CALL_DIR_MASK (0xff)
#define CALL_INDIR0_MASK (0xff)
#define CALL_INDIR1_MASK (0x38)
#define CALL_INDIR_REG_MASK (0xdf)
#define MOV_ECX_MASK (0xffff)
#define MOV_EDX_MASK (0xffff)
#define MOV_EBP_ESP_MASK (0xffff)
#endif /* __INCinstrI86h */
vxworks-6.9/target/h/arch/i86/intI86Lib.h
+119
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@@ -0,0 +1,119 @@
/* intI86Lib.h - I86-specific interrupt library header file */
/*
* Copyright (c) 2001,2003-2004,2007-2009 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01j,10jun09,sem Update intCpuMicroLock inline defines
01i,15apr09,sem Add new intCpuMicroLock API
01h,24mar09,sem Removed andl instruction from inline intCpuLock().
01g,21apr08,scm WIND00121559 - modified gnu versions of inline.
01f,19jun07,zl added _inline_intCpuLock() and _inline_intCpuUnlock()
01e,12oct04,jb Add interrupt lockout for automatic stack switch
01d,04dec03,jb Removing info message
01c,22aug03,to added inline intLock()/intUnlock().
deleted K&R style prototypes.
01b,09nov01,hdn added intConnectCode offset macros
01a,29aug01,hdn taken from T31 ver 01b.
*/
#ifndef __INCintI86Libh
#define __INCintI86Libh
#ifdef __cplusplus
extern "C" {
#endif
/* offset macro for stuff in the intConnect code */
#define ICC_INT_BASE 1
#define ICC_INT_ENT ICC_INT_BASE + 1 /* intConnectCode[1] */
#define ICC_BOI_PUSH ICC_INT_ENT + 7 /* intConnectCode[8] */
#define ICC_BOI_PARAM ICC_BOI_PUSH + 1 /* intConnectCode[9] */
#define ICC_BOI_ROUTN ICC_BOI_PARAM + 5 /* intConnectCode[14] */
#define ICC_INT_PARAM ICC_BOI_ROUTN + 5 /* intConnectCode[19] */
#define ICC_INT_ROUTN ICC_INT_PARAM + 5 /* intConnectCode[24] */
#define ICC_EOI_PARAM ICC_INT_ROUTN + 5 /* intConnectCode[29] */
#define ICC_EOI_CALL ICC_EOI_PARAM + 4 /* intConnectCode[33] */
#define ICC_EOI_ROUTN ICC_EOI_CALL + 1 /* intConnectCode[34] */
#define ICC_ADD_N ICC_EOI_ROUTN + 6 /* intConnectCode[40] */
#define ICC_INT_EXIT ICC_ADD_N + 5 /* intConnectCode[45] */
#ifndef _ASMLANGUAGE
#if defined (__DCC__)
__asm volatile int _inline_intCpuLock (void)
{
! "ax" /* ax is clobbered */
pushf /* push EFLAGS on stack */
cli /* clear interrupts */
popl %eax /* get EFLAGS in EAX */
}
__asm volatile void _inline_intCpuUnlock (int key)
{
!
% mem key; lab skip_sti /* input: key; declare label */
testl $0x200,key /* test EFLAGS_IF */
jz skip_sti /* if not set, skip sti */
sti /* else enable interrupts */
skip_sti:
}
#elif defined (__GNUC__)
static __inline__ int _inline_intCpuLock (void)
{
int key;
__asm__ volatile ("pushf; cli; popl %0; " \
: "=g" (key) : : "memory");
return key;
}
static __inline__ void _inline_intCpuUnlock
(
int key
)
{
__asm__ volatile ("testl $0x200,%0; jz 0f; sti; 0: " \
: : "g" (key) : "cc", "memory");
}
#else
#define _inline_intCpuLock() intCpuLock()
#define _inline_intCpuUnlock(key) intCpuUnlock(key)
#endif /* _VX_TOOL_FAMILY */
#define _inline_intCpuMicroLock() _inline_intCpuLock()
#define _inline_intCpuMicroUnlock(key) _inline_intCpuUnlock(key)
/* function declarations */
extern FUNCPTR intHandlerCreateI86 (FUNCPTR routine, int parameter,
FUNCPTR routineBoi, int parameterBoi,
FUNCPTR routineEoi, int parameterEoi);
extern void intVecSet2 (FUNCPTR * vector, FUNCPTR function,
int idtGate, int idtSelector);
extern void intVecGet2 (FUNCPTR * vector, FUNCPTR * pFunction,
int * pIdtGate, int * pIdtSelector);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCintI86Libh */
vxworks-6.9/target/h/arch/i86/ipiI86Lib.h
+130
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@@ -0,0 +1,130 @@
/* ipiI86Lib.h - I80X86 IPI library header */
/*
* Copyright (c) 2002,2006-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01m,03feb11,rbc WIND00253734 - Disable _WRS_VX_IA_IPI_INSTRUMENTATION for 32
Bit.
01l,03jun10,scm disable _WRS_VX_IA_IPI_INSTRUMENTATION for 64 bit...
01k,01jun10,jb Adding ipi instrumentation for AMP/SMP M-N debugging
01j,29apr10,pad Moved extern C statement after include statements.
01i,14jan09,scm Clean up old SMP restrictions.
01h,27aug08,jpb Renamed VSB header file
01g,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01f,01jun07,tor add DEBUG IPI num
01e,06apr07,scm clarify CPC "self" as meaning boot strap processor...
01d,08dec06,scm add additional SMP ipi support routines...
01c,28feb02,hdn took IPI_MAX_XXX macros from ipiArchLib.c
01b,27feb02,hdn renamed ipiStubShutdown() to ipiShutdownSup()
01a,20feb02,hdn written
*/
#ifndef __INCipiI86Libh
#define __INCipiI86Libh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define IPI_MAX_HANDLERS 8 /* max number of handlers */
#define IPI_MAX_RETRIES 3 /* max number of retries */
#define CPC_IPI_INUM 0xEF /* Must be highest possible int IPI */
#define DEBUG_IPI_INUM 0xEE /* second-highest possible IPI */
#define BEGIN_IPI_INUM 0xE8 /* First IPI Interrupt Number */
#define CPC_TO_ALL_BUT_SELF 0x0 /* special case for broadcasts */
#define CPC_TO_BSP 0x1
#define CPC_TO_AP_1 0x2
#define CPC_TO_AP_2 0x4
#define CPC_TO_AP_3 0x8
#define CPC_TO_ALL_CPUS 0xF
#ifndef _ASMLANGUAGE
/* variable declarations */
IMPORT char ipiCallTbl []; /* table of IPI stub calls */
#ifdef _WRS_CONFIG_LP64
#undef _WRS_VX_IA_IPI_INSTRUMENTATION
#else
#undef _WRS_VX_IA_IPI_INSTRUMENTATION
#endif /* _WRS_CONFIG_LP64 */
#ifdef _WRS_VX_IA_IPI_INSTRUMENTATION
struct ipiCounters
{
UINT32 ipiEmit[IPI_MAX_HANDLERS];
UINT32 ipiSent[IPI_MAX_HANDLERS];
UINT32 ipiRecv[IPI_MAX_HANDLERS];
};
extern struct ipiCounters *ipiCounters[VX_MAX_SMP_CPUS];
#endif /* _WRS_VX_IA_IPI_INSTRUMENTATION */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void ipiVecInit (UINT32 intNum);
extern void ipiHandler (UINT32 index);
extern STATUS ipiConnect (UINT32 intNum, VOIDFUNCPTR routine);
extern STATUS ipiStartup (UINT32 apicId, UINT32 vector, UINT32 nTimes);
extern STATUS ipiShutdown (UINT32 apicId, UINT32 vector);
extern STATUS ipiReset (UINT32 apicId);
extern void ipiStub (void);
extern void ipiShutdownSup (void);
extern void ipiHandlerTlbFlush (void);
extern void ipiHandlerTscReset (void);
extern void ipiHandlerShutdown (void);
/* CPC support routines... */
STATUS cpcIpiEmit (cpuset_t processor);
STATUS cpcIpiIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR handler, int param);
STATUS cpcIpiIntEnable (int vector);
STATUS cpcIpiIntDisable (int vector);
#else /* __STDC__ */
extern void ipiVecInit ();
extern void ipiHandler ();
extern STATUS ipiConnect ();
extern STATUS ipiStartup ();
extern STATUS ipiShutdown ();
extern STATUS ipiReset ();
extern void ipiStub ();
extern void ipiShutdownSup ();
extern void ipiHandlerTlbFlush ();
extern void ipiHandlerTscReset ();
extern void ipiHandlerShutdown ();
/* CPC support routines... */
STATUS cpcIpiEmit ();
STATUS cpcIpiIntConnect ();
STATUS cpcIpiIntEnable ();
STATUS cpcIpiIntDisable ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCipiI86Libh */
vxworks-6.9/target/h/arch/i86/ivI86.h
+88
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@@ -0,0 +1,88 @@
/* ivI86.h - I80x86 interrupt vectors */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01e,29aug01,hdn added support for streaming SIMD exception.
01d,29may94,hdn removed I80486 conditional.
01c,08jun93,hdn added support for c++. updated to 5.1.
01b,26mar93,hdn added a new vector for 486.
01a,28feb92,hdn written based on TRON, 68k version.
*/
#ifndef __INCivI86h
#define __INCivI86h
#ifdef __cplusplus
extern "C" {
#endif
/* 0 - 19 exception vector number */
#define IN_DIVIDE_ERROR 0
#define IN_DEBUG 1
#define IN_NON_MASKABLE 2
#define IN_BREAKPOINT 3
#define IN_OVERFLOW 4
#define IN_BOUND 5
#define IN_INVALID_OPCODE 6
#define IN_NO_DEVICE 7
#define IN_DOUBLE_FAULT 8
#define IN_CP_OVERRUN 9
#define IN_INVALID_TSS 10
#define IN_NO_SEGMENT 11
#define IN_STACK_FAULT 12
#define IN_PROTECTION_FAULT 13
#define IN_PAGE_FAULT 14
#define IN_RESERVED 15
#define IN_CP_ERROR 16
#define IN_ALIGNMENT 17
#define IN_MACHINE_CHECK 18
#define IN_SIMD 19
/* 20 - 31 unassigned, Intel reserved exceptions */
/* 32 - 255 user defined interrupt vectors */
#ifndef _ASMLANGUAGE
/* macros to convert interrupt vectors <-> interrupt numbers */
#define IVEC_TO_INUM(intVec) ((int) (intVec) >> 3)
#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *) ((intNum) << 3))
/* exception vector address/offset */
#define IV_DIVIDE_ERROR INUM_TO_IVEC (IN_DIVIDE_ERROR)
#define IV_DEBUG INUM_TO_IVEC (IN_DEBUG)
#define IV_NON_MASKABLE INUM_TO_IVEC (IN_NON_MASKABLE)
#define IV_BREAKPOINT INUM_TO_IVEC (IN_BREAKPOINT)
#define IV_OVERFLOW INUM_TO_IVEC (IN_OVERFLOW)
#define IV_BOUND INUM_TO_IVEC (IN_BOUND)
#define IV_INVALID_OPCODE INUM_TO_IVEC (IN_INVALID_OPCODE)
#define IV_NO_DEVICE INUM_TO_IVEC (IN_NO_DEVICE)
#define IV_DOUBLE_FAULT INUM_TO_IVEC (IN_DOUBLE_FAULT)
#define IV_CP_OVERRUN INUM_TO_IVEC (IN_CP_OVERRUN)
#define IV_INVALID_TSS INUM_TO_IVEC (IN_INVALID_TSS)
#define IV_NO_SEGMENT INUM_TO_IVEC (IN_NO_SEGMENT)
#define IV_STACK_FAULT INUM_TO_IVEC (IN_STACK_FAULT)
#define IV_PROTECTION_FAULT INUM_TO_IVEC (IN_PROTECTION_FAULT)
#define IV_PAGE_FAULT INUM_TO_IVEC (IN_PAGE_FAULT)
#define IV_RESERVED INUM_TO_IVEC (IN_RESERVED)
#define IV_CP_ERROR INUM_TO_IVEC (IN_CP_ERROR)
#define IV_ALIGNMENT INUM_TO_IVEC (IN_ALIGNMENT)
#define IV_MACHINE_CHECK INUM_TO_IVEC (IN_MACHINE_CHECK)
#define IV_SIMD INUM_TO_IVEC (IN_SIMD)
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCivI86h */
vxworks-6.9/target/h/arch/i86/mmuI86Lib.h
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/* mmuI86Lib.h - mmuI86Lib header for i86. */
/* Copyright 1984-2003 Wind River Systems, Inc. */
/*
modification history
--------------------
01g,24jun04,zmm Ported from mmuPro32Lib.h version 01f to P5 MMU.
01f,12jun02,hdn added arch specific VM library APIs' prototype
01e,22aug01,hdn moved GDT and GDT_ENTRIES to regsI86.h
01d,13may98,hdn added PAGE_SIZE_XXX and _ASMLANGUAGE macros.
01c,07jan95,hdn added GDT and GDT_ENTRIES.
01b,01nov94,hdn added MMU_STATE_CACHEABLE_WT for Pentium.
01a,26jul93,hdn written based on mc68k's version.
*/
#ifndef __INCmmuI86Libh
#define __INCmmuI86Libh
#ifdef __cplusplus
extern "C" {
#endif
#define PAGE_SIZE 0x1000
#define PAGE_BLOCK_SIZE 0x400000
#define PAGE_SIZE_4KB 0x1000
#define PAGE_SIZE_4MB 0x400000
#define N_PTES 1024
#define N_PDES 1024
#define DIRECTORY_BITS 0xffc00000
#define TABLE_BITS 0x003ff000
#define OFFSET_BITS_4KB 0x00000fff
#define DIRECTORY_INDEX 22
#define TABLE_INDEX 12
#define PTE_TO_ADDR_4KB 0xfffff000
#define PTE_INVALID PTE_TO_ADDR_4KB
#define PDE_INVALID PTE_INVALID
#define ADDR_TO_PAGE 12
#define ADDR_TO_PAGEBASE 0xffc00000
#ifndef _ASMLANGUAGE
typedef struct
{
unsigned present:1;
unsigned rw:1;
unsigned us:1;
unsigned pwt:1;
unsigned pcd:1;
unsigned access:1;
unsigned dirty:1;
unsigned zero:2;
unsigned avail:3;
unsigned page:20;
} PTE_FIELD;
typedef union pte
{
PTE_FIELD field;
unsigned int bits;
} PTE;
typedef struct mmuTransTblStruct
{
PTE *pDirectoryTable;
INT32 pageSize; /* Fixed size 4K or 4M if !mixed */
BOOL mixed; /* TRUE if mixed size pages */
} MMU_TRANS_TBL;
#define MMU_STATE_MASK_VALID 0x001
#define MMU_STATE_MASK_WRITABLE 0x002
#define MMU_STATE_MASK_USER 0x004
#define MMU_STATE_MASK_PROTECTION 0x006
#define MMU_STATE_MASK_WRITETHROUGH 0x008
#define MMU_STATE_MASK_WBACK 0x008
#define MMU_STATE_MASK_CACHEABLE 0x018 /* 0x018 was 0x10 in AE version */
#define MMU_STATE_MASK_GLOBAL 0x100
#define MMU_STATE_MASK_STATE 0x11f
#define MMU_STATE_VALID 0x001
#define MMU_STATE_VALID_NOT 0x000
#define MMU_STATE_WRITABLE 0x002
#define MMU_STATE_WRITABLE_NOT 0x000
#define MMU_STATE_USER 0x004
#define MMU_STATE_USER_NOT 0x000
#define MMU_STATE_WRITETHROUGH 0x008
#define MMU_STATE_WBACK 0x000
#define MMU_STATE_COPYBACK 0x000
#define MMU_STATE_CACHEABLE_NOT 0x018 /* 0x18 was 0x10 in AE version */
#define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT
#define MMU_STATE_CACHEABLE 0x000
#define MMU_STATE_GLOBAL 0x100
#define MMU_STATE_GLOBAL_NOT 0x000
#define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT) /* 0x0 */
#define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT) /* 0x4 */
#define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE) /* 0x2 */
#define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE) /* 0x6 */
/* wpOff is used to temporarily override supervisor write-protection.
* When using wpOff, interrupts should
* be locked because this disables write-protection system wide!
* Before unlocking interrupts, be sure to do a wpOn().
*/
#define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff)
#define wpOn() vxCr0Set (vxCr0Get() | 0x00010000)
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS mmuI86LibInit (int pageSize);
extern STATUS mmuI86Enable (BOOL enable);
extern void mmuI86On ();
extern void mmuI86Off ();
extern void mmuI86TLBFlush ();
extern void mmuI86PdbrSet (MMU_TRANS_TBL *transTbl);
extern void mmuI86Show (MMU_TRANS_TBL *transTbl, void * vaddr);
extern MMU_TRANS_TBL *mmuI86PdbrGet ();
#else /* __STDC__ */
extern STATUS mmuI86LibInit ();
extern STATUS mmuI86Enable ();
extern void mmuI86On ();
extern void mmuI86Off ();
extern void mmuI86TLBFlush ();
extern void mmuI86PdbrSet ();
extern void mmuI86Show ();
extern MMU_TRANS_TBL *mmuI86PdbrGet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuI86Libh */
vxworks-6.9/target/h/arch/i86/mmuPro32Lib.h
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/* mmuPro32Lib.h - mmuPpro32Lib header for i86. */
/*
* Copyright (c) 1984-2003, 2009, 2011, 2014, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01k,18jul18,hbu kernel page table isolation support (F10571)
01j,02may14,jb VXW6-81787 - add Intel Write Combining Option
01i,19jan11,jb Fix for WIND00185635 - mmu deoptimize locks do not work
01h,08sep09,rbc WIND00177961 - vmStateSet() can no longer been called from an
ISR
01g,21apr09,rbc Page Table Optimization.
01f,09dec03,zmm Ported to Base6 from AE version of mmuPro32Lib.h 01f,30nov99
01e,12jun02,hdn added arch specific VM library APIs' prototype
01d,23may02,hdn replaced PAGE_SIZE with PD_SIZE and PT_SIZE
01c,22aug01,hdn moved GDT and GDT_ENTRIES to regsI86.h
01b,13may98,hdn added _ASMLANGUAGE macro.
01a,11apr97,hdn written.
*/
#ifndef __INCmmuPro32Libh
#define __INCmmuPro32Libh
#ifdef __cplusplus
extern "C" {
#endif
#define PAGE_SIZE 0x1000
#define PAGE_BLOCK_SIZE 0x400000
#define PAGE_SIZE_4KB 0x1000
#define PAGE_SIZE_4MB 0x400000
#ifdef _WRS_CONFIG_KPTI
#define PD_TBL_SIZE (2 * PAGE_SIZE_4KB)
#define MMU_UMTBL_OFFSET (PAGE_SIZE_4KB)
#else
#define PD_TBL_SIZE PAGE_SIZE_4KB
#endif
#define N_PTES 1024
#define N_PDES 1024
#define DIRECTORY_BITS 0xffc00000
#define TABLE_BITS 0x003ff000
#define OFFSET_BITS_4KB 0x00000fff
#define OFFSET_BITS_4MB 0x003fffff
#define DIRECTORY_INDEX 22
#define TABLE_INDEX 12
#define PTE_TO_ADDR_4KB 0xfffff000
#define PTE_TO_ADDR_4MB 0xffc00000
#define PTE_INVALID PTE_TO_ADDR_4KB
#define PDE_INVALID PTE_TO_ADDR_4MB
#define PAGES_PER_BLOCK 0x400
#define ADDR_TO_PAGE 12
#define ADDR_TO_PAGEBASE 22
#ifndef _ASMLANGUAGE
#define PAGE_TABLE_PRESENT 1
#define PAGE_TABLE_RW 1
#define PAGE_TABLE_US 1
#define PAGE_TABLE_PWT 1
#define PAGE_TABLE_PCD 1
#define PAGE_TABLE_ACCESS 1
#define PAGE_TABLE_DIRTY 1
#define PAGE_TABLE_4KB 0
#define PAGE_TABLE_4MB 1
#define PAGE_TABLE_GLOBAL 1
/* Define use of hardware available bits */
#define PAGE_TABLE_AVAIL_MASK 0x7
#define PAGE_TABLE_MASK_NO_BLOCK 0x1
#define PAGE_TABLE_NO_BLOCK 0x1
typedef struct
{
unsigned present:1;
unsigned rw:1;
unsigned us:1;
unsigned pwt:1;
unsigned pcd:1;
unsigned access:1;
unsigned dirty:1;
unsigned pagesize:1;
unsigned global:1;
unsigned avail:3;
unsigned page:20;
} PTE_FIELD;
typedef union pte
{
PTE_FIELD field;
unsigned int bits;
} PTE;
typedef struct mmuTransTblStruct
{
PTE *pDirectoryTable;
PTE *pAltDirectoryTable;
VX_SEMAPHORE(mmuTransTblSem);
} MMU_TRANS_TBL;
#if (_VX_CPU != _VX_PENTIUM)
typedef union mmuPatReg
{
UINT64 mmuFullPat;
UINT32 mmuHalfPat[2];
UCHAR mmuCharPat[8];
} MMU_PAT_REG;
#define IA32_PAT_MSR 0x277
#define IA32_PAT_WC_IDX 0x02
#define IA32_PAT_WC 0x01
#endif /* (_VX_CPU != _VX_PENTIUM) */
#define MMU_STATE_MASK_VALID 0x001
#define MMU_STATE_MASK_WRITABLE 0x002
#define MMU_STATE_MASK_USER 0x004
#define MMU_STATE_MASK_PROTECTION 0x006
#define MMU_STATE_MASK_WRITETHROUGH 0x008
#define MMU_STATE_MASK_WBACK 0x008
#define MMU_STATE_MASK_CACHEABLE 0x018 /* 0x018 was 0x10 in AE version */
#define MMU_STATE_MASK_GLOBAL 0x100
#define MMU_STATE_MASK_NO_BLOCK 0x200
#ifdef _WRS_CONFIG_KPTI
#define MMU_STATE_MASK_UMPT 0x800
#define MMU_STATE_MASK_STATE 0xb1f
#else
#define MMU_STATE_MASK_STATE 0x31f
#endif
#define MMU_STATE_VALID 0x001
#define MMU_STATE_VALID_NOT 0x000
#define MMU_STATE_WRITABLE 0x002
#define MMU_STATE_WRITABLE_NOT 0x000
#define MMU_STATE_USER 0x004
#define MMU_STATE_USER_NOT 0x000
#define MMU_STATE_WRITETHROUGH 0x008
#define MMU_STATE_WBACK 0x000
#define MMU_STATE_COPYBACK 0x000
#define MMU_STATE_CACHEABLE_NOT 0x018 /* 0x18 was 0x10 in AE version */
#define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT
#if (_VX_CPU != _VX_PENTIUM)
#define MMU_STATE_MASK_WCOMBINE MMU_STATE_MASK_CACHEABLE
#define MMU_STATE_WCOMBINE 0x010 /* This requires mod to default PAT Table */
#define MMU_STATE_WCOMBINE_NOT 0x000
#endif /* (_VX_CPU != _VX_PENTIUM) */
#define MMU_STATE_CACHEABLE 0x000
#define MMU_STATE_GLOBAL 0x100
#define MMU_STATE_GLOBAL_NOT 0x000
#define MMU_STATE_NO_BLOCK 0x200
#define MMU_STATE_NO_BLOCK_NOT 0x000
#ifdef _WRS_CONFIG_KPTI
#define MMU_STATE_UMPT 0x800
#define MMU_STATE_UMPT_NOT 0x000
#endif
#define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT) /* 0x0 */
#define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT) /* 0x4 */
#define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE) /* 0x2 */
#define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE) /* 0x6 */
/* wpOff is used to temporarily override supervisor write-protection.
* When using wpOff, interrupts should
* be locked because this disables write-protection system wide!
* Before unlocking interrupts, be sure to do a wpOn().
*/
#define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff)
#define wpOn() vxCr0Set (vxCr0Get() | 0x00010000)
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS mmuPro32LibInit (int pageSize);
extern STATUS mmuPro32Enable (BOOL enable);
extern void mmuPro32On ();
extern void mmuPro32Off ();
extern void mmuPro32TLBFlush ();
extern void mmuPro32PdbrSet (MMU_TRANS_TBL *transTbl);
extern void mmuPro32Show (MMU_TRANS_TBL *transTbl, void * vaddr);
extern MMU_TRANS_TBL *mmuPro32PdbrGet ();
#else /* __STDC__ */
extern STATUS mmuPro32LibInit ();
extern STATUS mmuPro32Enable ();
extern void mmuPro32On ();
extern void mmuPro32Off ();
extern void mmuPro32TLBFlush ();
extern void mmuPro32PdbrSet ();
extern void mmuPro32Show ();
extern MMU_TRANS_TBL *mmuPro32PdbrGet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuPro32Libh */
vxworks-6.9/target/h/arch/i86/mmuPro36Lib.h
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/* mmuPro36Lib.h - mmuPro36Lib header for i86. */
/* Copyright 1984-2002, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01g,29apr10,pad Moved extern C statement after include statements.
01f,07apr04,scm Ported to Base6 ...
01e,12jun02,hdn added arch specific VM library APIs' prototype
01d,06jun02,hdn replaced PAGE_SIZE with PD_SIZE and PT_SIZE
01c,22aug01,hdn moved GDT and GDT_ENTRIES to regsI86.h
01b,13may98,hdn added _ASMLANGUAGE macro.
01a,11apr97,hdn written.
*/
#ifndef __INCmmuPro36Libh
#define __INCmmuPro36Libh
#include "arch/i86/pentiumLib.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PAGE_SIZE_4KB 0x1000
#define PAGE_SIZE_2MB 0x200000
#define PAGE_BLOCK_SIZE 0x200000
#define N_PTPTRS 4
#define N_PTES 512
#define N_PDES 512
#define DIR_PTR_BITS 0xc0000000
#define DIR_BITS 0x3fe00000
#define TBL_BITS 0x001ff000
#define OFFSET_BITS_4KB 0x00000fff
#define OFFSET_BITS_2MB 0x001fffff
#define DIR_PTR_BITS 0xc0000000
#define DIR_BITS 0x3fe00000
#define TBL_BITS 0x001ff000
#define DIR_PTR_INDEX 30
#define DIR_INDEX 21
#define TBL_INDEX 12
#define PTE_TO_ADDR_4KB 0xfffff000
#define PTE_TO_ADDR_2MB 0xffe00000
#define PDP_TO_ADDR 0xfffff000
#define PTE_INVALID PTE_TO_ADDR_4KB
#define PDE_INVALID PTE_INVALID
#define ADDR_TO_PAGE 12
#define ADDR_TO_PAGEBASE 0xffe00000
#ifndef _ASMLANGUAGE
typedef struct
{
unsigned present:1;
unsigned rw:1;
unsigned us:1;
unsigned pwt:1;
unsigned pcd:1;
unsigned access:1;
unsigned dirty:1;
unsigned pagesize:1;
unsigned global:1;
unsigned avail:3;
unsigned page:20;
unsigned page36:4;
unsigned reserved:28;
} PTE_FIELD;
typedef union pte
{
PTE_FIELD field;
UINT bits[2];
} PTE;
typedef struct mmuTransTblStruct
{
PTE * pDirectoryPtrTable; /* pointer to dir ptr tbl */
INT32 pageSize; /* 4K, 2M */
} MMU_TRANS_TBL;
#define MMU_STATE_MASK_VALID 0x001
#define MMU_STATE_MASK_WRITABLE 0x002
#define MMU_STATE_MASK_USER 0x004
#define MMU_STATE_MASK_PROTECTION 0x006
#define MMU_STATE_MASK_WRITETHROUGH 0x008
#define MMU_STATE_MASK_WBACK 0x008
#define MMU_STATE_MASK_CACHEABLE 0x018 /* 0x018 was 0x10 in AE version */
#define MMU_STATE_MASK_GLOBAL 0x100
#define MMU_STATE_MASK_STATE 0x11f
#define MMU_STATE_VALID 0x001
#define MMU_STATE_VALID_NOT 0x000
#define MMU_STATE_WRITABLE 0x002
#define MMU_STATE_WRITABLE_NOT 0x000
#define MMU_STATE_USER 0x004
#define MMU_STATE_USER_NOT 0x000
#define MMU_STATE_WRITETHROUGH 0x008
#define MMU_STATE_WBACK 0x000
#define MMU_STATE_COPYBACK 0x000
#define MMU_STATE_CACHEABLE_NOT 0x018 /* 0x18 was 0x10 in AE version */
#define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT
#define MMU_STATE_CACHEABLE 0x000
#define MMU_STATE_GLOBAL 0x100
#define MMU_STATE_GLOBAL_NOT 0x000
#define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT) /* 0x0 */
#define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT) /* 0x4 */
#define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE) /* 0x2 */
#define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE) /* 0x6 */
/* wpOff is used to temporarily override supervisor write-protection.
* When using wpOff, interrupts should
* be locked because this disables write-protection system wide!
* Before unlocking interrupts, be sure to do a wpOn().
*/
#define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff)
#define wpOn() vxCr0Set (vxCr0Get() | 0x00010000)
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS mmuPro36LibInit (int pageSize);
extern STATUS mmuPro36Enable (BOOL enable);
extern void mmuPro36On ();
extern void mmuPro36Off ();
extern void mmuPro36TLBFlush ();
extern void mmuPro36PdbrSet (MMU_TRANS_TBL *transTbl);
extern void mmuPro36Show (MMU_TRANS_TBL *transTbl, VIRT_ADDR vaddr);
extern MMU_TRANS_TBL *mmuPro36PdbrGet ();
#else /* __STDC__ */
extern STATUS mmuPro36LibInit ();
extern STATUS mmuPro36Enable ();
extern void mmuPro36On ();
extern void mmuPro36Off ();
extern void mmuPro36TLBFlush ();
extern void mmuPro36PdbrSet ();
extern void mmuPro36Show ();
extern MMU_TRANS_TBL *mmuPro36PdbrGet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuPro36Libh */
vxworks-6.9/target/h/arch/i86/pentiumLib.h
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/* pentiumLib.h - system dependent routines header */
/*
* Copyright 1997, 2001-2002, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01g,21may12,c_t Add pentiumUsDelay.(WIND00338455)
01f,04may11,scm WIND00238999, adjust parameters for 64 bits...
01e,29apr10,pad Moved extern C statement after include statements.
01d,15jun02,hdn added LL_UNION typedef for 36bit MMU support
01c,01nov01,hdn added PENTIUM_MSR, pentiumMsrInit/Show's prototype
01b,21aug01,hdn included regs.h for MTRR_ID.
added P5/P6 PMC routines.
01a,09jul97,hdn written
*/
#ifndef __INCpentiumLibh
#define __INCpentiumLibh
#ifndef _ASMLANGUAGE
#include "regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* typedefs */
typedef long long int LL_INT;
typedef union llUnion
{
long long int i64; /* 64bit integer */
int i32[2]; /* 32bit integer * 2 */
} LL_UNION;
typedef struct pentiumMsr
{
INT32 addr; /* address of the MSR */
INT8 * name; /* name of the MSR */
} PENTIUM_MSR;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern int pentiumCr4Get (void);
extern void pentiumCr4Set (size_t cr4);
extern STATUS pentiumPmcStart (int pmcEvtSel0, int pmcEvtSel1);
extern STATUS pentiumPmcStart0 (int pmcEvtSel0);
extern STATUS pentiumPmcStart1 (int pmcEvtSel1);
extern void pentiumPmcStop (void);
extern void pentiumPmcStop0 (void);
extern void pentiumPmcStop1 (void);
extern void pentiumPmcGet (long long int * pPmc0,
long long int * pPmc1);
extern void pentiumPmcGet0 (long long int * pPmc0);
extern void pentiumPmcGet1 (long long int * pPmc1);
extern void pentiumPmcReset (void);
extern void pentiumPmcReset0 (void);
extern void pentiumPmcReset1 (void);
extern STATUS pentiumP6PmcStart (int pmcEvtSel0, int pmcEvtSel1);
extern void pentiumP6PmcStop (void);
extern void pentiumP6PmcStop1 (void);
extern void pentiumP6PmcGet (long long int * pPmc0,
long long int * pPmc1);
extern void pentiumP6PmcGet0 (long long int * pPmc0);
extern void pentiumP6PmcGet1 (long long int * pPmc1);
extern void pentiumP6PmcReset (void);
extern void pentiumP6PmcReset0 (void);
extern void pentiumP6PmcReset1 (void);
extern STATUS pentiumP5PmcStart0 (int cesr);
extern STATUS pentiumP5PmcStart1 (int cesr);
extern void pentiumP5PmcStop0 (void);
extern void pentiumP5PmcStop1 (void);
extern void pentiumP5PmcGet (long long int * pPmc0,
long long int * pPmc1);
extern void pentiumP5PmcGet0 (long long int * pPmc0);
extern void pentiumP5PmcGet1 (long long int * pPmc1);
extern void pentiumP5PmcReset (void);
extern void pentiumP5PmcReset0 (void);
extern void pentiumP5PmcReset1 (void);
extern void pentiumTscGet64 (long long int * pTsc);
extern UINT32 pentiumTscGet32 (void);
extern void pentiumTscReset (void);
extern void pentiumMsrGet (size_t addr, long long int * pData);
extern void pentiumMsrSet (size_t addr, long long int * pData);
extern void pentiumTlbFlush (void);
extern void pentiumSerialize (void);
extern STATUS pentiumBts (char * pFlag);
extern STATUS pentiumBtc (char * pFlag);
extern void pentiumMtrrEnable (void);
extern void pentiumMtrrDisable (void);
extern STATUS pentiumMtrrGet (MTRR_ID pMtrr);
extern STATUS pentiumMtrrSet (MTRR_ID pMtrr);
extern void pentiumPmcShow (BOOL zap);
extern STATUS pentiumMsrInit (void);
extern void pentiumMsrShow (void);
extern void pentiumMcaEnable (BOOL enable);
extern void pentiumMcaShow (void);
extern void pentiumTSCDelay (int uSec);
#else /* __STDC__ */
extern int pentiumCr4Get ();
extern void pentiumCr4Set ();
extern STATUS pentiumPmcStart ();
extern STATUS pentiumPmcStart0 ();
extern STATUS pentiumPmcStart1 ();
extern void pentiumPmcStop ();
extern void pentiumPmcStop0 ();
extern void pentiumPmcStop1 ();
extern void pentiumPmcGet ();
extern void pentiumPmcGet0 ();
extern void pentiumPmcGet1 ();
extern void pentiumPmcReset ();
extern void pentiumPmcReset0 ();
extern void pentiumPmcReset1 ();
extern STATUS pentiumP6PmcStart ();
extern void pentiumP6PmcStop ();
extern void pentiumP6PmcStop1 ();
extern void pentiumP6PmcGet ();
extern void pentiumP6PmcGet0 ();
extern void pentiumP6PmcGet1 ();
extern void pentiumP6PmcReset ();
extern void pentiumP6PmcReset0 ();
extern void pentiumP6PmcReset1 ();
extern STATUS pentiumP5PmcStart0 ();
extern STATUS pentiumP5PmcStart1 ();
extern void pentiumP5PmcStop0 ();
extern void pentiumP5PmcStop1 ();
extern void pentiumP5PmcGet ();
extern void pentiumP5PmcGet0 ();
extern void pentiumP5PmcGet0 ();
extern void pentiumP5PmcGet1 ();
extern void pentiumP5PmcReset ();
extern void pentiumP5PmcReset0 ();
extern void pentiumTscGet64 ();
extern UINT32 pentiumTscGet32 ();
extern void pentiumTscReset ();
extern void pentiumMsrGet ();
extern void pentiumMsrSet ();
extern void pentiumTlbFlush ();
extern void pentiumSerialize ();
extern STATUS pentiumBts ();
extern STATUS pentiumBtc ();
extern void pentiumMtrrEnable ();
extern void pentiumMtrrDisable ();
extern STATUS pentiumMtrrGet ();
extern STATUS pentiumMtrrSet ();
extern void pentiumPmcShow ();
extern STATUS pentiumMsrInit ();
extern void pentiumMsrShow ();
extern void pentiumMcaEnable ();
extern void pentiumMcaShow ();
extern void pentiumTSCDelay ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCpentiumLibh */
vxworks-6.9/target/h/arch/i86/perMonLib.h
+266
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@@ -0,0 +1,266 @@
/* perMonLib.h - Performance Monitoring mechanism definitions header file */
/* Copyright 2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,30jul01,hdn written
*/
#ifndef __INCperMonLibh
#define __INCperMonLibh
#ifdef __cplusplus
extern "C" {
#endif
/* performance monitoring, number of counters, etc */
#define PM_N_COUNTER 18
#define EVENT_N_ESCR 2
#define EVENT_N_COUNTER 3
#define MSR_N_ESCR 8
/* performance monitoring event name/no */
#define PM_BRANCH_RETIRED 0
#define PM_MISPRED_BRANCH_RETIRED 1
#define PM_TC_DELIVER_MODE 2
#define PM_BPU_FETCH_REQUEST 3
#define PM_ITLB_REFERENCE 4
#define PM_MEMORY_CANCEL 5
#define PM_MEMORY_COMPLETE 6
#define PM_LOAD_PORT_REPLAY 7
#define PM_STORE_PORT_REPLAY 8
#define PM_MOB_LOAD_REPLAY 9
#define PM_PAGE_WALK_TYPE 10
#define PM_BSQ_2NDL_CACHE_REF 11
#define PM_IOQ_ALLOCATION 12
#define PM_FSB_DATA_ACTIVITY 13
#define PM_BSQ_ALLOCATION 14
#define PM_X87_ASSIST 15
#define PM_SSE_INPUT_ASSIST 16
#define PM_PACKED_SP_UOP 17
#define PM_PACKED_DP_UOP 18
#define PM_SCALAR_SP_UOP 19
#define PM_SCALAR_DP_UOP 20
#define PM_64BIT_MMX_UOP 21
#define PM_128BIT_MMX_UOP 22
#define PM_X87_FP_UOP 23
#define PM_X87_SIMD_MOVES_UOP 24
#define PM_MACHINE_CLEAR 25
#define PM_FRONT_END_EVENT 26
#define PM_EXECUTION_EVENT 27
#define PM_REPLAY_EVENT 28
#define PM_INSTR_RETIRED 29
#define PM_UOPS_RETIRED 30
/* metrics available for Front_end Tagging */
#define FRONT_MEMORY_LOADS 0
#define FRONT_MEMORY_STORES 1
/* metrics available for Execution Tagging */
#define EXEC_PACKED_SP_RETIRED 0
#define EXEC_PACKED_DP_RETIRED 1
#define EXEC_SCALAR_SP_RETIRED 2
#define EXEC_SCALAR_DP_RETIRED 3
#define EXEC_128BIT_MMX_RETIRED 4
#define EXEC_64BIT_MMX_RETIRED 5
#define EXEC_X87_FP_RETIRED 6
#define EXEC_X87_SIMD_MM_RETIRED 7
/* metrics available for Replay Tagging */
#define REPLAY_1CACHE_LOAD_MISS_RETIRED 0
#define REPLAY_2CACHE_LOAD_MISS_RETIRED 1
#define REPLAY_DTLB_LOAD_MISS_RETIRED 2
#define REPLAY_DTLB_STORE_MISS_RETIRED 3
#define REPLAY_DTLB_ALL_MISS_RETIRED 4
#define REPLAY_MOB_LOAD_REPLAY_RETIRED 5
#define REPLAY_SPLIT_LOAD_RETIRED 6
#define REPLAY_SPLIT_STORE_RETIRED 7
/* event mask available for Replay Tagging */
#define PARTIAL_DATA 0x10
#define UNALIGN_ADDR 0x20
#define SPLIT_LD 0x02
#define SPLIT_ST 0x02
/* CCCR bit definitions */
#define CCCR_ENABLE 0x00001000
#define CCCR_ENABLE_NOT 0xffffefff
#define CCCR_ESCR_SELECT 0x0000e000
#define CCCR_RSVD 0x00030000
#define CCCR_COMPARE 0x00040000
#define CCCR_COMPLIMENT 0x00080000
#define CCCR_THRESHOLD 0x00f00000
#define CCCR_EDGE 0x01000000
#define CCCR_FORCE_OVF 0x02000000
#define CCCR_OVF_PMI 0x04000000
#define CCCR_CASCADE 0x40000000
#define CCCR_OVF 0x80000000
/* ESCR bit definitions */
#define ESCR_USR 0x00000004
#define ESCR_OS 0x00000008
#define ESCR_TAG_ENABLE 0x00000010
#define ESCR_TAG_VALUE 0x000001e0
#define ESCR_EVENT_MASK 0x01fffe00
#define ESCR_EVENT_SELECT 0x7e000000
/* Replay Event Mask definitions */
#define REPLAY_NBOGUS 0x00000001
#define REPLAY_BOGUS 0x00000002
/* Execution Event Mask definitions */
#define EXEC_NBOGUS0 0x00000001
#define EXEC_NBOGUS1 0x00000002
#define EXEC_NBOGUS2 0x00000004
#define EXEC_NBOGUS3 0x00000008
#define EXEC_BOGUS0 0x00000010
#define EXEC_BOGUS1 0x00000020
#define EXEC_BOGUS2 0x00000040
#define EXEC_BOGUS3 0x00000080
#ifndef _ASMLANGUAGE
typedef struct perMonMsr /* PM CCCR-ESCR table */
{
short counter;
short cccr;
short escr[MSR_N_ESCR];
} PER_MON_MSR;
typedef struct perMonMsrUse /* PM MSRs selected and its value */
{
BOOL used;
int escrMsr;
int counterValue;
int cccrValue;
int escrValue;
int pebsEnable;
int pebsMatrix;
} PER_MON_MSR_USE;
typedef struct perMonEvent /* PM event table */
{
char * name;
short escr[EVENT_N_ESCR];
char counterNo[EVENT_N_ESCR][EVENT_N_COUNTER];
int eventSelect;
int eventMask;
int cccrSelect;
BOOL pebs;
} PER_MON_EVENT;
typedef struct perMonReplayTag /* Replay Tagging Metrics table */
{
char * name;
int pebsEnable;
int pebsMatrix;
int upEvent;
int upEventMask;
int eventMask;
} PER_MON_REPLAY_TAG;
typedef struct perMonExecTag /* Execution Tagging Metrics table */
{
char * name;
int upEvent;
int upEventMask;
int upTagValue;
int eventMask;
} PER_MON_EXEC_TAG;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void perMonLibInit (void);
extern STATUS perMonInt (void);
extern int perMonCget32 (int counterNo);
extern long long int perMonCget40 (int counterNo);
extern void perMonCenable (int cccr);
extern void perMonCdisable (int cccr);
extern void perMonIntEnable (void);
extern void perMonIntDisable (void);
extern int perMonCccrGet (int counterNo, PER_MON_MSR_USE * pMsrUse);
extern void perMonCccrSet (int counterNo, int value,
PER_MON_MSR_USE *pMsrUse);
extern int perMonEscrGet (int counterNo, PER_MON_MSR_USE *pMsrUse);
extern void perMonEscrSet (int counterNo, int value,
PER_MON_MSR_USE *pMsrUse);
extern void perMonOsSet (int counterNo, PER_MON_MSR_USE * pMsrUse);
extern void perMonUsrSet (int counterNo, PER_MON_MSR_USE * pMsrUse);
extern void perMonIntSet (int counterNo, PER_MON_MSR_USE * pMsrUse);
extern void perMonIntClear (int counterNo, PER_MON_MSR_USE * pMsrUse);
extern void perMonCset (int counterNo, long long int * pValue);
extern void perMonCstart (int counterNo);
extern void perMonCstop (int counterNo);
extern STATUS perMonEventSelect (int event, int escrMsr, int counterNo,
int eventMask, int * pCounterMsr,
int * pCccrMsr, int * pCccrValue,
int * pEscrValue);
extern STATUS perMonReplaySelect (int metric, int * pUpEvent, int * pUpEventM,
int * pPebsEnable, int * pPebsMatrix,
int * pEventMask);
extern STATUS perMonExecSelect (int metric, int * pUpEvent, int * pUpEventM,
int * pUpTagValue, int * pEventMask);
extern STATUS perMonEventSet (int event, int escrMsr, int counterNo,
int eventMask, int metric, int upEventNo,
int upEscrMsr, int upCounterNo,
PER_MON_MSR_USE * pMsrUse);
extern STATUS perMonMsrSet (PER_MON_MSR_USE * pMsrUse);
#else /* __STDC__ */
extern void perMonLibInit ();
extern STATUS perMonInt ();
extern int perMonCget32 ();
extern long long int perMonCget40 ();
extern void perMonCenable ();
extern void perMonCdisable ();
extern void perMonIntEnable ();
extern void perMonIntDisable ();
extern int perMonCccrGet ();
extern void perMonCccrSet ();
extern int perMonEscrGet ();
extern void perMonEscrSet ();
extern void perMonOsSet ();
extern void perMonUsrSet ();
extern void perMonIntSet ();
extern void perMonIntClear ();
extern void perMonCset ();
extern void perMonCstart ();
extern void perMonCstop ();
extern STATUS perMonEventSelect ();
extern STATUS perMonReplaySelect ();
extern STATUS perMonExecSelect ();
extern STATUS perMonEventSet ();
extern STATUS perMonMsrSet ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCperMonLibh */
vxworks-6.9/target/h/arch/i86/private/smpI86P.h
+421
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@@ -0,0 +1,421 @@
/* smpI86P.h - i80x86 private SMP assembler definitions header file */
/*
* Copyright (c) 2006-2013, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
02n,18jul18,r_h Add kernel page table isolation support (F10571)
02m,16may13,scm WIND00417700 SMP diab macro correction...
02l,09jan13,scm WIND00229494 - SMP dedicated segment register
02k,20dec12,yjw clear warning when load symbol table.(WIND00380360)
02j,11sep12,cwl Correct the macro _WRS_WIND_VARS_ARCH_GET for UP.
(WIND00375599)
02i,27jan12,scm WIND00326315 - live lock osm & cpc issue...
02h,10aug11,zl added _WRS_CPU_SMTSET_GET()
02g,04jan11,scm WIND00248698 adjust vxIntStackEnabled to type BOOL...
02f,12nov10,pch CQ240922: exclude refs to OSM when small footprint selected
02e,25oct10,rbc WIND00204240 - Add support for objVerifiedSafe.
02d,29jul10,pad Moved extern C statement after include statements.
02c,24may10,jb Mods for SMP M-N support
02b,05may10,jl add support for SMP GuestOS
02a,07may09,pee using generated offsets. Removing hardcoded offsets.
01z,15may09,gls moved VX_INSTR_BARRIER() to vxAtomicArchLibCommon.h
01y,12feb09,sem Added sysCr3 to the WIND_VARS_ARCH struct
Added sysCr3 access macros
01x,18sep08,gls added _WRS_KERNEL_LOCK_VAR_ALIGN
01w,27aug08,jpb Renamed VSB header file
01v,30jul08,rbc Fix undefines for _IA32_LOC_APIC_ID...
01u,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01t,20jun08,zl replaced _WRS_ASM() with _WRS_BARRIER()
01s,22apr08,zl ensure 32-bit _IA32_LOC_APIC_ID register access.
01r,10jan08,gls added VX_INSTR_BARRIER()
01q,01aug07,scm optimize _WRS_CPU_INDEX_GET()...
01p,31may07,scm add _IA32_CPU_ADRS_BASE_GET macro...
01o,04may07,scm correct _IA32_PER_CPU_VALUE_SET macro...
01m,17apr07,kk move VX_MAX_SMP_CPUS to archI86.h
01l,11dec06,kk removed references to VX_KERNEL_VARS define, no longer needed
01k,06dec06,scm correct macro for GNU compiler support...
01j,28nov06,scm remove def for _WRS_WIND_VARS_OFFSET_archVars...
01i,02nov06,scm rename pSysGdtCurrent for backward comp with P2/3/4...
01h,26oct06,scm add per Cpu OSM Scratch memory space for GDT data manipulation
01g,05oct06,scm add translation to _IA32_CPU_INDEX_GET...
01f,03oct06,scm additional macro work...
01e,15sep06,scm add specific vxKernelVars[] support...
01d,30aug06,scm expand _WRS_WIND_VARS_ARCH...
01c,21aug06,jb Combining smpI86P.h and vxCpuLibP.h
01b,01aug06,scm more SMP work...
01a,21jul06,scm created, added SMP Support Macros...
*/
#ifndef __INCasmI86Ph
#define __INCasmI86Ph
/************************************************************/
#include <vsbConfig.h>
#include <arch/i86/archI86.h>
#include <arch/i86/regsI86.h>
#include <private/kernelLockLibP.h>
#include <hwif/cpu/arch/i86/vxCpuIdLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
/*
* 0xFEE00020 is the address of the local APIC ID Register.
*/
#define _IA32_LOC_APIC_ID 0xFEE00020
#define _IA32_CPU_INDEX_SHIFT (0x18)
#define _IA32_CPU_INDEX_MASK (0xFF)
#ifdef _WRS_CONFIG_SMP
/*
* IA32 has been adapted to use the new object safe count feature for SMP.
* When all architectures have been adapted this can be removed from
* the code.
*/
#define _WRS_ARCH_HAS_OBJ_SAFE
/*
* This macro defines the alignment requirement for the WIND_VARS structure.
*
* There are 3 factors involved in selection of this value.
*
* 1. It's definition is no LESS than the maximum value of
* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
* cache line length growth.
* 2. It must be at least as large as the WIND_VARS structure.
* 3. It must be a power of 2.
*
* For example:
* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
* (rule 1).
* If WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
* (rules 2 and 3).
*
* For KPTI the alignment has to match WIND_RTP_VARS_ARCH; for that, we need
* _WRS_WIND_RTP_VARS_ALIGN bytes.
*/
#ifdef _WRS_CONFIG_KPTI
#define _WRS_WIND_VARS_ALIGN _WRS_WIND_RTP_VARS_ALIGN
#define _WRS_WIND_VARS_ALIGN_SHIFT _WRS_WIND_RTP_VARS_ALIGN_SHIFT
#else
#define _WRS_WIND_VARS_ALIGN 128
#define _WRS_WIND_VARS_ALIGN_SHIFT 7
#endif
/*
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
* XSCALE, etc), representing the maximum cache line size of the variants of
* the respective arch.
*
* For x86 this is 128 bytes.
*/
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
#ifndef _ASMLANGUAGE
#ifdef _WRS_CONFIG_WRHV_GUEST
/*
* wrhvVbCpuId is used to store the address of the virtual-core's cpuId.
* This global contains the virtual address for the core configuration
* and avoids making a VBI function call to get the wrhvVbConfig address
* and calculate the offset to the core id..
*/
extern UINT32 *wrhvVbCpuId;
#endif /* WRS_CONFIG_WRHV_GUEST */
/* mpCpuIndexTable is used in vxCpuArchLib.c, this gloabal avoids
* calling through vxbus and reduces overhead, table translations
* are done everywhere, but once up this table should never change...
*/
extern UINT8 mpCpuIndexTable[];
typedef struct wind_vars_arch
{
GDT *cpu_pSysGdt; /* 0x4c: Global Descriptor Table */
TSS *cpu_sysTssCurrent; /* 0x50: Task State Segmnet */
TSS *cpu_excOSMTssCurrent; /* 0x54: OSM TSS */
SEGDESC *cpu_sysOSMLdtCurrent; /* 0x58: Local Descriptor Table */
UINT32 *cpu_excOSMStackCurrent; /* 0x5c: OSM Stack */
UINT32 *cpu_sysOSMGdtScratchCurrent; /* 0x60: OSM Scratch memory */
UINT32 cpu_vxIntStackPtr; /* 0x64: Interrupt Stack Pointer */
BOOL cpu_vxIntStackEnabled; /* 0x68: Interrupt Stack Enabled */
unsigned int cpu_cpuIndex; /* 0x6c: logical cpu used by GS */
UINT32 cpu_cpuGsBaseCurrent; /* 0x70: &vxKernelVars in gsbase */
UINT32 cpu_intNest; /* 0x74: Interrupt Nested Count */
UINT32 cpu_sysCr3; /* 0x78: Local CR3 cache */
UINT32 cpu_sysOSMState; /* 0x7c: OSM State Flag */
} WIND_VARS_ARCH;
#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
/* macro to access the arch-specific fields of the vxKernelVars struct */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
/*
* _WRS_CPU_SMTSET_GET() is used by the SMP scheduler for Hyper-Threading
* support.
*/
#define _WRS_CPU_SMTSET_GET(smtSet, cpuIx) \
smtSet = sysCpuIdTopology.__smtSet[cpuIx]
/* Fast retrieve of cpuIndex using GS Base register offset */
#if defined (__DCC__)
__asm volatile unsigned int _vxGsBaseCpuIndexGet_inline (void)
{
! "ax" /* ax is clobbered */
mov %gs:(0x6c), %eax
}
#else /* if defined (__GNUC__) */
static __inline__ unsigned int _vxGsBaseCpuIndexGet_inline (void)
{
unsigned int cpu;
__asm__ volatile ("mov %%gs:(0x6c), %%eax" \
: "=a" (cpu) : /* no input */);
return cpu;
}
#endif /* __DCC__ */
#endif /* !_ASMLANGUAGE */
#ifdef _WRS_CONFIG_WRHV_GUEST
#define _WRS_CPU_INDEX_GET() \
(*(volatile UINT32 *)wrhvVbCpuId)
#else /* _WRS_CONFIG_WRHV_GUEST */
#define _WRS_CPU_INDEX_GET() _vxGsBaseCpuIndexGet_inline ()
#endif /* _WRS_CONFIG_WRHV_GUEST */
#else /* _WRS_CONFIG_SMP */
#define _WRS_CPU_INDEX_GET() 0
/* macro to access the arch-specific fields */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (glob)
#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
_WRS_KERNEL_CPU_GLOBAL_GET(ignored,glob)
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
#endif /* _WRS_CONFIG_SMP */
#ifdef _ASMLANGUAGE
#include <private/windLibP.h>
#if defined(_WRS_CONFIG_SMP)
/* generated macro values required by assembly macros below */
#include <private/offsetMacrosP.h>
/* SMP support */
#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
leal FUNC(vxKernelVars),reg; \
addl $_WIND_VARS_cpu_##label##_OFFSET,reg;
#define _WRS_WIND_VARS_OFFSET(reg) \
rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
#define _IA32_ASM_EXTERN_KERNEL_GLOBALS
#ifdef _WRS_CONFIG_WRHV_GUEST
#define _IA32_CPU_INDEX_GET(reg,scratch) \
movl wrhvVbCpuId,reg; \
movl 0x0(reg),reg;
#else /* _WRS_CONFIG_WRHV_GUEST */
#define _IA32_CPU_INDEX_GET(reg,scratch) \
movl $_IA32_LOC_APIC_ID,reg; \
movl 0x0(reg),reg; \
ror $_IA32_CPU_INDEX_SHIFT,reg; \
andl $_IA32_CPU_INDEX_MASK,reg; \
leal FUNC(mpCpuIndexTable)(reg),scratch; \
mov 0x0(scratch),reg; \
andl $_IA32_CPU_INDEX_MASK,reg; \
subl FUNC(vxBaseCpuPhysIndex), reg;
#endif /* _WRS_CONFIG_WRHV_GUEST */
/*
* Obtain the address of vxKernelVars[cpuid] for the current
* CPU in register 'reg', using 'scratch' as a scratch
* variable.
*/
#define _IA32_CPU_ADRS_BASE_GET(reg,scratch) \
_IA32_CPU_INDEX_GET(reg,scratch) \
_WRS_WIND_VARS_OFFSET(reg) \
leal FUNC(vxKernelVars)(reg), reg;
#define _IA32_PER_CPU_ADRS_GET(reg,scratch,label) \
_IA32_CPU_INDEX_GET(reg,scratch) \
_WRS_WIND_VARS_OFFSET(reg) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl reg,scratch; \
leal 0x0(scratch),reg;
#define _IA32_PER_CPU_VALUE_GET(reg,scratch,label) \
_IA32_CPU_INDEX_GET(reg,scratch) \
_WRS_WIND_VARS_OFFSET(reg) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl reg,scratch; \
movl 0x0(scratch),reg;
#define _IA32_PER_CPU_VALUE_SET(regv,scr1,scr2,label) \
_IA32_CPU_INDEX_GET(scr1,scr2) \
_WRS_WIND_VARS_OFFSET(scr1) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
addl scr1,scr2; \
movl regv,0x0(scr2);
#define _IA32_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,scratch,label) \
_IA32_CPU_INDEX_GET(regv,scratch) \
_WRS_WIND_VARS_OFFSET(regv) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl regv,scratch; \
leal 0x0(scratch),rega; \
movl 0x0(scratch),regv;
#define _IA32_PER_CPU_VALUE_INC(reg,scratch,label) \
_IA32_CPU_INDEX_GET(reg,scratch) \
_WRS_WIND_VARS_OFFSET(reg) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl reg,scratch; \
movl 0x0(scratch),reg; \
incl reg; \
movl reg,0x0(scratch);
#define _IA32_PER_CPU_VALUE_DEC(reg,scratch,label) \
_IA32_CPU_INDEX_GET(reg,scratch) \
_WRS_WIND_VARS_OFFSET(reg) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addl reg,scratch; \
movl 0x0(scratch),reg; \
decl reg; \
movl reg,0x0(scratch);
/*
* rega = register to store kernel lock owner
* regb = register to store cpu index
*
* typedef struct smpLock
* {
* volatile int state; /@ state of lock (free/taken) @/
* volatile int owner; /@ CPU which owns the lock @/
* int count; /@ recursive ownership nesting count @/
* int options; /@ options applicable to this lock @/
*/
#define _IA32_KERNEL_LOCK_OWNER_AND_INDEX_GET(rega, regb) \
_IA32_CPU_INDEX_GET(regb,rega) \
leal FUNC(kernelStateLock),rega; \
movl VX_KERNEL_LOCK_cpuIndex_OFFSET(rega),rega;
/* kernel spin lock owner */
#else /* _WRS_CONFIG_SMP */
#define _WRS_IA32_VAR_ADRS(label) FUNC(label)
#ifdef _WRS_CONFIG_MEM_ALLOT
/* exclude OSM references, because OSM requires malloc() */
#define _IA32_ASM_EXTERN_KERNEL_GLOBALS \
.globl FUNC(pSysGdt); /* Gdt */ \
.globl FUNC(intNest); /* nested intr cnt */ \
.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
.globl FUNC(sysCr3); /* local CR3 cache */
#else /* _WRS_CONFIG_MEM_ALLOT */
#define _IA32_ASM_EXTERN_KERNEL_GLOBALS \
.globl FUNC(sysTssCurrent); /* OSM Tss task info */ \
.globl FUNC(excOSMTssCurrent); /* OSM Tss */ \
.globl FUNC(sysOSMGdtScratchCurrent); /* OSM Scratch memory */ \
.globl FUNC(sysOSMState); /* OSM State Flag */ \
.globl FUNC(pSysGdt); /* Gdt */ \
.globl FUNC(intNest); /* nested intr cnt */ \
.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
.globl FUNC(sysCr3); /* local CR3 cache */
#endif /* _WRS_CONFIG_MEM_ALLOT */
#define _IA32_PER_CPU_ADRS_GET(reg,scratch,label) \
leal _WRS_IA32_VAR_ADRS(label),reg; /* get address of label */
#define _IA32_PER_CPU_VALUE_GET(reg,scratch,label) \
movl _WRS_IA32_VAR_ADRS(label),reg; /* get value at label */
#define _IA32_PER_CPU_VALUE_SET(regv,scr1,scr2,label) \
movl regv,_WRS_IA32_VAR_ADRS(label);
#define _IA32_PER_CPU_VALUE_AND_ADRS_GET(regv,rega,label) \
leal _WRS_IA32_VAR_ADRS(label),rega; /* get address of label */ \
leal 0x0(rega),regv; /* get value at label */
#define _IA32_PER_CPU_VALUE_INC(reg,scratch,label) \
incl _WRS_IA32_VAR_ADRS(label);
#define _IA32_PER_CPU_VALUE_DEC(reg,scratch,label) \
decl _WRS_IA32_VAR_ADRS(label);
#endif /* _ASMLANGUAGE */
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCasmI86Ph */
vxworks-6.9/target/h/arch/i86/private/vxPortableArchP.h
+102
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@@ -0,0 +1,102 @@
/* vxPortableArchP.h - x86/x86_64 portable library configuration */
/*
* Copyright (c) 2007-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01w,20jan11,scm WIND00251661 - PORTABLE macro should not be defined by
default.
01v,20oct10,s_s renamed _WRS_PORTABLE_vxCpuIndexGet to _WRS_PORTABLE_vxCpuLib
(CQ:WIND00199670)
01u,26may10,scm enable optimized syscallDispatcher...
01t,23mar10,scm enable _WRS_PORTABLE_vxAtomicLib for 64 bit...
01s,18mar10,scm enable _WRS_PORTABLE_kernelLockLib and
_WRS_PORTABLE_spinLockIsrNdLib
01r,04feb10,scm add ffs 64 bit flag...
01q,20jan10,scm enable qPriBMapLib & qPriBMapNext...
01p,07jan10,scm enable optimized libs for bLib, workQLib, dllLib, sllLib,
and ffsLib.
01o,09dec09,cww 64-bit ffsLib update
01n,27jul09,jb Make vxAtomic portable for LP64
01m,19jun09,mze replacing PAD64
01l,20apr09,cww Temp enabling of portable vxAtomicLib for LP64
01k,16oct08,jb 64bit - Enabling PORTABLE - To be disabled as optimized
routines are ported
01j,10oct08,kk renamed _WRS_PORTABLE_spinlockIsrNdLib to
_WRS_PORTABLE_spinLockIsrNdLib
01i,24mar08,scm enable optimized workQ routines...
01h,16mar08,scm enable optimized qPriBMapNext...
01g,13mar08,scm enabled optimized syscallDispatch...
01f,16jan08,dlk Rename spinLockFastLib --> spinlockIsrNdLib.
01e,10dec07,dlk Enabled i86-optimized fast spin locks.
01d,22sep07,zl enabled optimized kernel lock library.
01c,04jun07,scm update to support optimized implementations...
01b,15may07,scm restore settings
01a,04may07,zl created
*/
#ifndef __INCvxPortableArchPh
#define __INCvxPortableArchPh
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <private/vxPortableP.h>. It may undefine
* portable library definitions in order to enable architecture specific
* implementation of a library or routine.
*/
/* the following can be overridden with PORTABLE */
#ifdef _WRS_CONFIG_LP64
#ifndef PORTABLE
#undef _WRS_PORTABLE_kernelLockLib
#undef _WRS_PORTABLE_spinLockIsrNdLib
#undef _WRS_PORTABLE_vxAtomicLib
#undef _WRS_PORTABLE_bLib
#undef _WRS_PORTABLE_workQLib
#undef _WRS_PORTABLE_dllLib
#undef _WRS_PORTABLE_sllLib
#undef _WRS_PORTABLE_ffsLib
#undef _WRS_PORTABLE_ffs64Lib
#undef _WRS_PORTABLE_qPriBMapLib
#undef _WRS_PORTABLE_qPriBMapNext
#undef _WRS_PORTABLE_syscallDispatch
#endif
#else /* (LP64) */
#ifndef PORTABLE
#undef _WRS_PORTABLE_bLib
#undef _WRS_PORTABLE_dllLib
#undef _WRS_PORTABLE_ffsLib
#define _WRS_PORTABLE_ffs64Lib
#undef _WRS_PORTABLE_kernelLockLib
#undef _WRS_PORTABLE_sllLib
#undef _WRS_PORTABLE_spinLockIsrNdLib
#undef _WRS_PORTABLE_syscallDispatch
#undef _WRS_PORTABLE_qPriBMapLib
#undef _WRS_PORTABLE_qPriBMapNext
#undef _WRS_PORTABLE_workQLib
#undef _WRS_PORTABLE_vxAtomicLib
#endif
#endif /* (LP64) */
/* the following cannot be overridden with PORTABLE */
#undef _WRS_PORTABLE_vxCpuLib
#ifdef __cplusplus
}
#endif
#endif /* __INCvxPortableArchPh */
vxworks-6.9/target/h/arch/i86/private/vxdbgI86LibP.h
+55
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@@ -0,0 +1,55 @@
/* vxdbgI86LibP.h - private I86 VxDBG library header file */
/*
* Copyright (c) 2007-2008, 2010-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01f,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
SMP (CQ:WIND00253870).
01e,29apr10,pad Moved extern C statement after include statements.
01d,27aug08,jpb Renamed VSB header file
01c,24jun08,jpb Added include path for kernel configurations options set in
vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
01b,26oct07,rlp Added the VXDBG_INT_LOCK_LEVEL_COMPUTE macro (CQ:WIND00109321).
01a,11oct07,rlp Written
*/
#ifndef __INCvxdbgI86LibPh
#define __INCvxdbgI86LibPh
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This macro returns the <level> parameter modified with the interrupt lock
* level defined into the <value> parameter. The <level> parameter must be
* previously get with either intCpuLock() or intRegsLock() API.
*/
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~INT_FLAG) | (value & INT_FLAG))
#ifdef _WRS_CONFIG_SMP
/* return TRUE if interrupts are locked in specified register set. */
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->eflags & INT_FLAG) == \
INT_FLAG) ? FALSE : TRUE)
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxdbgI86LibPh */
vxworks-6.9/target/h/arch/i86/private/windArchLibP.h
+122
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@@ -0,0 +1,122 @@
/* windArchLibP.h - private WIND header file for i86 */
/*
* Copyright (c) 2018 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01a,18jul18,r_h created for kernel page table isolation support (F10571)
*/
#ifndef __INCwindArchLibPh
#define __INCwindArchLibPh
#include <vsbConfig.h>
#include <private/adrSpaceLibP.h>
#ifdef _ASMLANGUAGE
#include <private/offsetMacrosP.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _WRS_CONFIG_KPTI
#ifdef _WRS_CONFIG_LP64
#define _WRS_WIND_RTP_VARS_ALIGN 512
#define _WRS_WIND_RTP_VARS_ALIGN_SHIFT 9
#define RTP_TRAMPOLINE_STACK_SIZE 192
#define TSS_MAX_COUNT 1
#else
#define _WRS_WIND_RTP_VARS_ALIGN 1024
#define _WRS_WIND_RTP_VARS_ALIGN_SHIFT 10
#define RTP_TRAMPOLINE_STACK_SIZE 96
#define TSS_MAX_COUNT 2
#endif
#define GDT_MAX_COUNT 12
/* RTP region for 32-bit supervisor mode access */
#ifndef _WRS_CONFIG_LP64
#ifndef _ASMLANGUAGE
IMPORT char *trampolineBaseAddr;
#endif /* _ASMLANGUAGE */
#define KERNEL_RTP_SUP_RGN_BASE trampolineBaseAddr
#define KERNEL_RTP_SUP_RGN_SIZE 0x00400000
#endif
#define RTP_SUP_RGN_CODE_ADDR (KERNEL_RTP_SUP_RGN_BASE + 0x000000)
#define RTP_SUP_RGN_CODE_SIZE 0x2000
#define RTP_SUP_RGN_DATA_ADDR (KERNEL_RTP_SUP_RGN_BASE + RTP_SUP_RGN_CODE_SIZE)
#define RTP_SUP_RGN_DATA_SIZE (RTP_SUP_RGN_IDT_SIZE + RTP_SUP_RGN_VARS_SIZE)
/* space for 256 IDT entries, each entry is 16 bytes (4k total) */
#define RTP_SUP_RGN_IDT_ADDRESS (RTP_SUP_RGN_DATA_ADDR)
#define RTP_SUP_RGN_IDT_SIZE ((HIGH_VEC + 1) * 16)
/* 256 bytes for each CPU for WIND_RTP_VARS (up to 16k) */
#define RTP_SUP_RGN_VARS_ADDR (RTP_SUP_RGN_DATA_ADDR + RTP_SUP_RGN_IDT_SIZE)
#define RTP_SUP_RGN_VARS_SIZE (_WRS_WIND_RTP_VARS_ALIGN * VX_MAX_SMP_CPUS)
#ifndef _ASMLANGUAGE
/*
* per-CPU arch specific data accessible using the user-mode page table.
* For x86 the total size (including the arch-independent part) is 512
* bytes(64-bit mode) or 1024 bytes(32-bit mode), see
* _WRS_WIND_RTP_VARS_ALIGN / _WRS_WIND_VARS_ALIGN.
*
* Note: unlike the windVarsArch, this is used for UP as well.
*/
typedef struct windRtpVarsArch
{
TSS tss[TSS_MAX_COUNT]; /* 0x010 / 0x020: TSS */
#ifndef _WRS_CONFIG_LP64
ULONG tss_pad; /* ----- / : for future use */
#endif
ULONG cr3Offset; /* 0x22c / 0x088: offset to user mode CR3 */
GDT gdt[GDT_MAX_COUNT]; /* 0x230 / 0x090: GDT */
#ifdef _WRS_CONFIG_LP64
ULONG reserved[2]; /* ----- / 0x0f0: for future use */
#endif
char trampolineStack[RTP_TRAMPOLINE_STACK_SIZE];
/* 0x290 / 0x100: trampoline stack */
} WIND_RTP_VARS_ARCH;
#define _WRS_WIND_RTP_VARS_ARCH WIND_RTP_VARS_ARCH cpu_archVars
#define _WRS_WIND_RTP_VARS_ARCH_ACCESS(ix, var) \
_WRS_WIND_RTP_VARS_ACCESS (ix, archVars.var)
#define RTP_SUP_RGN_GDT_ADDRESS(cpu) \
(&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, gdt[0]))
#define RTP_SUP_RGN_TSS_ADDRESS(cpu) \
(&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, tss[0]))
#ifndef _WRS_CONFIG_LP64
#define RTP_SUP_RGN_OSMTSS_ADDRESS(cpu) \
(&_WRS_WIND_RTP_VARS_ARCH_ACCESS (cpu, tss[1]))
#endif
#endif /* _ASMLANGUAGE */
#endif /* _WRS_CONFIG_KPTI */
#ifdef __cplusplus
}
#endif
#endif /* __INCwindArchLibPh */
vxworks-6.9/target/h/arch/i86/regsGv3.h
+216
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@@ -0,0 +1,216 @@
/* regsGv3.h - Thermal Monitor and Geyserville III Technology registers */
/* Copyright 2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,26aug02,hdn written
*/
#ifndef __INCregsGv3h
#define __INCregsGv3h
#ifdef __cplusplus
extern "C" {
#endif
/* gv3Lib.c initialization status flags */
#define GV3_INIT_NOT_DONE 0x0001 /* gv3Lib initialization not done */
#define GV3_ERR_NO_TM 0x0002 /* no Thermal Monitor exist */
#define GV3_OK_NO_GV 0x0004 /* no GV1+ or GV3 exist */
#define GV3_OK_GV3 0x0008 /* GV3 exist */
#define GV3_OK_NO_MATCH 0x0010 /* no matching FREQ_VID table */
#define GV3_OK_TM2 0x0020 /* GV3 TM2 exist */
#define GV3_OK_TM1 0x0040 /* TM1 exist */
#define GV3_OK_AC 0x0080 /* power source is AC */
#define GV3_OK_BATT 0x0100 /* power source is Battery */
/* User Thermal Monitor Mode Configuration */
#define GV3_MAX_PERF 0x1 /* max performance */
#define GV3_OPT_BATT 0x2 /* battery optimized performance */
#define GV3_MAX_BATT 0x3 /* max battery */
#define GV3_AUTO 0x4 /* automatic */
#define GV3_DEFAULT 0x5 /* default */
/* GV3 Thermal Monitor Mode Used */
#define GV3_TM_1 0x1 /* Thermal Monitor 1 */
#define GV3_TM_2 0x2 /* Thermal Monitor 2 */
/* GV3 State Transition parameters default value */
#define GV3_UP_UTIL 95 /* def utilization(%) to go 1 up */
#define GV3_DOWN_UTIL 95 /* def utilization(%) to go 1 down */
#define GV3_UP_TIME 300 /* def time(millisec) to go 1 up */
#define GV3_DOWN_TIME 1000 /* def time(millisec) to go 1 down */
/* Thermal Throttle parameters default value */
#define GV3_DUTY_CYCLE 0x8 /* throttle duty cycle : 50.0% */
#define GV3_BUS_RATIO 0x8 /* throttle bus ratio : 800Mhz */
/* Geyserville III specific MSRs */
#define MSR_EBL_CR_POWERON 0x002a /* Power On Configuration */
#define MSR_BBL_CR_CTL 0x0119 /* Control Register */
#define MSR_BBL_CR_CTL3 0x011e /* Control Register 3 */
#define MSR_CLOCK_FLEX_MAX 0x0194 /* Flexible Bus Ratio/VID Control */
#define MSR_PERF_STS 0x0198 /* Performance (Geyserville) Status */
#define MSR_PERF_CTL 0x0199 /* Performance (Geyserville) Control */
#define MSR_GV_THERM 0x019d /* Geyserville Thermal Control */
#define MSR_GV1P_REG_PTR 0x019e /* Geyserville 1+ Pointer */
/* MSR_EBL_CR_POWERON bit difinition */
#define EBL_RATIO 0x07c00000 /* RO Core Clock to System Bus Ratio */
#define EBL_AGENT_ID 0x00300000 /* RO Agent ID */
#define EBL_BUS_FREQ 0x00040000 /* RO System Bus Frequency */
#define EBL_APIC_ID 0x00030000 /* RO APIC Cluster ID */
#define EBL_PO_RESET 0x00004000 /* RO 1M Power On Reset */
#define EBL_IOQ_DEP 0x00002000 /* RO In Order Queue Depth */
#define EBL_BINI_OBS_EN 0x00001000 /* RO BINIT# Observation Enabled */
#define EBL_AERR_OBS_EN 0x00000400 /* RO AERR# Observation Enabled */
#define EBL_BIST 0x00000200 /* RO Execute BIST */
#define EBL_TRI_STATE 0x00000100 /* RO Output Tri-state Enable */
#define EBL_BINI_EN 0x00000080 /* RW BINIT# Enable */
#define EBL_BERR_IE_EN 0x00000040 /* RW BERR# Enable, Internal Err */
#define EBL_QUICK 0x00000020 /* RO Quickstart Mode */
#define EBL_BERR_BR_EN 0x00000010 /* RW BERR# Enable, Bus Request */
#define EBL_AERR_EN 0x00000008 /* RW AERR# Enable */
#define EBL_RESP_CHK_EN 0x00000004 /* RW Response Error Check Enable */
#define EBL_DATA_CHK_EN 0x00000002 /* RW Data Error Check Enable */
/* MSR_BBL_CR_CTL3 bit difinition */
#define BBL_L2_NOT 0x00800000 /* RO L2 Not Present */
#define BBL_L2_RANGE 0x00700000 /* RO L2 Physical Address Range */
#define BBL_L2_EN 0x00000100 /* RW L2 Enabled */
#define BBL_L2_ECC_EN 0x00000020 /* RO L2 ECC Check Enabled */
#define BBL_L2_HARD_EN 0x00000001 /* RO L2 Hardware Enabled */
/* MSR_CLOCK_FLEX_MAX bit difinition */
#define FLEX_EN 0x00010000 /* RW Flex Enable */
#define FLEX_RATIO 0x00001f00 /* RW Flex Ratio */
#define FLEX_VID 0x0000003f /* RW Flex VID */
/* MSR_GV1P_REG_PTR bit difinition */
#define GV1P_REG_PTR 0x0000ffff /* RW GV1P pointer register */
/* MSR_PERF_CTL bit difinition */
#define BUS_RATIO_SEL 0x00001f00 /* RW Bus Ratio Selection */
#define GV_VID_SEL 0x0000003f /* RW VID Selection */
/* MSR_PERF_STS bit difinition (upper 32) */
#define BUS_RATIO_BOOT 0x1f000000 /* RO Boot Bus Ratio */
#define GV_VID_BOOT 0x003f0000 /* RO Boot VID */
#define BUS_RATIO_MAX 0x00001f00 /* RO Max Bus Ratio */
#define GV_VID_MAX 0x0000003f /* RO Max VID */
/* MSR_PERF_STS bit difinition (lower 32) */
#define BUS_RATIO_MIN 0x1f000000 /* RO Min Bus Ratio */
#define GV_TS 0x00200000 /* RO GV3 Transition Started */
#define GV_CMD_SEEK 0x00100000 /* RO GV3 Transition Performing */
#define GV_THERM_THROT 0x00080000 /* RO GV3 Thermal Throttle */
#define GV_TT 0x00040000 /* RO Thermal Trip Active */
#define GV_VIP 0x00020000 /* RO Voltage Transition Pending */
#define GV_FIP 0x00010000 /* RO Frequency Change Pending */
#define BUS_RATIO_STS 0x00001f00 /* RO Current Bus Ratio */
#define GV_VID_STS 0x0000003f /* RO Current VID */
/* MSR_GV_THERM bit difinition */
#define GV_THROT_SEL 0x00010000 /* RW Thermal Management Mode */
#define BUS_RATIO_THROT 0x00001f00 /* RW Throttling Bus Ratio */
#define GV_VID_THROT 0x0000003f /* RW Throttling VID */
#ifndef _ASMLANGUAGE
/* frequency - VID table : state entry */
typedef struct freqVidState {
UINT16 no; /* state no. */
UINT16 vid; /* VID_SEL value in MSR_PERF_CTL */
UINT16 ratio; /* BUS_RATIO_SEL value in MSR_PERF_CTL */
UINT16 power; /* power(mW) consumed by CPU in this state */
} FREQ_VID_STATE;
/* frequency - VID table : header */
typedef struct freqVidHeader {
UINT32 cpuId; /* CPU family-model-stepping value */
UINT8 maxVid; /* VID_MAX value in MSR_PERF_STS */
UINT8 maxRatio; /* BUS_RATIO_MAX value in MSR_PERF_STS */
UINT8 nState; /* no of states supported by this CPU */
FREQ_VID_STATE * pState;
} FREQ_VID_HEADER;
/* Thermal Monitor interrupt routines and arguments */
typedef struct sysTherm {
FUNCPTR hotRoutine; /* rtn to call on TM Hot int */
INT32 hotArg; /* its argument */
BOOL hotConnected;
FUNCPTR coldRoutine; /* rtn to call on TM Cold int */
INT32 coldArg; /* its argument */
BOOL coldConnected;
} SYS_THERM;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS gv3LibInit (UINT32 mode, UINT32 upUtil, UINT32 downUtil,
UINT32 upTime, UINT32 downTime,
FUNCPTR acCheckRtn);
extern STATUS gv3StateSet (UINT32 state);
extern STATUS gv3DutyCycleSet (UINT32 dutyCycleIx);
extern STATUS gv3DutyCycleEnable (BOOL enable);
extern BOOL gv3DutyCycleCheck (void);
extern BOOL gv3HotCheck (void);
extern BOOL gv3AcCheck (void);
extern STATUS gv3AutoEnable (BOOL enable);
extern STATUS gv3AutoSet (UINT32 upUtil, UINT32 downUtil,
UINT32 upTime, UINT32 downTime);
extern STATUS gv3AutoGet (UINT32 * pUpUtil, UINT32 * pDownUtil,
UINT32 * pUpTime, UINT32 * pDownTime);
extern VOID gv3ShowInit (void);
extern VOID gv3Show (void);
#else /* __STDC__ */
extern STATUS gv3LibInit ();
extern STATUS gv3StateSet ();
extern STATUS gv3DutyCycleSet ();
extern STATUS gv3DutyCycleEnable ();
extern BOOL gv3DutyCycleCheck ();
extern BOOL gv3HotCheck ();
extern BOOL gv3AcCheck ();
extern STATUS gv3AutoEnable ();
extern STATUS gv3AutoSet ();
extern STATUS gv3AutoGet ();
extern VOID gv3ShowInit ();
extern VOID gv3Show ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCregsGv3h */
vxworks-6.9/target/h/arch/i86/regsI86.h
+1015
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File diff suppressed because it is too large Load Diff
vxworks-6.9/target/h/arch/i86/regsP7.h
+120
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@@ -0,0 +1,120 @@
/* regsP7.h - Pentium4 architecture specific registers */
/* Copyright 2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,02sep02,hdn written
*/
#ifndef __INCregsP7h
#define __INCregsP7h
#ifdef __cplusplus
extern "C" {
#endif
/* MSR, Pentium4 specific */
#define MSR_EBC_HARD_POWERON 0x002a
#define MSR_EBC_SOFT_POWERON 0x002b
#define MSR_EBC_FREQUENCY_ID 0x002c
#define MSR_LER_FROM_LIP 0x01d7
#define MSR_LER_TO_LIP 0x01d8
#define MSR_LASTBRANCH_TOS 0x01da
#define MSR_LASTBRANCH_0 0x01db
#define MSR_LASTBRANCH_1 0x01dc
#define MSR_LASTBRANCH_2 0x01dd
#define MSR_LASTBRANCH_3 0x01de
#define MSR_BPU_COUNTER0 0x0300
#define MSR_BPU_COUNTER1 0x0301
#define MSR_BPU_COUNTER2 0x0302
#define MSR_BPU_COUNTER3 0x0303
#define MSR_MS_COUNTER0 0x0304
#define MSR_MS_COUNTER1 0x0305
#define MSR_MS_COUNTER2 0x0306
#define MSR_MS_COUNTER3 0x0307
#define MSR_FLAME_COUNTER0 0x0308
#define MSR_FLAME_COUNTER1 0x0309
#define MSR_FLAME_COUNTER2 0x030a
#define MSR_FLAME_COUNTER3 0x030b
#define MSR_IQ_COUNTER0 0x030c
#define MSR_IQ_COUNTER1 0x030d
#define MSR_IQ_COUNTER2 0x030e
#define MSR_IQ_COUNTER3 0x030f
#define MSR_IQ_COUNTER4 0x0310
#define MSR_IQ_COUNTER5 0x0311
#define MSR_BPU_CCCR0 0x0360
#define MSR_BPU_CCCR1 0x0361
#define MSR_BPU_CCCR2 0x0362
#define MSR_BPU_CCCR3 0x0363
#define MSR_MS_CCCR0 0x0364
#define MSR_MS_CCCR1 0x0365
#define MSR_MS_CCCR2 0x0366
#define MSR_MS_CCCR3 0x0367
#define MSR_FLAME_CCCR0 0x0368
#define MSR_FLAME_CCCR1 0x0369
#define MSR_FLAME_CCCR2 0x036a
#define MSR_FLAME_CCCR3 0x036b
#define MSR_IQ_CCCR0 0x036c
#define MSR_IQ_CCCR1 0x036d
#define MSR_IQ_CCCR2 0x036e
#define MSR_IQ_CCCR3 0x036f
#define MSR_IQ_CCCR4 0x0370
#define MSR_IQ_CCCR5 0x0371
#define MSR_BSU_ESCR0 0x03a0
#define MSR_BSU_ESCR1 0x03a1
#define MSR_FSB_ESCR0 0x03a2
#define MSR_FSB_ESCR1 0x03a3
#define MSR_FIRM_ESCR0 0x03a4
#define MSR_FIRM_ESCR1 0x03a5
#define MSR_FLAME_ESCR0 0x03a6
#define MSR_FLAME_ESCR1 0x03a7
#define MSR_DAC_ESCR0 0x03a8
#define MSR_DAC_ESCR1 0x03a9
#define MSR_MOB_ESCR0 0x03aa
#define MSR_MOB_ESCR1 0x03ab
#define MSR_PMH_ESCR0 0x03ac
#define MSR_PMH_ESCR1 0x03ad
#define MSR_SAAT_ESCR0 0x03ae
#define MSR_SAAT_ESCR1 0x03af
#define MSR_U2L_ESCR0 0x03b0
#define MSR_U2L_ESCR1 0x03b1
#define MSR_BPU_ESCR0 0x03b2
#define MSR_BPU_ESCR1 0x03b3
#define MSR_IS_ESCR0 0x03b4
#define MSR_IS_ESCR1 0x03b5
#define MSR_ITLB_ESCR0 0x03b6
#define MSR_ITLB_ESCR1 0x03b7
#define MSR_CRU_ESCR0 0x03b8
#define MSR_CRU_ESCR1 0x03b9
#define MSR_IQ_ESCR0 0x03ba
#define MSR_IQ_ESCR1 0x03bb
#define MSR_RAT_ESCR0 0x03bc
#define MSR_RAT_ESCR1 0x03bd
#define MSR_SSU_ESCR0 0x03be
#define MSR_MS_ESCR0 0x03c0
#define MSR_MS_ESCR1 0x03c1
#define MSR_TBPU_ESCR0 0x03c2
#define MSR_TBPU_ESCR1 0x03c3
#define MSR_TC_ESCR0 0x03c4
#define MSR_TC_ESCR1 0x03c5
#define MSR_IX_ESCR0 0x03c8
#define MSR_IX_ESCR1 0x03c9
#define MSR_ALF_ESCR0 0x03ca
#define MSR_ALF_ESCR1 0x03cb
#define MSR_CRU_ESCR2 0x03cc
#define MSR_CRU_ESCR3 0x03cd
#define MSR_CRU_ESCR4 0x03e0
#define MSR_CRU_ESCR5 0x03e1
#define MSR_TC_PRECISE_EVENT 0x03f0
#define MSR_PEBS_MATRIX_VERT 0x03f2
#ifdef __cplusplus
}
#endif
#endif /* __INCregsP7h */
vxworks-6.9/target/h/arch/i86/sigI86Codes.h
+45
View File
@@ -0,0 +1,45 @@
/* sigI86Codes.h - signal facility library header */
/* Copyright 1984-1993, 2010 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,29may94,hdn removed I80486 conditional.
01a,08jun93,hdn written.
*/
#ifndef __INCsigI86Codesh
#define __INCsigI86Codesh
#include "iv.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ILL_DIVIDE_ERROR IV_DIVIDE_ERROR
#define ILL_NON_MASKABLE IV_NON_MASKABLE
#define ILL_OVERFLOW IV_OVERFLOW
#define ILL_BOUND IV_BOUND
#define ILL_INVALID_OPCODE IV_INVALID_OPCODE
#define ILL_DOUBLE_FAULT IV_DOUBLE_FAULT
#define ILL_INVALID_TSS IV_INVALID_TSS
#define ILL_PROTECTION_FAULT IV_PROTECTION_FAULT
#define ILL_RESERVED IV_RESERVED
#define EMT_DEBUG IV_DEBUG
#define EMT_BREAKPOINT IV_BREAKPOINT
#define FPE_NO_DEVICE IV_NO_DEVICE
#define FPE_CP_OVERRUN IV_CP_OVERRUN
#define FPE_CP_ERROR IV_CP_ERROR
#define BUS_NO_SEGMENT IV_NO_SEGMENT
#define BUS_STACK_FAULT IV_STACK_FAULT
#define BUS_PAGE_FAULT IV_PAGE_FAULT
#define BUS_ALIGNMENT IV_ALIGNMENT
#ifdef __cplusplus
}
#endif
#endif /* __INCsigI86Codesh */
vxworks-6.9/target/h/arch/i86/syscallArgsx86.h
+870
View File
@@ -0,0 +1,870 @@
/* Aligned for x86 - no alignment needed */
/* THIS FILE IS AUTO_GENERATED. PLEASE DO NOT EDIT. */
#ifndef _ASMLANGUAGE
#include <vxWorks.h>
#include <taskLib.h>
#include <rtpLib.h>
#include <sdLib.h>
#include <shlLib.h>
#include <signal.h>
#include <socket.h>
#include <time.h>
#include <setjmp.h>
#include <ioLib.h>
#include <private/semSysCall.h>
#include <private/objLibP.h>
#include <private/rtpLibP.h>
#include <private/mqPxSysCall.h>
#include <private/pxObjSysCall.h>
#include <private/semPxSysCall.h>
#include <private/taskSysCall.h>
#include <private/timerSysCall.h>
#include <private/eventSysCall.h>
#include <sys/resource.h>
#include <sys/types.h>
#include <base/b_trace_attr_t.h>
#include <base/b_trace_id_t.h>
#include <base/b_trace_event_id_t.h>
#include <base/b_pthread_t.h>
struct _exitScArgs
{
int status;
};
struct _creatScArgs
{
const char * name;
mode_t flag;
};
struct _openScArgs
{
const char * name;
int flags;
int mode;
};
struct _closeScArgs
{
int fd;
};
struct _readScArgs
{
int fd;
void * buffer;
size_t maxbytes;
};
struct _writeScArgs
{
int fd;
const void * buffer;
size_t nbytes;
};
struct _ioctlScArgs
{
int fd;
int function;
_Vx_ioctl_arg_t arg;
};
struct dupScArgs
{
int fd;
};
struct dup2ScArgs
{
int fd;
int fd2;
};
struct pipeScArgs
{
int filedes[2];
};
struct removeScArgs
{
const char * name;
};
struct selectScArgs
{
int width;
fd_set * readFds;
fd_set * writeFds;
fd_set * excFds;
struct timeval * timeout;
};
struct socketScArgs
{
int domain;
int type;
int protocol;
};
struct bindScArgs
{
int s;
struct sockaddr * name;
int namelen;
};
struct listenScArgs
{
int s;
int backlog;
};
struct acceptScArgs
{
int s;
struct sockaddr * addr;
int *addrlen;
};
struct connectScArgs
{
int s;
struct sockaddr * name;
int namelen;
};
struct sendtoScArgs
{
int s;
caddr_t buf;
int bufLen;
int flags;
struct sockaddr * to;
int tolen;
};
struct sendScArgs
{
int s;
const char * buf;
int bufLen;
int flags;
};
struct sendmsgScArgs
{
int s;
struct msghdr * mp;
int flags;
};
struct recvfromScArgs
{
int s;
char * buf;
int bufLen;
int flags;
struct sockaddr *from;
int * pFromLen;
};
struct recvScArgs
{
int s;
char * buf;
int bufLen;
int flags;
};
struct recvmsgScArgs
{
int s;
struct msghdr * mp;
int flags;
};
struct setsockoptScArgs
{
int s;
int level;
int optname;
char * optval;
int optlen;
};
struct getsockoptScArgs
{
int s;
int level;
int optname;
char * optval;
int * optlen;
};
struct getsocknameScArgs
{
int s;
struct sockaddr *name;
int * namelen;
};
struct getpeernameScArgs
{
int s;
struct sockaddr *name;
int *namelen;
};
struct shutdownScArgs
{
int s;
int how;
};
struct mmapScArgs
{
void * addr;
size_t len;
int prot;
int flags;
int fildes;
off64_t off;
};
struct munmapScArgs
{
void * addr;
size_t len;
};
struct mprotectScArgs
{
void * addr;
size_t len;
int prot;
};
struct killScArgs
{
OBJ_HANDLE rtpId;
int signo;
};
struct sigpendingScArgs
{
sigset_t * pSet;
};
struct sigprocmaskScArgs
{
int how;
const sigset_t * pSet;
sigset_t * pOset;
};
struct _sigqueueScArgs
{
OBJ_HANDLE rtpId;
int signo;
const union sigval * pValue;
int sigCode;
};
struct _sigsuspendScArgs
{
const sigset_t * pSet;
};
struct _sigtimedwaitScArgs
{
const sigset_t * pSet;
struct siginfo * pInfo;
const struct timespec * pTime;
};
struct _sigactionScArgs
{
int signo;
const struct sigaction * pAct;
struct sigaction * pOact;
void * retAddr;
};
struct chdirScArgs
{
const char * name;
};
struct _getcwdScArgs
{
char * buffer;
int length;
};
struct _waitpidScArgs
{
OBJ_HANDLE childRtpId;
int * pStatus;
int options;
};
struct sysctlScArgs
{
int * pName;
u_int nameLen;
void * pOld;
size_t * pOldLen;
void * pNew;
size_t newLen;
};
struct _schedPxInfoGetScArgs
{
BOOL * pTimeSlicingOn;
ULONG * pTimeSlicePeriod;
};
struct sigaltstackScArgs
{
stack_t * ss;
stack_t * oss;
};
struct unlinkScArgs
{
const char * name;
};
struct linkScArgs
{
const char * name;
const char * newname;
};
struct _fsyncScArgs
{
int fd;
};
struct _fdatasyncScArgs
{
int fd;
};
struct renameScArgs
{
const char * oldname;
const char * newname;
};
struct fpathconfScArgs
{
int fd;
int name;
};
struct pathconfScArgs
{
const char * path;
int name;
};
struct accessScArgs
{
const char * path;
int amode;
};
struct chmodScArgs
{
const char * path;
mode_t mode;
};
struct pxTraceCreationScArgs
{
int cmd;
pid_t pid;
trace_attr_t * attr;
int fd;
trace_id_t * trid;
};
struct pxTraceCtlScArgs
{
int cmd;
trace_id_t trid;
struct trace_event_set_t * filter;
int how;
pthread_t thread_id;
void * pc;
void * ptr_out;
};
struct pxTraceEventScArgs
{
int cmd;
int id_in;
char * data;
size_t data_len;
pthread_t thread_id;
void * pc;
trace_event_id_t * id_out;
};
struct pxTraceEventNameQueryScArgs
{
int cmd;
trace_id_t trid;
int id_in1;
int id_in2;
char * name;
trace_event_id_t * id_out;
int * unavailable;
};
struct pxTraceLogScArgs
{
int cmd;
trace_id_t trid_in;
int fd;
trace_id_t *trid_out;
};
struct pxTraceEventGetScArgs
{
int cmd;
trace_id_t trid;
size_t num_bytes;
struct timespec * timeout;
struct posix_trace_event_info * event;
void * data;
size_t * data_len;
int * unavailable;
};
struct eventReceiveScArgs
{
UINT32 events;
UINT32 options;
_Vx_ticks_t timeout;
UINT32 * pEvtsReceived;
};
struct eventSendScArgs
{
int taskId;
UINT32 events;
};
struct eventCtlScArgs
{
OBJ_HANDLE handle;
VX_EVT_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct msgQSendScArgs
{
OBJ_HANDLE handle;
char * buffer;
size_t nBytes;
_Vx_ticks_t timeout;
int priority;
};
struct msgQReceiveScArgs
{
OBJ_HANDLE handle;
char * buffer;
size_t maxNBytes;
_Vx_ticks_t timeout;
};
struct _msgQOpenScArgs
{
const char * name;
size_t maxMsgs;
size_t maxMsgLength;
int options;
int mode;
void * context;
};
struct objDeleteScArgs
{
OBJ_HANDLE handle;
int options;
};
struct objInfoGetScArgs
{
OBJ_HANDLE handle;
void * pInfo;
size_t * pInfoSize;
int level;
};
struct _semTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semGiveScArgs
{
OBJ_HANDLE handle;
};
struct _semOpenScArgs
{
const char * name;
SEM_TYPE type;
int initState;
int options;
int mode;
void * context;
};
struct semCtlScArgs
{
OBJ_HANDLE handle;
VX_SEM_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct _taskOpenScArgs
{
struct vx_task_open_sc_args * pArgs;
};
struct taskCtlScArgs
{
int tid;
VX_TASK_CTL_CMD command;
void * pArg;
size_t * pArgSize;
};
struct taskDelayScArgs
{
_Vx_ticks_t ticks;
};
struct rtpSpawnScArgs
{
const char * rtpFileName;
const char ** argv;
const char ** envp;
int priority;
size_t uStackSize;
int options;
int taskOptions;
};
struct rtpInfoGetScArgs
{
OBJ_HANDLE rtpId;
RTP_DESC * rtpStruct;
};
struct taskKillScArgs
{
OBJ_HANDLE taskHandle;
int signo;
};
struct _taskSigqueueScArgs
{
OBJ_HANDLE taskHandle;
int signo;
const union sigval * pValue;
int sigCode;
};
struct _timer_openScArgs
{
const char * name;
int mode;
clockid_t clockId;
struct sigevent * evp;
void * context;
};
struct timerCtlScArgs
{
TIMER_CTL_CMD cmdCode;
OBJ_HANDLE timerHandle;
void * pArgs;
size_t pArgSize;
};
struct pxOpenScArgs
{
PX_OBJ_TYPE type;
const char * name;
int objOpenMode;
void * attr;
};
struct pxCloseScArgs
{
OBJ_HANDLE handle;
};
struct pxUnlinkScArgs
{
PX_OBJ_TYPE type;
const char * name;
};
struct pxCtlScArgs
{
OBJ_HANDLE handle;
PX_CTL_CMD_CODE cmdCode;
void * pArgs;
size_t * pArgSize;
};
struct pxMqReceiveScArgs
{
OBJ_HANDLE handle;
char * pMsg;
size_t msgLen;
unsigned int * pMsgPrio;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxMqSendScArgs
{
OBJ_HANDLE handle;
const char * pMsg;
size_t msgLen;
unsigned int msgPrio;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxSemWaitScArgs
{
OBJ_HANDLE handle;
PX_WAIT_OPTION waitOption;
const struct timespec * time_out;
};
struct pxSemPostScArgs
{
OBJ_HANDLE handle;
};
struct pipeDevCreateScArgs
{
const char * name;
size_t nMessages;
size_t nBytes;
};
struct pipeDevDeleteScArgs
{
const char * name;
BOOL force;
};
struct _sdCreateScArgs
{
char * name;
int options;
size_t size;
off64_t physAddress;
MMU_ATTR attr;
void ** pVirtAddress;
};
struct _sdOpenScArgs
{
char * name;
int options;
int mode;
size_t size;
off64_t physAddress;
MMU_ATTR attr;
void ** pVirtAddress;
};
struct sdDeleteScArgs
{
OBJ_HANDLE handle;
int options;
};
struct sdMapScArgs
{
OBJ_HANDLE handle;
MMU_ATTR attr;
int options;
};
struct sdUnmapScArgs
{
OBJ_HANDLE handle;
int options;
};
struct sdProtectScArgs
{
OBJ_HANDLE handle;
MMU_ATTR attr;
};
struct _edrErrorInjectScArgs
{
int kind;
const char *fileName;
int lineNumber;
REG_SET *regset;
void *addr;
const char *msg;
};
struct wvEventScArgs
{
int eventId;
const char * pData;
unsigned int dataSize;
};
struct rtpVarAddScArgs
{
void ** pVar;
void * value;
};
struct sdInfoGetScArgs
{
OBJ_HANDLE handle;
SD_DESC * pSdStruct;
};
struct _shlOpenScArgs
{
const char * name;
int options;
};
struct _shlUnlockScArgs
{
SHL_ID shlId;
};
struct _shlCloseScArgs
{
SHL_ID shlId;
};
struct _shlGetScArgs
{
SHL_ID shlId;
SHLINFO *pInfo;
};
struct _shlPutScArgs
{
SHL_ID shlId;
const SHLINFO *pInfo;
};
struct objUnlinkScArgs
{
const char * name;
enum windObjClassType classType;
};
struct getprlimitScArgs
{
int idtype;
OBJ_HANDLE handle;
int resource;
struct rlimit *rlp;
};
struct setprlimitScArgs
{
int idtype;
OBJ_HANDLE handle;
int resource;
struct rlimit *rlp;
};
struct _mctlScArgs
{
void * addr;
size_t len;
int function;
void * arg;
};
struct _taskOpenWithGuardScArgs
{
struct vx_task_open_guard_sc_args * pArgs;
};
struct clockCtlScArgs
{
clockid_t clock_id;
CLOCK_CTL_CMD cmdCode;
void * pArgStruct;
size_t * pArgSize;
};
struct _semRTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semWTakeScArgs
{
OBJ_HANDLE handle;
_Vx_ticks_t timeout;
};
struct _semExchangeScArgs
{
OBJ_HANDLE giveHandle;
OBJ_HANDLE takeHandle;
_Vx_ticks_t timeout;
};
struct wvRtpEventScArgs
{
int eventId;
const char * pData;
unsigned int dataSize;
};
struct _selectScArgs
{
int width;
fd_set * readFds;
fd_set * writeFds;
fd_set * excFds;
struct timeval * timeout;
};
struct _sigtimedwait2ScArgs
{
const sigset_t * pSet;
struct siginfo * pInfo;
const struct timespec * pTime;
};
#endif /* _ASMLANGUAGE */
vxworks-6.9/target/h/arch/i86/syscallI86.h
+151
View File
@@ -0,0 +1,151 @@
/* syscallI86.h - I86 specific System Call Infrastructure header */
/*
* Copyright (c) 2003-2005, 2007-2008, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01g,16oct12,scm WIND00376020 - fast system call support...
01f,14mar08,scm modify saved regs to reflect code changes...
01e,04may07,zl updated portable library build configuration.
01d,05may05,zmm Fix SYSCALL_ENTRY_FRAME_SIZE. SPR 108825
01c,02feb04,jb Fix SPR 93500
01b,04jan04,jb Adding context to syscall_entry_state
01a,18sep03,jb written.
*/
/*
DESCRIPTION
This header contains I86-specific definitions and constants used by
the System Call Infrastructure library.
*/
#ifndef __INCsyscallI86h
#define __INCsyscallI86h
#ifndef _ASMLANGUAGE
#include <taskLib.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#if (CPU != PENTIUM)
/*
* SYSENTER/SYSEXIT...
*
* When SYSENTER called, made from USR Mode (PL3) :
*
* IA32_SYSENTER_CS - sysCsSuper
* IA32_SYSENTER_EIP - address of syscallHandle routine
* IA32_SYSENTER_ESP - pTcbCurrent->pExcStackBase
*
* CS <--- loaded from IA32_SYSENTER_CS (target code segment)
* RIP <--- loaded from IA32_SYSENTER_EIP (target instruction)
* SS <--- Computed by adding 8 to IA32_SYSENTER_CS (stack segment)
* RSP <--- loaded from IA32_SYSENTER_ESP (stack pointer)
*
* When SYSEXIT called, made from Kernel Mode (PL0):
*
* IA32_SYSENTER_CS - sysCsSuper
* EDX - return address
* ECX - user stack
*
* CS <--- Computed by adding 16 to IA32_SYSENTER_CS (code segment)
* RIP <--- loaded from EDX (target instruction)
* SS <--- Computed by adding 24 to IA32_SYSENTER_CS (stack segment)
* RSP <--- loaded from ECX (stack pointer)
*
* NOTE: When using SYSENTER/SYSEXIT to implement system calls, any
* additional state that needs to be saved to allow a return to the
* calling procedure must be saved explicitly by the calling procedure
* or be predefined through programming conventions.
*
*/
#define SYSCALL_ENTRY_FRAME_SIZE 72 /* size of 'syscall' frame */
#define INSTR_SYSENTER_SIZE 2 /* size of 'sysenter' instruction */
#define SYSCALL_STACK_ARGS 8 /* number of arguments passed */
#else
#define SYSCALL_ENTRY_FRAME_SIZE 68
#define SYSCALL_STACK_ARGS 8
#endif /* (CPU != PENTIUM) */
#ifndef _ASMLANGUAGE
/* The call gate/Tss mechanism does the copy for us, this is not needed */
#define _SYSCALL_USER_SP_CHECK(sp)
/* typedefs */
/*
* The SYSCALL_ENTRY_STATE structure defines the saved machine state
* when the system call trap is taken. This information is architecture
* specific, and is used by the system call dispatcher to restart system
* calls that have been interrupted by the occurance of signals.
* System call restart is achieved by restoring the saved state at the
* time of the system call trap, and re-issuing the system call.
*
* All arguments to the system call are saved on the kernel stack, and
* the address of that array is passed as an argument to the dispatcher.
* The layout of this structure must exactly match the ordering of members
* of the system call entry frame in src/arch/I86/syscallALib.s.
*
*/
typedef struct syscall_entry_state
{
#if (CPU != PENTIUM)
long esi; /* Saved reg on entry to syscallHandle */
long edi; /* Saved reg on entry to syscallHandle */
long ebx; /* Saved reg on entry to syscallHandle */
void * pc; /* return to stub PC (edx) */
long * pUStack; /* usr stack pointer (ecx) */
long cs; /* return address code segment */
long upc; /* return to caller pc */
long args[8]; /* argument list */
long scn; /* System Call Number - Also temp error storage */
long errNo; /* errno status */
long eflags; /* EFLAGS */
#else
int esi; /* Save reg */
int edi; /* Save reg */
int ebx; /* Save reg */
void * pc; /* return address instruction pointer */
int cs; /* return address code segment */
int scn; /* System Call Number - Also temp error storage */
int upc; /* return to caller pc */
int args[8]; /* argument list */
int * pUStack; /* user-mode stack pointer */
int ss; /* user stack segment */
#endif /* (CPU != PENTIUM) */
} SYSCALL_ENTRY_STATE;
/* Prototype */
UINT32 sysModGdt (UINT32 offset, UINT32 limit, UINT32 base, UINT32 priority);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCsyscallI86h */
vxworks-6.9/target/h/arch/i86/vxAtomicArchLib.h
+321
View File
@@ -0,0 +1,321 @@
/* vxAtomicArchLib.h - IA32 specific atomic library header */
/*
* Copyright (c) 2006-2010, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
19sep18,m_w make sure the code map of inline ASM under GNU
is correct (VXW6-86665)
13sep10,scm WIND002322578 remove type-punning warnings...
29apr10,pad Moved extern C statement after include statements.
15may09,gls made memory barriers available in user space
28apr09,cww Add fixed size APIs
29aug08,to add inline atomic routines for GCC
16jun08,zl use _WRS_BARRIER() for memory barrier implementations.
17jan08,gls renamed inline routines
03jan08,gls fixed DCC _inline_vxCas()
11dec07,gls Added _inline_vxCas()
29nov06,scm Created
*/
#ifndef __INCvxAtomicArchLibh
#define __INCvxAtomicArchLibh
#include <arch/i86/vxAtomicArchLibCommon.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#if defined (__DCC__)
#define VXCAS_COMMON(address, old_value, new_value) \
movl old_value,%eax; /* get old_value to cmp */ \
lock; /* lock the Bus during the next inst */ \
cmpxchg new_value, (address); /* if (%eax == (address) */ \
/* {ZF = 1; (address) = %ecx;} */ \
/* else */ \
/* {ZF = 0; %eax = (address);} */ \
jz 2f; \
movl $0, %eax; /* set status to FALSE */ \
jmp 1f; \
2: \
movl $1, %eax; /* set status to TRUE */ \
1:
__asm volatile BOOL vxAtomicCas_inline (atomic_t * address, atomicVal_t old_value,
atomicVal_t new_value)
{
% reg address; mem old_value; mem new_value;
! "ax", "cx"
movl new_value,%ecx /* get new_value to set */
VXCAS_COMMON (address, old_value, %ecx)
% reg address; mem old_value; reg new_value;
! "ax"
VXCAS_COMMON (address, old_value, new_value)
% mem address; mem old_value; mem new_value;
! "ax", "cx", "dx"
movl new_value,%ecx /* get new_value to set */
movl address,%edx /* get address */
VXCAS_COMMON (%edx, old_value, %ecx)
% mem address; mem old_value; reg new_value;
! "ax", "dx"
movl address,%edx /* get address */
VXCAS_COMMON (%edx, old_value, new_value)
}
__asm volatile BOOL vxAtomic32Cas_inline (atomic32_t * address, atomic32Val_t old_value,
atomic32Val_t new_value)
{
% reg address; mem old_value; mem new_value;
! "ax", "cx"
movl new_value,%ecx /* get new_value to set */
VXCAS_COMMON (address, old_value, %ecx)
% reg address; mem old_value; reg new_value;
! "ax"
VXCAS_COMMON (address, old_value, new_value)
% mem address; mem old_value; mem new_value;
! "ax", "cx", "dx"
movl new_value,%ecx /* get new_value to set */
movl address,%edx /* get address */
VXCAS_COMMON (%edx, old_value, %ecx)
% mem address; mem old_value; reg new_value;
! "ax", "dx"
movl address,%edx /* get address */
VXCAS_COMMON (%edx, old_value, new_value)
}
#define vxCas_inline vxAtomicCas_inline
#define vxAtomicAdd_inline vxAtomicAdd
#define vxAtomic32Add_inline vxAtomic32Add
#define vxAtomicSub_inline vxAtomicSub
#define vxAtomic32Sub_inline vxAtomic32Sub
#define vxAtomicInc_inline vxAtomicInc
#define vxAtomic32Inc_inline vxAtomic32Inc
#define vxAtomicDec_inline vxAtomicDec
#define vxAtomic32Dec_inline vxAtomic32Dec
#define vxAtomicGet_inline vxAtomicGet
#define vxAtomic32Get_inline vxAtomic32Get
#define vxAtomicSet_inline vxAtomicSet
#define vxAtomic32Set_inline vxAtomic32Set
#define vxAtomicClear_inline vxAtomicClear
#define vxAtomic32Clear_inline vxAtomic32Clear
#elif defined (__GNUC__)
static __inline__ BOOL vxAtomic32Cas_inline
(
atomic32_t * target, /* memory location to compare-and-swap */
atomic32Val_t oldValue, /* compare to this value */
atomic32Val_t newValue /* swap with this value */
)
{
BOOL swapped;
__asm__ volatile
(
"movl %3, %%eax;" /* move oldValue to %eax */
"lock;" /* lock the Bus during the next inst */
"cmpxchg %4, %2;" /* if (%eax == *target) */
/* {ZF = 1; *target = newValue;} */
/* else */
/* {ZF = 0; %eax = *target;} */
"setz %%al;" /* if success, set swapped to TRUE else FALSE */
"movzbl %%al, %0" /* zero extend swapped */
: "=&a" (swapped), /* output: swapped is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)), /* input: *target is %2 */
"g" (oldValue), /* oldValue is %3 */
"r" (newValue) /* newValue is %4 */
: "memory" /* memory clobber for code barrier */
);
return swapped;
}
static __inline__ atomic32Val_t vxAtomic32Add_inline
(
atomic32_t * target,
atomic32Val_t value
)
{
__asm__ volatile
(
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = value + *target */
/* value = *target */
/* *target = TMP */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Sub_inline
(
atomic32_t * target,
atomic32Val_t value
)
{
__asm__ volatile
(
"negl %0;" /* Negate value... */
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = -value + *target */
/* value = *target */
/* *target = TMP */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Inc_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl $1, %0;" /* inc by 1 */
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = *target + 1 */
/* value = *target */
/* *target = TMP */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Dec_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl $(-1), %0;" /* dec by 1 */
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = *target - 1 */
/* value = *target */
/* *target = TMP */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Get_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl %1, %0" /* get value with bus-lock */
: "=r" (value) /* output: value is %0 */
: "m" (*(target)) /* input: *target is %1 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Set_inline
(
atomic32_t * target,
atomic32Val_t value
)
{
__asm__ volatile
(
"xchgl %0, %2" /* set value with bus-lock */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Clear_inline
(
atomic32_t * target
)
{
atomicVal_t value;
__asm__ volatile
(
"movl $0, %0;" /* 'clear' value to set */
"xchgl %0, %2" /* swap 'clear' value with bus-lock */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
#define vxCas_inline vxAtomic32Cas_inline
#define vxAtomicCas_inline vxAtomic32Cas_inline
#define vxAtomicAdd_inline vxAtomic32Add_inline
#define vxAtomicSub_inline vxAtomic32Sub_inline
#define vxAtomicInc_inline vxAtomic32Inc_inline
#define vxAtomicDec_inline vxAtomic32Dec_inline
#define vxAtomicGet_inline vxAtomic32Get_inline
#define vxAtomicSet_inline vxAtomic32Set_inline
#define vxAtomicClear_inline vxAtomic32Clear_inline
#else
#define vxCas_inline vxAtomicCas
#define vxAtomicCas_inline vxAtomicCas
#define vxAtomic32Cas_inline vxAtomic32Cas
#define vxAtomicAdd_inline vxAtomicAdd
#define vxAtomic32Add_inline vxAtomic32Add
#define vxAtomicSub_inline vxAtomicSub
#define vxAtomic32Sub_inline vxAtomic32Sub
#define vxAtomicInc_inline vxAtomicInc
#define vxAtomic32Inc_inline vxAtomic32Inc
#define vxAtomicDec_inline vxAtomicDec
#define vxAtomic32Dec_inline vxAtomic32Dec
#define vxAtomicGet_inline vxAtomicGet
#define vxAtomic32Get_inline vxAtomic32Get
#define vxAtomicSet_inline vxAtomicSet
#define vxAtomic32Set_inline vxAtomic32Set
#define vxAtomicClear_inline vxAtomicClear
#define vxAtomic32Clear_inline vxAtomic32Clear
#endif /* _VX_TOOL_FAMILY */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibh */
vxworks-6.9/target/h/arch/i86/vxAtomicArchLibCommon.h
+51
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@@ -0,0 +1,51 @@
/* vxAtomicArchLibCommon.h - IA32 specific atomic library header */
/*
* Copyright (c) 2009, 2011-2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01c,27apr12,scm WIND00346365 - VX_MEM_BARRIER_R()/_W()/_RW all using
mfence...
01b,05jan11,kk make VX_MEM_BARRIER_X() macros CPU variant dependent
01a,17may09,gls written.
*/
#ifndef __INCvxAtomicArchLibCommonh
#define __INCvxAtomicArchLibCommonh
#ifdef __cplusplus
extern "C" {
#endif
#define _WRS_ARCH_SUPPORTS_MEM_BARRIER
/*
* Macros to provide memory barrier.
*
* For variants older than PENTIUM4, the mfence instruction
* is not supported.
*/
#if (CPU==PENTIUM)
#define VX_MEM_BARRIER_R() _WRS_ASM("NOP")
#define VX_MEM_BARRIER_W() _WRS_ASM("NOP")
#define VX_MEM_BARRIER_RW() _WRS_ASM("NOP")
#define VX_INSTR_BARRIER() _WRS_ASM("NOP")
#else
#define VX_MEM_BARRIER_R() _WRS_BARRIER("lfence");
#define VX_MEM_BARRIER_W() _WRS_BARRIER("sfence");
#define VX_MEM_BARRIER_RW() _WRS_BARRIER("mfence");
#define VX_INSTR_BARRIER() _WRS_BARRIER("mfence");
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibCommonh */
vxworks-6.9/target/h/arch/i86/vxCpuArchLib.h
+66
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@@ -0,0 +1,66 @@
/*
* vxCpuArchLib.h - header for arch/board dependent CPU Identification
* support routines
*/
/*
* Copyright (c) 2006, 2008-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01k,28jan10,jb modifying per uHLD 1044
01j,18sep09,scm remove _WRS_CPU_BIOS_CONFIGURED ...
01i,16jan09,scm declare _func_cpuIndexGet...
01h,05jun08,rec add vxRsdpPtr
01g,01nov06,scm remove arch definitions for vxCpuEnabledGet &
vxCpuConfiguredGet
01f,30oct06,scm change references from vxCpuLib to vxCpuArchLib...
01e,14sep06,scm add count to track SMP initialized CPUs
01d,26jul06,scm tie vxCpuCount to MP Configuration Entry CPU counter
(mpApicNcpu).
01c,21jul06,scm _func_cpuIndexGet not required at this time...
01b,21jul06,scm Move SMP macros to private header.
01a,05jul06,scm written.
*/
#ifndef __INCvxCpuArchLibh
#define __INCvxCpuArchLibh
#ifdef __cplusplus
extern "C" {
#endif
/* typedefs */
typedef unsigned int cpuid_t; /* hardware CPU identification */
/* function declarations */
/* Arch or BSP system-dependent implementation routine */
extern unsigned int (*_func_cpuIndexGet) (void);
extern unsigned int vxCpuIndexGet (void);
extern unsigned int vxCpuPhysIndexGet (void);
extern unsigned int vxCpuIdToPhysIndex (cpuid_t cpuID);
extern cpuid_t vxCpuPhysIndexToId (unsigned int cpuPhysIdx);
extern unsigned int vxCpuCount;
extern char * vxRsdpPtr;
#ifdef __cplusplus
}
#endif
#endif /* __INCvxCpuArchLibh */
vxworks-6.9/target/h/arch/i86/vxI86Lib.h
+91
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@@ -0,0 +1,91 @@
/* vxI86Lib.h - header for arch/board dependent routines for the I80X86 */
/*
* Copyright (c) 2001-2003, 2005, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01i,09may12,j_l WIND00337546 - Add vxGdtrSet() and vxLdtrSet() prototypes.
Modify vxLdtrGet() prototype.
Adhere to coding standards more closely
01h,16feb05,aeg added various function prototypes (SPR #106381).
01g,24dec03,jb Adding prototype for vxDsGet
01f,04sep02,hdn added vxIdleHookAdd(), vxIdleShow() prototype.
01e,11apr02,pai Added vxCpuShow(), vxDrShow(), and vxSseShow() prototypes.
01d,26mar02,pai Added vxShowInit() prototype (SPR 74103).
01c,13nov01,ahm Added rudimentary support for power management (SPR#32599)
01b,26oct01,hdn added vxDr[SG]et(), vxTss[GS]et() prototype.
01a,22aug01,hdn written.
*/
#ifndef __INCvxI86Libh
#define __INCvxI86Libh
#ifdef __cplusplus
extern "C" {
#endif
/* power management mode definitions - used by vxPowerModeSet/Get */
#define VX_POWER_MODE_DISABLE (0x1) /* power mgt disable: loop when idle*/
#define VX_POWER_MODE_AUTOHALT (0x4) /* AutoHalt power management mode */
/* function declarations */
#ifndef _ASMLANGUAGE
extern void vxMemProbeTrap (void);
extern STATUS vxMemProbeSup (int length, char * adrs, char * pVal);
extern int vxCr0Get (void);
extern void vxCr0Set (int cr0);
extern int vxCr2Get (void);
extern void vxCr2Set (int cr2);
extern int vxCr3Get (void);
extern void vxCr3Set (int cr3);
extern int vxCr4Get (void);
extern void vxCr4Set (int cr4);
extern int vxCsGet (void);
extern int vxDsGet (void);
extern int vxSsGet (void);
extern int vxEflagsGet (void);
extern void vxEflagsSet (int eflags);
extern void vxDrGet (int * pDr0, int * pDr1, int * pDr2,
int * pDr3, int * pDr4, int * pDr5,
int * pDr6, int * pDr7);
extern void vxDrSet (int dr0, int dr1, int dr2, int dr3,
int dr4, int dr5, int dr6, int dr7);
extern int vxTssGet (void);
extern void vxTssSet (int value);
extern void vxGdtrGet (long long int * pGdtr);
extern void vxGdtrSet (long long int * pGdtr);
extern void vxIdtrGet (long long int * pIdtr);
extern void vxLdtrGet (UINT16 * pLdtr);
extern void vxLdtrSet (UINT16 ldtr);
IMPORT STATUS vxPowerModeSet (UINT32 mode);
IMPORT UINT32 vxPowerModeGet (void);
extern STATUS vxIdleHookAdd (FUNCPTR entHook, FUNCPTR exitHook);
extern VOID vxIdleEntHookRtn (void);
extern VOID vxIdleExtHookRtn (void);
extern UINT32 vxIdleUtilGet (void);
extern void vxShowInit (void);
extern void vxCpuShow (void);
extern void vxDrShow (void);
extern void vxSseShow (int);
extern void vxIdleShow (BOOL debug);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxI86Libh */
vxworks-6.9/target/h/arch/i86/vxInlineArch.h
+54
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@@ -0,0 +1,54 @@
/* vxInlineArch.h - i86/x86_64 inline macro configuration */
/*
* Copyright (c) 2007-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01g,24mar10,scm enable remaining inlines for 64 bit...
01f,24mar10,scm enable vxAtomic inlines...
01e,23mar10,scm adjust for vxAtomics...
01d,15apr09,sem Add new intCpuMicroLock API
01d,18nov08,pad For LP64 do not use inlines until they are adapted.
01c,29aug08,to add more inline atomic routines
01b,11dec07,gls added _WRS_INLINE_vxCas
01a,19jun07,zl created
*/
#ifndef __INCvxInlineArchh
#define __INCvxInlineArchh
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file is included from <vxInline.h>. It may define _WRS_INLINE_xxx
* build configuration macros in order to enable architecture specific
* inlined implementation of a macro definition.
*/
#define _WRS_INLINE_intCpuLock
#define _WRS_INLINE_intCpuUnlock
#define _WRS_INLINE_intCpuMicroLock
#define _WRS_INLINE_intCpuMicroUnlock
#define _WRS_INLINE_vxAtomicAdd
#define _WRS_INLINE_vxAtomicSub
#define _WRS_INLINE_vxAtomicInc
#define _WRS_INLINE_vxAtomicDec
#define _WRS_INLINE_vxAtomicGet
#define _WRS_INLINE_vxAtomicSet
#define _WRS_INLINE_vxAtomicClear
#define _WRS_INLINE_vxCas
#ifdef __cplusplus
}
#endif
#endif /* __INCvxInlineArchh */
vxworks-6.9/target/h/arch/i86/x86_64/archX86_64.h
+309
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@@ -0,0 +1,309 @@
/* archX86_64.h - Intel x86_64 specific header */
/*
* Copyright (c) 2009-2011, 2013 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01t,20jun13,scm WIND00420874 - correct workQAdd indexing for more than 8
core...
01s,14aug11,j_l Move _WRS_ARCH_HAS_CPU_PWR_MGMT outside of power management
ifdef.
01r,12aug11,rbc WIND00238999 - Fix conditional for CPU==NEHALEM
01q,11aug11,rbc WIND00238999 - Fix build errors
01p,09aug11,rbc WIND00238999 - Fix build error for windPwrDown()
01o,18may11,jb Requirement WIND00189850 - Increase VX_MAX_SMP_CPUS for HT/SMT support
01n,07feb11,rlp Enabled system mode agent for LP64.
01m,24nov10,kk Change _ALLOC_ALIGN_SIZE to 16
01l,28oct10,zl defined _WRS_ARCH_DEFERS_KERNEL_UNLOCK and
_WRS_ARCH_HAS_TASK_MMU_CURRENT_SET
01k,16sep10,gls added VX_OBJ_ALIGN_SIZE
01j,29jul10,pad Moved extern C statement after include statements.
01i,12mar10,zl added _WRS_ARCH_USES_DIRECT_MAP_REGION
01i,26feb10,rlp Added _WRS_ARCH_NO_SYSTEM_MODE_AGENT macro to disable WDB
system mode agent.
01h,10sep09,jb Add flag for _WRS_MMU_HAS_OPTIMIZATION_INFO_API
01g,31jul09,jb Adding defines for 64-bit MMU
01f,09jun09,cww Added _WRS_PAL_COPROC_LIB
01e,20may09,jb Change to kernel model
01d,08may09,jb Make pusha/popa interrupt safe
01c,25feb09,jb Adding 64-bit shortcut - may be moved
01b,12feb09,jb Fix reference to vxbConfig
01a,20jan09,jb Derived from 32-bit version 02p
*/
#ifndef __INCarchX86_64h
#define __INCarchX86_64h
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
#define _WRS_ARCH_KERNEL_MODEL /* compiler uses mcmodel=kernel */
#define _ARCH_SUPPORTS_GCC
/* temporary macro to indicate i86 uses the idle task stack */
#define _WRS_ARCH_HAS_IDLE_TASK
/* temporary macro to indicate i86 uses the type II kernel lock */
#define _WRS_ARCH_HAS_NEW_KERNEL_LOCK
#define _WRS_VX_NO_GLOBAL_ERRNO
/* arch supports new MMU APIs... */
#define _WRS_MMU_HAS_MAP_STATE_API
#define _WRS_MMU_HAS_SPL_TRANSLATE_API
#define _WRS_MMU_HAS_BLOCK_INFO_API
#define _WRS_MMU_HAS_OPTIMIZATION_INFO_API
/* arch has 64-bit mmu attributes */
#define _WRS_MMU_HAS_64BIT_ARCH_ATTR
/* this arch uses direct map region */
#define _WRS_ARCH_USES_DIRECT_MAP_REGION
/* this cpu family supports power management framework */
#define _WRS_ARCH_HAS_CPU_PWR_MGMT
#if (CPU==_VX_NEHALEM) || defined(_WRS_CONFIG_WRHV_GUEST)
#define _WRS_ARCH_HAS_WIND_PWR_DOWN
#define WIND_PWR_DOWN() windPwrDown()
/* support for device power management */
#if !defined(_WRS_CONFIG_WRHV_GUEST)
#define _WRS_ARCH_HAS_DEV_PWR_MGMT
#endif /* !defined(_WRS_CONFIG_WRHV_GUEST) */
#endif /* (CPU==_VX_NEHALEM) || defined(_WRS_CONFIG_WRHV_GUEST) */
#define _WRS_PAL_COPROC_LIB /* enable coprocessor abstraction */
/* arch needs deferred kernel unlock */
#define _WRS_ARCH_DEFERS_KERNEL_UNLOCK
/* arch provides taskMmuCurrentSet() */
#define _WRS_ARCH_HAS_TASK_MMU_CURRENT_SET
/* 64-bit Virt and Physical addresses */
#define _WRS_PHYS_ADDR_IS_64_BITS
#define _TYPE_PHYS_ADDR typedef unsigned long PHYS_ADDR
#define _TYPE_VX_PHYS_ADDR typedef unsigned long _Vx_PHYS_ADDR
#undef VX_MAX_SMP_CPUS
#if CPU==_VX_CORE
#define VX_MAX_SMP_CPUS 16 /* maximum processors in SMP configuration */
#define VX_MAX_SMP_CPU_SHIFT 4 /* allow workQ to calculate with Max CPUs */
#else
#define VX_MAX_SMP_CPUS 32 /* maximum processors in SMP configuration */
#define VX_MAX_SMP_CPU_SHIFT 5 /* allow workQ to calculate with Max CPUs */
#endif /* CPU==_VX_CORE */
#define _DYNAMIC_BUS_SIZING FALSE /* require alignment for swap */
#define _STACK_ALIGN_SIZE 16 /* required stack alignment for sse and sse2 instructions */
#define _ALLOC_ALIGN_SIZE 16
/*
* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
* This is used for both statically and dynamically allocated objects.
*
* NOTE:
*
* For the INTEL architecture VxWorks objects must be aligned to a 64-bit
* boundary for ILP32 and a 128-bit boundary for LP64. This is to allow
* the objVerifiedSafe() routine to be implemented using an atomic CAS of
* the 'safe' count and 'magic' value in an object handle.
*/
#define VX_OBJ_ALIGN_SIZE 16
#define _CACHE_ALIGN_SIZE 64
#ifdef _ASMLANGUAGE
/*
* system startup macros used by sysInit(sysALib.s) and romInit(romInnit.s).
* - no function calls to outside of BSP is allowed.
* - no references to the data segment is allowed.
* the CR4 is introduced in the Pentium processor.
*/
#define ARCH_REGS_INIT \
xorq %rax, %rax; /* zero EAX */ \
movq %cr0, %rdx; /* get CR0 */ \
andq $0x7ffafff1, %rdx; /* clear PG, AM, WP, TS, EM, MP */ \
movq %rdx, %cr0; /* set CR0 */ \
\
pushq %rax; /* initialize EFLAGS */ \
popfl;
#define ARCH_CR4_INIT \
xor %rax, %rax; /* zero EAX */ \
movq %eax, %cr4; /* initialize CR4 */
#define pushal \
subq $0x80, %rsp; /* move stack pointer */\
mov %rax, REG_RAX(%rsp); /* push rax */ \
mov %rcx, REG_RCX(%rsp); /* push rcx */ \
mov %rdx, REG_RDX(%rsp); /* push rdx */ \
mov %rbx, REG_RBX(%rsp); /* push rbx */ \
mov %rbp, REG_RBP(%rsp); /* push rbp */ \
mov %rsi, REG_RSI(%rsp); /* push rsi */ \
mov %rdi, REG_RDI(%rsp); /* push rdi */ \
mov %r8, REG_R8(%rsp); /* push r8 */ \
mov %r9, REG_R9(%rsp); /* push r9 */ \
mov %r10, REG_R10(%rsp); /* push r10 */ \
mov %r11, REG_R11(%rsp); /* push r11 */ \
mov %r12, REG_R12(%rsp); /* push r12 */ \
mov %r13, REG_R13(%rsp); /* push r13 */ \
mov %r14, REG_R14(%rsp); /* push r14 */ \
mov %r15, REG_R15(%rsp); /* push r15 */ \
mov %rsp, REG_RSP(%rsp); /* push rsp */ \
addq $0x80, REG_RSP(%rsp); /* Adjust rsp */
#define popal \
mov REG_RAX(%rsp), %rax; /* pop rax */ \
mov REG_RCX(%rsp), %rcx; /* pop rcx */ \
mov REG_RDX(%rsp), %rdx; /* pop rdx */ \
mov REG_RBX(%rsp), %rbx; /* pop rbx */ \
mov REG_RBP(%rsp), %rbp; /* pop rbp */ \
mov REG_RSI(%rsp), %rsi; /* pop rsi */ \
mov REG_RDI(%rsp), %rdi; /* pop rdi */ \
mov REG_R8(%rsp), %r8; /* pop r8 */ \
mov REG_R9(%rsp), %r9; /* pop r9 */ \
mov REG_R10(%rsp), %r10; /* pop r10 */ \
mov REG_R11(%rsp), %r11; /* pop r11 */ \
mov REG_R12(%rsp), %r12; /* pop r12 */ \
mov REG_R13(%rsp), %r13; /* pop r13 */ \
mov REG_R14(%rsp), %r14; /* pop r14 */ \
mov REG_R15(%rsp), %r15; /* pop r15 */ \
mov REG_RSP(%rsp), %rsp; /* pop rsp */
#else
/* no function declarations for makeSymTlb/symTbl.c */
/* macros for getting frame and return PC from a jmp_buf */
#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_fp)
#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
#endif /* _ASMLANGUAGE */
/* PAL additions */
/* architecture-specific overrides for fppSave and fppRestore in fppLib.c */
#define FPP_SAVE(p) (*_func_fppSaveRtn)(p)
#define FPP_RESTORE(p) (*_func_fppRestoreRtn)(p)
/* from h/usb/target/usbIsaLib.h */
/* DMA controller selection */
#define _WRS_DMA_I8237
/* trigger signed IO arguments in sysLib.h */
#define _WRS_SIGNED_IO_ARGS
#define _WRS_SYS_IO
/* override _WRS_SR_SIZE in taskArchLib.h */
#define _WRS_SR_SIZE ULONG
/*
* trigger definition of portWorkQAdd1 in trgLib.c and
* rBuffLib.c
*/
#define _WRS_PORT_WORK_Q_ADD1
/* used in cacheLib.c:cacheFuncsSet() */
#define _WRS_EXTERN_WRITEBACK
/* used in fppLib.c to align FP_CONTEXT */
/* dummy context must be in data section for now */
#define _WRS_ALIGN_FP_CONTEXT
#define _WRS_FPP_DUMMY_CONTEXT \
_WRS_DATA_ALIGN_BYTES(_CACHE_ALIGN_SIZE) fppDummyContext = {{{0}}}
/* architecture-specific overrides for fppSave and fppRestore in dbgLib.c */
#define _WRS_SHOW_SSE_REGS
#define FPP_DBG_SAVE(p) (*_func_fppSaveRtn)(p)
#define FPP_DBG_RESTORE(p) (*_func_fppRestoreRtn)(p)
/* from loadElfLib.c */
#define _WRS_USE_ELF_LOAD_FORMAT
/* from xdr_float.c */
#define FLOAT_NORM
/* from vmShow.c */
#define _WRS_SHOW_WBACK_STATE
#define _WRS_SHOW_GLOBAL_STATE
/* from taskShow.c */
#define _WRS_SHOW_SSE_REGS
/* from rBuffLib.c */
#define _WRS_PORT_WORK_Q_ADD1
/* from wdbFpLib.c */
#define _WRS_ALIGN_REG_SET
/* from schedLib.c */
#define _WRS_ENABLE_IDLE_INTS {intUnlock (-1);}
/* from sysOsmLib.c */
#define _WRS_OSM_INIT
/* Interrupt stack protection, used in usrDepend.c and usrKernelStack.c */
#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
/* if OSM support not available for stack protection,
* * then support can not be available for interrupt
* * stack protection.
* */
#if !defined(_WRS_OSM_INIT)
#undef _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
#endif
#ifdef __cplusplus
}
#endif
#include <arch/i86/archI86Common.h>
/* end of PAL additions */
#endif /* __INCarchX86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/asmX86_64.h
+121
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/* asmX86_64.h - x86_64 assembler definitions header file */
/*
* Copyright (c) 2009
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01b,17mar09,jb Update INT_CONNECT_CODE29
01a,20jan09,jb Derived from 32-bit version 01o
*/
#ifndef __INCasmX86_64h
#define __INCasmX86_64h
/************************************************************/
/*
* The following definitions are used for symbol name compatibility.
*
* When #if 1, sources are assembled assuming the compiler
* you are using does not generate global symbols prefixed by "_".
* (e.g. elf/dwarf)
*
* When #if 0, sources are assembled assuming the compiler
* you are using generates global symbols prefixed by "_".
* (e.g. coff/stabs)
*/
#if TRUE
#define FUNC(sym) sym
#define FUNC_LABEL(sym) sym:
#else
#define FUNC(sym) _##sym
#define FUNC_LABEL(sym) _##sym:
#endif
#define VAR(sym) FUNC(sym)
/*
* These macros are used to declare assembly language symbols that need
* to be typed properly(func or data) to be visible to the OMF tool.
* So that the build tool could mark them as an entry point to be linked
* correctly. This is an elfism. Use #if 0 for a.out.
*/
#if TRUE
#define GTEXT(sym) FUNC(sym) ; .type FUNC(sym),@function
#define GDATA(sym) FUNC(sym) ; .type FUNC(sym),@object
#else
#define GTEXT(sym) FUNC(sym)
#define GDATA(sym) FUNC(sym)
#endif
/* Introduced to abstract assembler idiosyncrasies */
#define FUNC_BEGIN(func) FUNC_LABEL(func)
#define FUNC_END(func) .size FUNC(func), . - FUNC(func)
/************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*
* fp offsets to arguments
*
* In 64-bits the first six arguments are in registers,
* the rest are on the stack. ARG0 - ARG6 should not
* be used.
*/
#define ARG7 16
#define ARG8 24
#define ARG9 32
#define ARG10 40
#define ARG11 48
#define ARG12 56
/* Should not be any double args. Will be in registers? */
#if 0
#define DARG1 8 /* double arguments */
#define DARG1L 12
#define DARG2 16
#define DARG2L 20
#define DARG3 24
#define DARG3L 28
#define DARG4 32
#define DARG4L 36
#endif
/*
* sp offsets to arguments
*
* In 64-bits the first six arguments are in registers,
* the rest are on the stack. SP_ARG0 - SP_ARG6 should
* not be used.
*/
#define SP_ARG7 0
#define SP_ARG8 8
#define SP_ARG9 16
#define SP_ARG10 24
#define SP_ARG11 32
#define SP_ARG12 40
/* offset to the IRQ number in the intConnectCode[] */
#define INT_CONNECT_CODE29 26 /* from the return address of intEnt() */
#ifdef __cplusplus
}
#endif
#endif /* __INCasmX86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/cacheX86_64.h
+80
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@@ -0,0 +1,80 @@
/* cacheX86_64Lib.h - x86_64 cache library header file */
/*
* Copyright 2009, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01d,29apr10,pad Moved extern C statement after include statements.
01c,18mar09,jb Add override for 64-bit calls
01b,13feb09,jb Fix cache type conflict
01a,27jan09,jb Created from 32-bit version 01f
*/
#ifndef __INCcacheX86_64Libh
#define __INCcacheX86_64Libh
#include "vxWorks.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CLFLUSH_DEF_BYTES 64 /* def bytes flushed by CLFLUSH */
#define CLFLUSH_MAX_BYTES 255 /* max bytes flushed with CLFLUSH */
/* Override cache calls */
#define cacheI86Reset cacheX86_64Reset
#define cacheI86Enable cacheX86_64Enable
#define cacheI86Disable cacheX86_64Disable
#define cacheI86Lock cacheX86_64Lock
#define cacheI86Unlock cacheX86_64Unlock
#define cacheI86Clear cacheX86_64Clear
#define cacheI86Flush cacheX86_64Flush
#define cachePen4Reset cacheX86_64Reset
#define cachePen4Enable cacheX86_64Enable
#define cachePen4Disable cacheX86_64Disable
#define cachePen4Lock cacheX86_64Lock
#define cachePen4Unlock cacheX86_64Unlock
#define cachePen4Clear cacheX86_64Clear
#define cachePen4Flush cacheX86_64Flush
#ifndef _ASMLANGUAGE
#if defined(__STDC__) || defined(__cplusplus)
extern void cacheX86_64Reset (void);
extern void cacheX86_64Enable (void);
extern void cacheX86_64Disable (void);
extern void cacheX86_64Lock (void);
extern void cacheX86_64Unlock (void);
extern void cacheX86_64Clear (CACHE_TYPE cache, void * address, size_t bytes);
extern void cacheX86_64Flush (CACHE_TYPE cache, void * address, size_t bytes);
#else
extern void cacheX86_64Reset ();
extern void cacheX86_64Enable ();
extern void cacheX86_64Disable ();
extern void cacheX86_64Lock ();
extern void cacheX86_64Unlock ();
extern void cacheX86_64Clear ();
extern void cacheX86_64Flush ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCcacheX86_64Libh */
vxworks-6.9/target/h/arch/i86/x86_64/dbgStrLib.h
+372
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@@ -0,0 +1,372 @@
/* dbgStrLib.h - Debug Store mechanism definitions header file */
/*
* Copyright 2001, 2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01c,29apr10,pad Moved extern C statement after include statements.
01b,24feb09,jb Update to 64-bits
01a,23jul01,hdn written
*/
#ifndef __INCdbgStrLibh
#define __INCdbgStrLibh
#include "arch/i86/regsP7.h"
#ifdef __cplusplus
extern "C" {
#endif
/* DS buffer : BTS/PEBS minimum/default/threshold size */
#define BTS_NBYTES_MIN 0x1000 /* 4KB minimum BTS buffer */
#define BTS_NBYTES_DEF 0x4000 /* 16KB default BTS buffer */
#define BTS_NBYTES_OFF 0x200 /* .5KB (max - threshold) BTS */
#define PEBS_NBYTES_MIN 0x1000 /* 4KB minimum PEBS buffer */
#define PEBS_NBYTES_DEF 0x4000 /* 16KB default PEBS buffer */
#define PEBS_NBYTES_OFF 0x200 /* .5KB (max - threshold) PEBS */
#define PEBS_DEF_RESET -1LL /* default reset counter value */
/* BTS : record bit */
#define BTS_PREDICTED 0x00000010 /* bit4: Branch Predicted */
/* PEBS : events */
#define PEBS_FRONT_END 0x01
#define PEBS_EXECUTION 0x02
#define PEBS_REPLAY 0x03
/* PEBS : metrics (Front End Event) */
#define PEBS_MEMORY_LOADS 0x01
#define PEBS_MEMORY_STORES 0x02
/* PEBS : metrics (Execution Event) */
#define PEBS_PACKED_SP 0x03
#define PEBS_PACKED_DP 0x04
#define PEBS_SCALAR_SP 0x05
#define PEBS_SCALAR_DP 0x06
#define PEBS_128BIT_MMX 0x07
#define PEBS_64BIT_MMX 0x08
#define PEBS_X87_FP 0x09
#define PEBS_X87_SIMD_MOVES 0x0a
/* PEBS : metrics (Replay Event) */
#define PEBS_1STL_CACHE_LOAD_MISS 0x0b
#define PEBS_2NDL_CACHE_LOAD_MISS 0x0c
#define PEBS_DTLB_LOAD_MISS 0x0d
#define PEBS_DTLB_STORE_MISS 0x0e
#define PEBS_DTLB_ALL_MISS 0x0f
#define PEBS_MOB_LOAD_REPLAY 0x10
#define PEBS_SPLIT_LOAD 0x11
#define PEBS_SPLIT_STORE 0x12
/* PEBS : ESCR, CCCR definitions (Front End Event) */
#define ESCR_FRONT_END \
(((0x08 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define CCCR_FRONT_END \
(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
CCCR_RSVD)
#define ESCR_MEMORY_LOADS \
(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define ESCR_MEMORY_STORES \
(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_2 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
/* PEBS : ESCR, CCCR definitions (Execution Event) */
#define ESCR_EXECUTION \
(((0x0c << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_0 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define CCCR_EXECUTION \
(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
CCCR_RSVD)
#define ESCR_PACKED_SP \
(((0x08 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_PACKED_DP \
(((0x0c << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_SCALAR_SP \
(((0x0a << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_SCALAR_DP \
(((0x0e << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_64BIT_MMX \
(((0x02 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_128BIT_MMX \
(((0x1a << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_X87_FP \
(((0x04 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_15 << DS_SHIFT_9) & ESCR_EVENT_MASK) |\
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define ESCR_X87_SIMD_MOVES \
(((0x2e << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
(((DS_BIT_3 | DS_BIT_4) << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
/* PEBS : ESCR, CCCR definitions (Replay Event) */
#define ESCR_REPLAY \
(((0x09 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_0 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
((DS_BIT_0 << DS_SHIFT_5) & ESCR_TAG_VALUE) | \
ESCR_TAG_ENABLE)
#define CCCR_REPLAY \
(((0x05 << DS_SHIFT_13) & CCCR_ESCR_SELECT) | \
CCCR_RSVD)
#define ESCR_MOB_LOAD_REPLAY \
(((0x03 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
(((DS_BIT_4 | DS_BIT_5) << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define ESCR_SPLIT_LOAD \
(((0x04 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
#define ESCR_SPLIT_STORE \
(((0x05 << DS_SHIFT_25) & ESCR_EVENT_SELECT) | \
((DS_BIT_1 << DS_SHIFT_9) & ESCR_EVENT_MASK) | \
ESCR_TAG_ENABLE)
/* DS : MSR(ESCR) bit definition */
#define DS_BIT_0 0x00000001
#define DS_BIT_1 0x00000002
#define DS_BIT_2 0x00000004
#define DS_BIT_3 0x00000008
#define DS_BIT_4 0x00000010
#define DS_BIT_5 0x00000020
#define DS_BIT_6 0x00000040
#define DS_BIT_7 0x00000080
#define DS_BIT_8 0x00000100
#define DS_BIT_9 0x00000200
#define DS_BIT_10 0x00000400
#define DS_BIT_11 0x00000800
#define DS_BIT_12 0x00001000
#define DS_BIT_13 0x00002000
#define DS_BIT_14 0x00004000
#define DS_BIT_15 0x00008000
#define DS_BIT_16 0x00010000
#define DS_BIT_17 0x00020000
#define DS_BIT_18 0x00040000
#define DS_BIT_19 0x00080000
#define DS_BIT_20 0x00100000
#define DS_BIT_21 0x00200000
#define DS_BIT_22 0x00400000
#define DS_BIT_23 0x00800000
#define DS_BIT_24 0x01000000
#define DS_BIT_25 0x02000000
#define DS_BIT_26 0x04000000
#define DS_BIT_27 0x08000000
#define DS_BIT_28 0x10000000
#define DS_BIT_29 0x20000000
#define DS_BIT_30 0x40000000
#define DS_BIT_31 0x80000000
/* DS : MSR(ESCR, CCCR) shift count definition */
#define DS_SHIFT_1 1
#define DS_SHIFT_2 2
#define DS_SHIFT_3 3
#define DS_SHIFT_4 4
#define DS_SHIFT_5 5
#define DS_SHIFT_6 6
#define DS_SHIFT_7 7
#define DS_SHIFT_8 8
#define DS_SHIFT_9 9
#define DS_SHIFT_10 10
#define DS_SHIFT_11 11
#define DS_SHIFT_12 12
#define DS_SHIFT_13 13
#define DS_SHIFT_14 14
#define DS_SHIFT_15 15
#define DS_SHIFT_16 16
#define DS_SHIFT_17 17
#define DS_SHIFT_18 18
#define DS_SHIFT_19 19
#define DS_SHIFT_20 20
#define DS_SHIFT_21 21
#define DS_SHIFT_22 22
#define DS_SHIFT_23 23
#define DS_SHIFT_24 24
#define DS_SHIFT_25 25
#define DS_SHIFT_26 26
#define DS_SHIFT_27 27
#define DS_SHIFT_28 28
#define DS_SHIFT_29 29
#define DS_SHIFT_30 30
#define DS_SHIFT_31 31
#ifndef _ASMLANGUAGE
typedef struct btsRec /* BTS (Branch Trace Store) record */
{
ULONG pcFm; /* Last Branch From */
ULONG pcTo; /* Last Branch To */
ULONG misc; /* bit4: Branch Predicted */
} BTS_REC;
typedef struct pebsRec /* PEBS (Precise Event Based Sampling) rec */
{
ULONG eflags; /* EFLAGS */
ULONG rip; /* Linear IP */
ULONG r15; /* R15 */
ULONG r14; /* R14 */
ULONG r13; /* R13 */
ULONG r12; /* R12 */
ULONG r11; /* R11 */
ULONG r10; /* R10 */
ULONG r9; /* R9 */
ULONG r8; /* R8 */
ULONG rax; /* RAX */
ULONG rbx; /* RBX */
ULONG rcx; /* RCX */
ULONG rdx; /* RDX */
ULONG rsi; /* RSI */
ULONG rdi; /* RDI */
ULONG rbp; /* RBP */
ULONG rsp; /* RSP */
} PEBS_REC;
typedef struct dsBufHeader /* DS (Debug Store) buffer management */
{
BTS_REC * btsBase; /* BTS buffer base */
BTS_REC * btsIndex; /* BTS index */
UINT32 btsMax; /* BTS absolute maximum */
UINT32 btsThreshold; /* BTS interrupt threshold */
PEBS_REC * pebsBase; /* PEBS buffer base */
PEBS_REC * pebsIndex; /* PEBS index */
UINT32 pebsMax; /* PEBS absolute maximum */
UINT32 pebsThreshold; /* PEBS interrupt threshold */
LL_INT pebsCtr; /* PEBS counter reset value */
UINT32 reserved[3]; /* reserved */
} DS_BUF_HEADER;
typedef struct dsConfig /* DS (Debug Store) configuration */
{
UINT32 btsNbytes; /* BTS buffer size */
BOOL btsAvailable; /* TRUE if BTS is available */
BOOL btsEnabled; /* TRUE if BTS is enabled */
BOOL btsIntMode; /* TRUE for interrupt mode */
BOOL btsBufMode; /* TRUE to store BTMs */
UINT32 pebsNbytes; /* PEBS buffer size */
BOOL pebsAvailable; /* TRUE if PEBS is available */
BOOL pebsEnabled; /* TRUE if PEBS is enabled */
INT32 pebsEvent; /* PEBS event */
INT32 pebsMetric; /* PEBS metric */
BOOL pebsOs; /* PEBS os */
LL_INT pebsCtr; /* PEBS counter */
DS_BUF_HEADER * pH; /* DS buffer header */
} DS_CONFIG;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS dbgStrLibInit (UINT32 nBytesBts, UINT32 nBytesPebs,
BOOL sysMode);
extern DS_BUF_HEADER * dbgStrBufInit (DS_BUF_HEADER * pH,
BTS_REC * btsBufAddr,
UINT32 btsMaxOffset,
UINT32 btsIntOffset,
PEBS_REC * pebsBufAddr,
UINT32 pebsMaxOffset,
UINT32 pebsIntOffset);
extern STATUS dbgStrBufAlloc (WIND_TCB * pTcb);
extern STATUS dbgStrBufFree (WIND_TCB * pTcb);
extern STATUS dbgStrConfig (WIND_TCB * pTcb,
BOOL btsEnable, BOOL pebsEnable,
BOOL btsIntMode, BOOL btsBufMode,
INT32 pebsEvent, INT32 pebsMetric,
BOOL pebsOs, LL_INT * pPebsValue);
extern STATUS dbgStrStart (WIND_TCB * pTcb);
extern STATUS dbgStrStop (WIND_TCB * pTcb);
extern STATUS dbgStrBtsModeSet (BOOL intMode, BOOL bufMode);
extern BOOL dbgStrBtsEnable (BOOL enable);
extern STATUS dbgStrPebsModeSet (INT32 event, INT32 metric, BOOL os,
LL_INT * pValue);
extern BOOL dbgStrPebsEnable (BOOL enable);
extern void dbgStrShowInit (void);
extern void dbgStrShow (WIND_TCB * pTcb, int type);
#else /* __STDC__ */
extern STATUS dbgStrLibInit ();
extern DS_BUF_HEADER * dbgStrBufInit ();
extern STATUS dbgStrBufAlloc ();
extern STATUS dbgStrBufFree ();
extern STATUS dbgStrConfig ();
extern STATUS dbgStrStart ();
extern STATUS dbgStrStop ();
extern STATUS dbgStrBtsModeSet ();
extern BOOL dbgStrBtsEnable ();
extern STATUS dbgStrPebsModeSet ();
extern BOOL dbgStrPebsEnable ();
extern void dbgStrShowInit ();
extern void dbgStrShow ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCdbgStrLibh */
vxworks-6.9/target/h/arch/i86/x86_64/dbgX86_64Lib.h
+171
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@@ -0,0 +1,171 @@
/* dbgX86_64Lib.h - header file for arch dependent portion of debugger */
/*
* Copyright (c) 2009-2010, 2012, 2016 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01l,20may16,jmp Imported from vxWorks 7 for WB4 debug support:
Added 8 bytes hardware breakpoint support (US11680).
Added VXDBG_HAS_HW_BP_SUPPORT_CHECK as VxDBG provides support
to dynamically detect if HW BP support is enabled on this
architecture (US39045).
01k,24jul12,scm WIND00225976 - syscall/sysret support...
01j,08nov10,scm adjust constants for 64 bit syscalls...
01i,22oct10,jmp Removed obsolete DSM() macro - Replaced by VXDBG_INSTR_CMP().
01h,23sep10,scm WIND00234092 -correctly manage "FS" during rtp breakpoint handling.
01g,17sep10,scm WIND00233372 -correct system call detection in
wdbDbgSysCallCheck.
01f,29apr10,pad Moved extern C statement after include statements.
01e,18may09,jmp Added missing prototypes for registers routines.
01d,13may09,rlp Added Hardware breakpoint support for LP64 model.
01c,20apr09,jb Update SAVED_DBGREGS for 64-bit
01b,20mar09,jmp removed DBG_INST_ALIGN definition (Use the default one).
01a,26jan09,jb Created from 32-bit version
*/
#ifndef __INCX86_64dbgh
#define __INCX86_64dbgh
/* includes */
#include <esf.h>
#include <regs.h>
#include <arch/i86/x86_64/instrX86_64.h>
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define BRK_INST (0x00) /* instruction hardware breakpoint */
#define BRK_DATAW1 (0x01) /* data write 1 byte breakpoint */
#define BRK_DATAW2 (0x05) /* data write 2 byte breakpoint */
#define BRK_DATAW4 (0x0d) /* data write 4 byte breakpoint */
#define BRK_DATAW8 (0x09) /* data write 8 byte breakpoint */
#define BRK_DATARW1 (0x03) /* data read-write 1 byte breakpoint */
#define BRK_DATARW2 (0x07) /* data read-write 2 byte breakpoint */
#define BRK_DATARW4 (0x0f) /* data read-write 4 byte breakpoint */
#define BRK_DATARW8 (0x0b) /* data read-write 8 byte breakpoint */
#define DEFAULT_HW_BP (BRK_DATARW1) /* default hardware breakpoint */
#define BRK_HARDWARE (0x10) /* hardware breakpoint bit */
#define BRK_HARDMASK (0x0f) /* hardware breakpoint mask */
#define SAVED_DBGREGS (0x30) /* 6 debug registers */
#define SAVED_REGS (0xC8) /* 19 + 6 registers */
#define TRACE_FLAG (0x0100) /* TF in EFLAGS */
#define INT_FLAG (0x0200) /* IF in EFLAGS */
#define DBG_HARDWARE_BP 1 /* hardware breakpoint support */
#define VXDBG_HAS_HW_BP_SUPPORT_CHECK 1
/* VxDBG provides HW BP support detection */
#ifndef _ASMLANGUAGE
#define DBG_BREAK_INST (0xcc) /* int 3 */
#define DBG_SYSCALL_SIZE 2 /* size of 'syscall' instruction */
/* instruction sequence of syscall */
#define DBG_SYSCALL_INST 0xfff883595b41050f
#define DBG_SYSCALL_INST_MASK 0xffffffffffffffff /* validate syscall matches */
/*
*
* Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B;
* System Programming Guide, Part 2 states:
*
* In 64-bit mode, the upper 32 bits of DR7 are reserved and must be written
* with zeros. Writing 1 to any of the upper 32 bits results in a #GP(0)
* exception.
*/
#define DR7_VALUE_SET(x) ((x) & 0xffffffff)
/* offsets to register fields in type REG_SET */
#define R15 (0)
#define R14 (1)
#define R13 (2)
#define R12 (3)
#define R11 (4)
#define R10 (5)
#define R9 (6)
#define R8 (7)
#define RDI (8)
#define RSI (9)
#define RBP (10)
#define RSP (11)
#define RBX (12)
#define RDX (13)
#define RCX (14)
#define RAX (15)
#define EFLAGS (16)
#define FS (19)
/* context save/load for WDB */
#define WDB_CTX_SAVE(pRegs) (_wdbCtxSave (pRegs))
#define WDB_CTX_LOAD(pRegs) (_wdbCtxLoad (pRegs))
/* typedefs */
/* aliases for type <ESF2> */
typedef ESF2 BREAK_ESF;
typedef ESF2 TRACE_ESF;
/* hardware breakpoint registers */
typedef struct /* DBG_REGS */
{
ULONG db0; /* debug register 0 */
ULONG db1; /* debug register 1 */
ULONG db2; /* debug register 2 */
ULONG db3; /* debug register 3 */
ULONG db6; /* debug register 6 */
ULONG db7; /* debug register 7 */
} DBG_REGS;
/* function declarations (XXX Following lines should be in a private file) */
extern void _wdbCtxLoad (const REG_SET *);
extern int _wdbCtxSave (const REG_SET *);
extern long rdi (long taskId);
extern long rsi (long taskId);
extern long rbp (long taskId);
extern long rsp (long taskId);
extern long rbx (long taskId);
extern long rdx (long taskId);
extern long rcx (long taskId);
extern long rax (long taskId);
extern long rflags (long taskId);
extern long r8 (long taskId);
extern long r9 (long taskId);
extern long r10 (long taskId);
extern long r11 (long taskId);
extern long r12 (long taskId);
extern long r13 (long taskId);
extern long r14 (long taskId);
extern long r15 (long taskId);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCX86_64dbgh */
vxworks-6.9/target/h/arch/i86/x86_64/dsmX86_64Lib.h
+762
View File
@@ -0,0 +1,762 @@
/* dsmX86_64Lib.h - x86_64 disassembler header */
/*
* Copyright (c) 2009, 2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01f,16sep10,mcm Get OPRINTF_OUTPUT_FUNCPTR prototype from stdio.h
01e,29apr10,pad Moved extern C statement after include statements.
01d,02sep09,scm clean up new compiler warnings...
01c,30jun09,scm resolve FUNCPTR...
01b,05may09,scm make 64bit compliant...
01a,10feb09,jb Created from 32-bit version 01m
*/
#ifndef __INCdsmX86_64Libh
#define __INCdsmX86_64Libh
/* includes */
#include <vwModNum.h>
#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
/* dsmLib status codes */
#define S_dsmLib_UNKNOWN_INSTRUCTION (M_dsmLib | 1)
#define DSM_BUFSIZE16 (16)
#define DSM_BUFSIZE32 (32)
#define DSM_BUFSIZE64 (64)
/* instruction table opcode entry format */
typedef struct /* INST */
{
char *pOpc; /* Instruction Name */
UINT type; /* instruction type */
UINT flag; /* instruction flag */
UINT flag2; /* instruction flag2 */
UINT flag3; /* instruction flag2 */
UCHAR op0; /* opcode 0 */
UCHAR op1; /* opcode 1 */
UCHAR op2; /* opcode 2 */
UCHAR op3; /* opcode 3 */
UCHAR op4; /* opcode 4 */
UCHAR op5; /* opcode 5 */
UCHAR mask0; /* mask 0 */
UCHAR mask1; /* mask 1 */
UCHAR mask2; /* mask 2 */
UCHAR mask3; /* mask 3 */
UCHAR mask4; /* mask 4 */
UCHAR mask5; /* mask 5 */
} INST;
/* FORMAT_X - repository for data collection on opcode entry */
typedef struct /* FORMAT_X */
{
INST *pI; /* pointer to an INST descriptor */
char *pD; /* opcode data pointer */
char *pOpc; /* instruction name pointer */
char *pRx; /* REX prefix name pointer */
BOOL prefixRex; /* prefix REX, 0x40 - 0x4f */
UINT instrOp; /* instruction opcode */
UINT rexOp; /* REX prefix opcode */
size_t pOpcLen; /* len of instruction + prefix string */
char obuf [DSM_BUFSIZE32]; /* instruction name buffer */
char rxbuf [DSM_BUFSIZE16]; /* REX prefix name buffer */
int a64; /* address size 0,1,2 */
int d64; /* data size 0,1,2 */
int lenO; /* opcode length 1,2,3 */
int lenD; /* displacement length 0,1,2,4 */
int lenI; /* immediate length 0,1,2,4 */
int modrm; /* MODRM byte present 0,1 */
int sib; /* SIB byte present 0,1 */
int w; /* W -data is byte or full-sized 0,1 */
int d; /* D -direction of data operation 0,1 */
int s; /* S -sign ext of immediate field 0,1 */
int mod; /* MODRM byte, mod bits 6,7 */
int reg; /* MODRM byte, reg bits 3,4,5, 8 bits */
int rm; /* MODRM byte, rm bits 0,1,2 */
int ss; /* SIB byte, scale bits 6,7 */
int index; /* SIB byte, index bits 3.4.5 */
int base; /* SIB byte, base bits 0,1,2 */
int mf;
int st;
int fd;
int rexW; /* rexW -64bit op size: 0,1 */
int rexR; /* rexR -ext reg field: 0,1 */
int rexX; /* rexX -ext index field: 0,1 */
int rexB; /* rexB -ext base field: 0,1 */
} FORMAT_X;
/* FORMAT_Y - format data collected on opcode entry */
typedef struct /* FORMAT_Y */
{
char *pD; /* opcode data pointer */
char *pOpc; /* instruction name pointer */
char *pOpr0; /* output string 0 */
char *pOpr1; /* output string 1 */
char *pOpr2; /* output string 2 */
int len; /* instruction length */
_Vx_usr_arg_t addr; /* address operand */
char obuf [DSM_BUFSIZE32]; /* opcode buffer */
char rbuf [DSM_BUFSIZE16]; /* register buffer */
char mbuf [DSM_BUFSIZE32]; /* memory buffer */
char temp [DSM_BUFSIZE32]; /* temporary buffer */
char ibuf [DSM_BUFSIZE16]; /* immediate buffer */
char dbuf [DSM_BUFSIZE16]; /* displacement buffer */
} FORMAT_Y;
/* bit definitions */
/* -/digiti, the reg field contains a digit betweeb 0 and 7 that
* provides an extension to the instruction's opcode
*/
#define DSM_SLSH_0 (0x00)
#define DSM_SLSH_1 (0x08)
#define DSM_SLSH_2 (0x10)
#define DSM_SLSH_3 (0x18)
#define DSM_SLSH_4 (0x20)
#define DSM_SLSH_5 (0x28)
#define DSM_SLSH_6 (0x30)
#define DSM_SLSH_7 (0x38)
/*
* 7 6 5 3 2 0
* +-----------------------+
* | Mod | Reg/Op | R/M | ModR/M
* +-----------------------+
*/
#define MODRM_MOD (0xc0)
#define MODRM_REG (0x38)
#define MODRM_RM (0x07)
#define DSM_REG (0x03)
#define DSM_MOD (0x06)
/*
* 7 6 5 3 2 0
* +-----------------------+
* | Scale | Index | Base | SIB
* +-----------------------+
*/
#define SIB_SS (0xc0)
#define SIB_INDEX (0x38)
#define SIB_BASE (0x07)
#define DSM_INDEX (0x03)
#define DSM_SS (0x06)
/* REX prefix bits: "0100_WRXB", 0x40 thru 0x4F */
/* NOTE: REX prefixes that promote legacy instructions to 64-bit behavior
* are not listed explicitly in the opcode column.
*/
#define REX (0x40)
#define REXB (0x01)
#define REXX (0x02)
#define REXR (0x04)
#define REXW (0x08)
#define DSM_EXT (0x08)
/* MSB of flag byte is not included in switch statement used
* to format the output.
*/
/* MODRM must be defined if REG, MMXREG, XMMREG are defined */
#define SF (0x10000000)
#define OP1 (0x20000000) /* 1 byte opcode format */
#define OP2 (0x40000000) /* 2 byte opcode format */
#define OP3 (0x80000000) /* 3 byte opcode format */
#define DSM_1B (0x00000001) /* 1 byte(s) of data represents opcode */
#define DSM_2B (0x00000002) /* 2 byte(s) of data represents opcode */
#define DSM_3B (0x00000004) /* 3 byte(s) of data represents opcode */
#define DSM_4B (0x00000008) /* 4 byte(s) of data represents opcode */
#define DSM_5B (0x00000010) /* 5 byte(s) of data represents opcode */
#define DSM_6B (0x00000020) /* 6 byte(s) of data represents opcode */
#define DSM_MXB (0x0000001f) /* range of byte(s) used to represent opcode */
/* (currently 1 thru 5) */
#define WFUL (0x01000000) /* operand size bit */
#define SEXT (0x02000000) /* sign extend flag */
#define DISR (0x04000000) /* data direction info encoded in opcode */
#define TTT (0x08000000) /* hack to look for rotate instructions */
#define TTTN (0x00100000) /* opcode least significant byte
* bits 0-4 = condition test field */
#define MF (0x00200000) /* opcode bits 1-2 are = register size info */
#define POP (0x00400000) /* cat a "P" to end of instruction name */
#define IMM (0x00000001)
#define I8 (0x00000002) /* imm8 byte exists */
#define DIS (0x00000004) /* displacement info */
#define D8 (0x00000008) /* displacement info */
#define D16 (0x00000010) /* displacement info */
#define AX (0x00000020) /* store into AX register */
#define CL (0x00000040) /* cat "CL" to end of operands */
#define REG (0x00000080) /* modrm bits 3-5 = register specifier */
#define SREG2 (0x00000100) /* modrm bits 3-4 = 2 bit segment register */
#define SREG3 (0x00000200) /* modrm bits 3-5 = 3 bit segment register */
#define MODRM (0x00000400) /* modrm byte exists */
#define EEE (0x00000800) /* modrm bits 3-5 = control/debug register */
#define REGRM (0x00001000) /* modrm bits 0-2 = register specifier */
#define PORT (0x00002000) /* use a port as an operand */
#define INS64 (0x00004000) /* 64 bit instruction */
#define D16L8 (0x00008000) /* displacement info */
#define FD (0x00010000) /* stack element is destination */
#define ST (0x00020000) /* stack element is operand */
#define MMXRM (0x00040000) /* modrm bits 0-2 = MMX register */
#define MMXREG (0x00080000) /* modrm bits 3-5 = MMX register */
#define GG (0x00800000) /* least sign opcode byte
* bits 0-1 = MMX granularity */
/* bit definitions of flag2 */
#define XMMRM (0x00000001) /* modrm bits 0-2 = XMM register */
#define XMMREG (0x00000002) /* modrm bits 3-5 = XMM register */
#define ESC (0xd8) /* for co-processor instructions */
/* instruction types */
#define itAddItoA 1
#define itAddItoRM 2
#define itAddRMtoRM 3
#define itAndItoA 4
#define itAndItoRM 5
#define itAndRMtoRM 6
#define itAsize 7
#define itBound 8
#define itBsf 9
#define itBsr 10
#define itBtI 11
#define itBtR 12
#define itBtcI 13
#define itBtcR 14
#define itBtrI 15
#define itBtrR 16
#define itBtsI 17
#define itBtsR 18
#define itCall 19
#define itCallRM 20
#define itCallSegRM 21
#define itCbw 22
#define itCjmp 23
#define itClc 24
#define itCld 25
#define itCli 26
#define itClts 27
#define itCmc 28
#define itCmpIwiA 29
#define itCmpIwiRM 30
#define itCmpRMwiRM 31
#define itCmps 32
#define itCs 33
#define itCset 34
#define itCwd 35
#define itDecRM 36
#define itDiv 37
#define itDs 38
#define itEnter 39
#define itEs 40
#define itFs 41
#define itGs 42
#define itHlt 43
#define itIdiv 44
#define itImulAwiRM 45
#define itImulRMwiI 46
#define itImulRwiRM 47
#define itInF 48
#define itInV 49
#define itIncRM 50
#define itIns 51
#define itInt 52
#define itInt3 53
#define itIret 54
#define itJcxz 55
#define itJmpD 56
#define itJmpRM 57
#define itJmpS 58
#define itJmpSegRM 59
#define itLar 60
#define itLea 61
#define itLeave 62
#define itLfs 63
#define itLgdt 64
#define itLgs 65
#define itLidt 66
#define itLldt 67
#define itLmsw 68
#define itLock 69
#define itLods 70
#define itLoop 71
#define itLoopnz 72
#define itLoopz 73
#define itLsl 74
#define itLss 75
#define itLtr 76
#define itMovAMtoMA 77
#define itMovC 78
#define itMovD 79
#define itMovItoR 80
#define itMovItoRM 81
#define itMovRMtoMR 82
#define itMovRMtoS 83
#define itMovRtoRM 84
#define itMovStoRM 85
#define itMovT 86
#define itMovs 87
#define itMovsx 88
#define itMovsxd 89
#define itMovzx 90
#define itMulAwiRM 91
#define itNeg 92
#define itNop 93
#define itNot 94
#define itOrItoA 95
#define itOrItoRM 96
#define itOrRMtoRM 97
#define itOsize 98
#define itOutF 99
#define itOutV 100
#define itOuts 101
#define itPopS 102
#define itPopR 103
#define itPopRM 104
#define itPopf 105
#define itPushS 106
#define itPushI 107
#define itPushR 108
#define itPushRM 109
#define itPushf 110
#define itRNcmps 111
#define itRNscas 112
#define itRcmps 113
#define itRet 114
#define itRetI 115
#define itRetSeg 116
#define itRetSegI 117
#define itRins 118
#define itRlods 119
#define itRmovs 120
#define itRolRMby1 121
#define itRolRMbyCL 122
#define itRolRMbyI 123
#define itRouts 124
#define itRscas 125
#define itRstos 126
#define itSbbIfrA 127
#define itSbbIfrRM 128
#define itSbbRMfrRM 129
#define itScas 130
#define itSgdt 131
#define itShldRMbyCL 132
#define itShldRMbyI 133
#define itShrdRMbyCL 134
#define itShrdRMbyI 135
#define itSmsw 136
#define itSs 137
#define itStc 138
#define itStd 139
#define itSti 140
#define itStos 141
#define itStr 142
#define itSubIfrA 143
#define itSubIfrRM 144
#define itSubRMfrRM 145
#define itTestIanA 146
#define itTestIanRM 147
#define itTestRManR 148
#define itWait 149
#define itXchgA 150
#define itXchgRM 151
#define itXlat 152
/* instructions for 387 */
#define itF2xm1 200
#define itFabs 201
#define itFaddIRM 202
#define itFaddST 203
#define itFchs 204
#define itFclex 205
#define itFcomIRM 206
#define itFcomST 207
#define itFcompIRM 208
#define itFcompST 209
#define itFcompp 210
#define itFcos 211
#define itFdecstp 212
#define itFdivIRM 213
#define itFdivST 214
#define itFfree 215
#define itFincstp 216
#define itFinit 217
#define itFld1 218
#define itFldBCDM 219
#define itFldERM 220
#define itFldIRM 221
#define itFldL2E 222
#define itFldL2T 223
#define itFldLG2 224
#define itFldLIM 225
#define itFldLN2 226
#define itFldPI 227
#define itFldST 228
#define itFldZ 229
#define itFldcw 230
#define itFldenv 231
#define itFmulIRM 232
#define itFmulST 233
#define itFnop 234
#define itFpatan 235
#define itFprem 236
#define itFprem1 237
#define itFptan 238
#define itFrndint 239
#define itFrstor 240
#define itFsave 241
#define itFscale 242
#define itFsin 243
#define itFsincos 244
#define itFsqrt 245
#define itFstIRM 246
#define itFstST 247
#define itFstcw 248
#define itFstenv 249
#define itFstpBCDM 250
#define itFstpERM 251
#define itFstpIRM 252
#define itFstpLIM 253
#define itFstpST 254
#define itFstsw 255
#define itFstswA 256
#define itFsubIRM 257
#define itFsubST 258
#define itFtst 259
#define itFucom 260
#define itFucomp 261
#define itFucompp 262
#define itFxam 263
#define itFxch 264
#define itFxtract 265
#define itFyl2x 266
#define itFyl2xp1 267
#define itFcmovb 268
#define itFcmove 269
#define itFcmovbe 270
#define itFcmovu 271
#define itFcmovnb 272
#define itFcmovne 273
#define itFcmovnbe 274
#define itFcmovnu 275
#define itFcomi 276
/* addendum */
#define itAdcItoRM 300
#define itAdcItoA 301
#define itAdcRMtoRM 302
#define itRep 303
#define itRepNe 304
#define itSidt 305
#define itSldt 306
#define itVerr 307
#define itVerw 308
#define itXorItoRM 309
#define itXorItoA 310
#define itXorRMtoRM 311
/* 80486 instructions */
#define itBswap 400
#define itCmpxchg 401
#define itInvd 402
#define itInvlpg 403
#define itWbinvd 404
#define itXadd 405
/* P5 instructions */
#define itCmpxchg8b 500
#define itCpuid 501
#define itRdtsc 502
#define itRdmsr 503
#define itWrmsr 504
/* P6 instructions */
#define itCmovcc 600
#define itRdpmc 601
#define itUd2 602
#define itSysenter 603
#define itSysexit 604
/* MMX/SSE2 instructions */
#define itEmms 700
#define itMovd 701
#define itMovq 702
#define itPackssdw 703
#define itPacksswb 704
#define itPackuswb 705
#define itPadd 706
#define itPadds 707
#define itPaddus 708
#define itPand 709
#define itPandn 710
#define itPcmpeq 711
#define itPcmpgt 712
#define itPcmpgtq 713
#define itPhadd 714
#define itPhminposuw 715
#define itPhsub 716
#define itPmadd 717
#define itPmaddubsw 718
#define itPmovsx 719
#define itPmovzx 720
#define itPmuldq 721
#define itPmulld 722
#define itPmulhrsw 723
#define itPmulh 724
#define itPmull 725
#define itPor 726
#define itPround 727
#define itPsign 728
#define itPsll 729
#define itPsra 730
#define itPsrl 731
#define itPsub 732
#define itPsubs 733
#define itPsubus 734
#define itPsubq 735
#define itPunpckh 736
#define itPunpckl 737
#define itPxor 738
/* SSE/SSE2 instructions */
#define itAddpd 800
#define itAddps 801
#define itAddsd 802
#define itAddss 803
#define itAndnpd 804
#define itAndnps 805
#define itAndpd 806
#define itAndps 807
#define itCmppd 808
#define itCmpps 809
#define itCmpsd 810
#define itCmpss 811
#define itComiss 812
#define itCvtdq2pd 813
#define itCvtdq2ps 814
#define itCvtpd2dq 815
#define itCvtpd2ps 816
#define itCvtpi2pd 817
#define itCvtpi2ps 818
#define itCvtps2dq 819
#define itCvtps2pd 820
#define itCvtps2pi 821
#define itCvtsd2si 822
#define itCvtsd2ss 823
#define itCvtsi2sd 824
#define itCvtsi2ss 825
#define itCvtss2sd 826
#define itCvtss2si 827
#define itCvttpd2dq 828
#define itCvttpd2pi 829
#define itCvttps2dq 830
#define itCvttps2pi 831
#define itCvttsd2si 832
#define itCvttss2si 833
#define itDivpd 834
#define itDivps 835
#define itDivsd 836
#define itDivss 837
#define itFxrstor 838
#define itFxsave 839
#define itLdmxcsr 840
#define itMaskmovdqu 841
#define itMaskmovq 842
#define itMaxpd 843
#define itMaxps 844
#define itMaxsd 845
#define itMaxss 846
#define itMinpd 847
#define itMinps 848
#define itMinsd 849
#define itMinss 850
#define itMovapd 851
#define itMovaps 852
#define itMovdq2q 853
#define itMovdqa 854
#define itMovdqu 855
#define itMovhlps 856
#define itMovhpd 857
#define itMovhps 858
#define itMovlhps 859
#define itMovlpd 860
#define itMovlps 861
#define itMovmskpd 862
#define itMovmskps 863
#define itMovntdq 864
#define itMovntpd 865
#define itMovntps 866
#define itMovntq 867
#define itMovq2dq 868
#define itMovsd 869
#define itMovss 870
#define itMovupd 871
#define itMovups 872
#define itMulpd 873
#define itMulps 874
#define itMulsd 875
#define itMulss 876
#define itOrpd 877
#define itOrps 878
#define itPavgb 879
#define itPavgw 880
#define itPextrw 881
#define itPextrd 882
#define itPinsrw 883
#define itPmaxsw 884
#define itPmaxub 885
#define itPminsw 886
#define itPminub 887
#define itPmovmskb 888
#define itPmulhuw 889
#define itPmuludq 890
#define itPrefetchnta 891
#define itPrefetcht0 892
#define itPrefetcht1 893
#define itPrefetcht2 894
#define itPsadbw 895
#define itPshufd 896
#define itPshufhw 897
#define itPshuflw 898
#define itPshufw 899
#define itPshufb 900
#define itPslldq 901
#define itPsrldq 902
#define itPtest 903
#define itPunpckhqdq 904
#define itPunpcklqdq 905
#define itRcpps 906
#define itRcpss 907
#define itRsqrtps 908
#define itRsqrtss 909
#define itSfence 910
#define itShufps 911
#define itShufpd 912
#define itSqrtpd 913
#define itSqrtps 914
#define itSqrtsd 915
#define itSqrtss 916
#define itStmxcsr 917
#define itSubpd 918
#define itSubps 919
#define itSubsd 920
#define itSubss 921
#define itUcomisd 922
#define itUcomiss 923
#define itUnpckhpd 924
#define itUnpckhps 925
#define itUnpcklpd 926
#define itUnpcklps 927
#define itXorpd 928
#define itXorps 929
/* Pentium 4 instructions */
#define itClflush 1000
#define itCrc32 1001
#define itLfence 1002
#define itMfence 1003
#define itMovnti 1004
#define itPause 1005
#define itPopcnt 1006
#define itRdtscp 1007
#define itSwapgs 1008
#define itSyscall 1009
#define itSysret 1010
#define itXrstor 1011
#define itXsave 1012
#define itXgetbv 1013
#define itXsetbv 1014
/* REX Prefixes */
#define itRex 1100
#define itRex_B 1101
#define itRex_X 1102
#define itRex_XB 1103
#define itRex_R 1104
#define itRex_RB 1105
#define itRex_RX 1106
#define itRex_RXB 1107
#define itRex_W 1108
#define itRex_WB 1109
#define itRex_WX 1110
#define itRex_WXB 1111
#define itRex_WR 1112
#define itRex_WRB 1113
#define itRex_WRX 1114
#define itRex_WRXB 1115
typedef void (*NPRTADDRESS_OUTPUT_FUNCPTR)(_Vx_usr_arg_t, OPRINTF_OUTPUT_FUNCPTR, _Vx_usr_arg_t);
/* function declarations */
#if defined (__STDC__) || defined (__cplusplus)
IMPORT int dsmData (UCHAR * pD, _Vx_usr_arg_t address, OPRINTF_OUTPUT_FUNCPTR oFn, _Vx_usr_arg_t oArg);
IMPORT int dsmInst (UCHAR * pD, _Vx_usr_arg_t address, NPRTADDRESS_OUTPUT_FUNCPTR prtAddress,
OPRINTF_OUTPUT_FUNCPTR, _Vx_usr_arg_t);
IMPORT int dsmNbytes (UCHAR *);
#else
IMPORT int dsmData ();
IMPORT int dsmInst ();
IMPORT int dsmNbytes ();
#endif /* __STDC__ */
#ifdef __cplusplus
}
#endif
#endif /* __INCdsmX86_64Libh */
vxworks-6.9/target/h/arch/i86/x86_64/elfX86_64.h
+65
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@@ -0,0 +1,65 @@
/* elfX86_64.h - i86-specific ELF loader header */
/*
* Copyright (c) 2001-2005 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software may be
* licensed only pursuant to the terms of an applicable Wind River license
* agreement.
*/
/*
modification history
--------------------
01c,25jul05,v_r Updated copyright.
01b,27feb04,pad Renamed relocation type R_386_JUMP_SLOT as R_386_JMP_SLOT as
per ABI.
01a,12sep01,pad Backported from TAE 3.1 to T2.2 with necessary adaptations
(base version: elfX86_64.h@@/main/tor3_x/1).
*/
#ifndef __INCelfX86_64h
#define __INCelfX86_64h
#ifdef __cplusplus
extern "C" {
#endif
#define EM_ARCH_MACHINE EM_386
#define EM_ARCH_MACH_ALT EM_486 /* not used */
/*
* Relocation Type Definitions
* The only ones that appear in vxWorks archives are "1" and "2"
*/
#define R_386_NONE 0 /* No reloc */
#define R_386_32 1 /* Direct 32 bit */
#define R_386_PC32 2 /* PC relative 32 bit */
#define R_386_GOT32 3 /* 32 bit GOT entry */
#define R_386_PLT32 4 /* 32 bit PLT address */
#define R_386_COPY 5 /* Copy symbol at runtime */
#define R_386_GLOB_DAT 6 /* Create GOT entry */
#define R_386_JMP_SLOT 7 /* Create PLT entry */
#define R_386_RELATIVE 8 /* Adjust by program base */
#define R_386_GOTOFF 9 /* 32 bit offset to GOT */
#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */
/* These 16-bit and 8-bit relocs should never show up */
#define R_386_16 20
#define R_386_PC16 21
#define R_386_8 22
#define R_386_PC8 23
#define R_386_max 24
/* These are GNU extensions to enable C++ vtable garbage collection. */
#define R_386_GNU_VTINHERIT 250
#define R_386_GNU_VTENTRY 251
#ifdef __cplusplus
}
#endif
#endif /* __INCelfX86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/esfX86_64.h
+114
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/* esfX86_64.h - x86_64 exception stack frames */
/*
* Copyright 2009 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01e,24feb09,jb Update to 64-bits
01d,21jan09,jb 64-bit version from 32-bit version 01c
*/
#ifndef __INCesfX86_64h
#define __INCesfX86_64h
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
/* Override eflags references */
#define eflags rflags
/* Exception stack frames. Most of these can happen only for one
CPU or another, but they are all defined for all CPU's */
/* Format-0 - no privilege change, no error code */
typedef struct
{
INSTR * pc; /* 0x00 : PC */
unsigned long cs; /* 0x08 : code segment */
unsigned long rflags; /* 0x10 : EFLAGS */
} ESF0; /* sizeof(ESF0) -> 0x18 */
/* Format-1 - no privilege change, error code */
typedef struct
{
unsigned long errCode; /* 0x00 : error code */
INSTR * pc; /* 0x08 : PC */
unsigned long cs; /* 0x10 : code segment */
unsigned long rflags; /* 0x18 : EFLAGS */
} ESF1; /* sizeof(ESF1) -> 0x20 */
/* Format-2 - privilege change, no error code */
typedef struct
{
INSTR * pc; /* 0x00 : PC */
unsigned long cs; /* 0x08 : code segment */
unsigned long rflags; /* 0x10 : EFLAGS */
unsigned long esp; /* 0x18 : ESP */
unsigned long ss; /* 0x20 : SS */
} ESF2; /* sizeof(ESF2) -> 0x28 */
/* Format-3 - privilege change, error code */
typedef struct
{
unsigned long errCode; /* 0x00 : error code */
INSTR * pc; /* 0x08 : PC */
unsigned long cs; /* 0x10 : code segment */
unsigned long rflags; /* 0x18 : EFLAGS */
unsigned long esp; /* 0x20 : ESP */
unsigned long ss; /* 0x28 : SS */
} ESF3; /* sizeof(ESF3) -> 0x30 */
#endif /* _ASMLANGUAGE */
#define ESF0_EIP 0x00 /* 0x00 : PC */
#define ESF0_CS 0x08 /* 0x08 : CS */
#define ESF0_EFLAGS 0x10 /* 0x10 : EFLAGS */
#define ESF1_ERROR 0x00 /* 0x00 : ERROR */
#define ESF1_EIP 0x08 /* 0x08 : PC */
#define ESF1_CS 0x10 /* 0x10 : CS */
#define ESF1_EFLAGS 0x18 /* 0x18 : EFLAGS */
#define ESF2_EIP 0x00 /* 0x00 : PC */
#define ESF2_CS 0x08 /* 0x08 : CS */
#define ESF2_EFLAGS 0x10 /* 0x10 : EFLAGS */
#define ESF2_ESP 0x18 /* 0x18 : ESP */
#define ESF2_SS 0x20 /* 0x20 : SS */
#define ESF3_ERROR 0x00 /* 0x00 : ERROR */
#define ESF3_EIP 0x08 /* 0x08 : PC */
#define ESF3_CS 0x10 /* 0x10 : CS */
#define ESF3_EFLAGS 0x18 /* 0x18 : EFLAGS */
#define ESF3_ESP 0x20 /* 0x20 : ESP */
#define ESF3_SS 0x28 /* 0x28 : SS */
#define ESF0_NBYTES 0x18 /* sizeof(ESF0) */
#define ESF1_NBYTES 0x20 /* sizeof(ESF1) */
#define ESF2_NBYTES 0x28 /* sizeof(ESF2) */
#define ESF3_NBYTES 0x30 /* sizeof(ESF3) */
#define ESF0_NLONGS 0x03 /* sizeof(ESF0) / sizeof(long) */
#define ESF1_NLONGS 0x04 /* sizeof(ESF1) / sizeof(long) */
#define ESF2_NLONGS 0x05 /* sizeof(ESF2) / sizeof(long) */
#define ESF3_NLONGS 0x06 /* sizeof(ESF3) / sizeof(long) */
#ifdef __cplusplus
}
#endif
#endif /* __INCesfX86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/excX86_64Lib.h
+130
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/* excX86_64Lib.h - exception library header */
/*
* Copyright 2009, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01c,25jun12,pad Added missing exception macro definitions (part of fix for
defect #353696).
01b,23feb09,jb Initial port to 64-bits
01a,26jan09,jb Created from 32-bit version
*/
#ifndef __INCexcX86_64Libh
#define __INCexcX86_64Libh
#ifdef __cplusplus
extern "C" {
#endif
/* lowest and highest vector number to initialize */
#define LOW_VEC 0 /* lowest initialized vector */
#define HIGH_VEC 0xff /* highest initialized vector */
/* ESF Pointer for exception handler */
#define ESF_EXCBASE 0x90
#ifndef _ASMLANGUAGE
typedef struct
{
UINT16 valid; /* indicators that following fields are valid */
UINT16 vecNum; /* vector number */
ULONG errCode; /* error code */
INSTR * pc; /* program counter */
ULONG rflags; /* rflags register */
UINT16 cs; /* code segment register */
UINT16 pad; /* pad to four byte boundary */
ULONG esp; /* stack pointer in the ESF */
ULONG ss; /* stack segment in the ESF */
ULONG esp0; /* supervisor (PL0) stack pointer */
ULONG cr2; /* CR2 */
ULONG cr3; /* CR3 */
ULONG esp00; /* content of the stack *(esp0 + 0) */
ULONG esp01; /* content of the stack *(esp0 + 1) */
ULONG esp02; /* content of the stack *(esp0 + 2) */
ULONG esp03; /* content of the stack *(esp0 + 3) */
ULONG esp04; /* content of the stack *(esp0 + 4) */
ULONG esp05; /* content of the stack *(esp0 + 5) */
ULONG esp06; /* content of the stack *(esp0 + 6) */
ULONG esp07; /* content of the stack *(esp0 + 7) */
ULONG reserved0; /* reserved 0 */
ULONG reserved1; /* reserved 1 */
ULONG reserved2; /* reserved 2 */
ULONG reserved3; /* reserved 3 */
} EXC_INFO;
#define _WRS_IS_SUPV_EXC() (((excInfo.cs & 0x3) == 0) ? TRUE : FALSE)
/* exception info valid bits */
#define EXC_VEC_NUM 0x01 /* vector number valid */
#define EXC_ERROR_CODE 0x02 /* error code valid */
#define EXC_ESP_SS 0x04 /* ESP and SS valid */
#define EXC_CR2 0x08 /* CR2 valid */
#define EXC_FP_CONTEXT 0x10 /* FP_CONTEXT valid */
#define EXC_INVALID_TYPE 0x80 /* special indicator: ESF type was bad;
* type is in funcCode field */
/* exception vector number */
#define EXC_DIVIDE_ERROR 0x00 /* divide error */
#define EXC_DEBUG 0x01 /* debug */
#define EXC_NMI 0x02 /* NMI */
#define EXC_INT3 0x03 /* breakpoint */
#define EXC_OVERFLOW 0x04 /* overflow */
#define EXC_BOUNDS_CHECK 0x05 /* bounds check */
#define EXC_INVALID_OPCODE 0x06 /* invalid opcode */
#define EXC_DEVICE_NOT_AVAILABLE 0x07 /* device not available */
#define EXC_DOUBLE_FAULT 0x08 /* double fault */
#define EXC_COPROC_OVERRUN 0x09 /* coprocessor segment overrun */
#define EXC_INVALID_TSS 0x0a /* invalid TSS */
#define EXC_SEGMENT_NOT_PRESENT 0x0b /* segment not present */
#define EXC_STACK_SEGMENT_FAULT 0x0c /* stack segment fault */
#define EXC_GENERAL_PROTECTION 0x0d /* general protection */
#define EXC_PAGE_FAULT 0x0e /* page fault */
#define EXC_RESERVED 0x0f /* Intel-reserved */
#define EXC_FP_ERROR 0x10 /* Floating-point error */
#define EXC_ALIGNMENT_CHECK 0x11 /* alignment check */
#define EXC_MACHINE_CHECK 0x12 /* machine check */
#define EXC_SIMD_ERROR 0x13 /* SIMD Float exception */
/* variable declarations */
extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void excStub (void);
extern void excStub0 (void);
extern void excStub1 (void);
extern void excIntStub (void);
#else /* __STDC__ */
extern void excStub ();
extern void excStub0 ();
extern void excStub1 ();
extern void excIntStub ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCexcX86_64Libh */
vxworks-6.9/target/h/arch/i86/x86_64/fppX86_64Lib.h
+311
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/* fppX86_64Lib.h - floating-point coprocessor support library header */
/* Copyright 2009-2011 Wind River Systems, Inc. */
/*
modification history
--------------------
01h,22dec11,jjk WIND00313302 - Fix display of FP/MMX registers
01g,27jul11,g_x add xmm[] and ymm[] to FPREG_SET (WIND00285122)
01f,22mar11,ggm WIND00262870 - Added fppArchCpuInit.
01e,19jan11,ggm XSave / XRestore implementation for extended state context
switch.
01d,29sep10,scm adjust offset for FPXREG_FPX for DOUBLEX_SSE structs...
01c,23sep10,scm adjust 64 bit structures...
01b,08jul09,scm FUNCPTR conversion...
01a,26jan09,jb Create 64-bit version from 32-bit version 01h
*/
#ifndef __INCfppX86_64Libh
#define __INCfppX86_64Libh
#ifdef __cplusplus
extern "C" {
#endif
/* control register: defines for control word */
#define FPCR_IM 0x0001 /* IM exc-mask invalid operation */
#define FPCR_DM 0x0002 /* DM exc-mask denormalized operand */
#define FPCR_ZM 0x0004 /* ZM exc-mask zero divide */
#define FPCR_OM 0x0008 /* OM exc-mask overflow */
#define FPCR_UM 0x0010 /* UM exc-mask underflow */
#define FPCR_PM 0x0020 /* PM exc-mask precision */
#define FPCR_PC_SINGLE 0x0000 /* PC single precision(24 bits) */
#define FPCR_PC_DOUBLE 0x0200 /* PC double precision(53 bits) */
#define FPCR_PC_EXTENDED 0x0300 /* PC extended precision(64 bits) */
#define FPCR_PC_MASK 0xfcff /* PC extended precision(64 bits) */
#define FPCR_RC_NEAREST 0x0000 /* RC round to nearest */
#define FPCR_RC_DOWN 0x0400 /* RC round down */
#define FPCR_RC_UP 0x0800 /* RC round up */
#define FPCR_RC_ZERO 0x0c00 /* RC round to zero */
#define FPCR_RC_MASK 0xf3ff /* RC round bits mask */
#define FPCR_X 0x1000 /* X infinity control */
/* status register: defines for status word */
#define FPSR_IE 0x0001 /* IE exc-flag invalid operation */
#define FPSR_DE 0x0002 /* DE exc-flag denormalized operand */
#define FPSR_ZE 0x0004 /* ZE exc-flag zero divide */
#define FPSR_OE 0x0008 /* OE exc-flag overflow */
#define FPSR_UE 0x0010 /* UE exc-flag underflow */
#define FPSR_PE 0x0020 /* PE exc-flag precision */
#define FPSR_SF 0x0040 /* SF stack fault */
#define FPSR_ES 0x0080 /* ES error summary status */
#define FPSR_C0 0x0100 /* C0 condition code */
#define FPSR_C1 0x0200 /* C1 condition code */
#define FPSR_C2 0x0400 /* C2 condition code */
#define FPSR_TOP 0x3800 /* TOP top of stack pointer */
#define FPSR_C3 0x4000 /* C3 condition code */
#define FPSR_B 0x8000 /* FPU busy */
/* number of FP/MM and XMM registers on coprocessor */
#define FP_NUM_REGS 8 /* number of FP/MM registers */
#define XMM_NUM_REGS 16 /* number of XMM registers */
#define FP_NUM_RESERVED 6 /* reserved area in FPX_CONTEXT */
#define XSAVE_HEADER 64 /* number of bytes for the XSAVE header */
/* maximum size of floating-point coprocessor state frame */
#define FPO_STATE_FRAME_SIZE 108 /* nBytes of FPO_CONTEXT */
#define FPX_STATE_FRAME_SIZE 512 /* nBytes of FPX_CONTEXT */
/* FPREG_SET structure offsets */
#define FPREG_FPCR 0x00 /* offset to FPCR in FPREG_SET */
#define FPREG_FPSR 0x04 /* offset to FPSR in FPREG_SET */
#define FPREG_FPTAG 0x08 /* offset to FPTAG in FPREG_SET */
#define FPREG_OP 0x0c /* offset to OP in FPREG_SET */
#define FPREG_IP 0x10 /* offset to IP in FPREG_SET */
#define FPREG_CS 0x14 /* offset to CS in FPREG_SET */
#define FPREG_DP 0x18 /* offset to DP in FPREG_SET */
#define FPREG_DS 0x1c /* offset to DS in FPREG_SET */
#define FPREG_FPX(n) (0x20 + (n)*sizeof(DOUBLEX)) /* offset to FPX(n) */
/* FPX_CONTEXT REG_SET - structure offsets for New FP context */
#define FPXREG_FPCR 0x00 /* offset to FPCR in FPREG_SET */
#define FPXREG_FPSR 0x02 /* offset to FPSR in FPREG_SET */
#define FPXREG_FPTAG 0x04 /* offset to FPTAG in FPREG_SET */
#define FPXREG_OP 0x06 /* offset to OP in FPREG_SET */
#define FPXREG_IP 0x08 /* offset to IP in FPREG_SET */
#define FPXREG_CS 0x0c /* offset to CS in FPREG_SET */
#define FPXREG_DP 0x10 /* offset to DP in FPREG_SET */
#define FPXREG_DS 0x14 /* offset to DS in FPREG_SET */
#define FPXREG_RSVD0 0x18 /* offset to RESERVED0 in FPREG_SET */
#define FPXREG_RSVD1 0x1c /* offset to RESERVED1 in FPREG_SET */
#define FPXREG_FPX(n) (0x20 + (n)*sizeof(DOUBLEX_SSE)) /* offset to FPX(n) */
#ifndef _ASMLANGUAGE
/* DOUBLEX - double extended precision */
typedef struct
{
UCHAR f[10]; /* ST[0-7] or MM[0-7] */
} DOUBLEX;
/* DOUBLEX_SSE - double extended precision used in FPX_CONTEXT for SSE */
typedef struct
{
UCHAR xmm[16]; /* for 128 bits XMM registers */
} DOUBLEX_SSE;
/* FPREGO_SET - FP register set that is different from FPO_CONTEXT */
typedef struct fpregOSet
{
int fpcr; /* control word */
int fpsr; /* status word */
int fptag; /* tag word */
int op; /* last FP instruction op code */
int ip; /* instruction pointer */
int cs; /* instruction pointer selector */
int dp; /* data pointer */
int ds; /* data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* FR[0-7] non-TOS rel. order */
} FPREGO_SET;
/* FPREGX_SET - FP register set that is corresponding to FPX_CONTEXT */
typedef struct fpregXSet
{
int fpcr; /* control word */
int fpsr; /* status word */
int fptag; /* tag word */
int op; /* last FP instruction op code */
int ip; /* instruction pointer */
int cs; /* instruction pointer selector */
int dp; /* data pointer */
int ds; /* data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 16*16 XMM[0-15] */
} FPREGX_SET;
/* FPREGX_EXT_SET - FP register set that is corresponding to FPX_EXT_CONTEXT */
typedef struct fpregX_ExtSet
{
int fpcr; /* control word */
int fpsr; /* status word */
int fptag; /* tag word */
int op; /* last FP instruction op code */
int ip; /* instruction pointer */
int cs; /* instruction pointer selector */
int dp; /* data pointer */
int ds; /* data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 16*16 XMM[0-15] */
DOUBLEX_SSE ymm[XMM_NUM_REGS]; /* 16*16 higher 128 bits of YMM[0-15] */
} FPREGX_EXT_SET;
/* FPREG_SET - Common FP register set */
typedef struct fpregSet
{
union n
{
FPREGO_SET o; /* old FPREGO_SET for fsave/frstor */
FPREGX_SET x; /* new FPREGX_SET for fxsave/fxrstor */
FPREGX_EXT_SET x_ext; /* FPREGX_EXT_SET for xsave/xrstor */
} n;
} FPREG_SET;
/* FPO_CONTEXT - Old FP context used by fsave/frstor instruction */
typedef struct fpOcontext
{
int fpcr; /* 4 control word */
int fpsr; /* 4 status word */
int fptag; /* 4 tag word */
int ip; /* 4 instruction pointer */
short cs; /* 2 instruction pointer selector */
short op; /* 2 last FP instruction op code */
int dp; /* 4 data pointer */
int ds; /* 4 data pointer selector */
DOUBLEX fpx[FP_NUM_REGS]; /* 8*10 FR[0-7] non-TOS rel. order */
} FPO_CONTEXT; /* 108 bytes total */
/* FPX_CONTEXT - New FP context used by fxsave/fxrstor instruction */
typedef struct fpXcontext
{
short fpcr; /* 2 control word */
short fpsr; /* 2 status word */
short fptag; /* 2 tag word */
short op; /* 2 last FP instruction op code */
int ip; /* 4 instruction pointer */
int cs; /* 4 instruction pointer selector */
int dp; /* 4 data pointer */
int ds; /* 4 data pointer selector */
int reserved0; /* 4 reserved */
int reserved1; /* 4 reserved */
DOUBLEX_SSE fpx[FP_NUM_REGS]; /* 8*16 FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 16*16 XMM[0-15] */
DOUBLEX_SSE res2[FP_NUM_RESERVED]; /* 8*16 reserved */
} FPX_CONTEXT; /* 512 bytes total */
/* FPX_EXT_CONTEXT - Extended FP context used by xsave/xrstor instruction */
typedef struct fpX_ExtContext
{
short fpcr; /* 2 control word */
short fpsr; /* 2 status word */
short fptag; /* 2 tag word */
short op; /* 2 last FP instruction op code */
int ip; /* 4 instruction pointer */
int cs; /* 4 instruction pointer selector */
int dp; /* 4 data pointer */
int ds; /* 4 data pointer selector */
int reserved0; /* 4 reserved */
int reserved1; /* 4 reserved */
DOUBLEX_SSE fpx[FP_NUM_REGS]; /* 8*16 FR[0-7] non-TOS rel. order */
DOUBLEX_SSE xmm[XMM_NUM_REGS]; /* 16*16 XMM[0-15] */
DOUBLEX_SSE res2[FP_NUM_RESERVED]; /* 6*16 reserved */
UCHAR xSaveHeader[XSAVE_HEADER]; /* 64 XSave header */
DOUBLEX_SSE ymm[XMM_NUM_REGS]; /* 16*16 higher 128 bits of YMM[0-15] */
} FPX_EXT_CONTEXT; /* 832 bytes total */
/* FP_CONTEXT - Common FP context */
typedef struct fpContext
{
union u
{
FPO_CONTEXT o; /* old FPO_CONTEXT for fsave/frstor */
FPX_CONTEXT x; /* new FPX_CONTEXT for fxsave/fxrstor */
FPX_EXT_CONTEXT x_ext; /* FPX_EXT_CONTEXT for xsave/xrstor */
} u;
} FP_CONTEXT;
/* variable declarations */
extern REG_INDEX fpRegName[]; /* f-point data register table */
extern REG_INDEX fpXregName[]; /* f-point data register table for FPX and FPX_EXT */
extern REG_INDEX fpCtlRegName[]; /* f-point control register table */
extern REG_INDEX fpXctlRegName[]; /* new f-point control register table */
extern WIND_TCB *pFppTaskIdPrevious; /* task id for deferred exceptions */
#if !defined (_WRS_PAL_COPROC_LIB)
extern FUNCPTR fppCreateHookRtn; /* arch dependent create hook routine */
#endif /* !_WRS_PAL_COPROC_LIB */
/* func ptr to fppSave/fppXsave */
extern void (* _func_fppSaveRtn) (FP_CONTEXT *);
/* func ptr to fppRestore/fppXrestore */
extern void (* _func_fppRestoreRtn) (FP_CONTEXT *);
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern void fppArchCpuInit(void);
extern void fppArchInit (void);
extern void fppArchTaskCreateInit (FP_CONTEXT *pFpContext);
extern STATUS fppProbeSup (void);
extern void fppProbeTrap (void);
extern void fppDtoDx (DOUBLEX *pDx, double *pDouble);
extern void fppDxtoD (double *pDouble, DOUBLEX *pDx);
extern void fppXrestore (FP_CONTEXT *pFpContext);
extern void fppXsave (FP_CONTEXT *pFpContext);
extern void fppXregsToCtx (FPREG_SET *pFpRegSet, FP_CONTEXT *pFpContext);
extern void fppExtXregsToCtx (FPREG_SET *pFpRegSet, FP_CONTEXT *pFpContext);
extern void fppXctxToRegs (FP_CONTEXT *pFpContext, FPREG_SET *pFpRegSet);
extern void fppExtXctxToRegs (FP_CONTEXT *pFpContext, FPREG_SET *pFpRegSet);
extern void fppArchSwitchHook (WIND_TCB * pOldTcb, WIND_TCB * pNewTcb);
extern STATUS fppArchSwitchHookEnable (BOOL enable);
#else
extern void fppArchCpuInit();
extern void fppArchInit ();
extern void fppArchTaskCreateInit ();
extern STATUS fppProbeSup ();
extern void fppProbeTrap ();
extern void fppDtoDx ();
extern void fppDxtoD ();
extern void fppXrestore ();
extern void fppXsave ();
extern void fppXregsToCtx ();
extern void fppExtXregsToCtx ();
extern void fppXctxToRegs ();
extern void fppExtXctxToRegs ();
extern void fppArchSwitchHook ();
extern STATUS fppArchSwitchHookEnable ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCfppX86_64Libh */
vxworks-6.9/target/h/arch/i86/x86_64/instrX86_64.h
+129
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/* instrx86_64.h - header for x86_64 instruction fields */
/*
* Copyright (c) 2004,2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,20sep10,scm add additional trc/dbg constants...
01c,01apr10,scm update instruction codes...
01b,01jun09,scm add REX and RIP idents...
01a,26apr04,jmp created from target/h/dbgI86Lib.h
*/
/*
* WARNING: This file is shared between i86 and VxSim/i86 arches,
* and between Kernel and User sides.
* Please make sure that any modifications to this file
* does not break other arches.
*/
#ifndef __INCinstrI86h
#define __INCinstrI86h
/* defines */
#define ADDI08_0 (0x83)
#define ADDI08_1 (0xc4)
#define ADDI32_0 (0x81)
#define ADDI32_1 (0xc4)
#define ADD_EAX (0x01)
#define SUB_EAX (0x29)
#define INC_EDX (0xff)
#define LEAD08_0 (0x8d)
#define LEAD08_1 (0x64)
#define LEAD08_2 (0x24)
#define LEAD32_0 (0x8d)
#define LEAD32_1 (0xa4)
#define LEAD32_2 (0x24)
#define JMPD08 (0xeb)
#define JMPD32 (0xe9)
#define ENTER (0xc8)
#define SC_PUSH (0x68)
#define PUSH_EBX (0x53)
#define POP_EBX (0x5b)
#define POP_EBP (0x5d)
#define POP_REG (0x50)
#define PUSH_EBP (0x55)
#define PUSH_ESI (0x56)
#define MOV_EAX (0x89)
#define MOV_EDI (0xbf)
#define MOV_ESP0 (0x89)
#define MOV_ESP1 (0xe5)
#define MOV_ESP_ESI (0xe689)
#define MOV_RIP (0x8b)
#define CMP1_EAX (0x39)
#define CMP2_EAX (0x38)
#define LEAVE (0xc9)
#define RET (0xc3)
#define RETADD (0xc2)
#define REX_PRE (0x40)
#define REX_PRE_B (0x41)
#define REX_PRE_X (0x42)
#define REX_PRE_R (0x44)
#define REX_PRE_W (0x48)
#define RIP_REL (0x05)
#define SC_CALL0 (0xff)
#define SC_CALL1 (0x1c)
#define SC_CALL2 (0x25)
#define CALL_DIR (0xe8)
#define CALL_INDIR0 (0xff)
#define CALL_INDIR1 (0x10)
#define CALL_INDIR_REG_EAX (0xd0)
#define CALL_INDIR_REG_ECX (0xd1)
#define CALL_INDIR_REG_EDX (0xd2)
#define CALL_INDIR_REG_EBX (0xd3)
#define MOV_ECX (0x0d8b)
#define MOV_EDX (0x158b)
#define MOV_EBP_ESP (0xe589)
#define ADDI08_0_MASK (0xff)
#define ADDI08_1_MASK (0xff)
#define ADDI32_0_MASK (0xff)
#define ADDI32_1_MASK (0xff)
#define ADD_MASK (0xff)
#define SUB_MASK (0xff)
#define INC_MASK (0xff)
#define LEAD08_0_MASK (0xff)
#define LEAD08_1_MASK (0xff)
#define LEAD08_2_MASK (0xff)
#define LEAD32_0_MASK (0xff)
#define LEAD32_1_MASK (0xff)
#define LEAD32_2_MASK (0xff)
#define JMPD08_MASK (0xff)
#define JMPD32_MASK (0xff)
#define ENTER_MASK (0xff)
#define POP_EBX_MASK (0xff)
#define POP_EBP_MASK (0xff)
#define POP_REG_MASK (0xff)
#define SC_PUSH_MASK (0xff)
#define PUSH_EBX_MASK (0xff)
#define PUSH_EBP_MASK (0xff)
#define PUSH_ESI_MASK (0xff)
#define MOV_MASK (0xff)
#define MOV_ESP0_MASK (0xff)
#define MOV_ESP1_MASK (0xff)
#define MOV_ESP_ESI_MASK (0xffff)
#define MOV_RIP_MASK (0xff)
#define CMP_MASK (0xff)
#define LEAVE_MASK (0xff)
#define RET_MASK (0xff)
#define RETADD_MASK (0xff)
#define REX_PRE_MASK (0xff)
#define RIP_REL_MASK (0xff)
#define SC_CALL_MASK (0xff)
#define CALL_DIR_MASK (0xff)
#define CALL_INDIR0_MASK (0xff)
#define CALL_INDIR1_MASK (0x38)
#define CALL_INDIR_REG_MASK (0xdf)
#define MOV_ECX_MASK (0xffff)
#define MOV_EDX_MASK (0xffff)
#define MOV_EBP_ESP_MASK (0xffff)
#endif /* __INCinstrx86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/intX86_64Lib.h
+102
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/* intX86_64Lib.h - X86_64-specific interrupt library header file */
/*
* Copyright (c) 2009-2010 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01e,24mar10,scm add support for 64 bit inlines...
01d,12jan10,scm adjust proto typing...
01c,08sep09,scm FUNCPTR update...
01b,20may09,jb Change to kernel model
01a,12mar09,jb Adding 64-bit support, created from 32 bit version 01g
*/
#ifndef __INCintX86_64Libh
#define __INCintX86_64Libh
#ifdef __cplusplus
extern "C" {
#endif
/* offset macro for stuff in the intConnect code */
#ifdef _WRS_ARCH_KERNEL_MODEL
#define ICC_ADDR_SIZE 4
#define ICC_INT_BASE 0
#define ICC_INT_ENT ICC_INT_BASE + 0x2 /* intConnectCode[2] */
#define ICC_BOI_PUSH ICC_INT_BASE + 0x13 /* intConnectCode[0x13] */
#define ICC_BOI_SIZE 16 /* Size of BOI arg and call */
#define ICC_BOI_PARAM ICC_INT_BASE + 0x15 /* intConnectCode[0x15] */
#define ICC_BOI_ROUTN ICC_INT_BASE + 0x1F /* intConnectCode[0x1F] */
#define ICC_INT_PARAM ICC_INT_BASE + 0x25 /* intConnectCode[0x25] */
#define ICC_INT_ROUTN ICC_INT_BASE + 0x2F /* intConnectCode[0x2F] */
#define ICC_EOI_PARAM ICC_INT_BASE + 0x35 /* intConnectCode[0x35] */
#define ICC_EOI_CALL ICC_INT_BASE + 0x3E /* intConnectCode[0x3E] */
#define ICC_EOI_SIZE 6
#define ICC_EOI_ROUTN ICC_INT_BASE + 0x40 /* intConnectCode[0x40] */
#define ICC_INT_EXIT ICC_INT_BASE + 0x53 /* intConnectCode[0x53] */
#else
#define ICC_ADDR_SIZE 8
#error _WRS_ARCH_KERNEL_MODEL is only supported model
#endif /* _WRS_ARCH_KERNEL_MODEL */
#ifndef _ASMLANGUAGE
typedef STATUS (*SYS_INT_LVL_ENABLE_RTN_PTR)(int);
typedef STATUS (*SYS_INT_LVL_DISABLE_RTN_PTR)(int);
#if defined (__GNUC__)
static __inline__ int _inline_intCpuLock (void)
{
long key;
__asm__ volatile ("pushf; cli; pop %0; " \
: "=g" (key) : : "memory");
return (int) key;
}
static __inline__ void _inline_intCpuUnlock
(
int key
)
{
__asm__ volatile ("testl $0x200,%0; jz 0f; sti; 0: " \
: : "g" (key) : "cc", "memory");
}
#else
#define _inline_intCpuLock() intCpuLock()
#define _inline_intCpuUnlock(key) intCpuUnlock(key)
#endif /* _VX_TOOL_FAMILY */
#define _inline_intCpuMicroLock() _inline_intCpuLock()
#define _inline_intCpuMicroUnlock(key) _inline_intCpuUnlock(key)
/* function declarations */
extern FUNCPTR intHandlerCreateX86_64 (FUNCPTR routine, _Vx_usr_arg_t parameter,
FUNCPTR routineBoi, _Vx_usr_arg_t parameterBoi,
FUNCPTR routineEoi, _Vx_usr_arg_t parameterEoi);
extern void intVecSet2 (FUNCPTR * vector, FUNCPTR function,
int idtGate, int idtSelector);
extern void intVecGet2 (FUNCPTR * vector, FUNCPTR * pFunction,
int * pIdtGate, int * pIdtSelector);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCintX86_64Libh */
vxworks-6.9/target/h/arch/i86/x86_64/ivX86_64.h
+91
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/* ivX86_64.h - x86_64 interrupt vectors */
/*
* Copyright 2009 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01b,23feb09,jb Convert to 64-bit
01a,20jan09,jb Adding 64-bit support
*/
#ifndef __INCivX86_64h
#define __INCivX86_64h
#ifdef __cplusplus
extern "C" {
#endif
/* 0 - 19 exception vector number */
#define IN_DIVIDE_ERROR 0
#define IN_DEBUG 1
#define IN_NON_MASKABLE 2
#define IN_BREAKPOINT 3
#define IN_OVERFLOW 4
#define IN_BOUND 5
#define IN_INVALID_OPCODE 6
#define IN_NO_DEVICE 7
#define IN_DOUBLE_FAULT 8
#define IN_CP_OVERRUN 9
#define IN_INVALID_TSS 10
#define IN_NO_SEGMENT 11
#define IN_STACK_FAULT 12
#define IN_PROTECTION_FAULT 13
#define IN_PAGE_FAULT 14
#define IN_RESERVED 15
#define IN_CP_ERROR 16
#define IN_ALIGNMENT 17
#define IN_MACHINE_CHECK 18
#define IN_SIMD 19
/* 20 - 31 unassigned, Intel reserved exceptions */
/* 32 - 255 user defined interrupt vectors */
#ifndef _ASMLANGUAGE
/* macros to convert interrupt vectors <-> interrupt numbers */
#define IVEC_TO_INUM(intVec) ( (long)(intVec) >> 4)
#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *) ((intNum) << 4))
/* exception vector address/offset */
#define IV_DIVIDE_ERROR INUM_TO_IVEC (IN_DIVIDE_ERROR)
#define IV_DEBUG INUM_TO_IVEC (IN_DEBUG)
#define IV_NON_MASKABLE INUM_TO_IVEC (IN_NON_MASKABLE)
#define IV_BREAKPOINT INUM_TO_IVEC (IN_BREAKPOINT)
#define IV_OVERFLOW INUM_TO_IVEC (IN_OVERFLOW)
#define IV_BOUND INUM_TO_IVEC (IN_BOUND)
#define IV_INVALID_OPCODE INUM_TO_IVEC (IN_INVALID_OPCODE)
#define IV_NO_DEVICE INUM_TO_IVEC (IN_NO_DEVICE)
#define IV_DOUBLE_FAULT INUM_TO_IVEC (IN_DOUBLE_FAULT)
#define IV_CP_OVERRUN INUM_TO_IVEC (IN_CP_OVERRUN)
#define IV_INVALID_TSS INUM_TO_IVEC (IN_INVALID_TSS)
#define IV_NO_SEGMENT INUM_TO_IVEC (IN_NO_SEGMENT)
#define IV_STACK_FAULT INUM_TO_IVEC (IN_STACK_FAULT)
#define IV_PROTECTION_FAULT INUM_TO_IVEC (IN_PROTECTION_FAULT)
#define IV_PAGE_FAULT INUM_TO_IVEC (IN_PAGE_FAULT)
#define IV_RESERVED INUM_TO_IVEC (IN_RESERVED)
#define IV_CP_ERROR INUM_TO_IVEC (IN_CP_ERROR)
#define IV_ALIGNMENT INUM_TO_IVEC (IN_ALIGNMENT)
#define IV_MACHINE_CHECK INUM_TO_IVEC (IN_MACHINE_CHECK)
#define IV_SIMD INUM_TO_IVEC (IN_SIMD)
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCivX86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/mmuX86_64Lib.h
+522
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/* mmuX86_64Lib.h - mmuX86_64Lib header for x86_64. */
/*
* Copyright 2009-2010, 2014, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01m,18jul18,hbu kernel page table isolation support (F10571)
01l,02may14,jb VXW6-24753 - add Intel Write Combining Option
01k,23dec10,jlv WIND00241261 - set default WP state for GuestOs
01j,24jun10,scm WIND00217705 - check for correct physical address size...
01i,29apr10,pad Moved extern C statement after include statements.
01h,22mar10,j_l Modify MMU_CVT_VIRT_SYS to consider both direct mapped and
kernel system mapped regions
01g,03feb10,scm update to exploit dllLib macros...
01f,19oct09,jb Phase2 Update
01e,15oct09,jb Fix mmuPteGet bug
01d,27aug09,jb First phase of direct mapped design
01c,25aug09,jb Add non-canonical address defs, remove Page0 Unmap
01b,03aug09,jb Enable Page0 Unmap
01a,28may09,jb written.
*/
#ifndef __INCmmuX86_64Libh
#define __INCmmuX86_64Libh
#include <dllLib.h>
#include <arch/i86/pentiumLib.h>
#include <arch/i86/x86_64/private/adrSpaceArchLibP.h>
#ifdef __cplusplus
extern "C" {
#endif
#define MMU_CVT_VIRT_SYS(virtAddr) \
((virtAddr & ~(KERNEL_DIRECT_MAP_RGN_BASE | (~KERNEL_SYS_MEM_RGN_BASE))) ? \
((VIRT_ADDR)(virtAddr & ~KERNEL_DIRECT_MAP_RGN_BASE) | KERNEL_DIRECT_MAP_RGN_BASE) : \
((VIRT_ADDR)(virtAddr & ~KERNEL_SYS_MEM_RGN_BASE) | KERNEL_SYS_MEM_RGN_BASE))
#define MMU_CVT_PHYS_SYS(physAddr) ((PHYS_ADDR)physAddr | KERNEL_SYS_MEM_RGN_BASE)
#define MMU_CVT_PHYS_DIR(physAddr) ((PHYS_ADDR)physAddr | KERNEL_DIRECT_MAP_RGN_BASE)
/*
* Enable Temp optimized mmuTableZero
*/
#define MMU_OPTIMIZED_INIT /* Optimized table init */
#define MMU_ENABLE_INSTRUMENTATION /* Table use instrumentation */
#define MMU_OPTIMIZE_TABLE_ALLOC_ENABLE /* Page Table allocation optimization */
#define MMU_ENABLE_PAGE_TABLE_OPTIMIZATION /* Page Table size optimization (TLB) */
/*
* Canonical address definitions
*/
#define CANONICAL_BITS 0xffff800000000000
#define NON_CANONICAL_PAGES 0xffff000000000
#define CANONICAL_UPPER CANONICAL_BITS
#define ADDR_IS_CANONICAL(va) ((((va) & CANONICAL_BITS) == 0) || \
(((va) & CANONICAL_BITS) == CANONICAL_BITS))
/*
* Private definitions for use in the avail
* slots of PDE and PT records. bit 9 (0x1)
* is reserved for NOBLOCK
*/
/*
* TABLE_ALLOC_OPT indicates table was allocated
* as part of a block alocation. Free at the top.
*/
#define TABLE_ALLOC_OPT 0x4 /* bit in Avail0 */
#define MMU_TABLE_ALLOC_OPT 0x800L /* Absolute bit */
/*
* Table size definitions
*/
#ifndef PAGE_SIZE_4KB
#define PAGE_SIZE_4KB 0x1000
#endif
#ifndef PAGE_SIZE_2MB
#define PAGE_SIZE_2MB 0x200000
#endif
#ifdef _WRS_CONFIG_KPTI
#define PML4_TBL_SIZE (4 * PAGE_SIZE_4KB)
#define MMU_UMTBL_OFFSET (PAGE_SIZE_4KB)
#else
# define PML4_TBL_SIZE PAGE_SIZE_4KB
#endif
#define PAGE_BLOCK_SIZE 0x200000 /* 2MB */
#define PAGES_PER_BLOCK 512
#define PDE_BLOCK_SIZE 0x40000000 /* 1GB */
#define PAGES_PER_PDE 262144
#define PDP_BLOCK_SIZE 0x8000000000 /* 512GB */
#define PAGES_PER_PDP 134217728
#define N_PML4 512
#define N_PDPTE 512
#define N_PDE 512
#define N_PTE 512
/*
* Bits used to mask and shift virtual addresses
* when calculating indices into the tables
*/
#define PML4_PTR_BITS 0x0000ff8000000000L
#define DIR_PTR_BITS 0x0000007fc0000000L
#define DIR_BITS 0x000000003fe00000L
#define TBL_BITS 0x00000000001ff000L
#define PML4_PTR_INDEX 39
#define DIR_PTR_INDEX 30
#define DIR_INDEX 21
#define TBL_INDEX 12
/* Mask for extracting addresses from PDEs */
#define OFFSET_BITS_4KB 0x0000000000000fffL
#define ASM_OFFSET_BITS_4KB 0x0000000000000fff
#define OFFSET_BITS_2MB 0x00000000001fffffL
#define PTE_TO_BITFIELD_4KB 0x0fffffff
#define PTE_TO_ADDR_4KB 0x000000fffffff000L
#define PTE_TO_BITFIELD_2MB 0x000fffff
#define PTE_TO_ADDR_2MB 0x000000ffffe00000L
#define PTP_TO_ADDR 0x000000fffffff000L
#define PDE_TO_ADDR 0x000000fffffff000L
#define PDP_TO_ADDR 0x000000fffffff000L
#define PML4_TO_ADDR 0x000000fffffff000L
#define ASM_PML4_TO_ADDR 0xfffffff000
/* Value used to indicate an unmapped page */
#define MMU_ENTRY_UNMAPPED 0x7ff000fffffff000
#define ADDR_TO_PAGE 12
#define ADDR_TO_PAGE_MASK 0xfffffff
#ifndef _ASMLANGUAGE
/*
* Page-Map-Level-4-Table Entry
*/
typedef struct
{
ULONG present:1; /* Entry is valid */
ULONG rw:1; /* Read/Write when set, R/O when clear */
ULONG us:1; /* User/Supervisor, User when set,
Supervisor when clear */
ULONG pwt:1; /* Page-level write through, wt when set,
copy back when clear */
ULONG pcd:1; /* Page-level cache disable, disabled when set */
ULONG access:1; /* Page or Page Table has been accessed */
ULONG rsvd0:3; /* Reserved, must be zero */
ULONG avail0:3; /* Available to system programmers */
ULONG page:28; /* Bits 39 - 12, points to PDPTE or PDE if used
as PDPE_FIELD */
ULONG rsvd1:12; /* Reserved, must be zero */
ULONG avail1:11; /* Available to system programmers */
ULONG exd:1; /* Execute Disable Bit */
} PML4_FIELD;
typedef union pml4
{
PML4_FIELD field;
ULONG bits;
}PML4;
/*
* Page-Directory-Pointer-Table Entry
* Same at PLM4
*/
typedef PML4_FIELD PDPE_FIELD;
typedef union pdpt
{
PDPE_FIELD field;
ULONG bits;
}PDPT;
/*
* Page-Directory Entry 4k Page Table
*/
typedef struct
{
ULONG present:1; /* Entry is valid */
ULONG rw:1; /* Read/Write when set, R/O when clear */
ULONG us:1; /* User/Supervisor, User when set,
Supervisor when clear */
ULONG pwt:1; /* Page-level write through, wt when set,
copy back when clear */
ULONG pcd:1; /* Page-level cache disable, disabled when set */
ULONG access:1; /* Page or Page Table has been accessed */
ULONG mbz:3; /* Must be zero, includes bit 7, page size as 0 */
ULONG avail0:3; /* Available to system programmers */
ULONG page:28; /* Bits 39 - 12, physical address of PTEs */
ULONG rsvd1:12; /* Reserved, must be zero */
ULONG avail1:11; /* Available to system programmers */
ULONG exd:1; /* Execute Disable Bit, disabled when set */
} PDE4K_FIELD;
typedef union pde
{
PDE4K_FIELD field;
ULONG bits;
}PDE4K;
/*
* Page-Directory Entry 2m Page Table
*/
typedef struct
{
ULONG present:1; /* Entry is valid */
ULONG rw:1; /* Read/Write when set, R/O when clear */
ULONG us:1; /* User/Supervisor, User when set,
Supervisor when clear */
ULONG pwt:1; /* Page-level write through, wt when set,
copy back when clear */
ULONG pcd:1; /* Page-level cache disable, disabled when set */
ULONG access:1; /* Page or Page Table has been accessed */
ULONG dirty:1; /* Page has been written */
ULONG pagesize:1; /* Page Size, 2mb when set, 4k ptr when clear */
ULONG global:1; /* Global bit, Global page when set */
ULONG avail0:3; /* Available to system programmers */
ULONG pat:1; /* Page attribute table index */
ULONG rsvd1:8; /* Reserved, must be zero */
ULONG page:19; /* Bits 39 - 21, physical address of 2m page */
ULONG rsvd2:12; /* Reserved, must be zero */
ULONG avail1:11; /* Available to system programmers */
ULONG exd:1; /* Execute Disable Bit, disabled when set */
} PDE2M_FIELD;
typedef union pde2m
{
PDE2M_FIELD field;
ULONG bits;
}PDE2M;
/*
* NOTE: Generic Page-Directory Entry is same as 2MB entry.
* This is for type determination.
*/
typedef PDE2M PDET;
/*
* Page-Table Entry 4k Page
*/
typedef struct
{
ULONG present:1; /* Entry is valid */
ULONG rw:1; /* Read/Write when set, R/O when clear */
ULONG us:1; /* User/Supervisor, User when set,
Supervisor when clear */
ULONG pwt:1; /* Page-level write through, wt when set,
copy back when clear */
ULONG pcd:1; /* Page-level cache disable, disabled when set */
ULONG access:1; /* Page or Page Table has been accessed */
ULONG dirty:1; /* Page has been written */
ULONG pat:1; /* Page attribute table index */
ULONG global:1; /* Global bit, Global page when set */
ULONG avail0:3; /* Available to system programmers */
ULONG page:28; /* Bits 39 - 12, physical address of 4k page */
ULONG rsvd1:12; /* Reserved, must be zero */
ULONG avail1:11; /* Available to system programmers */
ULONG exd:1; /* Execute Disable Bit, disabled when set */
} PTE_FIELD;
typedef union pte
{
PTE_FIELD field;
ULONG bits;
} PTE;
/*
* Page Table Allocation Info. Enables efficient
* allocation/de-allocation of page table resources.
*/
typedef struct mmuPageAllocInfo
{
struct mmuPageAllocInfo * next; /* Pointer to next alloc struct */
VIRT_ADDR vAddr; /* Virtual Address of allocated buffer */
size_t pages; /* Number of pages for this allocation */
} PGALLOCINFO;
#ifdef MMU_ENABLE_PAGE_TABLE_OPTIMIZATION
/*
* Each Page Table Backing Store has up to 64 pages
*/
typedef struct mmuPgTblStore
{
DL_NODE node;
short flags; /* Indicates type, 0 = auto, 1 = manual */
short resvd; /* reserved */
short pgCnt; /* Number of pages in this store */
short freeCnt; /* Free pages in this store */
ULONG freeField; /* Bit field indicating free blocks */
ULONG * storage; /* The storage itself */
} PGTBLSTORE;
/* Backing store defs */
#define MMU_BACKING_PAGE_PER_NODE 64
#define MMU_BACKING_L_PER_PAGE 512
#define MMU_BACKING_ALL_BITS 0xFFFFFFFFFFFFFFFFL
#define MMU_STORE_AUTO 0
#define MMU_STORE_MANUAL 1
#endif /* MMU_ENABLE_PAGE_TABLE_OPTIMIZATION */
typedef struct mmuTransTblStruct
{
PML4 * pPml4; /* pointer to PML4 ptr tbl */
PGALLOCINFO * pAlloc; /* Page resource alloc info */
PGALLOCINFO * pAllocLast; /* Quick access to last structure */
#ifdef MMU_ENABLE_INSTRUMENTATION
ULONG totAllocPages;
#endif /* MMU_ENABLE_INSTRUMENTATION */
#ifdef MMU_ENABLE_PAGE_TABLE_OPTIMIZATION
DL_LIST pgTblStore;
#ifdef MMU_ENABLE_INSTRUMENTATION
int storeCnt; /* Number of backing store nodes */
#endif /* MMU_ENABLE_INSTRUMENTATION */
#endif /* MMU_ENABLE_PAGE_TABLE_OPTIMIZATION */
#ifdef MMU_ENABLE_INSTRUMENTATION
PGALLOCINFO * pMapped; /* mmuPageMap calls */
PGALLOCINFO * pMappedLast;
int mappedPages;
int pdptCnt;
int pdeCnt;
int ptCnt;
#ifdef MMU_OPTIMIZE_TABLE_ALLOC_ENABLE
int orphanCnt;
#endif /* MMU_OPTIMIZE_TABLE_ALLOC_ENABLE */
#ifdef MMU_ENABLE_PAGE_TABLE_OPTIMIZATION
int optCnt;
#endif /* MMU_ENABLE_PAGE_TABLE_OPTIMIZATION */
int stateChg;
#endif /* MMU_ENABLE_INSTRUMENTATION */
} MMU_TRANS_TBL;
/*
* For Write Combining setup
*/
typedef union mmuPatReg
{
UINT64 mmuFullPat;
UINT32 mmuHalfPat[2];
UCHAR mmuCharPat[8];
} MMU_PAT_REG;
#define IA32_PAT_MSR 0x277
#define IA32_PAT_WC_IDX 0x02
#define IA32_PAT_WC 0x01
/*
* Private MACRO to convert Physical addresses from tables to
* Virtual addresses useable by the mmu code.
* This relationship must exist for the current 64-bit mmu
* library to work.
*/
#define MMU_CVT_PHYS_VIRT(physAddr) ((PHYS_ADDR)physAddr | mmuX86_64PToVC)
#define MMU_STATE_MASK_VALID 0x001
#define MMU_STATE_MASK_WRITABLE 0x002
#define MMU_STATE_MASK_USER 0x004
#define MMU_STATE_MASK_EXEC_DIS 0x8000000000000000L
#define MMU_STATE_MASK_PROTECTION 0x8000000000000006L
#define MMU_STATE_MASK_WRITETHROUGH 0x008
#define MMU_STATE_MASK_WBACK 0x008
#define MMU_STATE_MASK_CACHEABLE 0x018
#define MMU_STATE_MASK_WCOMBINE MMU_STATE_MASK_CACHEABLE
#define MMU_STATE_MASK_GLOBAL 0x100
#define MMU_STATE_MASK_NO_BLOCK 0x200
#ifdef _WRS_CONFIG_KPTI
#define MMU_STATE_MASK_UMPT 0x800
#define MMU_STATE_MASK_STATE 0x8000000000000b1FL
#else
# define MMU_STATE_MASK_STATE 0x800000000000031FL
#endif
#define MMU_STATE_VALID 0x001
#define MMU_STATE_VALID_NOT 0x000
#define MMU_STATE_WRITABLE 0x002
#define MMU_STATE_WRITABLE_NOT 0x000
#define MMU_STATE_USER 0x004
#define MMU_STATE_USER_NOT 0x000
#define MMU_STATE_EXEC_DIS 0x8000000000000000L
#define MMU_STATE_EXEC_DIS_NOT 0x0000000000000000L
#define MMU_STATE_WRITETHROUGH 0x008
#define MMU_STATE_WBACK 0x000
#define MMU_STATE_WCOMBINE 0x010 /* This requires mod to default PAT Table */
#define MMU_STATE_COPYBACK 0x000
#define MMU_STATE_CACHEABLE_NOT 0x018
#define MMU_STATE_WBACK_NOT MMU_STATE_CACHEABLE_NOT
#define MMU_STATE_WCOMBINE_NOT 0
#define MMU_STATE_CACHEABLE 0x000
#define MMU_STATE_GLOBAL 0x100
#define MMU_STATE_GLOBAL_NOT 0x000
#define MMU_STATE_NO_BLOCK 0x200
#define MMU_STATE_NO_BLOCK_NOT 0x000
#ifdef _WRS_CONFIG_KPTI
#define MMU_STATE_UMPT 0x800
#define MMU_STATE_UMPT_NOT 0x000
#endif
#define MMU_STATE_INVALID 0xffffffffffffffffL
#ifndef _WRS_CONFIG_WRHV_GUEST
#define MMU_STATE_SUP_RO (MMU_STATE_EXEC_DIS | MMU_STATE_USER_NOT | \
MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_SUP_ROX (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_USR_RO (MMU_STATE_EXEC_DIS | MMU_STATE_USER | \
MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_USR_ROX (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_SUP_RW (MMU_STATE_EXEC_DIS | MMU_STATE_USER_NOT | \
MMU_STATE_WRITABLE)
#define MMU_STATE_SUP_RWX (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE)
#define MMU_STATE_USR_RW (MMU_STATE_EXEC_DIS | MMU_STATE_USER | \
MMU_STATE_WRITABLE)
#define MMU_STATE_USR_RWX (MMU_STATE_USER | MMU_STATE_WRITABLE)
#else
#define MMU_STATE_SUP_RO (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_SUP_ROX (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_USR_RO (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_USR_ROX (MMU_STATE_USER | MMU_STATE_WRITABLE_NOT)
#define MMU_STATE_SUP_RW (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE)
#define MMU_STATE_SUP_RWX (MMU_STATE_USER_NOT | MMU_STATE_WRITABLE)
#define MMU_STATE_USR_RW (MMU_STATE_USER | MMU_STATE_WRITABLE)
#define MMU_STATE_USR_RWX (MMU_STATE_USER | MMU_STATE_WRITABLE)
#endif /* _WRS_CONFIG_WRHV_GUEST */
/* wpOff is used to temporarily override supervisor write-protection.
* When using wpOff, interrupts should
* be locked because this disables write-protection system wide!
* Before unlocking interrupts, be sure to do a wpOn().
*/
#define wpOff() vxCr0Set (vxCr0Get() & 0xfffeffff)
#define wpOn() vxCr0Set (vxCr0Get() | 0x00010000)
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
extern STATUS mmuX86_64LibInit (int pageSize);
extern STATUS mmuX86_64Enable (BOOL enable);
extern void mmuX86_64On ();
extern void mmuX86_64Off ();
extern void mmuX86_64TLBFlush ();
extern void mmuX86_64Pml4Set (MMU_TRANS_TBL *transTbl);
extern STATUS mmuX86_64Show (MMU_TRANS_TBL *transTbl,
VIRT_ADDR vaddr, size_t numPages, int flag);
extern PML4 * mmuX86_64Pml4Get ();
extern unsigned int mmuX86_64GetPhysAddrSize ();
#else /* __STDC__ */
extern STATUS mmuX86_64LibInit ();
extern STATUS mmuX86_64Enable ();
extern void mmuX86_64On ();
extern void mmuX86_64Off ();
extern void mmuX86_64TLBFlush ();
extern void mmuX86_64Pml4Set ();
extern void mmuX86_64Show ();
extern MMU_TRANS_TBL *mmuX86_64Pml4Get ();
extern unsigned int mmuX86_64GetPhysAddrSize ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCmmuX86_64Libh */
vxworks-6.9/target/h/arch/i86/x86_64/private/adrSpaceArchLibP.h
+64
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@@ -0,0 +1,64 @@
/* adrSpaceArchLibP.h - address space header file for x86_64 */
/*
* Copyright (c) 2009-2010, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,18jul18,r_h Add kernel page table isolation support (F10571)
01c,14apr10,zl changed RTP private region base to 2M
01b,23dec09,zl fixed shared region base address.
01a,24aug09,zl created with 64-bit region definitions.
*/
#ifndef __INCadrSpaceArchLibPh
#define __INCadrSpaceArchLibPh
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define __UL_CONST(x) x
#else
#define __UL_CONST(x) x##UL
#endif
/* virtual memory region definitions */
#define RTP_PRIVATE_RGN_BASE __UL_CONST(0x0000000000200000)
#define RTP_PRIVATE_RGN_SIZE __UL_CONST(0x000007ffffe00000)
#define SHARED_RGN_BASE __UL_CONST(0x0000780000000000)
#define SHARED_RGN_SIZE __UL_CONST(0x0000080000000000)
#define KERNEL_VIRT_POOL_RGN_BASE __UL_CONST(0xffff800000000000)
#define KERNEL_VIRT_POOL_RGN_SIZE __UL_CONST(0x0000080000000000)
#define KERNEL_SYS_MEM_RGN_BASE __UL_CONST(0xffffffff80000000)
#define KERNEL_SYS_MEM_RGN_SIZE __UL_CONST(0x0000000080000000)
#define KERNEL_DIRECT_MAP_RGN_BASE __UL_CONST(0xfffff00000000000)
#define KERNEL_DIRECT_MAP_RGN_SIZE __UL_CONST(0x0000080000000000)
#ifdef _WRS_CONFIG_KPTI
/*
* RTP region for supervisor mode access; size is 512GB, the size
* described by one PLM4 entry (L1 table entry)
*/
#define KERNEL_RTP_SUP_RGN_BASE __UL_CONST(0xfffff80000000000)
#define KERNEL_RTP_SUP_RGN_SIZE __UL_CONST(0x0000008000000000)
#endif
#ifdef __cplusplus
}
#endif
#endif /* __INCadrSpaceArchLibPh */
vxworks-6.9/target/h/arch/i86/x86_64/private/smpX86_64P.h
+331
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@@ -0,0 +1,331 @@
/* smpX86_64P.h - x86_64 private SMP assembler definitions header file */
/*
* Copyright (c) 2009-2013, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01s,18jul18,r_h Add kernel page table isolation support (F10571)
01r,09jan13,scm WIND00229494 - SMP dedicated segment register
01q,11sep12,cwl Correct the macro _WRS_WIND_VARS_ARCH_GET for UP.
(WIND00375599)
01p,21feb12,scm WIND00326315 - live lock osm & cpc issue...
01o,14aug11,j_l added vxCpuIdLib.h include.
01n,10aug11,zl added _WRS_CPU_SMTSET_GET().
01m,06jan11,scm WIND00240019: add _X86_64_PER_CPU_VALUE_SET_INT macro for SMP support...
01l,04jan11,scm WIND00248698 adjust vxIntStackEnabled to type BOOL...
01k,27oct10,rbc WIND00204240 - Add support for objVerifiedSafe.
01j,29jul10,pad Moved extern C statement after include statements.
01i,22jun10,j_l Delete _X86_64_LOC_APIC_ID.
01h,02jun10,scm modify for smp m to n...
01g,16may10,scm SMP 64 bit macro clean up...
01f,13may10,scm removal of unused vars...
01e,29apr10,scm local apic register access adjustment...
01d,22mar10,scm update for sysCr3...
01c,18mar10,scm add Local CR3 cache to WIND_VARS_ARCH...
01b,12feb09,jb Tuning for 64-bit
01a,26jan09,jb Creating 64-bit version from 32-bit version 01x
*/
#ifndef __INCsmpX86_64Ph
#define __INCsmpX86_64Ph
/************************************************************/
#include <vsbConfig.h>
#include <arch/i86/x86_64/archX86_64.h>
#include <regs.h>
#include <private/kernelLockLibP.h>
#include <hwif/cpu/arch/i86/vxCpuIdLib.h>
#ifdef __cplusplus
extern "C" {
#endif
#define _WRS_ARCH_SUPPORTS_VX_CPU_STATE_INIT
#define _X86_64_CPU_INDEX_SHIFT (0x18)
#define _X86_64_CPU_INDEX_MASK (0xFF)
#ifdef _WRS_CONFIG_SMP
/*
* IA has been adapted to use the new object safe count feature for SMP.
* When all architectures have been adapted this can be removed from
* the code.
*/
#define _WRS_ARCH_HAS_OBJ_SAFE
/*
* This macro defines the alignment requirement for the WIND_VARS structure.
*
* There are 3 factors involved in selection of this value.
*
* 1. It's definition is no LESS than the maximum value of
* _CPU_CACHE_ALIGN_SIZE, and may be larger to provide for future
* cache line length growth.
* 2. It must be at least as large as the WIND_VARS structure.
* 3. It must be a power of 2.
*
* For example:
* If WIND_VARS is 56 bytes, _WRS_WIND_VARS_ALIGN must be no less than 64
* (rule 1).
* if WIND_VARS is 72 bytes, _WRS_WIND_VARS_ALIGN must be no less than 128
* (rules 2 and 3).
*
* For KPTI configuration the alignment has to match WIND_RTP_VARS (512 bytes).
*/
#ifdef _WRS_CONFIG_KPTI
# define _WRS_WIND_VARS_ALIGN _WRS_WIND_RTP_VARS_ALIGN
# define _WRS_WIND_VARS_ALIGN_SHIFT _WRS_WIND_RTP_VARS_ALIGN_SHIFT
#else
# define _WRS_WIND_VARS_ALIGN 256
# define _WRS_WIND_VARS_ALIGN_SHIFT 8
#endif
/*
* Much like the _WRS_WIND_VARS_ALIGN the _WRS_KERNEL_LOCK_VAR_ALIGN macro
* must be defined for the common CPU build variants (e.g. PPC32, MIPS32,
* XSCALE, etc), representing the maximum cache line size of the variants of
* the respective arch.
*
* For x86 this is 128 bytes.
*/
#define _WRS_KERNEL_LOCK_VAR_ALIGN 128
#ifndef _ASMLANGUAGE
/*
* This macro is used to provide an instruction barrier. It is in this file
* only until the semantics are solidified, at which point it should be
* moved to vxAtomicArchLib.h.
*
* The current definition is a replication of the VX_MEM_BARRIER_R() macro. It
* should be revisited when the semantics are finalized.
*/
#define VX_INSTR_BARRIER() _WRS_BARRIER("mfence")
/* mpCpuIndexTable is used in vxCpuArchLib.c, this gloabal avoids
* calling through vxbus and reduces overhead, table translations
* are done everywhere, but once up this table should never change...
*/
extern UINT8 mpCpuIndexTable[];
typedef struct wind_vars_arch
{
GDT *cpu_pSysGdt; /* 0x70: Global Descriptor Table */
TSS *cpu_sysTssCurrent; /* 0x78: Task State Segmnet */
TSS *cpu_excOSMTssCurrent; /* 0x80: OSM TSS */
ULONG *cpu_excOSMStackCurrent; /* 0x88: OSM Stack */
ULONG cpu_vxIntStackPtr; /* 0x90: Interrupt Stack Pointer */
BOOL cpu_vxIntStackEnabled; /* 0x98: Interrupt Stack Enabled */
unsigned int cpu_cpuIndex; /* 0x9c: logical cpu used by GS ref. */
ULONG cpu_sysCr3; /* 0xa0: Local CR3 cache */
UINT32 cpu_intNest; /* 0xa8: Interrupt Nested Count */
UINT32 cpu_sysOSMState; /* 0xac: OSM State Flag */
} WIND_VARS_ARCH;
#define _WRS_WIND_VARS_ARCH WIND_VARS_ARCH cpu_archVars
/* macro to access the arch-specific fields of the vxKernelVars struct */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (archVars.cpu_##glob)
#define _WRS_WIND_VARS_ARCH_SET(cpuid,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(cpuid,archVars.cpu_##glob,var)
#define _WRS_WIND_VARS_ARCH_GET(cpuid,glob) \
_WRS_KERNEL_CPU_GLOBAL_GET(cpuid,archVars.cpu_##glob)
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_SET(archVars.cpu_##glob,var)
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET(archVars.cpu_##glob,var)
/*
* _WRS_CPU_SMTSET_GET() is used by the SMP scheduler for Hyper-Threading
* support.
*/
#define _WRS_CPU_SMTSET_GET(smtSet, cpuIx) \
smtSet = sysCpuIdTopology.__smtSet[cpuIx]
/* Fast retrieve of cpuIndex using GS Base register offset */
static __inline__ unsigned int _vxGsBaseCpuIndexGet_inline (void)
{
unsigned int cpu;
__asm__ volatile ("mov %%gs:(0x9c), %%eax" \
: "=a" (cpu) : /* no input */);
return cpu;
}
#endif /* !_ASMLANGUAGE */
#define _WRS_CPU_INDEX_GET() _vxGsBaseCpuIndexGet_inline ()
#else /* _WRS_CONFIG_SMP */
#define _WRS_CPU_INDEX_GET() 0
/* macro to access the arch-specific fields */
#define _WRS_WIND_VARS_ARCH_ACCESS(glob) \
_WRS_KERNEL_GLOBAL_ACCESS (glob)
#define _WRS_WIND_VARS_ARCH_SET(ignored,glob,var) \
_WRS_KERNEL_CPU_GLOBAL_SET(ignored,glob,var)
#define _WRS_WIND_VARS_ARCH_GET(ignored,glob) \
_WRS_KERNEL_CPU_GLOBAL_GET(ignored,glob)
#define _WRS_ARCH_LOCKED_GLOBAL_SET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_SET(glob,var)
#define _WRS_ARCH_LOCKED_GLOBAL_GET(glob, var) \
_WRS_KERNEL_LOCKED_GLOBAL_GET(glob,var)
#endif /* _WRS_CONFIG_SMP */
#ifdef _ASMLANGUAGE
#include <private/windLibP.h>
#if defined(_WRS_CONFIG_SMP)
/* SMP support */
#define _WRS_WIND_VARS_OFFSET_pSysGdt (_WRS_WIND_VARS_OFFSET_archVars+0x0)
#define _WRS_WIND_VARS_OFFSET_sysTssCurrent (_WRS_WIND_VARS_OFFSET_archVars+0x8)
#define _WRS_WIND_VARS_OFFSET_excOSMTssCurrent (_WRS_WIND_VARS_OFFSET_archVars+0x10)
#define _WRS_WIND_VARS_OFFSET_excOSMStackCurrent (_WRS_WIND_VARS_OFFSET_archVars+0x18)
#define _WRS_WIND_VARS_OFFSET_vxIntStackPtr (_WRS_WIND_VARS_OFFSET_archVars+0x20)
#define _WRS_WIND_VARS_OFFSET_vxIntStackEnabled (_WRS_WIND_VARS_OFFSET_archVars+0x28)
#define _WRS_WIND_VARS_OFFSET_cpuIndex (_WRS_WIND_VARS_OFFSET_archVars+0x2c)
#define _WRS_WIND_VARS_OFFSET_sysCr3 (_WRS_WIND_VARS_OFFSET_archVars+0x30)
#define _WRS_WIND_VARS_OFFSET_intNest (_WRS_WIND_VARS_OFFSET_archVars+0x38)
#define _WRS_WIND_VARS_OFFSET_sysOSMState (_WRS_WIND_VARS_OFFSET_archVars+0x3c)
#define _WRS_LOAD_REG_WITH_VAR_BASE(label,reg) \
lea FUNC(vxKernelVars),reg; \
add $_WRS_WIND_VARS_OFFSET_##label,reg;
#define _WRS_WIND_VARS_OFFSET(reg) \
rol $_WRS_WIND_VARS_ALIGN_SHIFT,reg;
#define _X86_64_ASM_EXTERN_KERNEL_GLOBALS
/*
* Obtain the address of vxKernelVars[cpuid] for the current
* CPU in register 'reg', using 'scratch' as a scratch
* variable.
*/
#define _X86_64_CPU_ADRS_BASE_GET(reg,scratch) \
_WRS_WIND_VARS_OFFSET(reg) \
leaq FUNC(vxKernelVars)(reg), reg;
#define _X86_64_PER_CPU_ADRS_GET(reg,scratch,label) \
_WRS_WIND_VARS_OFFSET(reg) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addq reg,scratch; \
leaq 0x0(scratch),reg;
#define _X86_64_PER_CPU_VALUE_GET_INT(reg,regv,scratch,label) \
_WRS_WIND_VARS_OFFSET(regv) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
add regv,scratch; \
movl 0x0(scratch),reg;
#define _X86_64_PER_CPU_VALUE_GET_LONG(reg,scratch,label) \
_WRS_WIND_VARS_OFFSET(reg) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addq reg,scratch; \
movq 0x0(scratch),reg;
#define _X86_64_PER_CPU_VALUE_SET_INT(regv,scr1,scr2,label) \
_WRS_WIND_VARS_OFFSET(scr1) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
addq scr1,scr2; \
movl regv,0x0(scr2);
#define _X86_64_PER_CPU_VALUE_SET_LONG(regv,scr1,scr2,label) \
_WRS_WIND_VARS_OFFSET(scr1) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scr2) \
addq scr1,scr2; \
movq regv,0x0(scr2);
#define _X86_64_PER_CPU_VALUE_AND_ADRS_GET_LONG(regv,rega,scratch,label) \
_WRS_WIND_VARS_OFFSET(regv) \
_WRS_LOAD_REG_WITH_VAR_BASE(label,scratch) \
addq regv,scratch; \
leaq 0x0(scratch),rega; \
movq 0x0(scratch),regv;
#else /* _WRS_CONFIG_SMP */
#define _WRS_X86_64_VAR_ADRS(label) FUNC(label)
#define _X86_64_ASM_EXTERN_KERNEL_GLOBALS \
.globl FUNC(sysTssCurrent); /* OSM Tss task info */ \
.globl FUNC(excOSMTssCurrent); /* OSM Tss */ \
.globl FUNC(pSysGdt); /* Gdt */ \
.globl FUNC(intNest); /* nested intr cnt */ \
.globl FUNC(vxIntStackPtr); /* intr stk ptr */ \
.globl FUNC(vxIntStackEnabled); /* intr stk enabled flag */ \
.globl FUNC(sysCr3); /* local CR3 cache */ \
.globl FUNC(sysOSMState); /* OSM State Flag */
#define _X86_64_PER_CPU_ADRS_GET(reg,scratch,label) \
lea _WRS_X86_64_VAR_ADRS(label),reg; /* get address of label */
#define _X86_64_PER_CPU_VALUE_GET_INT(reg,scratch,label) \
movl _WRS_X86_64_VAR_ADRS(label),reg; /* get value at label */
#define _X86_64_PER_CPU_VALUE_GET_LONG(reg,scratch,label) \
movq _WRS_X86_64_VAR_ADRS(label),reg; /* get value at label */
#define _X86_64_PER_CPU_VALUE_SET_INT(regv,scr1,scr2,label) \
movl regv,_WRS_X86_64_VAR_ADRS(label);
#define _X86_64_PER_CPU_VALUE_SET_LONG(regv,scr1,scr2,label) \
movq regv,_WRS_X86_64_VAR_ADRS(label);
#define _X86_64_PER_CPU_VALUE_AND_ADRS_GET_INT(regv,rega,label) \
leaq _WRS_X86_64_VAR_ADRS(label),rega; /* get address of label */ \
leal 0x0(rega),regv; /* get value at label */
#define _X86_64_PER_CPU_VALUE_AND_ADRS_GET_LONG(regv,rega,label) \
leaq _WRS_X86_64_VAR_ADRS(label),rega; /* get address of label */ \
leaq 0x0(rega),regv; /* get value at label */
#define _X86_64_PER_CPU_VALUE_INC(reg,scratch,label) \
incl _WRS_X86_64_VAR_ADRS(label);
#define _X86_64_PER_CPU_VALUE_DEC(reg,scratch,label) \
decl _WRS_X86_64_VAR_ADRS(label);
#endif /* _ASMLANGUAGE */
#endif /* _WRS_CONFIG_SMP */
#ifdef __cplusplus
}
#endif
#endif /* __INCsmpX86_64Ph */
vxworks-6.9/target/h/arch/i86/x86_64/private/vxdbgX86_64LibP.h
+62
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@@ -0,0 +1,62 @@
/* vxdbgX86_64LibP.h - private X86_64 VxDBG library header file */
/*
* Copyright (c) 2009-2011 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use of this
* software may be licensed only pursuant to the terms of an applicable Wind
* River license agreement.
*/
/*
modification history
--------------------
01e,09feb11,rlp Defined VXDBG_INT_LOCK_LEVEL_COMPUTE macro for both UP and
SMP (CQ:WIND00253870).
01d,29apr10,pad Moved extern C statement after include statements.
01c,06may09,rlp Added wdbDbgPreBreakpoint and wdbDbgPreTrace prototypes.
01b,24feb09,jb Update register reference
01a,18feb09,jb Created from 32-bit version 01d
*/
#ifndef __INCvxdbgX86_64LibPh
#define __INCvxdbgX86_64LibPh
#ifndef _ASMLANGUAGE
#include <vsbConfig.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This macro returns the <level> parameter modified with the interrupt lock
* level defined into the <value> parameter. The <level> parameter must be
* previously get with either intCpuLock() or intRegsLock() API.
*/
#define VXDBG_INT_LOCK_LEVEL_COMPUTE(level, value) \
((level & ~INT_FLAG) | (value & INT_FLAG))
#ifdef _WRS_CONFIG_SMP
/* return TRUE if interrupts are locked in specified register set. */
#define VXDBG_INT_REGS_IS_LOCKED(pRegs) (((pRegs->rflags & INT_FLAG) == \
INT_FLAG) ? FALSE : TRUE)
#endif /* _WRS_CONFIG_SMP */
/* function declarations */
extern void wdbDbgPreBreakpoint (BREAK_ESF * info, long * regs, BOOL hardware);
extern void wdbDbgPreTrace (BREAK_ESF * info, long * regs, BOOL hardware);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxdbgX86_64LibPh */
vxworks-6.9/target/h/arch/i86/x86_64/regsX86_64.h
+1036
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File diff suppressed because it is too large Load Diff
vxworks-6.9/target/h/arch/i86/x86_64/syscallArgsX86_64.h
+1004
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File diff suppressed because it is too large Load Diff
vxworks-6.9/target/h/arch/i86/x86_64/syscallX86_64.h
+155
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@@ -0,0 +1,155 @@
/* syscallX86_64.h - x86_64 specific System Call Infrastructure header */
/*
* Copyright (c) 2003-2005, 2007-2009, 2012, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01i,18jul18,r_h Add kernel page table isolation support (F10571)
01h,24jul12,scm WIND00225976 - syscall/sysret support...
01g,01dec09,scm make 64 bit compliant...
01f,14mar08,scm modify saved regs to reflect code changes...
01e,04may07,zl updated portable library build configuration.
01d,05may05,zmm Fix SYSCALL_ENTRY_FRAME_SIZE. SPR 108825
01c,02feb04,jb Fix SPR 93500
01b,04jan04,jb Adding context to syscall_entry_state
01a,18sep03,jb written.
*/
/*
DESCRIPTION
This header contains x86_64-specific definitions and constants used by
the System Call Infrastructure library.
*/
#ifndef __INCsyscallX86_64h
#define __INCsyscallX86_64h
#ifndef _ASMLANGUAGE
#include <taskLib.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
#define SYSCALL_ENTRY_FRAME_SIZE 144 /* size of 'syscall' frame */
#define INSTR_SYSCALL_SIZE 2 /* size of 'syscall' instruction */
#define SYSCALL_STACK_ARGS 8 /* number of arguments passed */
/*
* Stack save area offsets.
* Please make the frame size a uniform value to cover all
* CPU variants. This helps maintain a uniform stack usage
* pattern for a given architecture.
*/
#define SC_STK_USR_SS 136 /* user stack segment */
#define SC_STK_USR_SP 128 /* user-mode stack pointer */
#define SC_STK_RTNCS 120 /* return address code segment */
#define SC_STK_RTN 112 /* return address instruction pointer */
#define SC_STK_R11 104
#define SC_STK_RCX 96
#define SC_STK_ARG8 88 /* argument list */
#define SC_STK_ARG7 80
#define SC_STK_ARG6 72
#define SC_STK_ARG5 64
#define SC_STK_ARG4 56
#define SC_STK_ARG3 48
#define SC_STK_ARG2 40
#define SC_STK_ARG1 32
#define SC_STK_URTN 24 /* return to caller pc */
#define SC_STK_SCN 16 /* System Call Number - Also temp error storage */
#define SC_STK_RBX 8 /* Saved reg on entry to syscallHandle */
#define SC_STK_RAX 0 /* Saved reg on entry to syscallHandle */
#define USR_STK_ARG8 56
#define USR_STK_ARG7 48
#define USR_STK_UPC 40
#define USR_STK_SCN 32
#define USR_STK_RCX 24
#define USR_STK_R11 16
#define USR_STK_RIP 8
#define USR_STK_EFLAGS 0
/*
* Define for error handling.
*/
#define EXC_INV_OPCODE 30 /* Invalid Op Code error offset into */
/* exception table */
#define EXC_GEN_PROTECT 65 /* General Protection error offset into */
/* exception table */
#define CANONICAL_CHECK 0xffff800000000000
#ifndef _ASMLANGUAGE
/* The call gate/Tss mechanism does the copy for us, this is not needed */
#define _SYSCALL_USER_SP_CHECK(sp)
/* typedefs */
/*
* The SYSCALL_ENTRY_STATE structure defines the saved machine state
* when the system call trap is taken. This information is architecture
* specific, and is used by the system call dispatcher to restart system
* calls that have been interrupted by the occurance of signals.
* System call restart is achieved by restoring the saved state at the
* time of the system call trap, and re-issuing the system call.
*
* All arguments to the system call are saved on the kernel stack, and
* the address of that array is passed as an argument to the dispatcher.
* The layout of this structure must exactly match the ordering of members
* of the system call entry frame in src/arch/X86_64/x86_64/syscallALib.s.
*
*/
typedef struct syscall_entry_state
{
long rax; /* Saved reg on entry to syscallHandle */
long rbx; /* Saved reg on entry to syscallHandle */
long scn; /* System Call Number - Also temp error storage */
long upc; /* return to caller pc */
long args[8]; /* argument list */
long rcx; /* save off SYSCALL/SYSRET use for RIP */
long r11; /* save off SYSCALL/SYSRET use for EFLAGS */
void * pc; /* return address instruction pointer */
long cs; /* return address code segment */
long * pUStack; /* user-mode stack pointer */
long ss; /* user stack segment */
} SYSCALL_ENTRY_STATE;
/* Prototype */
UINT32 sysModGdt (UINT32 offset, UINT32 limit, UINT32 base, UINT32 priority);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCsyscallX86_64h */
vxworks-6.9/target/h/arch/i86/x86_64/vxAtomicArchLib.h
+438
View File
@@ -0,0 +1,438 @@
/* vxAtomicArchLib.h - x86_64 IA32 specific atomic library header */
/*
* Copyright (c) 2006-2008, 2010, 2018 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
19sep18,m_w make sure the code map of inline ASM under GNU
is correct (VXW6-86665)
13sep10,scm WIND002322578 remove type-punning warnings...
29apr10,pad Moved extern C statement after include statements.
23mar10,scm add inline gnu routines for 64 bit
23mar10,scm add fixed size APIs, made memory barriers available in user space
16jun08,zl use _WRS_BARRIER() for memory barrier implementations.
17jan08,gls renamed inline routines
03jan08,gls fixed DCC _inline_vxCas()
11dec07,gls Added _inline_vxCas()
29nov06,scm Created
*/
#ifndef __INCvxAtomicArchLibh
#define __INCvxAtomicArchLibh
#include <arch/i86/x86_64/vxAtomicArchLibCommon.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#if defined (__DCC__)
#define vxCas_inline vxAtomicCas
#define vxAtomicCas_inline vxAtomicCas
#define vxAtomic64Cas_inline vxAtomic64Cas
#define vxAtomic32Cas_inline vxAtomic32Cas
#define vxAtomicAdd_inline vxAtomicAdd
#define vxAtomic64Add_inline vxAtomic64Add
#define vxAtomic32Add_inline vxAtomic32Add
#define vxAtomicSub_inline vxAtomicSub
#define vxAtomic64Sub_inline vxAtomic64Sub
#define vxAtomic32Sub_inline vxAtomic32Sub
#define vxAtomicInc_inline vxAtomicInc
#define vxAtomic64Inc_inline vxAtomic64Inc
#define vxAtomic32Inc_inline vxAtomic32Inc
#define vxAtomicDec_inline vxAtomicDec
#define vxAtomic64Dec_inline vxAtomic64Dec
#define vxAtomic32Dec_inline vxAtomic32Dec
#define vxAtomicGet_inline vxAtomicGet
#define vxAtomic64Get_inline vxAtomic64Get
#define vxAtomic32Get_inline vxAtomic32Get
#define vxAtomicSet_inline vxAtomicSet
#define vxAtomic64Set_inline vxAtomic64Set
#define vxAtomic32Set_inline vxAtomic32Set
#define vxAtomicClear_inline vxAtomicClear
#define vxAtomic64Clear_inline vxAtomic64Clear
#define vxAtomic32Clear_inline vxAtomic32Clear
#elif defined (__GNUC__)
static __inline__ BOOL vxAtomic64Cas_inline
(
atomic64_t * target, /* memory location to compare-and-swap */
atomic64Val_t oldValue, /* compare to this value */
atomic64Val_t newValue /* swap with this value */
)
{
BOOL swapped;
__asm__ volatile
(
"movq %3, %%rax;" /* move oldValue to %rax */
"lock;" /* lock the Bus during the next inst */
"cmpxchgq %4, %2;" /* if (%rax == *target) */
/* {ZF = 1; *target = newValue;} */
/* else */
/* {ZF = 0; %rax = *target;} */
"setz %%al;" /* if success, set swapped to TRUE else FALSE */
"movzb %%al, %0" /* zero extend swapped */
: "=&a" (swapped), /* output: swapped is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)), /* input: *target is %2 */
"g" (oldValue), /* oldValue is %3 */
"r" (newValue) /* newValue is %4 */
: "memory" /* memory clobber for code barrier */
);
return swapped;
}
static __inline__ BOOL vxAtomic32Cas_inline
(
atomic32_t * target, /* memory location to compare-and-swap */
atomic32Val_t oldValue, /* compare to this value */
atomic32Val_t newValue /* swap with this value */
)
{
BOOL swapped;
__asm__ volatile
(
"movl %3, %%eax;" /* move oldValue to %eax */
"lock;" /* lock the Bus during the next inst */
"cmpxchgl %4, %2;" /* if (%eax == *target) */
/* {ZF = 1; *target = newValue;} */
/* else */
/* {ZF = 0; %eax = *target;} */
"setz %%al;" /* if success, set swapped to TRUE else FALSE */
"movzbl %%al, %0" /* zero extend swapped */
: "=&a" (swapped), /* output: swapped is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)), /* input: *target is %2 */
"g" (oldValue), /* oldValue is %3 */
"r" (newValue) /* newValue is %4 */
: "memory" /* memory clobber for code barrier */
);
return swapped;
}
static __inline__ atomic64Val_t vxAtomic64Add_inline
(
atomic64_t * target,
atomic64Val_t value
)
{
__asm__ volatile
(
"lock;" /* lock the Bus during the next inst */
"xaddq %0, %2" /* TMP = value + *target */
/* value = *target */
/* *target = TMP */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Add_inline
(
atomic32_t * target,
atomic32Val_t value
)
{
__asm__ volatile
(
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = value + *target */
/* value = *target */
/* *target = TMP */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic64Val_t vxAtomic64Sub_inline
(
atomic64_t * target,
atomic64Val_t value
)
{
__asm__ volatile
(
"negq %0;" /* Negate value... */
"lock;" /* lock the Bus during the next inst */
"xaddq %0, %2" /* TMP = -value + *target */
/* value = *target */
/* *target = TMP */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Sub_inline
(
atomic32_t * target,
atomic32Val_t value
)
{
__asm__ volatile
(
"negl %0;" /* Negate value... */
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = -value + *target */
/* value = *target */
/* *target = TMP */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic64Val_t vxAtomic64Inc_inline
(
atomic64_t * target
)
{
atomic64Val_t value;
__asm__ volatile
(
"movq $1, %0;" /* inc by 1 */
"lock;" /* lock the Bus during the next inst */
"xaddq %0, %2" /* TMP = *target + 1 */
/* value = *target */
/* *target = TMP */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Inc_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl $1, %0;" /* inc by 1 */
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = *target + 1 */
/* value = *target */
/* *target = TMP */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic64Val_t vxAtomic64Dec_inline
(
atomic64_t * target
)
{
atomic64Val_t value;
__asm__ volatile
(
"movq $(-1), %0;" /* dec by 1 */
"lock;" /* lock the Bus during the next inst */
"xaddq %0, %2" /* TMP = *target - 1 */
/* value = *target */
/* *target = TMP */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Dec_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl $(-1), %0;" /* dec by 1 */
"lock;" /* lock the Bus during the next inst */
"xaddl %0, %2" /* TMP = *target - 1 */
/* value = *target */
/* *target = TMP */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic64Val_t vxAtomic64Get_inline
(
atomic64_t * target
)
{
atomic64Val_t value;
__asm__ volatile
(
"movq %1, %0" /* get value with bus-lock */
: "=r" (value) /* output: value is %0 */
: "m" (*(target)) /* input: *target is %1 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Get_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl %1, %0" /* get value with bus-lock */
: "=r" (value) /* output: value is %0 */
: "m" (*(target)) /* input: *target is %1 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic64Val_t vxAtomic64Set_inline
(
atomic64_t * target,
atomic64Val_t value
)
{
__asm__ volatile
(
"xchgq %0, %2" /* set value with bus-lock */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Set_inline
(
atomic32_t * target,
atomic32Val_t value
)
{
__asm__ volatile
(
"xchgl %0, %2" /* set value with bus-lock */
: "+r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic64Val_t vxAtomic64Clear_inline
(
atomic64_t * target
)
{
atomic64Val_t value;
__asm__ volatile
(
"movq $0, %0;" /* 'clear' value to set */
"xchgq %0, %2" /* swap 'clear' value with bus-lock */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
static __inline__ atomic32Val_t vxAtomic32Clear_inline
(
atomic32_t * target
)
{
atomic32Val_t value;
__asm__ volatile
(
"movl $0, %0;" /* 'clear' value to set */
"xchgl %0, %2" /* swap 'clear' value with bus-lock */
: "=&r" (value), /* output: value is %0 */
"=m" (target) /* target is %1 */
: "m" (*(target)) /* input: *target is %2 */
: "memory" /* memory clobber for code barrier */
);
return value;
}
#define vxCas_inline vxAtomic64Cas_inline
#define vxAtomicCas_inline vxAtomic64Cas_inline
#define vxAtomicAdd_inline vxAtomic64Add_inline
#define vxAtomicSub_inline vxAtomic64Sub_inline
#define vxAtomicInc_inline vxAtomic64Inc_inline
#define vxAtomicDec_inline vxAtomic64Dec_inline
#define vxAtomicGet_inline vxAtomic64Get_inline
#define vxAtomicSet_inline vxAtomic64Set_inline
#define vxAtomicClear_inline vxAtomic64Clear_inline
#else
#define vxCas_inline vxAtomicCas
#define vxAtomicCas_inline vxAtomicCas
#define vxAtomic64Cas_inline vxAtomic64Cas
#define vxAtomic32Cas_inline vxAtomic32Cas
#define vxAtomicAdd_inline vxAtomicAdd
#define vxAtomic64Add_inline vxAtomic64Add
#define vxAtomic32Add_inline vxAtomic32Add
#define vxAtomicSub_inline vxAtomicSub
#define vxAtomic64Sub_inline vxAtomic64Sub
#define vxAtomic32Sub_inline vxAtomic32Sub
#define vxAtomicInc_inline vxAtomicInc
#define vxAtomic64Inc_inline vxAtomic64Inc
#define vxAtomic32Inc_inline vxAtomic32Inc
#define vxAtomicDec_inline vxAtomicDec
#define vxAtomic64Dec_inline vxAtomic64Dec
#define vxAtomic32Dec_inline vxAtomic32Dec
#define vxAtomicGet_inline vxAtomicGet
#define vxAtomic64Get_inline vxAtomic64Get
#define vxAtomic32Get_inline vxAtomic32Get
#define vxAtomicSet_inline vxAtomicSet
#define vxAtomic64Set_inline vxAtomic64Set
#define vxAtomic32Set_inline vxAtomic32Set
#define vxAtomicClear_inline vxAtomicClear
#define vxAtomic64Clear_inline vxAtomic64Clear
#define vxAtomic32Clear_inline vxAtomic32Clear
#endif /* _VX_TOOL_FAMILY */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibh */
vxworks-6.9/target/h/arch/i86/x86_64/vxAtomicArchLibCommon.h
+41
View File
@@ -0,0 +1,41 @@
/* vxAtomicArchLibCommon.h - x86_64 specific atomic library header */
/*
* Copyright (c) 2010, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01b,27apr12,scm WIND00346365 - VX_MEM_BARRIER_R()/_W()/_RW all using
mfence...
01a,23mar10,scm written.
*/
#ifndef __INCvxAtomicArchLibCommonh
#define __INCvxAtomicArchLibCommonh
#ifdef __cplusplus
extern "C" {
#endif
#define _WRS_ARCH_SUPPORTS_MEM_BARRIER
/*
* Macros to provide memory barrier.
*/
#define VX_MEM_BARRIER_R() _WRS_BARRIER("lfence");
#define VX_MEM_BARRIER_W() _WRS_BARRIER("sfence");
#define VX_MEM_BARRIER_RW() _WRS_BARRIER("mfence");
#define VX_INSTR_BARRIER() _WRS_BARRIER("mfence")
#ifdef __cplusplus
}
#endif
#endif /* __INCvxAtomicArchLibCommonh */
vxworks-6.9/target/h/arch/i86/x86_64/vxX86_64Lib.h
+85
View File
@@ -0,0 +1,85 @@
/* vxX86_64Lib.h - header for arch/board dependent routines for x86_64 */
/*
* Copyright 2009, 2012 Wind River Systems, Inc.
*
* The right to copy, distribute or otherwise make use of this software
* may be licensed only pursuant to the terms of an applicable Wind River
* license agreement.
*/
/*
modification history
--------------------
01c,09may12,j_l WIND00337546 - Add vxGdtrSet() and vxLdtrSet() prototypes.
Modify vxLdtrGet() prototype.
Adhere to coding standards more closely
01b,24feb09,jb Update to 64-bits
01a,26jan09,jb Created from 32-bit version 01h
*/
#ifndef __INCvxX86_64Libh
#define __INCvxX86_64Libh
#ifdef __cplusplus
extern "C" {
#endif
/* power management mode definitions - used by vxPowerModeSet/Get */
#define VX_POWER_MODE_DISABLE (0x1) /* power mgt disable: loop when idle*/
#define VX_POWER_MODE_AUTOHALT (0x4) /* AutoHalt power management mode */
/* function declarations */
#ifndef _ASMLANGUAGE
extern void vxMemProbeTrap (void);
extern STATUS vxMemProbeSup (int length, char * adrs, char * pVal);
extern long vxCr0Get (void);
extern void vxCr0Set (long cr0);
extern long vxCr2Get (void);
extern void vxCr2Set (long cr2);
extern long vxCr3Get (void);
extern void vxCr3Set (long cr3);
extern long vxCr4Get (void);
extern void vxCr4Set (long cr4);
extern int vxCsGet (void);
extern int vxDsGet (void);
extern int vxSsGet (void);
extern long vxEflagsGet (void);
extern void vxEflagsSet (long rflags);
extern void vxDrGet (long * pDr0, long * pDr1, long * pDr2,
long * pDr3, long * pDr4, long * pDr5,
long * pDr6, long * pDr7);
extern void vxDrSet (long dr0, long dr1, long dr2, long dr3,
long dr4, long dr5, long dr6, long dr7);
extern int vxTssGet (void);
extern void vxTssSet (long value);
extern void vxGdtrGet (long long int * pGdtr);
extern void vxGdtrSet (long long int * pGdtr);
extern void vxIdtrGet (long long int * pIdtr);
extern void vxLdtrGet (UINT16 * pLdtr);
extern void vxLdtrSet (UINT16 ldtr);
IMPORT STATUS vxPowerModeSet (UINT32 mode);
IMPORT UINT32 vxPowerModeGet (void);
extern STATUS vxIdleHookAdd (FUNCPTR entHook, FUNCPTR exitHook);
extern VOID vxIdleEntHookRtn (void);
extern VOID vxIdleExtHookRtn (void);
extern UINT32 vxIdleUtilGet (void);
extern void vxShowInit (void);
extern void vxCpuShow (void);
extern void vxDrShow (void);
extern void vxSseShow (long);
extern void vxIdleShow (BOOL debug);
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCvxX86_64Libh */