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/* vfpArmLib.h - Arm Version of Vector Floating-Point Include File */
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/*
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* Copyright (c) 2005, 2009-2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01f,22aug13,mpc Add VFP support for ARMARCH7M
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01e,09oct12,jdw Add support to configure Round To Zero mode in FPSCR
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01d,25jul11,jdw Add support for VFPv3-D32 for ARMARCH7
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,15may09,mdo Assembler is fixed
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01a,29jun05,scm VFP written
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*/
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#ifndef __INCvfpArmLibh
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#define __INCvfpArmLibh
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#include <vxWorks.h>
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#include <regs.h>
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#include <esf.h>
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#if (CPU == ARMARCH7M)
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#include <arch/arm/arm-m/vfpArmLib.h>
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#else
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* VFP System Registers */
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/* FPSID (Floating Point System ID Register) bit definitions */
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/* READ ONLY register, RESET State:0x410120b3, Access Mode:Any */
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#define FPSID_IMPLEMENTOR_MSK 0xFF000000
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#define FPSID_ARM_LTD 0x41000000 /* ARM Limited */
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#define FPSID_SW_MSK (1<<23)
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#define FPSID_SW FPSID_SW_MSK
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#define FPSID_HW 0x00000000
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#define FPSID_FORMATR_MSK 0x00600000
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#define FPSID_STNDRD_F1 0x00000000
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#define FPSID_STNDRD_F2 (1<<21)
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#define FPSID_RSRVD_F (1<<22)
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#define FPSID_NONSTDRD_F 0x00600000
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#define FPSID_SNG_MSK (1<<20)
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#define FPSID_SNG_ONLY FPSID_SNG_MSK
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#define FPSID_ARCH_MSK 0x000F0000
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#define FPSID_VFP1 0x00000000
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#define FPSID_VFP2 0x00010000 /* VFPv2 */
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#define FPSID_PRTNUM_MSK 0x0000FF00
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#define FPSID_VFP11 0x00002000 /* VFP11 */
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#define FPSID_VARIANT_MSK 0x000000F0
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#define FPSID_ARM11_VFP 0x000000B0 /* ARM 11 VFP */
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#define FPSID_REV_MSK 0x0000000F
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/* FPSCR (Floating Status and Control Register) bit definitions */
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/* READ/WRITE register, RESET State:0x00000000, Access Mode:Any */
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/*
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* At the time of implementation bits 27-25,19,15-13, and 7-5,
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* are described as DNM (DO NOT MODIFY), one must employ
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* read/modify/write techniques when handling the FPSCR in order
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* to ensure that these bits are not modified...
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*/
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#define FPSCR_N_BIT (1<<31) /* less than result */
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#define FPSCR_Z_BIT (1<<30) /* equal result */
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#define FPSCR_C_BIT (1<<29) /* equal, greater than, or unordered result */
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#define FPSCR_V_BIT (1<<28) /* unordered result */
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#define FPSCR_DN_BIT (1<<25) /* Default NaN mode control */
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#define FPSCR_DN_MSK FPSCR_DN_BIT
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#define FPSCR_DN_ENABLE FPSCR_DN_BIT
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#define FPSCR_DN_DISABLE 0x00000000
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#define FPSCR_FZ_BIT (1<<24) /* flush to zero mode control */
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#define FPSCR_FZ_MSK FPSCR_FZ_BIT
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#define FPSCR_FZ_ENABLE FPSCR_FZ_BIT
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#define FPSCR_FZ_DISABLE 0x00000000
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/* Trap Enable Bits */
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#define FPSCR_IDE_BIT (1<<15) /* Input Subnormal */
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#define FPSCR_IXE_BIT (1<<12) /* Inexact */
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#define FPSCR_UFE_BIT (1<<11) /* Underflow */
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#define FPSCR_OFE_BIT (1<<10) /* Overflow */
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#define FPSCR_DZE_BIT (1<<9) /* Division By Zero */
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#define FPSCR_IOE_BIT (1<<8) /* Invalid Operation */
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/* Cumulative Exception Bits */
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#define FPSCR_IDC_BIT (1<<7) /* Input Subnormal */
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#define FPSCR_IXC_BIT (1<<4) /* Inexact */
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#define FPSCR_UFC_BIT (1<<3) /* Underflow */
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#define FPSCR_OFC_BIT (1<<2) /* Overflow */
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#define FPSCR_DZC_BIT (1<<1) /* Division By Zero */
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#define FPSCR_IOC_BIT (1<<0) /* Invalid Operation */
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#define FPSCR_RMODES_MSK 0x00C00000
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#define FPSCR_RN 0x00000000
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#define FPSCR_RP 0x00400000
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#define FPSCR_RM 0x00800000
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#define FPSCR_RZ 0x00C00000
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#define FPSCR_STRIDE_MSK 0x00300000
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#define FPSCR_LEN_MSK 0x00070000
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/* FPEXC (Floating Exception Register) bit definitions */
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/* READ/WRITE register, RESET State:0x00000000, Access Mode:Privileged */
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#define FPEXC_EX_BIT (1<<31) /* status bit */
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#define FPEXC_EN_BIT (1<<30) /* global enable bit */
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#define FPEXC_FP2V_BIT (1<<28) /* FPINST2 instruction valid bit */
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/* Vector Iteration */
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#define FPEXC_VECITR_MSK 0x00000700
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#define FPEXC_VECITR_1 0x00000000
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#define FPEXC_VECITR_2 0x00000100
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#define FPEXC_VECITR_3 0x00000200
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#define FPEXC_VECITR_4 0x00000300
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#define FPEXC_VECITR_5 0x00000400
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#define FPEXC_VECITR_6 0x00000500
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#define FPEXC_VECITR_7 0x00000600
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#define FPEXC_VECITR_8 0x00000700
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#define FPEXC_INV_BIT (1<<7) /* Input Exception bit */
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#define FPEXC_UFC_BIT (1<<3) /* Potential Underflow bit */
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#define FPEXC_OFC_BIT (1<<2) /* Potential Overflow bit */
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#define FPEXC_IOC_BIT (1<<0) /* Potential Invalid Operation bit */
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/* VFP11 Specific System Registers */
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/* FPINST (Floating Point Instruction Register) bit definitions */
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/* READ/WRITE register, RESET State:0xEE000A00, Access Mode:Privileged */
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/*
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* FPINST register contains the exceptional instruction
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*/
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/* FPINST2 (Floating Point Instruction Register 2) bit definitions */
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/* READ/WRITE register, RESET State:Unpredictable, Access Mode:Privileged */
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/*
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* FPINST2 register contains the instruction that was issued to the VFP11
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* coprocessor before the exception was detected
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*/
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/* MFVFR0 (Media and VFP Feature Register 0) bit definitions */
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/* READ ONLY register, RESET State:0x11111111, Access Mode:Any */
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/* MFVFR1 (Media and VFP Feature Register 1) bit definitions */
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/* READ ONLY register, RESET State:0x00000000, Access Mode:Any */
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/* initialization parameters */
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/*
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* The VFP coprocessor allows the Round To Zero mode to be used to perform
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* faster VFP computations, but is not strictly IEEE-754 compliant. The
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* default for ARM is to enable Round To Zero mode. See the ARM Architecture
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* Reference Manual for more information.
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*/
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#ifdef _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO
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#define FPSCR_INIT FPSCR_DN_MSK
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#else /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
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#define FPSCR_INIT (FPSCR_DN_MSK | FPSCR_FZ_BIT)
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#endif /* _WRS_CONFIG_DISABLE_VFP_ROUND_TO_ZERO */
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#define _VFP_ALIGN_SIZE 8 /* 64 bit */
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#define VFPREG_SET VFP_CONTEXT
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/* FP_CONTEXT structure offsets */
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#define VFP_FPSID 0x00
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#define VFP_FPSCR 0x04
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#define VFP_FPEXC 0x08
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#define VFP_FPINST 0x0C
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#define VFP_FPINST2 0x10
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#define VFP_MVVFR0 0x14
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#define VFP_MVVFR1 0x18
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#define VFP_PAD -
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#define VFP_GPR 0x20 /* OFFSET(FP_CONTEXT, vfp_gpr[0]) */
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#define VFP_GPR_OFFSET(n) (VFP_GPR + (n)*4) /* vfp_gpr[n]) */
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/* VFP_REG_SET - ARM VFP register set */
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#ifdef _WRS_CONFIG_ENABLE_VFPV3_D32
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/*
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* VFPv3-D32 / NEON
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* 64 single precision or 32 double precision general purpose
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*/
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#define VFP_DGPR_NUM 32 /* 32-double precision general purpose */
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#define VFP_SGPR_NUM 64 /* 64-single precision general purpose */
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#else /* _WRS_CONFIG_ENABLE_VFPV3_D32 */
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/*
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* VFPv3-D16
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* 32 single precision or 16 double precision general purpose
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*/
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#define VFP_DGPR_NUM 16 /* 16-double precision general purpose */
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#define VFP_SGPR_NUM 32 /* 32-single precision general purpose */
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#endif /* _WRS_CONFIG_ENABLE_VFPV3_D32 */
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#if (_BYTE_ORDER == _LITTLE_ENDIAN)
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# define HREG 1
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# define LREG 0
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#else /* _BYTE_ORDER != _LITTLE_ENDIAN */
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# define HREG 0
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# define LREG 1
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#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#ifndef _ASMLANGUAGE
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typedef union
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{
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double u64;
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UINT32 u32[2];
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} VFP_UNION64D;
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typedef struct vfpContext /* VFP Context */
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{
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UINT32 fpsid; /* system ID register : 4 */
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UINT32 fpscr; /* status and control register : 4 */
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UINT32 fpexc; /* exception register : 4 */
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UINT32 fpinst; /* instruction register : 4 */
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UINT32 fpinst2; /* instruction register 2 : 4 */
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UINT32 mfvfr0; /* media and VFP feature Register 0: 4 */
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UINT32 mfvfr1; /* media and VFP feature Register 1: 4 */
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UINT32 pad;
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UINT32 vfp_gpr[VFP_SGPR_NUM]; /* general purpose registers : 128 or 256 */
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/* TOTAL : 156 or 284 */
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} WRS_PACK_ALIGN(_VFP_ALIGN_SIZE) VFP_CONTEXT;
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/* function declarations */
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IMPORT void vfpArchInit (void);
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IMPORT void vfpArchTaskCreateInit (VFP_CONTEXT *pDspContext);
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IMPORT void vfpSave (VFP_CONTEXT *);
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IMPORT void vfpRestore (VFP_CONTEXT *);
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IMPORT STATUS vfpProbe (void);
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IMPORT STATUS vfpProbeTrap (void);
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IMPORT STATUS vfpEnable (void);
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IMPORT STATUS vfpDisable (void);
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IMPORT VFP_CONTEXT * vfpCtxCreate (int);
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IMPORT STATUS vfpCtxDelete (VFP_CONTEXT *);
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IMPORT void vfpCtxShow (VFP_CONTEXT *);
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void vfpRegsToCtx (VFPREG_SET *, VFP_CONTEXT *);
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void vfpCtxToRegs (VFP_CONTEXT *, VFPREG_SET *);
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#ifdef _WRS_HW_VFP_SUPPORT
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IMPORT int vfpIsEnabled (void);
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IMPORT int vfpHasException (void);
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IMPORT STATUS vfpProbeSup (void);
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IMPORT UINT32 vfpFpSidGet (void);
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IMPORT UINT32 vfpFpScrGet (void);
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IMPORT void vfpFpScrSet (UINT32);
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#endif
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* CPU == ARMARCH7M */
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#endif /* __INCvfpArmLibh */
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