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/* intArmLib.h - ARM-specific interrupt library header file */
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/*
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* Copyright (c) 1997-1998, 2003, 2007-2010, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01l,07may12,jdw Add ARMARCH7M header include
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01j,03dec10,j_b add unified FIQ/IRQ handling support
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01i,23oct09,j_b fix _inline_intCpuMicroUnlock for gnu
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01h,18may09,j_b add _inline_intCpuMicroLock/Unlock support
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01h,25feb09,j_b merge ARM SMP support:
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21jun07,jb3 Convert to vxBus
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01g,16jun08,zl added memory clobber for GNUC version of inline routines.
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01f,20may08,j_b fix memory accesses outside lock in
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_inline_intCpuLock/Unlock for gnu (WIND00121559)
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01e,07aug07,jb3 Defect00095620 wrong gnu assembler instruction.
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01d,21jun07,zl updated inline build configuration.
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01c,22aug03,to added inline intLock()/intUnlock().
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01b,20aug98,cdp added intIFLock(), intIFUnlock().
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01a,25nov97,cdp created.
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*/
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#ifndef __INCintArmLibh
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#define __INCintArmLibh
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#if (CPU == ARMARCH7M)
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#include <arch/arm/arm-m/intArmLib.h>
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#else /* (CPU == ARMARCH7M) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* interrupt model feature selection bits (OR'd together) */
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#define INT_NON_PREEMPT_MODEL 0
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#define INT_PREEMPT_MODEL 1
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#define INT_HDWE_LOCK_LVL 2
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#ifndef _ASMLANGUAGE
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/* inline intCpuLock()/intCpuUnlock() and intCpuMicroLock/Unlock() */
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#if !(ARM_THUMB)
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#if defined (__DCC__)
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__asm volatile int _inline_intCpuLock ()
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{
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! "r1" /* r1 clobbered */
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mrs r1, cpsr /* get current status */
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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and r0, r1, #0xC0 /* return current I & F in r0 */
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orr r1, r1, #0xC0 /* set I & F (1<<7 | 1<<6) */
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#else
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and r0, r1, #0x80 /* return current I_BIT in r0 */
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orr r1, r1, #0x80 /* set I_BIT (1<<7) */
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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msr cpsr, r1 /* set new status */
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}
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__asm volatile void _inline_intCpuUnlock (int key)
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{
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% reg key; /* input: key in r0 */
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! "r0", "r1" /* r0, r1 clobbered */
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mrs r1, cpsr /* get current status */
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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bic r1, r1, #0xC0 /* clear I & F (1<<7 | 1<<6) */
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and r0, key, #0xC0 /* get passed I & F values */
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#else
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bic r1, r1, #0x80 /* clear I_BIT (1<<7) */
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and r0, key, #0x80 /* get passed I_BIT value */
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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orr r1, r1, r0 /* or in passed value */
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msr cpsr,r1 /* set new status */
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}
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__asm volatile int _inline_intCpuMicroLock ()
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{
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! "r1" /* r1 clobbered */
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mrs r0, cpsr /* get, return current status */
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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orr r1, r0, #0xC0 /* set I & F (1<<7 | 1<<6) */
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#else
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orr r1, r0, #0x80 /* set I_BIT (1<<7) */
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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msr cpsr_c, r1 /* set new status */
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}
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__asm volatile void _inline_intCpuMicroUnlock (int key)
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{
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% reg key; /* input: key in r0 */
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msr cpsr_c, key /* restore previous status */
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}
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#elif defined (__GNUC__)
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static __inline__ int _inline_intCpuLock (void)
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{
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int key;
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__asm__ volatile
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(
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"mrs r1, cpsr; " /* get current status */
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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"and %0, r1, #0xC0; " /* return current I & F */
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"orr r1, r1, #0xC0; " /* set I & F (1<<7 | 1<<6) */
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#else
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"and %0, r1, #0x80; " /* return current I_BIT */
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"orr r1, r1, #0x80; " /* set I_BIT (1<<7) */
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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"msr cpsr, r1 " /* set new status */
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: "=&r" (key) /* output: key is %0 */
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: /* no input */
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: "r1", "memory" /* r1 clobbered; memory */
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/* clobber for code barrier */
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);
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return key;
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}
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static __inline__ void _inline_intCpuUnlock (int key)
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{
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__asm__ volatile
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(
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"mrs r1, cpsr; " /* get current status */
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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"bic r1, r1, #0xC0; " /* clear I & F (1<<7 | 1<<6) */
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"and r0, %0, #0xC0; " /* get passed I & F values */
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#else
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"bic r1, r1, #0x80; " /* clear I_BIT (1<<7) */
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"and r0, %0, #0x80; " /* get passed I_BIT value */
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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"orr r1, r1, r0; " /* or in passed I_BIT value */
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"msr cpsr, r1" /* set new status */
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: /* no output */
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: "r" (key) /* input: key is %0 */
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: "r0", "r1", "memory" /* r0, r1 clobbered; memory */
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/* clobber for code barrier */
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);
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}
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static __inline__ int _inline_intCpuMicroLock (void)
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{
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int key;
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__asm__ volatile
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(
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"mrs %0, cpsr; " /* get, return current status */
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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"orr r1, %0, #0xC0; " /* set I & F (1<<7 | 1<<6) */
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#else
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"orr r1, %0, #0x80; " /* set I_BIT (1<<7) */
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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"msr cpsr_c, r1 " /* set new status */
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: "=&r" (key) /* output: key is %0 */
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: /* no input */
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: "r1", "memory" /* r1 clobbered; memory */
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/* clobber for code barrier */
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);
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return key;
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}
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static __inline__ void _inline_intCpuMicroUnlock (int key)
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{
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__asm__ volatile
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(
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"msr cpsr_c, %0" /* restore previous status */
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: /* no output */
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: "r" (key) /* input: key is %0 */
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/* no regs, memory clobbered */
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);
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}
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#else
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#define _inline_intCpuLock() intCpuLock()
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#define _inline_intCpuUnlock(key) intCpuUnlock(key)
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#define _inline_intCpuMicroLock() intCpuMicroLock()
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#define _inline_intCpuMicroUnlock(key) intCpuMicroUnlock(key)
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#endif /* __DCC__ */
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#endif /* !ARM_THUMB */
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/* functions in intArchLib.c and intALib.s */
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extern STATUS intDisable (int);
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extern STATUS intEnable (int);
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extern STATUS intLibInit (int, int, int);
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extern int intIFLock (void);
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extern void intIFUnlock (int);
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#ifdef _WRS_CONFIG_UNIFIED_FIQ_IRQ
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extern int intILock (void);
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extern void intIUnlock (int);
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extern int intFLock (void);
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extern void intFUnlock (int);
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#endif /* _WRS_CONFIG_UNIFIED_FIQ_IRQ */
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/*
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* Function pointers used in intArchLib.c and interrupt driver
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*/
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IMPORT FUNCPTR sysIntLvlVecChkRtn;
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IMPORT FUNCPTR sysIntLvlVecAckRtn;
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IMPORT FUNCPTR sysIntLvlChgRtn;
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IMPORT FUNCPTR sysIntLvlEnableRtn;
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IMPORT FUNCPTR sysIntLvlDisableRtn;
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/*
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* vxBus function pointers used in intArchLib.c and interrupt driver
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*/
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IMPORT FUNCPTR _func_IntLvlVecChkRtn;
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IMPORT FUNCPTR _func_IntLvlVecAckRtn;
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IMPORT FUNCPTR _func_IntLvlChgRtn;
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IMPORT FUNCPTR _func_IntLvlEnableRtn;
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IMPORT void * intCtlrDevID;
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IMPORT FUNCPTR _func_IntLvlDisableRtn;
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* (CPU == ARMARCH7M) */
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#endif /* __INCintArmLibh */
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