original files of m241
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/* cacheArm940tLib.h - ARM 940T cache library header file */
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/* Copyright 1998-2005 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01d,27jul06,m_h vxWorks 6.x Support
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01c,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
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01b,11dec03,scm flushing out aim...
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01a,24nov98,jpd created
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*/
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#ifndef __INCcacheArm940tLibh
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#define __INCcacheArm940tLibh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define D_CACHE_SIZE (4*1024) /* 4 kbytes DCache */
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/*
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* Some cache designs (e.g. Harvard) have D-cache either fully or
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* partially not coherent with I-cache
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*/
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#define ARMCACHE_NOT_COHERENT TRUE
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/*
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* This is a writethrough cache
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*/
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#define ARMCACHE_HAS_WRITETHROUGH TRUE
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/*
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* Does not have a mini-cache
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*/
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#define ARMCACHE_HAS_MINICACHE FALSE
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/*
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* Do not need an Instruction Memory Barrier
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*/
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#define ARMCACHE_NEEDS_IMB FALSE
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#ifndef _ASMLANGUAGE
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IMPORT void cacheArm940tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
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PHYS_ADDR(virtToPhys) (VIRT_ADDR));
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#if 0
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/* if true, not building with cacheAIM support... */
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/* The following prototypes are pre-cacheAIM support */
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IMPORT void cacheArm940tDClearDisable (void);
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IMPORT void cacheArm940tDFlush (void * addr);
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IMPORT void cacheArm940tDFlushAll (void);
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IMPORT void cacheArm940tDInvalidateAll (void);
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IMPORT void cacheArm940tIInvalidateAll (void);
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IMPORT void cacheArm940tIInvalidate (void * addr);
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IMPORT void cacheArm940tDClearAll (void);
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IMPORT void cacheArm940tDClear (void * addr);
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IMPORT void cacheArm940tIClearDisable (void);
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IMPORT void cacheArm940tArchPipeFlush (void);
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#else
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/* else, cacheAIM support... */
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/* definitions to allow for non-cacheAiIM direct calls */
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#define cacheArm940tDClearDisable cacheAim940tDClearDisable
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#define cacheArm940tIClearDisable cacheAim940tIClearDisable
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#endif
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcacheArm940tLibh */
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